Phase change memory cell and memory device

Abstract

The embodiment of the utility model relates to a phase change memory unit and a memory device. A phase change memory cell includes a heater having first and second lateral sides opposed to each other along a first axis, and top and bottom sides opposed to each other along a second axis orthogonal to the first axis; and a memory region made of a phase change material layer, the memory region being electrically and thermally coupled to the top side of the heater; and a conductive element having a resistive property, the conductive element extending parallel to the first axis away from the first lateral side; wherein the conductive element is positioned adjacent the first lateral side and in contact with the memory region. According to the embodiment of the invention, a window or a gap between the set / reset resistance values of the two states is advantageously increased.

Description

Technical Field

[0001] The present disclosure generally relates to a phase change memory cell and a memory device including the phase change memory cell. Specifically, the phase change memory cell is configured to support multi-bit storage. Background Art

[0002] A phase change material layer is a material capable of switching between a crystalline phase and an amorphous phase, or between a fully amorphous state and a fully crystalline state, among different detectable states of local order across the entire spectrum under the action of heat. Since the resistance of an amorphous material is significantly greater than that of the crystalline phase of the same material, this phenomenon is used to define two storage states, such as 0 and 1, which are distinguished by the resistance measured through the phase change material layer.

[0003] It is well known that phase change memory devices use a phase change material layer for electronic storage applications. The state of the phase change material layer is also non-volatile because when set to a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, it retains that value until changed by another programming event, because the value represents the phase or physical state of the material (e.g., crystalline or amorphous). This state is not affected by the removal of power.

[0004] Currently, alloys of Group VI of the periodic table, such as Te or Se, known as chalcogenides or chalcogenide materials, can be advantageously used as the phase change material layer in a phase change cell. The most promising chalcogenides are formed from Ge, Sb, and Te alloys (Ge 2 Sb 2 Te 5 ), also known as GST, which is currently widely used to store information in rewritable discs.

[0005] In chalcogenides, when the material changes from the amorphous phase (more resistive) to the crystalline phase (more conductive), the resistivity changes by two or more orders of magnitude, and vice versa.

[0006] The phase change can be obtained by locally raising the temperature. All phases are stable below 150°C. Above 200°C (i.e., the temperature at which nucleation begins), rapid nucleation of microcrystals occurs, and if the material is held at the crystallization temperature for a sufficient length of time, it changes its phase and becomes crystalline (the so-called set state). To return the chalcogenide to the amorphous state (reset state), the temperature needs to be raised above the melting temperature (about 600°C), and then the chalcogenide is rapidly cooled. Intermediate phases can be obtained at appropriate temperatures at different times, which leads to the formation of amorphous "spots" or "bubbles" of different sizes in contact with the heater.

[0007] From an electrical point of view, the chalcogenide material can be changed in state by passing an electric current through a resistive element called a heater, which heats the chalcogenide material by the Joule effect.

[0008] The basic structure of the PCM element 1 operating according to the above principle is shown in Figure 1 and includes a heater element 2 and a memory element 3 of chalcogenide material. A part of the memory element 3 (usually crystalline or polycrystalline) is in thermal contact with the heater 2 and a phase change occurs between the amorphous and crystalline states. Figure 1 The PCM element in an intermediate state is shown, where the part that has not changed phase and allows good current flow is called the crystalline part 4, and the part that has changed state is called the amorphous part 5. The size of the amorphous part 5 defines the total resistivity of the memory region 3 and thus the total resistivity of the PCM element 1. Therefore, different resistance levels can be associated with different bits and can be obtained by generating an appropriate programming current that makes the amorphous part 5 assume different sizes.

[0009] A conductive layer 7 (having a predetermined resistance and thus also called a "resistive layer" here) is interposed between the memory element 3 and the heater 2, and the conductive layer 7 is between the memory element 3 and an insulating or dielectric layer 6 that laterally surrounds the heater 2. In other words, the resistive layer 7 is formed and rests on the upper surface of the dielectric layer 6 and the upper surface of the heater 2, and the resistive layer 7 is in electrical contact with the heater 2. The memory element 3 is formed and rests on the upper surface of the resistive layer 7. The resistive layer 7 is made of, for example, any refractory metal and / or refractory metal nitride, such as TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), or W (tungsten).

[0010] Also refer to Figure 2A -2D, Figure 2A -2D shows the Figure 1 PCM element 1 under different programming conditions, which is obtained using a gradually increasing programming current. In Figure 2A -2D, the same reference numerals as in Figure 1 are used, while the number 6 represents the insulating or dielectric material layer surrounding the heater 2.

[0011] As Figure 2A -2D shows, the amorphous part 5 has different sizes (radii). Specifically, in Figure 2A , when using a lower programming current ip (for example, ip = 160 - 200 μA), the phase change part 5 only slightly extends beyond the edge of the heater 2, while in Figure 2B , 2C, 2D (obtained with a gradually higher programming current ip - up to 300 - 350 μA), the protruding part of the phase change part 5 beyond the edge of the heater 2 becomes gradually larger.

[0012] The current path from the heater 2 to the crystallization section 4 is affected by the high-resistance amorphous section 5; thus, the current path resistance is very high under all four conditions. Therefore, the resistance difference between the four conditions is small compared to its absolute value.

[0013] Furthermore, the programmed resistance is fully correlated with the high resistivity of the amorphized section.

[0014] European Patent No. 2034536 B1 (incorporated herein by reference) discusses the multi-level structure of the PCM. The resistance of the intermediate state between two programmed states (also referred to as SET and RESET) is controlled (geometrically) by the volume of the amorphous section 5.

[0015] During the read process, current flows through two parallel paths (not shown), thus surrounding the amorphous section 5. That is, the read current flows in the resistance layer 7 rather than in the amorphous section 5. Each of these two paths includes a respective one of two branches of the resistance layer 7 that extends in opposite directions from the upper surface of the heater 2 and is covered by the amorphous section 5 (each branch having a resistance R L ). For a specific programmed state SET / RESET, the amorphous volume of section 5 only determines the length of the resistance layer 7 through which the read current flows (and thus the resistance seen by the current).

[0016] Benefits of this approach include a significant reduction in temperature dependence, drift, and 1 / f noise. However, the gap between the resistance values of the two states (SET / RESET) is reduced due to the fact that for each amorphous volume configuration, there are two identical current paths in parallel (due to the symmetry of the layout of the resistance layer 7). For example, by defining: the resistance in the SET state as R SET = R H ; the resistance in the RESET state as R RESET = R H + R L / 2 (where R L / 2 is the equivalent resistance of the portion of the resistance layer 7 through which the current flows during the read of the memory element 3 when programmed in the RESET state).

[0017] R RESET and R SET The ratio between represents the window W or gap between the resistance values of the two states SET / RESET:

[0018]

[0019] The higher the window W, the easier it is to detect the corresponding state SET / RESET during the read.

[0020] There is a need in the art to provide a phase change memory cell, a memory device including the phase change memory cell, and a method for manufacturing the phase change memory cell, which has improved performance and overcomes the above-mentioned drawbacks. Summary of the Utility Model

[0021] An object of the present disclosure is to provide a phase change memory cell and a memory device to at least partially solve the above problems existing in the prior art.

[0022] One aspect of the present disclosure provides a phase change memory cell, comprising: a heater having a first lateral side and a second lateral side opposite to each other along a first axis, and a top side and a bottom side opposite to each other along a second axis orthogonal to the first axis; and a memory region made of a phase change material layer, the memory region being electrically and thermally coupled to the top side of the heater; and a conductive element having a resistive property, the conductive element extending parallel to the first axis away from the first lateral side; wherein the conductive element is positioned adjacent to the first lateral side and in contact with the memory region.

[0023] According to one or more embodiments, wherein the conductive element has a first extension at the first lateral side and along the first axis, and the length of the first extension is equal to the corresponding first length of the memory region along the first axis at the first lateral side.

[0024] According to one or more embodiments, wherein the conductive element extends only at the first lateral side parallel to the first axis, and the conductive element is absent at the second lateral side.

[0025] According to one or more embodiments, wherein the conductive element further extends parallel to the first axis away from the second lateral side with a second extension, and the length of the second extension is less than the corresponding second length of the memory region along the first axis at the second lateral side.

[0026] According to one or more embodiments, wherein the phase change material layer of the memory region can be configured to be crystalline and amorphous, and wherein the resistive property is such that the resistivity of the conductive element is between the resistivity of the crystalline state of the phase change material layer and the resistivity of the amorphous state of the phase change material layer.

[0027] According to one or more embodiments, wherein the conductive element is made of the same material as the heater.

[0028] According to one or more embodiments, wherein the conductive element is made of a material different from the heater.

[0029] According to one or more embodiments, the conductive element is integral with the heater and protrudes from the heater with electrical and physical continuity.

[0030] According to one or more embodiments, the conductive element is sandwiched between a first insulating region and the memory region.

[0031] According to one or more embodiments: the first insulating region is physically separated from the memory region by the conductive element; and further includes a second insulating region on the second side of the heater, the second insulating region being at least partially in direct contact with the memory region.

[0032] According to one or more embodiments, the heater is centered relative to the memory region.

[0033] According to one or more embodiments, the heater is staggered or offset with respect to a symmetry axis parallel to the second axis of the memory region.

[0034] Another aspect of the present disclosure provides a memory device including: at least one phase change memory cell according to the foregoing embodiments.

[0035] Using the embodiments of the present disclosure advantageously increases the window or gap between the resistance values of two state set / reset. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The foregoing features and advantages, as well as other features and advantages, will be given in the following description of specific embodiments with reference to the drawings in an illustrative rather than limiting manner, in which:

[0037] To better understand the present disclosure, its preferred embodiments are now described only by way of non-limiting example and with reference to the drawings, in which:

[0038] Figure 1 Shows an exemplary structure of a known phase change memory element;

[0039] Figures 2A - 2D Shows a phase change memory element Figure 1 under different programming conditions;

[0040] Figure 3 Is a simplified cross-sectional view of an example of a phase change memory device including a phase change memory cell;

[0041] Figure 4 Is a simplified cross-sectional view of an example of a phase change memory device including a phase change memory cell according to another embodiment;

[0042] Figure 5is a simplified cross-sectional view of an example of a phase change memory device including phase change memory cells according to another embodiment;

[0043] Figure 6 is a simplified cross-sectional view of an example of a phase change memory device including phase change memory cells according to another embodiment;

[0044] Figure 7 is a simplified cross-sectional view of an example of a phase change memory device including phase change memory cells according to another embodiment;

[0045] Figure 8 is a simplified cross-sectional view of an example of a phase change memory device including phase change memory cells according to another embodiment;

[0046] Figure 9A - Figure 9C shows the writing Figure 3 or Figure 4 - Figure 8 of a phase change memory cell in three simplified cross-sectional views of the respective steps of the method;

[0047] Figure 10A - Figure 10I shows the process steps for manufacturing Figure 3 of a phase change memory device performed on a wafer;

[0048] Figure 11A - Figure 11C shows the process steps for manufacturing Figure 8 of a phase change memory device performed on a wafer;

[0049] Figure 12A - Figure 12H shows the process steps for manufacturing Figure 5 of a phase change memory device performed on a wafer;

[0050] Figure 13A - Figure 13C shows the process steps for manufacturing another phase change memory device not shown in the previous figures performed on a wafer; and

[0051] Figure 14 schematically shows an embodiment of a memory. DETAILED DESCRIPTION

[0052] In the respective drawings, the same features are denoted by the same reference numerals. In particular, the structural and / or functional features common to the respective embodiments may have the same reference numerals and may be provided with the same structure, dimensions, and material properties.

[0053] For clarity, only the operations and elements that are useful for understanding the embodiments described herein are described in detail. Specifically, the memory cell includes elements not described in detail, such as selection elements (e.g., transistors) or electrical connections.

[0054] Figure 3 is a simplified perspective view of a memory cell 100, which is part of a phase change memory (PCM) device 10 (only a part thereof is shown), and the phase change memory device 10 includes a plurality of memory cells 100. Figure 3 The memory cell 100 is shown in a three-axis system (Cartesian system) of mutually orthogonal axes X, Y, and Z.

[0055] Phase change memory cells (such as Figure 3 the memory cell 100 depicted in

[0056] are typically embedded in a non-volatile memory (NVM) device (such as an electrically erasable programmable read-only memory (EEPROM)). Programming of each memory cell in such a memory device is typically performed during the manufacture of the memory device and can subsequently be modified several times, especially during its use.

[0057] The memory cells 100 of the memory device 10 are arranged in a grid or matrix pattern. In other words, the memory device 10 consists of an array of memory cells 100. Each memory cell 100 is located at the intersection of a row and a column of the array.

[0057] Columns that are parallel to each other are also referred to as "bit lines" (BL). Rows that are parallel to each other and perpendicular to the bit lines are also referred to as "word lines" (WL).

[0058] Each phase change memory cell 100 of the memory device 10 includes a heater 102 or a resistive element. In Figure 3 the example of

[0059] the heater 102 has an L-shaped cross-section (and thus has a vertical portion extending along the Z axis and a horizontal portion extending along the X axis). However, other shapes are also possible, such as an "I" shaped cross-section (where only the vertical portion exists).

[0059] The heater 102 is typically surrounded by one or more insulating or dielectric layers ( Figure 3 only one layer 104 is shown in 2 ), and the insulating or dielectric layer is typically composed of nitrates (e.g., SiN) and / or oxides (e.g., SiO 2 ).

[0060] The upper surface 102c of the vertical portion of the heater 102 is coplanar with the upper surface 104a of the insulating layer 104. As will be better explained later, the thickness t of the insulating layer 104 along the Z axis 1The thickness at one side 102a of the heater 102 is made smaller than the thickness t of the insulating layer 104 at the opposite side 102b (along the X axis) of the heater 102. 2 Due to the presence of the conductive layer 210 having resistive characteristics (hereinafter, also referred to as "resistive lamina 210"), the thickness t 1 is reduced relative to the thickness t 2 The resistive lamina 210 has a main extension in the X direction and extends (or protrudes) away from the heater 102 with the main extension from one side 102a of the heater 102. The upper surface 104a' of the insulating layer 104 extending at one side 102a of the heater 102 is coplanar with the lower surface of the resistive lamina 210.

[0061] Each memory cell 100 further includes an associated memory region 106 which is separated from other memory regions 106 by an interposed dielectric or insulating layer. The memory region 106 is made of a phase change material layer. The memory region 106 is made of a chalcogenide material, for example, an alloy belonging to the group of tellurium-based chalcogenide alloys, particularly an alloy including germanium (Ge), antimony (Sb), and tellurium (Te). Such an alloy is referred to as "GST". There are other groups of chalcogenide alloys (selenium-based and sulfur-based) that can be used to fabricate the memory region 106. In any case, the embodiments herein are not limited to a specific material for the memory region 106.

[0062] Generally, the crystalline phase of the memory region 106 is native (that is, after the memory cell 100 is fabricated and before the write / program operation starts, the memory region 106 is in a fully crystalline state / phase). Therefore, in the following description, the memory region 106 is also referred to as "crystalline layer 106".

[0063] The crystalline layer 106 is formed and rests on both the upper surface 104a of the insulating layer 104 and the upper surface 102c of the vertical portion of the heater 102. The heater 102 is in electrical contact and thermal contact with the crystalline layer 106 through the vertical portion of the heater 102.

[0064] In Figure 3 the illustrated embodiment, the heater 102 is centered with respect to the axis of symmetry (parallel to the Z axis and orthogonal to the X axis) of the memory cell 100.

[0065] According to one embodiment, the aforementioned resistive lamina 210 is interposed transversely to the heater 102 between a portion of the insulating layer 104 and a corresponding portion of the crystalline layer 106. The heater 102 is in electrical contact with the resistive lamina 210, particularly in direct electrical contact with the resistive lamina 210. Specifically, the resistive lamina 210 is transversely connected to the heater 102 (i.e., it is connected to the heater 102 at one side 102a of the heater 102).

[0066] The conductive metal layer 108 extends on top of the crystalline layer 106. This conductive layer 108 generally forms the electrode of the memory cell 100. Conductive vias (not shown) may be provided to connect each electrode 108 to, for example, a metallization level located above the memory cell 100 of the memory device 10.

[0067] The conductive layer 108 forms the electrode of the memory cell 100 (to be connected to a bit line), while the heater 102 forms the other electrode of the memory cell 100 (to be connected to a word line). The two electrodes are also referred to herein as the "top" electrode 108 and the "bottom" electrode 102, but this does not imply a limitation on the orientation of the memory cell 100 during operation.

[0068] The heater 102 of the memory cell 100 is generally connected through its foot 102d (i.e., the bottom surface of its horizontal portion) to a bottom contact or pillar 112 made of a conductive material (such as doped polysilicon or metal). This bottom contact 112 extends vertically through the insulating layer 111 and is connected to a substrate 114 extending below the insulating layer 111.

[0069] The substrate 114 may have a multi-layer structure, for example, consisting of three layers: a first layer 114a made of a thin silicon film to which the bottom contact 112 is connected; a second layer 114b made of a thin buried oxide; and a third layer 114c made of a material suitable for providing mechanical support, also referred to as the "operating substrate".

[0070] The bottom contact 112 of each memory cell 100 is connected to one terminal of a selection element 113. The selection element 113, commonly referred to as a selector or access device, provides the ability to individually address / select each memory cell 100 of the memory device 10.

[0071] In Figure 3 the example of, the selection element 113 is a bipolar junction transistor (BJT) device, whose emitter terminal is electrically coupled to the bottom contact 112, the collector terminal is electrically coupled to a common reference potential (usually the ground potential), and the base terminal receives a bias voltage in use.

[0072] The crystalline phase of the memory region 106 corresponds to, for example, the logical value "1". Data storage within the phase change memory 10 is then performed by writing / programming some of the memory cells 100 of the phase change memory 10, while other memory cells 100 of the phase change memory 10 remain in their native state (i.e., in the crystalline state).

[0073] To write to or program a given phase change memory cell 100 of the memory 10, first the memory cell 100 is selected by applying an appropriate voltage bias to the base terminal of the BJT. Then a current flows through the crystallization layer 106. The potential or intensity of the current is tuned so as to sufficiently increase the temperature of the heater 102, thereby heating the region of the crystallization layer 106 in contact with the upper end 102c of the heater 102 by Joule heating. This causes at least a portion of the phase change material layer to melt. When the voltage pulse is abrupt, the current ends rapidly, so the local temperature of the phase change material layer decreases rapidly, quenching the glassy structure of the melted portion of the phase change material layer. As a result, the electrical pulse transforms a portion of the phase change material layer from a low-resistance crystalline phase to a high-resistance amorphous state. For example, assume that this amorphous state corresponds to the logic value "0".

[0074] To read a given phase change memory cell 100, first the memory cell 100 is selected by applying an appropriate bias voltage to the base terminal of the BJT. Then, by activating the selector element, an appropriate potential is applied such that a current flowing through the cell 100 is low enough in value to avoid any unintentional phase change. Then the resistance between the electrode 108 and the heater 102 can be measured. This resistance reflects the value "0" or "1" previously stored in the memory cell 100.

[0075] The material of the resistance sheet 210 can be selected based on a trade-off between the programming current and the ability to distinguish intermediate programming states represented by different resistance levels. The resistance of the resistance sheet 210 is selected as needed, for example, to be approximately the resistance value of the heater 210, and / or less than the resistance of the amorphous region of the layer 106. More specifically, the resistivity value of the sheet 210 is between the respective resistivity values of the crystalline and amorphous states of the phase change material layer of the crystallization layer 106. The resistivity of the sheet 210 can be significantly lower than the resistivity of the amorphous state of the phase change material layer. For example, the resistivity of the sheet 210 can be between about 1 / 1000 times and 1 / 10 times the resistivity of the amorphous state of the phase change material layer of the layer 106. At the same time, the resistivity of the sheet 210 is higher than the resistivity of the crystalline state of the phase change material layer. In one embodiment, the sheet 210 can be selected to have a resistivity in the range of about 1 mΩ·cm to 0.1 Ω·cm. Exemplary materials that can be used for the sheet 210 can include, but are not limited to, carbon (C) and metal compounds such as TiSiN, TiAlN, and SiC. Other materials conventionally used for resistors in the integrated circuit industry can also be employed. For example, the resistance sheet 210 can also be made of any refractory metal and / or refractory metal nitride, such as TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), or W (tungsten).

[0076] The thickness of the resistance sheet 210 along the Z-axis is less than 10 nm, preferably 1 - 10 nm, and most preferably 4 - 5 nm.

[0077] According to one embodiment, in Figure 3 the cross-sectional view of 3 , the resistive sheet 210 has an extension portion t along the X-axis

[0078] Specifically, in Figure 3 the embodiment of Figure 3 , the resistive sheet 210 extends only at one side 102a of the heater 102 ( Figure 3 the right hand side in

[0079] ), and is in electrical contact (specifically, direct electrical contact) with the heater 102 at the one side 102a. At the opposite side 102b of the heater 102 ( Figure 4 the left hand side in 4 ), there is no resistive sheet 210. 3 Specifically, the length t 3 along the X-axis and at the one side 102a of the heater 102 corresponds to the entire length of the crystallization layer 106 extending at the one side 102a (i.e., the length of the layer 106 measured along the X-axis from the one side 102a until the end of the layer 106 of the memory cell 100 under consideration). The length t 4 along the X-axis and at the one side 102b of the heater 102 corresponds to a part of the length of the crystallization layer 106 extending at the one side 102b (i.e., the length of the layer 106 measured along the X-axis from the one side 102b until the end of the layer 106 of the memory cell 100 under consideration).

[0080] In Figure 5 the another embodiment shown in Figure 3 - Figure 4 , the resistive sheet 210 is made integral with the heater 102 (which is opposite to being separate from the heater in

[0081] As discussed with reference to Figure 3 and Figure 4 , similarly inFigure 5 In the embodiment of, the resistive sheet 210 has an extension portion t along the Figure 4 X-axis in the cross-sectional view of, which is larger on one side (here side 102a) of the heater 102 than on the opposite side (here side 102b) relative to the heater 102. In particular, in the 3 embodiment of, the resistive sheet 210 is only present at one side 102a and is absent at the other side 102b. Figure 5 In the embodiment of, the resistive sheet 210 is only present at one side 102a and is absent at the other side 102b.

[0082] In the Figure 5 embodiment based on the Figure 6 embodiment of, the resistive sheet 210 is integral with the heater 102 and also extends on both sides 102a and 102b of the heater 102. The length t of the portion of the resistive sheet 210 at one side 102b 4 is less than the length t of the portion of the resistive sheet 210 at the first side 102a 3 (along the X-axis).

[0083] As shown in Figure 7 , according to another embodiment, the heater 102 (in particular the vertical portion of the heater 102) is not centered with respect to the symmetry axis of the memory cell 100 ( Figure 7 shown and identified as SZ in), but is staggered or offset with respect to this symmetry axis; in other words, the heater 102 and the pillar 112 are shifted to the left or right side with respect to the symmetry axis SZ. Although Figure 7 shows the case where the resistive sheet 210 is not integral with the heater 102 ( Figure 3 and 4 embodiments of), but the Figure 7 teaching also applies to the embodiment where the resistive sheet 210 is integral with the heater 102 (as shown in Figure 5 and 6 ).

[0084] Furthermore, also in the Figure 7 embodiment of, the resistive sheet 210 has an extension along the X-axis in the cross-sectional view, which is larger on one side 102a of the heater 102 than on the opposite side 102b relative to the heater 102. Specifically, the resistive sheet 210 may only be present at one side 102a and be absent at the second side 102b; or the resistive sheet 210 also extends at the second side 102b of the heater 102, where the length of the portion of the resistive sheet 210 at the second side 102b is less than the length of the portion of the resistive sheet 210 at the first side 102a (along the X-axis).

[0085] As shown in Figure 8As shown, according to another embodiment, the selection element 113 is a metal oxide semiconductor field effect transistor (MOSFET) device having one conductive terminal (source or drain) electrically coupled to the bottom contact 112, an opposite conductive terminal (drain or source) electrically coupled to a common reference potential, typically ground potential, and a gate that receives a bias voltage in use. Depending on its value, this bias voltage allows the current flowing through the selector to be enabled or disabled. In Figure 8 the example of, the selection transistors of the memory cells 100 belonging to a given word line or row share the same gate. In the memory device, the gate extends longitudinally along the WL direction (extending to the front and rear in Figure 8 ). Thus, all the selection transistors of the memory cells of a given word line are connected to the same gate. The conductive layer 108 and the gate thus form a matrix or grid-like pattern, where each intersection is substantially vertically aligned with the memory cell 100.

[0086] When the MOSFET device is used as a selector device, a dummy heater (not shown) can be implemented to account for the size and electrical connection of the gate.

[0087] Figure 8 Based on Figure 3 ; however, it is also possible to implement the MOSFET as the selector device 113 for Figure 4 -7 embodiments.

[0088] Figure 3 - Figure 8 shows the corresponding embodiment where the resistive sheet 210 has a greater length (along the X axis) at the right hand side 102a of the heater 102 than with respect to the left hand side 102b (where the sheet 210 may even be absent). However, the teachings of this specification apply similarly to such embodiments (not shown) where the resistive sheet 210 extends only from the left hand side 102b of the heater 102, or has a greater length (along the X axis) at the left hand side 102b of the heater 102 than with respect to the right hand side 102a. Similarly, the memory device 10 may include multiple memory cells 100, where one or more (but not all) of the memory cells 100 include a respective resistive sheet 210 that extends only from the right hand side 102a of the respective heater 102, or has a greater length (along the X axis) extending from the right hand side 102a of the heater 102 with respect to the left hand side 102b; the remaining one or more memory cells 100 of such a memory device 10 extend only from the left hand side 102b of the heater 102, or have a greater length (along the X axis) extending from the left hand side 102b of the heater 102 with respect to the right hand side 102a. See for example Figure 10I, which shows a portion of a device 10 , including some heaters 102 having corresponding resistive sheets 210 extending from a right-hand side 102a of the heater 102 and other heaters 102 having corresponding resistive sheets 210 extending from a left-hand side 102b of the heater 102 .

[0089] refer to Figure 9A - Figure 9C The write operation is discussed, where only Figure 3 1. A portion of a phase change memory 10 (specifically, a detail of a phase change cell 100) is shown. To write in the memory cell 100, a voltage is applied between the top electrode 108 (conductive layer) and the bottom electrode or heater 102. This voltage causes a current to flow through the layer 106, which is initially composed entirely of a crystalline phase. The memory cell 100 is thus heated by the heater 102 to a temperature sufficient to amorphize at least a portion 105a of the crystalline layer 106.

[0090] exist Figure 9B , a larger portion 105b of layer 106 changes phase due to Joule heating of current flowing through memory cell 100, thereby forming a larger amorphous region above upper surface 102c of heater 102. The amorphous region forms a dome that is vertically aligned with upper surface 102c of the vertical portion of heater 102.

[0091] exist Figure 9C , the increased heating obtained with a suitably increased current flowing through the memory cell 100 causes a larger portion 105c of the layer 106 to change phase, thereby forming a larger amorphous region above the upper surface 102c of the heater 102. The process of transforming the crystalline GST into amorphous GST can result in a situation where the upper surface of the resistive sheet 210 is completely covered by amorphous GST.

[0092] In the amorphous region directly above the heater 102, the GST making up the layer 106 has changed / switched from the crystalline phase to the amorphous state due to the heating. The layout of the resistive sheet 210 (in this example extending only on one side of the heater 102) has no influence on the formation of the amorphous regions 105a-105c. The shape and position of the amorphous regions actually depends on the arrangement of the heater 102. If a similar arrangement is chosen Figure 9A - Figure 9C The memory unit 100 shown in FIG.

[0093] The cell is used for reading, and if the top electrode 108 and the bottom electrode (or heater 102)

[0094] Applying an appropriate voltage bias between the two, the electrical read current flows through layer 106 to reach the

[0095] The resistor sheet 210 on one side of the heater 102.

[0096] Memory cell 100 implements multi-level programming, as shown in Figure 9A -9C. In this case

[0097] during a write (programming) operation, it is assumed that the voltage applied between the top electrode 108 and the bottom electrode is increased in order to increase the current intensity flowing through layer 106. This causes the temperature within layer 106 to increase, resulting in a phase change within the crystalline phase around the already amorphized regions.

[0098] Consequently, an increasing amount of the crystalline GST contained within the crystalline regions is gradually transformed into amorphous GST,

[0099] which results in a gradually expanding amorphous region as the programming current gradually increases.

[0100] Consistently, the extent of the portion of the resistive sheet 210 covered by the amorphous region also expands (as gradually shown in

[0101] -), and its resistance increases approximately proportionally to the length of the surface of the sheet 210 covered by the amorphous region. Figure 9A - Figure 9C Therefore, the read resistance of cell 100 also

[0102] increases.

[0103]

[0104] For the above embodiment, the resistive sheet 210 is asymmetric along at least one axis (here the X axis)

[0105] In particular, introducing the asymmetry of the resistive sheet 210 forces the read current to flow only

[0106] in a specific direction, namely where the resistive sheet 210 is present. With this solution

[0107] the window

[0108] W or gap between the resistance values of two states SET / RESET (and intermediate programming states in a multi-state memory for multi-bit storage) is increased relative to known solutions.

[0109] In particular, if the resistance in the set state is R SET = R H , then the resistance in the reset state is R RESET = R H + R L (where R L is the resistance of the portion of the resistive sheet

[0110] 210 through which the current flows during a read).

[0111] Define the ratio between R of window W RESET and R SET as being:

[0112]

[0113] This is increased by a factor of 2 relative to the solution of the prior art.

[0114] Figure 10A -10I shows a cross-sectional view of the steps for manufacturing a phase change memory device

[0115] in accordance with one embodiment.

[0116] Referring to Figure 10A , a wafer 300 is provided that has undergone manufacturing steps known in the art and will not be further detailed herein. Specifically, wafer 300 includes a substrate 114 having a selector device 113 (here a BJT) on which an insulating layer 111 is formed. Insulating layer 111 is made of, for example, silicon oxide or other insulating or dielectric materials. A plurality of bottom contacts or pillars 112 (made of a conductive material such as metal or doped polysilicon) extend through insulating layer 111. For example, pillars 112 are formed by etching trenches in insulating layer 111 and then filling these trenches with a conductive material. Bottom contacts 112 extend through insulating layer 111 over the entire thickness of insulating layer 111.

[0117] Referring to Figure 10B , the step of depositing another insulating or dielectric layer 304 on insulating layer 111 is performed; in this embodiment, insulating layer 304 is made of silicon nitride (SiN). Then, steps are performed to form (e.g., by deposition) a resistive layer 305 on insulating layer 304. Here, at this step of the process, resistive layer 305 is a continuous strip or sheet of conductive material that extends over the entire surface of insulating layer 304. In further manufacturing steps described later, resistive layer 305 will form the resistive sheet 210 that has been described. On resistive layer 305, another insulating layer 310 is formed by depositing, for example, the same material as insulating layer 304. Thus, resistive layer 305 is effectively buried between two dielectric layers. On insulating layer 310, a mask layer 312 is formed, for example, by depositing TEOS.

[0118] Next, Figure 10C, the patterned mask layer 312 is formed to create an etch mask that is used to remove selective portions of the underlying layers (i.e., the two dielectric layers 304, 310 and the buried resistor layer 305). This etching step removes the unmasked portions of these layers until the respective surface regions of the insulating layer 111 are exposed. Specifically, the mask 312 and the etching step are designed such that the remaining portions of the two dielectric layers 304, 310 and the remaining portion of the buried resistor layer 305 (the masked stack 315) extend in a strip-like manner along the Y-axis in a top view (in the XY plane), and are separated from each other along the X-axis by the gaps left by the removed portions. Each masked stack 315 extends along the X-axis from one pillar 112 to the next consecutive pillar 112, only partially covering the surfaces of these two pillars. Two consecutive pillars 112 along the X-axis are only partially covered by a corresponding masked stack 315.

[0119] As Figure 10D shown, the step of depositing a continuous resistive material layer 320 is performed. The resistive material layer 320 covers the masked stack 315, the exposed surfaces of the pillars 112, and the exposed surface of the insulating layer 111 between the pillars 112. This resistive material layer 320 will form a plurality of heaters 102 in subsequent steps. Thus, the material of layer 320 and its thickness are selected according to the requirements of the heaters 102 and / or the design requirements. For example, the material is made of TiSiN and the thickness is in the range of 3.5 to 6 nm.

[0120] Next, Figure 10E , an insulating layer 322 (e.g., made of silicon nitride) is deposited to cover the masked stack 315 and the space between the masked stacks 315. Then a mask etching step is performed to remove selective portions of the insulating layer 322 on and between the masked stacks 315. The portion of the insulating layer 322 removed between each pair of masked stacks 315 has an extension d along the X-axis 1 , which is less than the distance d along the X-axis between such masked stacks 315 2 . The entire thickness of the insulating layer 322 is etched to expose the corresponding surfaces of the underlying resistive layer 320. During the etching of the insulating layer 322, the resistive layer 320 functions as an etch stop layer. Then, a further etching step is performed to remove a portion of the entire thickness of the exposed resistive layer 320. Due to the etch selectivity of the materials of the resistive layer 320 and the insulating layer 322, this etching step may not be masked.

[0121] Then, in Figure 10F , another step of filling the gaps between the masked stacks 315 is performed to fill the openings left by the etching step described with reference to Figure 10E .

[0122] Then, perform the steps of removing the mask 312 and the insulating layer 310 from each masking stack 315 until the resistive layer 305 is exposed. This step can be performed by an etching chemical that selectively removes the layers 312 and 310, or by a CMP step that is configured to be implemented on the resistive layer 305 without damaging or over-removing the resistive layer 305.

[0123] Then, perform Figure 10G the step of forming a memory region. To this end, deposit a crystalline layer 106; the crystalline layer 106 is made of a phase change material layer, in particular made of a chalcogenide material such as a GST alloy. A sealing layer 326, for example made of silicon nitride, is deposited on the crystalline layer 106 and serves as a Figure 10H mask for subsequent steps.

[0124] Figure 10H Show the wafer 300 in a cross-section taken along the Y axis to better understand the etching steps for defining the grid-like or matrix pattern for the memory cells 100. Through this step, the crystalline layer 106 and the underlying resistive layer and insulating layer 305, 304 are patterned along the Y axis to form a plurality of memory regions (identified by the same reference numeral 106) physically separated from each other, and each memory region is coupled to a corresponding resistive strip 210 (layer 305) and a corresponding heater 102 (which is not shown in the Figure 10H cross-section).

[0125] Figure 10I Show a cross-sectional view of the wafer 300 along the XZ plane to understand that each memory region 106 is coupled to a corresponding heater 102 and a corresponding resistive strip 210, and the resistive strip 210 only extends from one side of the heater 102 and there is no remaining resistive layer 305 on the other side.

[0126] Then, the fabrication of the memory device 10 can be completed by forming a conductive metal layer 108 on top of the crystalline layer 106 and filling the gaps with a dielectric or insulating layer (not shown). Then, appropriate electrical connections can be formed. These steps themselves are not part of the present disclosure and will not be discussed further.

[0127] The insulating layers 322 and 304 form the aforementioned insulating layer 104.

[0128] Figure 11A -11C shows the steps of manufacturing the memory device 10, where the select element 113 is a MOSFET device (as discussed in reference Figure 8 ).

[0129] Only some of the manufacturing steps are shown and described because the manufacturing process is partly similar to the Figure 10AThe manufacturing process of -10I. The same components are denoted by the same reference numerals.

[0130] Reference Figure 11A , provides a wafer 400 that has been processed as described in reference Figure 10A -10B. The mask layer 312 is patterned to form an etch mask that is used to remove the underlying layers (i.e., the two dielectric layers 304, 310) and a selective portion of the buried resistor layer 305. This etch step removes the unmasked portions of these layers until the respective surface regions of the insulating layer 111 are exposed. Specifically, the mask 312 and the etch step are designed such that the remaining portions of the two dielectric layers 304, 310 and the remaining portion of the buried resistor layer 305 (the masked stack 315) extend in a strip-like manner along the Y-axis in a top view (in the XY plane), and are separated from each other along the X-axis by the gaps left by the removed portions, as Figure 10C shown. However, herein, each of the masked stacks 315 extends along the X-axis from one pillar 112 (only partially covering the surface of this pillar 112) to the next successive pillar 112, completely covering the surface of this successive pillar 112.

[0131] As Figure 11B shown, similar to Figure 10D , the step of depositing a continuous resistive material layer 320 is performed. This layer forms the heater 102 in a further step.

[0132] Similarly, the steps described in reference Figure 10D - Figure 10H are performed for manufacturing the Figure 8 memory device, and thus will not be further described in detail for illustration.

[0133] After steps similar to those described in reference Figure 10H , an embodiment is obtained Figure 11C wherein dummy heaters 410 alternate with the substantial heater 102 along the X-axis (the dummy heaters 410 do not operate because they are not electrically connected to the pillars 112).

[0134] The manufacturing of the memory device 10 can then be completed by forming a conductive metal layer 108 on top of the crystalline layer 106 and filling the pores with a dielectric or insulating layer (i.e., completing the formation of the insulating layer 104). Then appropriate electrical connections can be formed. These steps themselves are not part of the present disclosure and will not be further discussed.

[0135] Figure 12A - Figure 12H shows the steps for manufacturing the Figure 6 memory device, where a resistive sheet 210 extends from the heater 102 as an integral part of the heater 102.

[0136] Reference Figure 12A , a wafer 500 is provided which has undergone manufacturing steps known in the art and will not be further detailed herein. In particular, the wafer 500 has been processed to form a selector 113 (here, a BJT selector device 113) in the substrate 114; an insulating layer 111 is formed on the substrate 114. The insulating layer 111 is made of, for example, silicon oxide or other insulating or dielectric materials. Through the insulating layer 111, a plurality of bottom contacts or posts extending in respective trenches 112 (made of a conductive material such as metal or doped polysilicon) are formed. The bottom contacts 112 extend through the insulating layer 111 over the entire thickness of the insulating layer 111.

[0137] The step of depositing another insulating or dielectric layer 504 on the insulating layer 111 is performed; in this embodiment, the insulating layer 504 is made of silicon nitride (SiN).

[0138] Then, in Figure 12B , the insulating layer 111 is patterned (e.g., by a photolithography and etching process). The etching step removes the unmasked portions of the insulating layer 504 until the corresponding surface regions of the insulating layer 111 are exposed. Specifically, the patterning is designed such that the remaining portions of the dielectric layer 504 extend in a strip-like manner along the Y-axis in a top-down plan view (in the XY plane) and are separated from each other along the X-axis by the spaces left by the removed portions. Each portion of the remaining portions of the dielectric layer 504 extends along the X-axis from one post 112 to the next adjacent post 112, only partially covering the surfaces of these two posts. Two adjacent posts 112 along the X-axis are only partially covered by a corresponding remaining portion of the dielectric layer 504.

[0139] As Figure 12C shown, the step of depositing a continuous resistive material layer 520 is performed. The resistive material layer 520 covers the dielectric layer 504, the exposed surfaces of the posts 112, and the portions of the exposed surfaces of the insulating layer 111 between the posts 112. This layer of resistive material 520 will form a plurality of heaters 102 and resistive flakes 210 in subsequent steps. Therefore, the material of the layer 520 and its thickness are selected according to the requirements and / or design specifications of the heaters 102 and resistive flakes 210. For example, the material is made of TiSiN and the thickness is in the range of 3.5 to 6 nm.

[0140] Next, Figure 12D , a protective layer 522 (e.g., made of silicon nitride) is deposited to cover the resistive material layer 520. Then, another step of depositing a filling layer 525 is performed to fill the gaps between the portions of the dielectric layer 504 and cover the portions of the dielectric layer 504.

[0141] Then the step of ( Figure 12E), to remove selective portions of the fill layer 525 over these portions of the dielectric layer 504, thereby exposing the resistive layer 520 over these portions of the dielectric layer 504. The fill layer 525 remains between these portions of the dielectric layer 504. This step can be performed by a masking etch process (e.g., a photolithography process), or by a CMP step configured to land on the resistive layer 520 without damaging or over-removing the resistive layer 520 on top of the portions of the dielectric layer 504.

[0142] Then, perform Figure 12F the step of forming the memory regions. To this end, a crystalline layer 106 is deposited; the crystalline layer 106 is made of a phase change material layer, particularly a chalcogenide material such as a GST alloy. A sealing layer 526, made of silicon nitride for example, is deposited on the crystalline layer 106 and serves as a Figure 12G mask for subsequent steps.

[0143] Figure 12G The wafer 500 is shown in a cross-section taken along the Y-axis to better understand the etching steps for defining the grid-like or matrix pattern for the memory cells 100. With this step, the crystalline layer 106 and the underlying resistive and insulating layers 320, 504 are patterned along the Y-axis to form a plurality of memory regions (identified by the same reference numeral 106) physically separated from each other and each coupled to a respective heater 102.

[0144] Figure 12H The wafer 500 is shown along the X-axis to understand that each memory region 106 is coupled to a respective heater 102 and a respective resistive strip 210, the resistive strip 210 leaving only from one side of the heater 102 and being integral with the heater 102, while leaving the other side without the remaining portion of the resistive layer 520 extending along the X-axis.

[0145] Layers 504, 522, and 525 will together form the aforementioned insulating layer 104.

[0146] Next, the fabrication of the memory device 10 can be completed by forming a conductive metal layer 108 on top of the crystalline layer 106 and filling the pores with a dielectric or insulating layer, thereby completing the formation of the insulating layer 104. Then, appropriate electrical connections can be formed. These steps themselves are not part of the present disclosure and thus will not be discussed further.

[0147] Figure 13A - Figure 13C Shows the steps of manufacturing the memory device 10, where the resistive strip 210 extends from the heater 102 as an integral part of the heater 102, but the selector device 113 is a MOSFET.

[0148] Since the manufacturing process is similar to that already discussedFigure 12A The manufacturing process of -12H is thus only some manufacturing steps are shown and described. Identical elements are denoted by the same reference numerals.

[0149] Reference Figure 13A , a wafer 550 is provided which has undergone manufacturing steps known in the art and will not be further detailed herein. In particular, the wafer 550 includes a substrate 114 on which an insulating layer 111 extends. The insulating layer 111 is made of, for example, silicon oxide or other insulating or dielectric materials. A plurality of bottom contacts or posts 112 (made of a conductive material such as metal or doped polysilicon) extend through the insulating layer 111. The bottom contacts 112 extend through the insulating layer 111 over the entire thickness of the insulating layer 111.

[0150] The step of depositing another insulating or dielectric layer 554 on the insulating layer 111 is performed; in this embodiment, the insulating layer 554 is made of silicon nitride (SiN).

[0151] Then, the insulating layer 554 is patterned (e.g., by photolithography and etching processes). The etching step removes selective portions of the insulating layer 554 until various surface regions of the insulating layer 111 are exposed. Specifically, the patterning is designed such that the remaining portions of the dielectric layer 554 extend in a strip-like manner along the Y-axis in a top-down plan view (in the XY plane) and are separated from each other along the X-axis by spaces left by the removed portions. Each of the remaining portions of the dielectric layer 554 extends along the X-axis from one post 112 (covering only a portion of the surface of this post 112) to another immediately subsequent post 112, completely covering the surface of this subsequent post 112.

[0152] As Figure 13B shown, the step of depositing a continuous resistive material layer 560 is performed. The resistive material layer 560 covers the dielectric layer 554, the exposed surfaces of the posts 112, and portions of the exposed surface of the insulating layer 111 between the posts 112. In a subsequent step, this resistive material layer 560 will form a plurality of heaters 102 and resistive flakes 210. Thus, the material of layer 560 and its thickness are selected according to the requirements and / or design specifications of the heaters 102 and resistive flakes 210. For example, the material is made of TiSiN and has a thickness in the range of 350 - 400 nm.

[0153] Then, the manufacturing process continues similar to that described with reference to Figure 12D - Figure 12H already described.

[0154] After steps similar to those described with reference to Figure 12G are obtained Figure 13CAn embodiment, where dummy heaters 570 are alternated with substantial heaters 102 along the X axis (the dummy heaters 510 are not operative as they are not electrically connected to the pillars 112).

[0155] The fabrication of the memory device 10 can then be completed by forming a conductive metal layer 108 on top of the crystallization layer 106 and filling the pores with a dielectric or insulating layer. Appropriate electrical connections can then be formed. These steps are not part of the present disclosure and are thus not discussed further.

[0156] Figure 14 An embodiment of a memory 600 is schematically illustrated. The memory 600 includes: one or more memory devices, such as a device including memory cells 100 described previously with respect to each of the disclosed embodiments and shown by block 602 (NVM); a data processing unit represented by block 604 (PU), such as a microprocessor; one or more memory devices, represented by block 606 (MEM), and which can be a different memory device from the memory devices of block 602; block 608 (FCT), including other electronic functions, such as sensors, load control circuits, etc.; a data bus 610 enabling data transfer between different components. Figure 14 Block 602 preferably includes circuitry for addressing the memory cell array 100.

[0157] For the memory device of block 506, instead of being a phase change memory device, it can be a RAM, a reprogrammable volatile memory (EEPROM, flash memory, etc.).

[0158] As an alternative, block 606 can be omitted. Then, the memory devices of the memory 600 are merely memory devices such as those including the memory cells 100. The memory is then entirely non - volatile.

[0159] In one embodiment, a phase change memory cell includes: a heater having a first lateral side and a second lateral side that are opposite each other along a first axis, and a top side and a bottom side that are opposite each other along a second axis orthogonal to the first axis; a memory region made of a phase change material layer that is electrically and thermally coupled to the top side of the heater; and a conductive element having resistive characteristics that extends parallel to the first axis at the first lateral side, and the conductive element is adjacent to the first lateral side of the heater and adjacent to the memory region.

[0160] The embodiment further includes a memory device including the phase change memory cell.

[0161]

[0162] ​In one embodiment, a method for manufacturing a phase change memory cell includes: forming a heater having a first lateral side and a second lateral side that are opposite each other along a first axis, and a top side and a bottom side that are opposite each other along a second axis orthogonal to the first axis; forming a memory region made of a phase change material layer, the memory region being electrically and thermally connected to the top side of the heater; and forming a conductive element having resistive characteristics, the conductive element being parallel to the first axis at the first lateral side, and the conductive element being adjacent to the first lateral side of the heater and adjacent to the memory region.

[0163] One aspect of the present disclosure provides a method for manufacturing a phase change memory cell, including: forming a heater having a first lateral side and a second lateral side that are opposite each other along a first axis, and a top side and a bottom side that are opposite each other along a second axis orthogonal to the first axis; and forming a memory region made of a phase change material layer, the memory region being electrically and thermally coupled to the top side of the heater; and forming a conductive element having resistive characteristics, the conductive element extending parallel to the first axis at the first lateral side, the conductive element being adjacent to the first lateral side of the heater and adjacent to the memory region.

[0164] According to one or more embodiments, forming the conductive element includes forming the conductive element to have a first extension at the first lateral side and along the first axis, the first extension being equal to a corresponding first length of the memory region along the first axis at the first lateral side.

[0165] According to one or more embodiments, the conductive element is not formed at the second lateral side.

[0166] According to one or more embodiments, forming the conductive element includes forming the conductive element to have a second extension at the second lateral side and along the first axis, the second extension being less than a corresponding second length of the memory region along the first axis at the second lateral side.

[0167] According to one or more embodiments, the phase change material layer of the memory region can be configured in a crystalline state and an amorphous state, and wherein the resistive characteristics are such that the resistivity of the conductive element is between the resistivity of the phase change material layer in the crystalline state and the resistivity of the phase change material layer in the amorphous state.

[0168] According to one or more embodiments, the conductive element is made of the same material as the heater.

[0169] According to one or more embodiments, the conductive element is made of a material different from that of the heater.

[0170] According to one or more embodiments, the conductive element is integrally formed with the heater and protrudes from the heater with electrical and physical continuity.

[0171] According to one or more embodiments, the method further includes sandwiching the conductive element between a first insulating region and the memory region.

[0172] According to one or more embodiments, the conductive element is formed above the first insulating region so as to physically separate the first insulating region from the memory region; and further includes forming a second insulating region on the second side of the heater that is at least partially in direct contact with the memory region.

[0173] According to one or more embodiments, the heater is formed centered with respect to the memory region.

[0174] According to one or more embodiments, the heater is formed staggered or offset with respect to a symmetry axis of the memory region that is parallel to the second axis.

[0175] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will readily occur to those skilled in the art.

[0176] Finally, based on the functional descriptions provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.

Claims

1. A phase change memory cell, characterized in that, comprising: a heater having a first lateral side and a second lateral side opposite to each other along a first axis, and a top side and a bottom side opposite to each other along a second axis orthogonal to the first axis; and a memory region made of a phase change material layer, the memory region being electrically and thermally coupled to the top side of the heater; and a conductive element having a resistance characteristic, the conductive element extending parallel to the first axis away from the first lateral side; wherein the conductive element is positioned adjacent to the first lateral side and in contact with the memory region.

2. The phase change memory cell according to claim 1, characterized in that, the conductive element has a first extension at the first lateral side and along the first axis, the length of the first extension being equal to the corresponding first length of the memory region along the first axis at the first lateral side.

3. The phase change memory cell according to claim 2, characterized in that, the conductive element extends only at the first lateral side parallel to the first axis, while the conductive element is absent at the second lateral side.

4. The phase change memory cell according to claim 2, characterized in that, the conductive element further extends parallel to the first axis away from the second lateral side with a second extension, the length of the second extension being less than the corresponding second length of the memory region along the first axis at the second lateral side.

5. The phase change memory cell according to claim 1, characterized in that, the phase change material layer of the memory region can be configured to be crystalline and amorphous, and wherein the resistance characteristic is such that the resistivity of the conductive element is between the resistivity of the crystalline state of the phase change material layer and the resistivity of the amorphous state of the phase change material layer.

6. The phase change memory cell according to claim 1, characterized in that, the conductive element is made of the same material as the heater.

7. The phase change memory cell according to claim 1, characterized in that, the conductive element is made of a material different from the heater.

8. The phase change memory cell according to claim 1, characterized in that, the conductive element is integral with the heater and protrudes from the heater with electrical and physical continuity.

9. The phase change memory cell according to claim 1, characterized in that, the conductive element is sandwiched between a first insulating region and the memory region.

10. The phase change memory cell according to claim 9, characterized in that: wherein the first insulating region is physically separated from the memory region by the conductive element; and further comprising a second insulating region on the second lateral side of the heater, the second insulating region being at least partially in direct contact with the memory region.

11. The phase change memory cell according to claim 1, characterized in that, the heater is centered relative to the memory region.

12. The phase change memory cell according to claim 1, characterized in that, The heater is staggered or offset with respect to a symmetry axis parallel to the second axis of the memory region.

13. A memory device, characterized in that, comprising: at least one phase change memory cell according to claim 1.

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