Dead time control circuit for inverter and inverter driving device

Abstract

The utility model relates to a dead time control circuit for an inverter and an inverter driving device comprising the same. The circuit includes: an input pin connected to a controller; the first output pin is connected to a lower bridge arm of the inverter, and the second output pin is connected to an upper bridge arm of the inverter; each trigger comprises a data input end, a clock input end and an output end, the output end of the first trigger is connected to the first output pin, the output end of the second trigger is connected to the second output pin, and the data input end of the second trigger is connected to the input pin; a first inverter; and the first time delay circuit and the second time delay circuit are used for controlling the dead time of a high-side driving signal and a low-side driving signal of the inverter. According to the control circuit provided by the utility model, the dead time can be flexibly adjusted according to different application requirements, and meanwhile, the reliability of the circuit is improved in a low-cost manner.

Description

Technical Field

[0001] The utility model relates to the field of inverter control, and more specifically, to a dead time control circuit for an inverter, and an inverter drive device comprising the control circuit. Background Art

[0002] In the field of power electronics, inverters, as a key power conversion device, undertake the crucial task of converting direct current (DC) into alternating current (AC) and are widely used in electric vehicles. The inverter's control core relies on precisely controlling the switching of the three-phase power modules using the MCU (Microcontroller Unit) to generate the desired AC waveform. To ensure safe operation of the power modules, simultaneous conduction of the upper and lower bridge power devices in each phase must be avoided. This is because if both the upper and lower bridge arms are conducting simultaneously, the positive and negative poles of the DC power supply will be directly short-circuited, generating a significant short-circuit current that can instantly damage the power devices in the inverter.

[0003] Therefore, in order to avoid this short circuit risk, an interval time, namely the dead time, must be introduced between the upper and lower arms of the inverter to ensure that at any time, the power devices in the upper and lower arms of the same phase are not in the on state at the same time. Utility Model Content

[0004] The utility model aims to propose a dead time generation scheme with simple structure, high cost-effectiveness and reliability, thereby improving the overall performance and safety of the inverter control system.

[0005] According to a first aspect of the present invention, a dead time control circuit for an inverter is provided. The inverter includes an upper bridge arm and a lower bridge arm. The upper bridge arm and the lower bridge arm are turned on and off by means of a PWM signal output by a controller. The circuit includes:

[0006] an input pin connected to the controller to receive a PWM signal therefrom;

[0007] First and second output pins, wherein the first output pin is connected to the lower bridge arm of the inverter to provide a low-side drive signal thereto, and the second output pin is connected to the upper bridge arm to provide a high-side drive signal thereto;

[0008] a first and a second flip-flop, each flip-flop comprising a data input terminal, a clock input terminal, and an output terminal, the output terminal of the first flip-flop being connected to the first output pin, the output terminal of the second flip-flop being connected to the second output pin, and the data input terminal of the second flip-flop being connected to the input pin;

[0009] a first inverter, wherein an input terminal of the first inverter is connected to the input pin of the circuit, and an output terminal of the first inverter is connected to a data input terminal of the first flip-flop; and

[0010] The first and second delay circuits are used to control the dead time of the high-side drive signal and the low-side drive signal of the inverter, wherein the first delay circuit is arranged between the output end of the first trigger and the clock input end of the second trigger, and the second delay circuit is arranged between the output end of the second trigger and the clock input end of the first trigger.

[0011] Advantageously, the first delay circuit comprises a first RC charging circuit for delaying the high-side driving signal output by the second flip-flop according to the output signal of the first flip-flop.

[0012] Advantageously, the first delay circuit includes a second inverter, a first capacitor and a first resistor, wherein the input end of the second inverter is connected to the output end of the first trigger, the output end of the second inverter is connected to the first end of the first resistor, the second end of the first resistor is connected to the clock input end of the second trigger, one end of the first capacitor is connected to the second end of the first resistor, and the other end of the first capacitor is grounded.

[0013] Advantageously, the second delay circuit includes a second RC charging circuit, configured to delay the low-side driving signal output by the first flip-flop according to the output signal of the second flip-flop.

[0014] Advantageously, the second delay circuit includes a third inverter, a second capacitor and a second resistor, wherein the input end of the third inverter is connected to the output end of the second trigger, the output end of the third inverter is connected to the first end of the second resistor, the second end of the second resistor is connected to the clock input end of the first trigger, one end of the second capacitor is connected to the second end of the second resistor, and the other end of the second capacitor is grounded.

[0015] Advantageously, the dead time of the high-side drive signal is set by adjusting the capacitance value of the first capacitor and the resistance value of the first resistor, and the dead time of the low-side drive signal is set by adjusting the capacitance value of the second capacitor and the resistance value of the second resistor, so as to match different inverter products.

[0016] Advantageously, the dead time of the high-side driving signal and the dead time of the low-side driving signal are set to be the same.

[0017] Advantageously, the first and second flip-flops each comprise a reset input terminal, wherein the reset input terminal of the first flip-flop is connected to the output terminal of the first inverter, and the reset input terminal of the second flip-flop is connected to the input pin of the circuit.

[0018] According to the second aspect of the present invention, an inverter drive device is also proposed, which includes a controller for outputting PWM signals for controlling the on and off of the upper bridge arm and the lower bridge arm of the inverter, and the device also includes the dead time control circuit as described above.

[0019] The dead-time control circuit of this utility model utilizes a combination of a trigger and an RC charging circuit to achieve precise control of the PWM signal. In the circuit's structural design, the PWM signal provided by the control unit is split into two paths, generating the dead-time required for the high-side drive signal and the low-side drive signal, respectively. This design cleverly utilizes the natural delay characteristics of the RC charging circuit, avoiding dependence on the MCU and reducing system risks caused by MCU failure. Furthermore, by matching the resistance and capacitance parameters in the RC charging circuit, the control accuracy and stability of the dead-time can be further ensured. This circuit's structural design significantly reduces the manufacturing and maintenance costs of the inverter drive device and improves the circuit's reliability and ease of use. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] By incorporation into this document of the accompanying drawings and Figure 1 With reference to the specific embodiments used to illustrate certain principles of the present invention, other features and advantages of the method of the present invention will become clear or be described in more detail.

[0021] Figure 1 The figure shows an internal structure diagram of a dead time control circuit for an inverter according to an exemplary embodiment of the present invention.

[0022] Figure 2 Shows the use of Figure 1 Waveform diagram of the high-side and low-side drive signals generated by the dead time control circuit in FIG. DETAILED DESCRIPTION

[0023] The dead time control circuit for an inverter according to the present invention will be described below by way of example with reference to the accompanying drawings. In the following description, numerous specific details are set forth to provide those skilled in the art with a more comprehensive understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be implemented without some of these specific details. Rather, the present invention may be implemented using any combination of the following features and elements, regardless of whether they relate to different embodiments. Therefore, the following aspects, features, embodiments, and advantages are provided for illustrative purposes only and should not be construed as elements or limitations of the claims.

[0024] Currently, there are two main methods for generating dead time in the control process of the upper and lower bridge arms of inverters: one is to set the dead time internally within the inverter control unit; the other is to rely on external circuitry to generate the dead time. The method of setting the dead time internally within the MCU relies on software programming to control the output of the PWM signal. This method offers the advantage of high flexibility, allowing the dead time length to be adjusted as needed. However, this also means that the stability and reliability of the MCU are crucial to the safety of the entire system. A malfunction of the MCU may cause the dead time control to fail, increasing system risk. On the other hand, while external circuitry can reduce reliance on the MCU to a certain extent, these circuits are often complex and costly, and may be affected by external environmental factors, making it difficult to guarantee the accuracy and stability of the dead time. Therefore, how to ensure the accuracy and stability of dead time control while reducing system cost and complexity is a challenge that needs to be addressed in current inverter control technology.

[0025] In response to the defects in existing inverter dead time generation schemes, the utility model proposes a new dead time control circuit for an inverter, which aims to generate dead time in a simpler, cost-effective and reliable manner, thereby improving the overall performance and safety of the inverter control system.

[0026] Figure 1 The internal structure of the dead time control circuit for an inverter according to an exemplary embodiment of the present invention is shown. The circuit is designed to accurately control the switching action of the upper bridge arm HS and the lower bridge arm LS in the inverter to prevent the power devices in the upper and lower bridge arms from being turned on at the same time and damaging the circuit. Figure 1 To introduce the internal structure and working principle of the control circuit in detail.

[0027] Reference Figure 1 The dead-time control circuit may have one input pin and two output pins. The input pin may be connected to an external controller, such as an inverter control unit, to receive a PWM signal from the external controller. This PWM signal is key to the inverter control process, determining the switching states of the upper and lower bridge arms. The first of the two output pins is responsible for providing a low-side drive signal to the lower bridge arm LS of the inverter, while the second output pin is responsible for providing a high-side drive signal to the upper bridge arm HS of the inverter.

[0028] The core structure of the control circuit includes two triggers T1 and T2, an inverter U1 and two delay circuits 10 and 20 ( Figure 1As shown in the dotted box in the figure). Each of the triggers T1 and T2 includes three key terminals: data input terminal D, clock input terminal CLK, and output terminal Q. In addition, they may also include a reset input terminal CLR and a reverse input terminal. The D terminal receives the input data signal—here, a PWM signal from an external controller. This signal is typically transmitted to the output of the flip-flop under the control of a clock signal. The CLK terminal receives the clock signal, and the corresponding flip-flop synchronizes data updates and state transitions based on the rising or falling edge of the clock signal. The Q output is a logical output of the flip-flop's internal state, providing the current state of the flip-flop. For example, in a flip-flop, the Q terminal typically updates its output based on the input state of the D terminal on the rising (or falling) edge of the clock signal. The CLR terminal is used to clear or reset the flip-flop's state. The terminal is used to provide the inverted signal of the Q terminal, that is, when the Q terminal is high, The terminal outputs a low level, and vice versa.

[0029] exist Figure 1 In this embodiment, the output of the first flip-flop T1 is connected to the first output pin for outputting and controlling the low-side drive signal; the output of the second flip-flop T2 is connected to the second output pin for outputting and controlling the high-side drive signal. The data input of the second flip-flop T2 is directly connected to the input pin to receive the PWM signal. The data input of the first flip-flop T1 is connected to the input pin via an inverter U1, which can invert the PWM input signal.

[0030] The two delay circuits 10 and 20 are the core of the dead-time control circuit. They are respectively arranged between the output of the first flip-flop T1 and the clock input of the second flip-flop T2, and between the output of the second flip-flop T2 and the clock input of the first flip-flop T1. These delay circuits function to introduce dead time, ensuring that the upper and lower bridge arms are never simultaneously conductive, thereby preventing shoot-through damage to power devices.

[0031] Specifically, the first delay circuit 10 controls the timing of the high-side drive signal generation by introducing a delay between the output of the first flip-flop T1 and the clock input of the second flip-flop T2. Similarly, the second delay circuit 20 controls the timing of the low-side drive signal generation by introducing a delay between the output of the second flip-flop T2 and the clock input of the first flip-flop T1. By precisely controlling these two delay circuits, the inverter dead time can be precisely controlled.

[0032] The delay circuits 10 and 20 can be respectively composed of RC charging circuits, which can use the output signal of the first trigger T1 to delay the high-side drive signal output by the second trigger T2, or delay the low-side drive signal output by the first trigger T1 according to the output signal of the second trigger T2.

[0033] The first delay circuit 10 is composed of a second inverter U2, a first capacitor C1, and a first resistor R1. The second inverter U2 receives the output signal of the first trigger T1, inverts it, and then passes it to the first end of the first resistor R1. As the first capacitor C1 is charged through the first resistor R1, a delay occurs when the signal is passed to the clock input of the second trigger T2. This delay is the required dead time. The dead time is determined by the charging time of the charging circuit formed by the first capacitor C1 and the first resistor R1. It is understandable that in order to match different inverter products, the length of the dead time can be precisely controlled by selecting the appropriate C1 capacitance value and R1 resistance value to ensure the safe operation of the corresponding inverter product.

[0034] The second delay circuit 20 is composed of a third inverter U3, a second capacitor C2, and a second resistor R2. The third inverter U3 inverts the output signal of the second trigger T2 and transmits it to the first end of the second resistor R2. The second capacitor C2 is charged through the second resistor R2, generating a delay, thereby controlling the output timing of the low-side drive signal. The delay time of the second delay circuit 20 is determined by the charging time of the charging circuit composed of the second capacitor C2 and the second resistor R2. This design allows the second delay circuit 20 to achieve precise dead time control similar to the first delay circuit 10. It is also understandable that in order to match different inverter products, the dead time of the low-side drive signal can be precisely controlled by selecting appropriate C2 capacitance value and R2 resistance value to ensure the safe operation of the corresponding inverter product.

[0035] For example, by properly adjusting the resistance values ​​of R1 and R2 and the capacitance values ​​of C1 and C2, the dead time D1 and D2 of the high and low driving signals can be set to be the same.

[0036] The first flip-flop T1 and the second flip-flop T2 can each include a reset input terminal CLR. The reset input terminal of T1 is connected to the output terminal of the first inverter U1, while the reset input terminal of T2 is connected to the input pin of the circuit. This configuration ensures that the state of the flip-flop can be quickly reset when needed, improving the flexibility and reliability of the circuit. Figure 1 The structural diagram is used to describe the working principle of the control circuit.

[0037] When the control circuit's input pin receives the PWM signal from the inverter's control unit, the signal is split into two paths: one path enters inverter U1 for inversion, and the other path directly enters the D and CLR terminals of the second flip-flop T2. The inverted output signal from U1 then enters the D and CLR terminals of flip-flop T1, while the PR terminal receives a pull-up signal to ensure proper operation of the flip-flop. T1's Q-terminal output serves as the HS drive signal and is provided to the inverter's upper arm. This signal, also inverted by inverter U2, is used to charge capacitor C1, forming the first delay link in the circuit.

[0038] The charging process of capacitor C1 is controlled by resistor R1, while the other end of C1 is connected to the CLK terminal of T1. C1 and capacitor C2 are grounded together. The charging process of capacitor C2 is similar. The signal output from the Q terminal of T2 is inverted by inverter U3 and then charged through resistor R2. C2 is also connected to the CLK terminal of T1, forming a second delay link. In this circuit design, R1 is selected to be equal to R2, and C1 is selected to be equal to C2 to ensure that the generated dead times D1 and D2 have the same length, thereby achieving symmetrical control of the upper and lower bridge arms of the inverter.

[0039] Figure 2 Shows the use of Figure 1 The waveform diagram of the high and low side drive signals generated by the dead time control circuit in FIG. Figure 2 As can be seen in the figure, the PWM signal output by the inverter's control unit is a regular duty cycle signal. When the PWM signal level changes, such as a rising edge, T2's input receives a high level, while T1's input receives a low level due to the inversion of U1. According to the flip-flop's truth table, T1's Q terminal outputs a low level, which causes U2's output to invert to a high level, thereby starting to charge C1. After a set delay D1, T2 receives the rising edge signal and triggers, causing the PWM signal to invert to a rising edge after a delay of D1 at the HS terminal. This process ensures a precise dead time D1 before the HS terminal outputs the control signal, preventing the upper and lower bridge arms of the inverter from conducting simultaneously.

[0040] Similarly, for the falling edge of the PWM signal, delay D2 can be obtained at the LS terminal in a similar manner. Therefore, this circuit ensures stable operation under varying PWM signal variations. By adjusting the resistance and capacitance values ​​in the charging circuit, the dead time of the power device can be flexibly adjusted to suit different inverter control requirements.

[0041] The dead-time control circuit of this utility model utilizes a combination of a DQ trigger and an RC charging circuit to achieve precise control of the PWM signal. In the circuit's structural design, the PWM signal provided by the control unit is split into two paths, generating the dead-time required for the high-side drive signal and the low-side drive signal, respectively. This design cleverly utilizes the natural delay characteristics of the RC charging circuit, avoiding dependence on the MCU and reducing system risks caused by MCU failure. Furthermore, by matching the resistance and capacitance parameters in the RC charging circuit, the control accuracy and stability of the dead-time can be further ensured. This circuit's structural design significantly reduces the manufacturing and maintenance costs of the inverter drive device and improves the circuit's reliability and ease of use.

[0042] This utility model also proposes an inverter driver designed to precisely control the switching operation of the upper bridge arm HS and lower bridge arm LS of an inverter. Specifically, the device may include a controller for providing a PWM signal and the dead-time control circuit described above. Through the coordinated operation of the PWM signal controller and the dead-time control circuit, the inverter driver achieves precise control of the switching operation of the upper and lower bridge arms of the inverter, thereby improving the performance and reliability of the inverter.

[0043] Although the present invention has been disclosed above with reference to preferred embodiments, the present invention is not limited thereto. Any changes and modifications made without departing from the spirit and scope of the present invention shall be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims.

Claims

1. A dead time control circuit for an inverter, wherein the inverter comprises an upper bridge arm (HS) and a lower bridge arm (LS), wherein the upper bridge arm and the lower bridge arm are turned on and off by means of a PWM signal output by a controller, wherein: The dead time control circuit comprises: an input pin connected to the controller to receive a PWM signal therefrom; First and second output pins, wherein the first output pin is connected to the lower bridge arm (LS) of the inverter to provide a low-side drive signal thereto, and the second output pin is connected to the upper bridge arm (HS) to provide a high-side drive signal thereto; First and second flip-flops (T1, T2), each flip-flop comprising a data input terminal (D), a clock input terminal (CLK), and an output terminal (Q), the output terminal of the first flip-flop (T1) being connected to the first output pin, the output terminal of the second flip-flop (T2) being connected to the second output pin, and the data input terminal of the second flip-flop (T2) being connected to the input pin; a first inverter (U1), wherein an input terminal of the first inverter is connected to the input pin of the dead time control circuit, and an output terminal of the first inverter is connected to a data input terminal of the first flip-flop (T1); and First and second delay circuits (10, 20) for controlling the dead time of a high-side drive signal and a low-side drive signal of the inverter, wherein the first delay circuit (10) is arranged between the output end of a first trigger (T1) and the clock input end of a second trigger (T2), and the second delay circuit (20) is arranged between the output end of the second trigger (T2) and the clock input end of the first trigger (T1).

2. The dead time control circuit according to claim 1, wherein: The first delay circuit (10) comprises a first RC charging circuit, which is used for delaying a high-side driving signal output by a second trigger (T2) according to an output signal of a first trigger (T1).

3. The dead time control circuit according to claim 2, wherein: The first delay circuit (10) comprises a second inverter (U2), a first capacitor (C1) and a first resistor (R1), wherein the input end of the second inverter (U2) is connected to the output end of the first trigger (T1), the output end of the second inverter (U2) is connected to the first end of the first resistor (R1), the second end of the first resistor (R1) is connected to the clock input end of the second trigger (T2), one end of the first capacitor (C1) is connected to the second end of the first resistor (R1), and the other end of the first capacitor (C1) is grounded.

4. The dead time control circuit according to claim 3, wherein: The second delay circuit (20) comprises a second RC charging circuit, which is used for delaying the low-side driving signal output by the first trigger (T1) according to the output signal of the second trigger (T2).

5. The dead time control circuit according to claim 4, characterized in that: The second delay circuit (20) includes a third inverter (U3), a second capacitor (C2) and a second resistor (R2), wherein the input end of the third inverter (U3) is connected to the output end of the second trigger (T2), the output end of the third inverter (U3) is connected to the first end of the second resistor (R2), the second end of the second resistor (R2) is connected to the clock input end of the first trigger (T1), one end of the second capacitor (C2) is connected to the second end of the second resistor (R2), and the other end of the second capacitor (C2) is grounded.

6. The dead time control circuit according to claim 5, characterized in that: The dead time of the high-side drive signal is set by adjusting the capacitance value of the first capacitor (C1) and the resistance value of the first resistor (R1), and the dead time of the low-side drive signal is set by adjusting the capacitance value of the second capacitor (C2) and the resistance value of the second resistor (R2), so as to match different inverter products.

7. The dead time control circuit according to claim 5, wherein: The dead time of the high-side driving signal and the dead time of the low-side driving signal are set to be the same.

8. The dead time control circuit according to any one of claims 1 to 7, characterized in that: The first and second flip-flops (T1, T2) respectively include a reset input terminal (CLR), the reset input terminal of the first flip-flop (T1) is connected to the output terminal of the first inverter (U1), and the reset input terminal of the second flip-flop (T2) is connected to the input pin of the dead time control circuit.

9. An inverter drive device, comprising a controller for outputting PWM signals for controlling the on / off switching of an upper bridge arm (HS) and a lower bridge arm (LS) of an inverter, characterized in that: The inverter drive device further includes a dead time control circuit according to any one of claims 1 to 8.

Images