Semiconductor evaluation equipment and semiconductor evaluation methods

Abstract

Semiconductor evaluation device (1) evaluating a plurality of vertical semiconductor devices (52) provided in a semiconductor wafer (51), wherein the vertical semiconductor devices each comprise a front electrode (52a) and a back electrode (52b) provided on a front and a back of the semiconductor wafer respectively, wherein the semiconductor evaluation device comprises: a semiconductor wafer holding area (6) that holds the semiconductor wafer; a front probe (11) which is electrically connected to the front electrode in the case of contacting the front electrode on the semiconductor wafer which is held by the semiconductor wafer holding area; a backside interconnection area (6, 14a, 34) which is electrically connected to the backside electrode in a case of contacting the backside electrode on the semiconductor wafer which is held by the semiconductor wafer holding area; a backside potential exit area (18) comprising an end area located on one side of the back side of the semiconductor wafer, which is held by the semiconductor wafer holding area, and electrically connected to the backside interconnect area, and comprising the other end area located on one side of the front side of the semiconductor wafer, which is held by the semiconductor wafer holding area, and electrically connected to the first end area; and an evaluation unit (27) which conducts current through the front electrode and the back electrode via the front probe or the other end region of the back potential exit region to evaluate electrical properties of the vertical semiconductor devices, wherein the semiconductor wafer and the semiconductor wafer holding region holding the semiconductor wafer, or the front probe, back interconnect region and back potential exit region are movable in the direction of a plane of the semiconductor wafer, and In a case where the semiconductor wafer and the semiconductor wafer holding section holding the semiconductor wafer, or the front probe, rear interconnect area and rear potential exit area are moved in the direction of the plane, the semiconductor wafer or a portion of the rear potential exit area located in one direction of the plane from the semiconductor wafer is fixed near the outside of one moving section of the other.

Description

BACKGROUND OF THE INVENTIONField of the invention

[0001] The present invention relates to a semiconductor evaluation apparatus that evaluates a plurality of vertical semiconductor devices provided in a semiconductor wafer, and a semiconductor evaluation method therefor. Description of the state of the art

[0002] A method of bringing a mounting surface of an object to be measured into contact with a clamping layer and fixing the mounting surface thereto by vacuum adsorption is conventionally used when measuring (evaluating) electrical characteristics of the object to be measured, such as a semiconductor wafer and a semiconductor chip. In an evaluation device that evaluates semiconductor devices having a vertical structure configured to conduct current in directions out of a plane of the semiconductor device, the clamping layer that fixes the mounting surface of the semiconductor wafer is used as one of measuring electrodes. In such an evaluation device, a cable connected to the clamping layer is connected to an evaluation unit, and the cable has a length of its own that is longer than a length for routing.The longer cable causes a larger parasitic inductance in a measurement path, which leads to the problem of deteriorating the accuracy of evaluation of the vertical semiconductor devices.

[0003] Meanwhile, for example, in JP 2013 - 118 320 A, a wafer inspection device was developed that shortened the measurement path and reduced parasitic inductance. The wafer inspection device includes a probe contact region in addition to a wafer holding area. For example, in JP 2013 - 32 938 A, a device was developed that places a contact plate near an object to be measured, allowing resistance in a measurement line to be reduced.

[0004] However, in the conventional technology, regions (a clamping layer and a probe contact region in JP 2013 - 118 320 A) at high voltage have large areas and are close to each other, which leads to a problem that ensuring insulation becomes more difficult as the applied voltage during evaluation increases.

[0005] US 9 069 008 B2 discloses a test apparatus comprising front-side electrode probes, back-side electrode probes, and a chuck table. The front-side electrode probes and back-side electrode probes are formed on the upper surface of the chuck table, and a probe contact area electrically extends to a wafer holding area and the front-side electrode probes and back-side probes. The electrodes are arranged so that a gap remains between them in the horizontal direction, so that the back-side electrode probes move relatively within the probe contact area, while the front-side electrode probes are moved relatively within the wafer to be tested by the movement of the chuck table.

[0006] US 2013 / 0 141 132 A1 discloses a test apparatus comprising front-side electrode probes, back-side electrode probes, and a chuck stage, wherein the front-side electrode probes and the back-side electrode probes are formed on the upper surface of the chuck and the probe contact surface is electrically continuous with the wafer holding surface, and the front-side electrode probes and the back-side electrode probes are arranged to leave a gap therebetween in the horizontal direction such that the back-side electrode probes move relatively within the probe contact surface when the front-side electrode probes are moved relatively within the wafer to be tested by the movement of the chuck stage.

[0007] US 8,779,792 B2 discloses a tester and a semiconductor device tester including the tester. The tester includes a test head configured to transmit electronic signals to a probe card. The tester also has a leveling unit attached to the tester head. The leveling unit is configured to apply a load to the probe card to maintain a level state of the probe card. Summary of the invention

[0008] It is an object of the present invention to provide a semiconductor evaluation device capable of ensuring isolation in an evaluation of vertical semiconductor devices and a semiconductor evaluation method therefor.

[0009] This object is achieved by the features of claim 1 and claim 15, respectively. The subclaims disclose preferred developments of the invention.

[0010] A semiconductor evaluation device according to the present invention evaluates a plurality of vertical semiconductor devices provided in a semiconductor wafer. The vertical semiconductor devices each detect a front-side electrode and a back-side electrode provided on a front side and a back side of the semiconductor wafer, respectively. The semiconductor evaluation device includes: a semiconductor wafer holding portion that holds the semiconductor wafer; a front-side probe that is electrically connected to the front-side electrode in a case of contacting the front-side electrode on the semiconductor wafer held by the semiconductor wafer holding portion; and a back-side connection portion that is electrically connected to the back-side electrode in a case of contacting the back-side electrode on the semiconductor wafer held by the semiconductor wafer holding portion.The semiconductor evaluation device includes: a backside potential-pulling region having one end portion located on one side of the backside of the semiconductor wafer held by the semiconductor wafer holding region and electrically connected to the backside connection region, and having the other end portion located on one side of the frontside of the semiconductor wafer held by the semiconductor wafer holding region and electrically connected to the one end portion; and an evaluation unit that passes current through the frontside electrode and the backside electrode via the frontside probe and the other end portion of the backside potential-pulling region, respectively, to evaluate electrical characteristics of the vertical semiconductor devices.The semiconductor wafer and the semiconductor wafer holding portion that holds the semiconductor wafer, or the front-side probe, the back-side connection portion, and the back-side potential-releasing portion are movable in the direction of a plane of the semiconductor wafer. In a case where the semiconductor wafer and the semiconductor wafer holding portion that holds the semiconductor wafer, or the front-side probe, the back-side connection portion, and the back-side potential-releasing portion are moved in the direction of the plane, the semiconductor wafer or a portion of the back-side potential-releasing portion located in the direction of the plane of the semiconductor wafer is fixed near the outside of one moving region of the other.

[0011] A high potential area can be reduced more than that of the prior art, while easily ensuring isolation in the evaluation of vertical semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Further details, features, and advantages of the present invention will become apparent from the following description of exemplary embodiments with reference to the drawings, in which: Fig. 1 and Fig. 2 are cross-sectional views illustrating a schematic configuration of a semiconductor evaluation device according to a first preferred embodiment; Fig. 3A, Fig. 3B and Fig. 3C are side views for describing a front probe according to the first preferred embodiment; Fig. 4 is a cross-sectional view illustrating a schematic configuration of the semiconductor evaluation device according to the first preferred embodiment; Fig. 5 is a cross-sectional view illustrating a schematic configuration of a semiconductor evaluation device according to a second modification; Fig. 6 is a plan view illustrating a schematic configuration of an electrode region provided on a film according to a third modification; Fig. 7 is a plan view illustrating a schematic configuration of electrode regions provided on a film according to a fourth modification; Fig. 8 is a side view illustrating a schematic configuration of a layer according to a fifth modification; Fig. 9 is a cross-sectional view illustrating a schematic configuration of a semiconductor evaluation device according to a sixth modification; Fig. 10 is a cross-sectional view illustrating a schematic configuration of a semiconductor evaluation apparatus according to a seventh modification; Fig. 11 is a cross-sectional view illustrating a schematic configuration of a semiconductor evaluation device according to an eighth modification; Fig. 12 is a cross-sectional view illustrating a schematic configuration of a semiconductor evaluation device according to a ninth modification; and Fig. 13 and Fig. 14 are cross-sectional views illustrating schematic configurations of a semiconductor evaluation device according to a second preferred embodiment. DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Preferred Embodiment>

[0013] Fig. 1 and Fig. 2 are cross-sectional views illustrating a schematic configuration of a semiconductor evaluation device 1 according to a first preferred embodiment of the present invention. Fig. 1 and Fig. 2 show different operating states of the semiconductor evaluation device 1. In addition, Fig. 2 also shows an enlarged view of an area in a circle.

[0014] The semiconductor evaluation device 1 is a device that evaluates a plurality of vertical semiconductor devices 52 provided in a semiconductor wafer 51, that is, semiconductor devices such as a transistor and a diode with a vertical structure that are configured to conduct a large current in out-of-plane directions (in the vertical direction, Z direction). As shown in Fig. As shown in Figure 2, the vertical semiconductor devices 52 subject to evaluation include front-side electrodes 52a and a back-side electrode 52b provided on a front side (+Z side) and a back side (-Z side) of the semiconductor wafer 51, respectively. Furthermore, the front-side electrodes 52a are provided separately for each of the plurality of vertical semiconductor devices 52, while the back-side electrode 52b is normally not separated and is integrated into the wafer layer.

[0015] For simplicity, Fig. 2 shows the state where three of the vertical semiconductor devices 52 are provided in the semiconductor wafer 51, however, two, four or more of the vertical semiconductor devices 52 may be provided. Furthermore, for the sake of simplicity, the vertical semiconductor devices 52, the front-side electrodes 52a and the back-side electrode 52b may be Fig. 2 following drawings are omitted.

[0016] The semiconductor evaluation device 1 includes a semiconductor wafer holding section 6, a movable arm 7, a front-side probe 11, a layer 14, a back-side potential-releasing section 18, a probe substrate 21, probe connection sections 22a, 22b, a test head 23, a signal line 26, and an evaluation control unit 27 that collectively controls them. The back-side potential-releasing section 18 includes a wiring section 15, an extension electrode 16, and an extension electrode front-side probe 17.

[0017] The semiconductor wafer holding portion 6 holds the semiconductor wafer 51. In the first preferred embodiment, the semiconductor wafer holding portion 6 is in contact with all or part of a peripheral portion of the semiconductor wafer 51 to hold the semiconductor wafer 51. In addition, Fig. 1, two parts of the semiconductor wafer holding portion 6 are arranged separately at both end portions of the semiconductor wafer 51, but the two parts are connected at least at the near side or the far side.

[0018] As in Fig. 1 and Fig. As shown in Figure 2, the movable arm 7 moves the semiconductor wafer holding portion 6 and the semiconductor wafer 51 held by the semiconductor wafer holding portion 6, primarily in the in-plane directions (X, Y directions) of the semiconductor wafer 51. In other words, in the first preferred embodiment, the semiconductor wafer 51 and the semiconductor wafer holding portion 6 holding the semiconductor wafer 51 are movable in the in-plane directions of the semiconductor wafer 51 with respect to the front-side probe 11, the layer 14 (the electrode region 14a), and the back-side potential lead-out portion 18. While the semiconductor wafer 51 or the like is moved as described above, the vertical semiconductor devices 52 are brought into contact with the front-side probe 11 or the like at the time of evaluation.

[0019] Note that two or more of the vertical semiconductor devices 52 may be brought into contact with the front-side probe 11 or the like for evaluation, as described below in a modification. Furthermore, a plurality of movable arms 7 may stably hold and move the semiconductor wafer holding portion 6 instead of the single movable arm 7 that holds and moves the semiconductor wafer holding portion 6.

[0020] The front probe 11 is an electrode for connecting the front electrodes 52a and the outside (the probe connection area 22a) in the evaluation of the vertical semiconductor devices 52. The front probe 11 is electrically connected to the front electrodes 52a in a case of contacting the front electrodes 52a on the semiconductor wafer 51 held by the semiconductor wafer holding area 6. The front probe 11 is mechanically connected to the probe substrate 21, while it is electrically connected to the probe connection area 22a regardless of the contact with the front electrodes 52a. In addition, Fig. 1 shows only one front-side probe 11 for the sake of simplicity, but a plurality of front-side probes 11 may be provided if a relatively large current (e.g., 5A or more) is supplied.

[0021] Layer 14 is a small clamping layer, sufficiently small compared to the conventional one on which the entire semiconductor wafer is mounted. For example, when layer 14 evaluates the vertical semiconductor devices 52 individually, layer 14 corresponds to a size (chip size) of one vertical semiconductor device 52. Layer 14 constructed as described above can suppress replacement costs due to breakage, surface roughness, or the like. Furthermore, layer 14 can reduce an increase in current density and suppress heat generation compared to a case where the backside probe is directly in contact with the backside electrode 52b of the vertical semiconductor devices.

[0022] The electrode region 14a provided on the layer 14 is an electrode for connecting the backside electrode 52b and the outside (the probe connection region 22b) in the evaluation of the vertical semiconductor devices 52. The electrode region 14a is provided on the front side of the layer 14, wherein the front side is mechanically and electrically in contact with the backside of the semiconductor wafer 51. For the sake of simplicity, the electrode region 14a may also be omitted when illustrating the devices shown on Fig. 2 following drawings are omitted.

[0023] In the first preferred embodiment, the electrode region 14a having the configuration as described above is used as a back-side connection region, which is electrically connected to the back-side electrode 52b in a case of contacting the back-side electrode 52b on the semiconductor wafer 51 held by the semiconductor wafer holding region 6. The electrode region 14a is electrically connected to the extension electrode 16 through the wiring region 15 regardless of the contact with the back-side electrode 52b.

[0024] The main body component of the layer 14 is formed of a metal such as nickel, and a metal such as copper is used as the material for the electrode region 14a. Note that this is not limiting, and the electrode region 14a may be coated with other elements such as gold, palladium, tantalum, and platinum from the viewpoint of improving the conductivity of the electrode region 14a, improving its durability, or the like.

[0025] The back-side potential-leading region 18 has one end portion located on one side of the back side of the semiconductor wafer 51 held by the semiconductor wafer holding region 6, and the other end portion located on one side of the front side of the semiconductor wafer 51 held by the semiconductor wafer holding region 6. In the first preferred embodiment, the wiring region 15 serves as one end portion of the back-side potential-leading region 18, while the extension electrode front-side probe 17 serves as the other end portion of the back-side potential-leading region 18. One end portion of the back-side potential-leading region 18 is electrically connected to the electrode portion 14a of the layer 14, while the other end portion of the back-side potential-leading region 18 is electrically connected to the one end portion of the back-side potential-leading region 18 through the wiring region 15 or the like.

[0026] Next, the structural components (the wiring section 15, the extension electrode 16, and the extension electrode front probe 17) are described respectively.

[0027] The wiring portion 15 electrically connects the electrode portion 14a of the layer 14 and the extension electrode 16. A conductive material such as a cable or a metal plate is used for the wiring portion 15, and is described herein assuming that the metal plate hardly changes in shape and is used to easily ensure a cross-sectional area.

[0028] The extension electrode 16 serves as a portion of the backside potential lead-out region 18, excluding the aforementioned one end portion, and is electrically connected to the one end portion. In the first preferred embodiment, the extension electrode 16 is electrically connected to the electrode portion 14a of the layer 14 through the wiring portion 15, as an example. The same material as that of the layer 14 is used, for example, as the material for the extension electrode 16.

[0029] The extension electrode front probe 17 is mechanically connected to the probe substrate 21, and is electrically connected to the probe connection portion 22b. In addition, Fig. 1 and Fig. 2 shows only one extension electrode front side probe 17 for the sake of simplicity, however, a plurality of extension electrode front side probes 17 may be provided when the relatively large current (e.g., 5A or more) is supplied.

[0030] In the first preferred embodiment, the extension electrode 16 and the extension electrode front-side probe 17 are configured to allow contact with each other and separate from each other. In a case where the extension electrode 16 and the extension electrode front-side probe 17 are in contact with each other, the electrode portion 14a and the extension electrode front-side probe 17 are electrically connected. In a case where the extension electrode 16 and the extension electrode front-side probe 17 are separated from each other, the electrical connection between the electrode portion 14a and the extension electrode front-side probe 17 is severed. Furthermore, an electrode portion similar to the electrode portion 14a may be provided on the front side of the extension electrode 16, the front side being in contact with the extension electrode front-side probe 17.

[0031] In a case where, in the first preferred embodiment, the semiconductor wafer 51 and the semiconductor wafer holding portion 6 holding the semiconductor wafer 51 are arranged in the directions of a plane of the semiconductor wafer 51 as shown in Fig. 1 and Fig. 2, a portion of the back-side potential-discharge region 18 located in the in-plane direction of the semiconductor wafer 51 is fixed near the outside of the moving region of the semiconductor wafer 51. In other words, the back-side potential-discharge region 18 is fixed in a state where the portion of the back-side potential-discharge region 18 corresponding to the in-plane direction of the semiconductor wafer 51 is located near the end portion of the moving region of the semiconductor wafer 51. With this configuration, the wiring portion 15 can be made as short as possible, and thereby the parasitic inductance can be reduced.

[0032] The probe substrate 21, which is an insulating substrate, fixes the front-side probe 11 and the extension electrode front-side probe 17. The probe substrate 21 is a member for individually and electrically connecting the front-side electrodes 52a of the vertical semiconductor devices 52 and the back-side electrode 52b thereof, respectively, to the probe connection portions 22a, 22b through the probes (the front-side probe 11 and the extension electrode front-side probe 17).

[0033] The probe substrate 21 is manufactured according to a type of semiconductor wafer 51 or vertical semiconductor devices 52. By replacing the probe substrate 21 with another probe substrate 21, the front-side probe 11 and the extension electrode front-side probe 17 are also replaceable with another front-side probe 11 and another extension electrode front-side probe 17, respectively. With this configuration, replacing the probe substrate 21 (the probe card) can change a contact position in the vertical semiconductor devices 52 that are brought into contact with the front-side probe 11. This can make it suitable for different sizes of the semiconductor wafer 51 or different sizes, numbers, or contact positions of the vertical semiconductor devices 52. Furthermore, each probe is easily replaceable at the time of breakage.

[0034] The probe connection portions 22a, 22b, which are, for example, terminals, are configured for freely attaching and detaching the test head 23 to or from the probe substrate 21.

[0035] The test head 23 is electrically connected to the front-side probe 11 through the probe connection portion 22a in a case where the probe substrate 21 is attached to the test head 23, and is electrically connected to the extension electrode front-side probe 17 through the probe connection portion 22b.

[0036] In addition, the test head 23 includes a section that supplies a voltage and a current to the vertical semiconductor devices 52, a section that measures the voltage and current, and a mechanism for selectively switching their use. The test head 23 is electrically connected to the evaluation control unit 27 downstream of the test head 23 through the signal line 26 and is arranged near the vertical semiconductor devices 52 in addition to the evaluation control unit 27.

[0037] The evaluation control unit 27, which constitutes the evaluation unit, controls the test head 23 to pass current through the front-side electrodes 52a via the front-side probe 11 and to pass current through the back-side electrode 52b via the extension electrode front-side probe 17, which serves as the other end portion of the back-side potential lead-out portion 18. The evaluation control unit 27 evaluates electrical characteristics of the vertical semiconductor devices 52 by passing current. < Front probe 11 and extension electrode front probe 17 >

[0038] Next, the structures of the front-side probe 11 and the extension electrode front-side probe 17 will be described in detail. The structure of the extension electrode front-side probe 17 is almost the same as that of the front-side probe 11, so the structure of the front-side probe 11 will be mainly described.

[0039] Fig. 3A, Fig. 3B and Fig. 3C show side views illustrating a schematic structure and operations of the front-side probe 11 according to the first preferred embodiment. The front-side probe 11 includes a substrate mounting portion 11a, a tip portion 11b, a printing portion 11c, and an external connection portion 11d.

[0040] The substrate mounting region 11a is formed as a base and is mechanically connected to the probe substrate 21. The tip region 11b has a contact region 11b1 that enables mechanical and electrical contact with the front side of the front electrode 52a of the vertical semiconductor device 52.

[0041] A spring element, such as a spring, installed inside the substrate mounting portion 11a can vibrate the pressure portion 11c when the contact portion 11b1 comes into contact with the front-side electrode 52a. In other words, the pressure portion 11c can cause the contact portion 11b1 to come into contact with the front-side electrode 52a to bias the front-side electrode 52a and can change the distance between the substrate mounting portion 11a and the tip portion 11b. The pressure portion 11c electrically connects the contact portion 11b1 and the external connection portion 11d. The external connection portion 11d, which is electrically connected to the contact portion 11b1, serves as an output terminal to the outside (as the probe connection portion 22a).

[0042] In the first preferred embodiment, as described above, the spring probe with the built-in spring is used on the front probe 11. For the operation of the front probe 11, the front probe 11 is lowered to the lower side (-Z side) in the state where the contact portion 11b1 of the front probe 11 is separated from the front electrode 52a, as shown in Fig. 3A, and then the contact area 11b1 comes into contact with the front side electrode 52a, as shown in Fig. 3B is shown.

[0043] Subsequently, the front probe 11 is further lowered, and then the printing area 11c is pressed into the substrate mounting area 11a, as shown in Fig. 3C. The front-side probe 11 having such a configuration can reliably establish contact between the front-side probe 11 and the front-side electrode 52a of the vertical semiconductor device 52, and thus electrical connection therebetween.

[0044] The extension electrode front probe 17 and the front probe 11 are the same except that the front electrode 52a and the probe connection portion 22a are replaced with the extension electrode 16 and the probe connection portion 22b in the configuration of the front probe 11 as described above.

[0045] In other words, in the first preferred embodiment, the spring probe with the built-in spring is used on the extension electrode front probe 17. In this configuration, the extension electrode front probe 17 can Fig. 3A to 3C, so that the alignment of the extension electrode 16 in the Z direction can be easily performed.

[0046] As described above, the front probe 11 and the extension electrode front probe 17 are spring probes that oscillate in the Z direction, which is not limiting, and can be, for example, cantilever probes. When the probe with oscillation in the Z direction is used on the front probe 11 and the extension electrode front probe 17, this is not limited to the spring type and can be, for example, a stack probe or a wire probe.

[0047] Metal materials with conductivity, such as copper, tungsten, and rhenium-tungsten, are used for the materials of the front-side probe 11 and the extension electrode front-side probe 17. Note that this is not limitative, and in particular, the contact portion 11b1 or the like may be coated with other elements such as gold, palladium, tantalum, and platinum from the viewpoint of improving the conductivity of the electrode portion 14a, improving its durability, or the like. <Arbeitsvorgänge>

[0048] Next, an operation of the semiconductor evaluation device 1 according to the first preferred embodiment will be described.

[0049] First, as in Fig. 4, the semiconductor wafer 51 including the plurality of vertical semiconductor devices 52 is placed in the semiconductor wafer holding area 6, and then the semiconductor wafer 51 is moved so that the front electrode 52a of the one vertical semiconductor device 52 to be evaluated is located immediately below the front probe 11, the front electrode 52a being located between the front probe 11 and the layer 14.

[0050] Subsequently, the front-side probe 11 and the layer 14 approach the semiconductor wafer 51 from a front side and a back side of the semiconductor wafer 51, respectively. The front-side probe 11 and the electrode region 14a come into contact with the front-side electrode 52a and the back-side electrode 52b of the semiconductor device 52 to be evaluated, respectively. Here, in the first preferred embodiment, a metal plate is used for the wiring region 15, so that the layer 14, the wiring region 15, and the extension electrode 16 are substantially integrated into a solid. In this configuration, as shown in Fig. 1, the electrode portion 14a comes into contact with the back electrode 52b, and almost simultaneously the extension electrode 16 comes into contact with the extension electrode front probe 17.

[0051] Next, the vertical semiconductor device 52 is evaluated for the desired electrical properties. After the evaluation is completed, the front-side probe 11 and the layer 14 are separated from the front-side electrode 52a and the back-side electrode 52b, respectively. The metal plate is used for the wiring region 15 in the first preferred embodiment, so that the electrode region 14a is separated from the back-side electrode 52b, and the extension electrode 16 is separated from the extension electrode front-side probe 17 almost simultaneously, as shown in FIG. Fig. 4, is separated.

[0052] After the separation as described above, in order to connect the one vertical semiconductor device 52 to be evaluated next to the front probe 11 or the like, the movable arm 7 connected to the semiconductor wafer holding section 6 is used to move the semiconductor wafer 51 substantially in the directions of a plane. Thus, the vertical semiconductor devices 52, which, as shown in Fig. 1, are arranged on the periphery of the semiconductor wafer 51, are evaluated and the vertical semiconductor devices 52, which, as shown in Fig. 2, arranged in the center of the semiconductor wafer 51, can also be evaluated.

[0053] Here, in the first preferred embodiment, the front side electrodes 52a and the back side electrode 52b have a rotationally symmetrical shape in their plan view, and the semiconductor wafer holding regions 5 are configured to allow a rotation of the semiconductor wafer 51 by 180 degrees in the plan view of the semiconductor wafer 51. Thereafter, the evaluation of the semiconductor wafer 51 begins from the circumference, as shown in Fig. 1. In a case where the evaluation of the center of the semiconductor wafer 51 as shown in Fig. 2, the semiconductor wafer 51 is rotated 180 degrees instead of evaluating the remainder of the evaluation in the same direction of movement of the semiconductor wafer 51 in which it was previously evaluated. After that, the semiconductor wafer 51 is rotated back in the direction of Fig. 2 to Fig. 1 moves.

[0054] With this configuration, the maximum width of the moving region of the semiconductor wafer 51 is approximately 1.5 times the length of the semiconductor wafer 51, rather than approximately twice the length. Therefore, the space required for evaluation by the semiconductor evaluation device 1 can be reduced.

[0055] Furthermore, in the case where the semiconductor wafer 51 is rotated, the front-side probe 11 and the electrode region 14a of the layer 14 can be configured to rotate 180 degrees in the same direction as (or opposite to) the rotation of the semiconductor wafer 51 while maintaining their positions. This configuration can achieve the same effects as those described above, even if the front-side electrodes 52a and the back-side electrode 52b have a rotationally asymmetric shape. < Summary of the First Preferred Embodiment >

[0056] In the semiconductor evaluation device 1 having the configuration as described above and the semiconductor evaluation method according to the first preferred embodiment, in the case where the semiconductor wafer 51 and the semiconductor wafer holding portion 6 holding the semiconductor wafer 51 move in the in-plane directions of the semiconductor wafer 51, the portion of the backside potential lead-out portion 18 located in the in-plane direction of the semiconductor wafer 51 is fixed near the outside of the moving region of the semiconductor wafer 51.

[0057] With this configuration, the high-potential area (region) can be reduced more than that of conventional technology, thus ensuring isolation easily. Therefore, improvement in evaluation reliability, improvement in evaluation accuracy, reduction in cost, and shortening of steps are achieved. Furthermore, shortening of the wiring (e.g., the wiring region 15) with respect to the probe in contact with the semiconductor wafer 51 and, consequently, reduction of parasitic impedance are expected. Furthermore, with the shortening of the wiring region 15 or the like, miniaturization of the semiconductor evaluation device 1 is also expected.

[0058] In the first preferred embodiment, the wiring portion 15 is formed from the metal plate. With this configuration, the cross-sectional area of ​​the wiring portion 15 is easily secured, so that high temperatures due to heat generation when using the relatively large current can be avoided. < Modifications of the First Preferred Embodiment >

[0059] Next, first to ninth modifications will be described. The first to ninth modifications described here can also be applied to a second preferred embodiment described below. < First modification >

[0060] In the first preferred embodiment, the semiconductor wafer 51 and the semiconductor wafer holding portion 6 that holds the semiconductor wafer 51 are movable in the in-plane directions (X, Y directions) of the semiconductor wafer 51 with respect to the front-side probe 11, the layer 14 (the electrode portion 14a), and the back-side potential-releasing portion 18. However, this is not limiting, and the configuration including, for example, the front-side probe 11, the layer 14 (the electrode portion 14a), and the back-side potential-releasing portion 18 is provided with a movable mechanism and thus can be movable in the in-plane directions (X, Y directions) of the semiconductor wafer 51 with respect to the semiconductor wafer 51 and the semiconductor wafer holding portion 6 that holds the semiconductor wafer 51.

[0061] In the case where the front-side probe 11, the layer 14 (the electrode region 14a), and the back-side potential-lead-out region 18 move in the in-plane directions of the semiconductor wafer 51, the semiconductor wafer 51 can be fixed near the outside of the moving region of the back-side potential-lead-out region 18 located in the in-plane direction of the semiconductor wafer 51. The configuration according to the first modification as described above can achieve the same effects as those in the first preferred embodiment. < Second modification >

[0062] In the first preferred embodiment, the semiconductor evaluation device 1 comprises the one probe substrate 21 which mechanically fixes both the front-side probe 11 and the extension electrode front-side probe 17.

[0063] In contrast, as in Fig. As shown in Figure 5, a semiconductor evaluation device 1 according to a second modification includes a first probe substrate 21a (first insulating substrate) that fixes a front-side probe 11 and a second probe substrate 21b (second insulating substrate) that fixes the extension electrode front-side probe 17. Furthermore, the semiconductor device 1 according to the second modification includes a frame 31 that holds the first and second probe substrates 21a, 21b.

[0064] A probe head 23 according to the second modification is electrically connected to the front-side probe 11 through the probe connection portion 22a in a case where the first probe substrate 21a is attached to the probe head 23, while the probe head 23 is electrically connected to the extension electrode front-side probes 17 through the probe connection portion 22b in a case where the second probe substrate 21b is attached to the probe head 23. By replacing the first probe substrate 21a with another first probe substrate 21a, the front-side probe 11 is also interchangeable with another front-side probe 11.

[0065] The semiconductor evaluation device 1 according to the second modification described above can be adapted to various semiconductor wafers 51 and various vertical semiconductor devices 52 by replacing the first probe substrate 21a while the extension electrode front-side probes 17 and the second probe substrate 21b are substantially fixed to the test head 23. Therefore, the replacement can be easily performed, and consequently, reduced costs are achieved. < Third Modification >

[0066] Fig. Fig. 6 is a plan view illustrating a schematic configuration of an electrode region 14a provided on a layer 14 according to a third modification. Next, a semiconductor evaluation device 1 according to the third modification will be described with reference to Fig. Fig. 5, which was used in the second modification, and Fig. 6. Furthermore, the third modification need not include the first and second probe substrates 21a, 21b.

[0067] As in Fig. 6, the one electrode region 14a includes a collecting detection electrode 14a1 (detection electrode) for measuring a voltage applied to a vertical semiconductor device 52, and a collecting force electrode 14a2 (force electrode) for supplying a current and a voltage to the vertical semiconductor devices 52. In other words, the one electrode region 14a is divided into the collecting detection electrode 14a1 and the collecting force electrode 14a2.

[0068] The collecting detection electrode 14a1 and the collecting force electrode 14a2 are electrically insulated from each other, and the collecting detection electrode 14a1 and the collecting force electrode 14a2 can simultaneously be in contact with the back surface electrode 52b of the vertical semiconductor device 52, wherein the back surface electrode 52b corresponds to the collecting detection electrode 14a1 and the collecting force electrode 14a2.

[0069] The semiconductor evaluation device 1 according to the third modification, which includes the collecting detection electrode 14a1 and the collecting force electrode 14a2 as described above, can improve the accuracy of evaluation.

[0070] In Fig. 5, two extension electrodes 16 and two extension electrode front probes 17 are provided corresponding to the collecting detection electrode 14a1 and the collecting force electrode 14a2. However, this is not limiting, and the extension electrode 16 may replace the two extension electrodes 16 in Fig. 5 combined into one, maintaining the insulation between the two, and the extension electrode front probe 17 can combine the two extension electrode front probes 17 into Fig. 5 combined into one, maintaining isolation between the two. < Fourth Modification >

[0071] Fig. 7 is a plan view illustrating a schematic configuration of electrode regions 14a provided on a layer 14 according to a fourth modification. Furthermore, in the fourth modification, each electrode region 14a need not include a collecting detection electrode 14a1 and a collecting force electrode 14a2.

[0072] As in Fig. As shown in FIG. 7, a plurality of (here, two) electrode regions 14a are provided on the layer 14. The two electrode regions 14a can be in contact with two vertical semiconductor devices 52 simultaneously. Although not shown in the illustration, the front-side probes 11 can be in contact with the two vertical semiconductor devices 52 in the same way. Then, an evaluation control unit 27 can evaluate electrical characteristics of the two vertical semiconductor devices 52 simultaneously, with the two vertical semiconductor devices 52 in contact with the front-side probes 11 and the two electrode regions 14a.

[0073] As described above, the semiconductor evaluation device 1 according to the fourth modification can be collectively in contact with the plurality of vertical semiconductor devices 52 for evaluation, and thus the evaluation steps can be shortened.

[0074] In addition, the number of electrode areas is 14 in Fig. 7 equals two, which is not limiting, and can be three or more. < Fifth Modification >

[0075] Fig. Fig. 8 is a side view illustrating a schematic configuration of a layer 14 according to a fifth modification. In the fifth modification, an electrode region 14a is provided on the layer 14, similarly to the first preferred embodiment. However, in the fifth modification, the electrode region 14a is interchangeable with another electrode region 14a.

[0076] In a semiconductor evaluation device 1 according to the fifth modification described above, by replacing the electrode region 14a according to a size of a vertical semiconductor device 52 or a size of a backside electrode 52b, the electrode region 14a can be used in an appropriate size. Furthermore, replacing the electrode region 14a is simpler than replacing the layer 14 itself, thus achieving reduced costs.

[0077] Fig. 8 shows a state where the electrode portion 14a with a small area is mounted on the layer 14, but the electrode portion 14a with a large area can be securely mounted on the layer 14. The connection between the electrode portion 14a and the layer 14 is assumed to be a mating connection or a screw connection, but this is not limiting. Furthermore, the electrode portion 14a and / or the layer 14 is formed with a recessed portion into which an alignment pin is fitted, thereby facilitating alignment at the time of replacement. < Sixth Modification >

[0078] In the first preferred embodiment, the wiring portion 15 is formed from the metal plate. In contrast, in a sixth modification, as shown in Fig. As shown in Figure 9, a wiring portion 15 is formed from a wire whose shape is variable. In other words, in the sixth modification, a layer 14, the wiring portion 15, and an extension electrode 16 are not integrated into a solid.

[0079] The semiconductor evaluation device 1 according to the sixth modification described above can bring the layer 14 (the electrode region 14a) into contact with or separate it from the layer of a semiconductor wafer 51 in a state where the extension electrode 16 and an extension electrode front-side probe 17 are in contact with each other. This can reduce the number of times the extension electrode 16 comes into contact with or separates from the extension electrode front-side probe 17, thereby saving the Z-direction alignment time due to the process of bringing the extension electrode 16 and the extension electrode front-side probe 17 back into contact with each other. Furthermore, a shortening of the evaluation steps is expected. < Seventh Modification >

[0080] In the first preferred embodiment, the semiconductor wafer holding region 6 is in contact with the peripheral region of the semiconductor wafer 51 to hold the semiconductor wafer 51. The above-described backside connection region includes the electrode region 14a of the layer 14.

[0081] However, the thickness of the semiconductor wafer 51 in which the vertical semiconductor devices 52 are formed has recently continued to decrease (e.g., to 100 μm or less). Therefore, the configuration that supports only the peripheral portion of the semiconductor wafer 51 easily causes bending in the semiconductor wafer 51, potentially leading to breakage at the time of contact with a probe or film. A semiconductor evaluation device 1 according to a seventh modification can solve these problems.

[0082] Fig. 10 is a cross-sectional view illustrating a schematic configuration of the semiconductor evaluation device 1 according to the seventh modification. In the seventh modification, a semiconductor wafer holding portion 6 has a tray shape and holds the back surface of a semiconductor wafer 51. The semiconductor wafer holding portion 6 is formed of metal (for example, copper) with conductive properties and is in contact with the back surface of the semiconductor wafer 51 to be electrically connected to the back surface of the semiconductor wafer 51. A back surface connection portion is formed from the semiconductor wafer holding portion 6 instead of the electrode portion 14a.

[0083] The semiconductor evaluation device 1 according to the seventh modification having the configuration as described above can suppress the breakage of the semiconductor wafer 51 whose thickness has been further reduced.

[0084] The problem of voltage drop can also be reduced if the semiconductor wafer holding region 6 is configured to be thin in addition to having mechanical strength. Although not shown, a vacuum adsorption mechanism may be applied to the semiconductor wafer holding region 6 having a tray shape to increase adhesion between the semiconductor wafer 51 and the semiconductor wafer holding region 6. < Eighth Modification >

[0085] In the configuration of the first preferred embodiment and the configurations described above, the probe connection region 22a extending in the Z direction is provided immediately above the front-side probe 11 for electrically connecting the front-side probe 11 and the test head 23 at the shortest distance. Furthermore, the evaluated vertical semiconductor device 52 is in contact with the layer 14 immediately below the vertical semiconductor device 52.

[0086] In contrast, in an eighth modification, as in Fig. 11, a probe connection region 22a also extends in horizontal directions (X, Y directions). A position in the horizontal directions where a portion of the probe connection region 22a is connected to a test head 23 (hereinafter referred to as a "head connection region") does not coincide with a position in the horizontal directions where the evaluated semiconductor device 52 is arranged. In addition, a layer 14 may be electrically connected to the evaluated vertical semiconductor device 52 through a portion extending in the horizontal directions of a semiconductor wafer holding region 6, and thus the position of the head connection region in the horizontal directions is close to the position of the layer 14 in the horizontal directions.

[0087] In a semiconductor evaluation device 1 according to the eighth modification having the above-described configuration, a direction of a conduction path of the probe connection portion 22a (an element) electrically connecting a front-side probe 11 and the test head 23 is parallel and opposite to a direction of a conduction path of the semiconductor wafer holding portion 6. For this reason, the direction of current flowing through the probe connection portion 22a is opposite to the direction of current flowing through the semiconductor wafer holding portion 6, thereby achieving a reduction in inductance.

[0088] In addition, the probe connection region 22a is sufficiently spaced from the semiconductor wafer holding region 6 so that insulation is ensured even at high current. < Ninth Modification >

[0089] Fig. 12 is a cross-sectional view illustrating a schematic configuration of a semiconductor evaluation device 1 according to a ninth modification. In the ninth modification, a backside connection region does not include an electrode region 14a and a semiconductor wafer holding region 6, and includes backside probes 34. Even if the semiconductor evaluation device 1 according to the ninth modification has such a configuration, the semiconductor evaluation device 1 can achieve effects similar to those in the first preferred embodiment. < Second Preferred Embodiment >

[0090] Fig. 13 and Fig. 14 show cross-sectional views illustrating schematic configurations of a semiconductor evaluation device 1 according to a second preferred embodiment of the present invention. Fig. 13 and Fig. 14 show configurations different from each other. In the semiconductor evaluation device 1 according to the second preferred embodiment, the same components or similar components to those described above are denoted by the same reference numerals, and differences will be mainly described.

[0091] In the second preferred embodiment, the extension electrode front-side probe 17 is omitted, and the extension electrode 16 extends toward the probe substrate 21 along the Z direction and is electrically connected to the probe connection portion 22b. In other words, the back-side potential-releasing portion 18 is formed from the wiring portion 15 and the extension electrode 16, and the wiring portion 15 serves as one end portion of the back-side potential-releasing portion 18, while the extension electrode 16 serves as the other end portion of the back-side potential-releasing portion 18. The extension electrode 16 is configured to be attachable and detachable by inserting it into a socket disposed in the probe substrate 21, but this is not limitative.

[0092] In the second preferred embodiment, the backside potential-lead region 18 comprises a movable mechanism 38 configured to bring the electrode region 14a of the layer 14 close to and separate it from the frontside probe 11. In the configuration in Fig. 13, the back potential lead-out portion 18 includes the movable mechanism 38 at the connection portion between the wiring portion 15 and the extension electrode 16, while in the configuration of Fig. 14, the backside potential-discharging portion 18 includes the movable mechanism 38 in the center of the wiring area 15. It is assumed that a joint equipped with a rotating mechanism is used for the movable mechanism 38, but this is not limiting. < Summary of the Second Preferred Embodiment >

[0093] In the first preferred embodiment, the extension electrode front-side probe 17 and the extension electrode 16 are brought into contact with and separated from each other every time the semiconductor wafer 51 moves. In contrast, in the semiconductor evaluation apparatus 1 according to the second preferred embodiment, the movable mechanism 38 is provided, and thus the layer 14 (the electrode region 14a) can be brought into contact with and separated from the semiconductor wafer 51 without performing the contact and separation in the manner described above. As a result, the continuity between the extension electrode front-side probe 17 and the extension electrode 16 does not need to be checked, further simplifying the steps. In addition, heat generation from the connection region between the extension electrode front-side probe 17 and the extension electrode 16 can also be suppressed.

[0094] The configuration of Fig. 14 can provide a space for the movement of layer 14 further than the configuration in Fig. 13, and therefore the miniaturization of the semiconductor evaluation device 1 is expected. In summary:

[0095] A backside potential release region 18 has one end portion located on one side of a back side of a semiconductor wafer 51 held by a semiconductor wafer holding portion 6, and the other end portion located on a side of a front side of the semiconductor wafer 51 held by the semiconductor wafer holding portion 6. The semiconductor wafer 51 and the semiconductor wafer holding portion 6 holding the semiconductor wafer 51 are movable in the direction of a plane of the semiconductor wafer 51. In a case where the semiconductor wafer 51 and the semiconductor wafer holding portion 6 holding the semiconductor wafer 51 are moved in the plane direction, a portion of the backside potential release region 18 located in the direction of the plane of the semiconductor wafer 51 is fixed near the outside of a moving region of the other. LIST OF REFERENCE SYMBOLS 1 semiconductor evaluation device 6, 14a, 34 Semiconductor wafer holding area 7 movable arm 11 Front probe 11a Substrate mounting area 11b peak area 11b1 Contact area 11c Print area 11d external connection area 14 shift 14a Electrode area 14a1 Detection electrode, collective detection electrode 14a2 Force electrode, collecting force electrode 15 Wiring element I 16 Extension electrode 17 Extension electrode front probe 18 Rear potential discharge area 21 Probe substrate 21a first insulating substrate, probe substrate 21b second insulating substrate, probe substrate 22a, 22b connecting areas 23 test head 26 signal lines 27 Evaluation Unit 34 Rear probe 51 semiconductor wafers 52 semiconductor devices 52a Front electrode 52b back electrode

Claims

[1] A semiconductor evaluation device (1) that evaluates a plurality of vertical semiconductor devices (52) provided in a semiconductor wafer (51), the vertical semiconductor devices each comprising a front-side electrode (52a) and a back-side electrode (52b) provided on a front side and a back side of the semiconductor wafer, respectively, the semiconductor evaluation device comprising: a semiconductor wafer holding portion (6) holding the semiconductor wafer; a front-side probe (11) electrically connected to the front-side electrode in a case of contacting the front-side electrode on the semiconductor wafer held by the semiconductor wafer holding portion; a backside connection portion (6, 14a, 34) electrically connected to the backside electrode in a case of contacting the backside electrode on the semiconductor wafer held by the semiconductor wafer holding portion; a backside potential lead-out region (18) having one end region disposed on one side of the backside of the semiconductor wafer held by the semiconductor wafer holding region and electrically connected to the backside connection region, and having the other end region disposed on one side of the frontside of the semiconductor wafer held by the semiconductor wafer holding region and electrically connected to the one end region; and an evaluation unit (27) that passes current through the front electrode and the back electrode via the front probe and the other end portion of the back potential lead-out portion, respectively, to evaluate electrical characteristics of the vertical semiconductor devices, wherein the semiconductor wafer and the semiconductor wafer holding portion that holds the semiconductor wafer, or the front probe, the back connection portion and the back potential lead-out portion are movable toward a plane of the semiconductor wafer, and In a case where the semiconductor wafer and the semiconductor wafer holding portion holding the semiconductor wafer, or the front-side probe, the back-side connection portion, and the back-side potential-releasing portion are moved in the in-plane direction, the semiconductor wafer or a portion of the back-side potential-releasing portion located in an in-plane direction from the semiconductor wafer is fixed near the outside of one moving portion of the other. [2] The semiconductor evaluation device (1) according to claim 1, wherein the backside connection portion (6, 14a, 34) comprises a backside probe (34), or comprises an electrode portion (14a) provided on a layer (14) of the semiconductor wafer (51), or is formed of the semiconductor wafer holding portion (6) which is in contact with the backside of the semiconductor wafer to be electrically connectable to the backside of the semiconductor wafer. [3] A semiconductor evaluation device (1) according to claim 1 or 2, wherein the backside potential lead-out region (18) comprises: an extension electrode (16) electrically connected to an end portion; and an extension electrode front probe (17) serving as another end portion; and the extension electrode and the extension electrode front probe are arranged to be in contact with each other and separated from each other. [4] Semiconductor evaluation device (1) according to one of the preceding claims, wherein the backside potential lead-out region (18) comprises a movable mechanism (38) configured to bring the backside connection region (6, 14a, 34) close to the frontside probe (11) and to separate the backside connection region (6, 14a, 34) therefrom. [5] A semiconductor evaluation device (1) according to any one of the preceding claims, wherein the semiconductor wafer holding portion (6) is in contact with a peripheral portion of the semiconductor wafer (51) to hold the semiconductor wafer. [6] The semiconductor evaluation device (1) according to any one of the preceding claims, wherein the backside potential lead-out region (18) further comprises a metal plate or a cable serving as the one end portion and electrically connecting the backside connection region (6, 14a, 34) and the extension electrode (16). [7] Semiconductor evaluation device (1) according to one of the preceding claims, wherein the backside connection region (6, 14a, 34) comprises a plurality of electrode regions (14a) provided on the layer (14), and the plurality of electrode regions are arranged to be in contact with two or more of the vertical semiconductor devices (52) simultaneously [8] Semiconductor evaluation device (1) according to one of the preceding claims, wherein the backside connection region (6, 14a, 34) comprises the electrode region (14a) provided on the layer (14), and the electrode area is interchangeable with another electrode area. [9] Semiconductor evaluation device (1) according to one of the preceding claims, wherein the backside connection region (6, 14a, 34) comprises the electrode region (14a) provided on the layer (14), the electrode region comprises a detection electrode (14a1) and a force electrode (14a2), and the detection electrode (14a1) and the force electrode (14a2) are arranged to be in contact with the backside electrode (52b) of the vertical semiconductor devices (52) at the same time, the backside electrode corresponding to the detection electrode and the force electrode. [10] Semiconductor evaluation device (1) according to one of claims 3 to 9, further comprising: an insulating substrate (21) fixing the front probe (11) and the extension electrode front probe (17); and a test head (23) electrically connected to the evaluation unit (27) and, in a case where the insulating substrate is attached to the test head, electrically connected to the front probe and the extension electrode front probe (17), wherein by replacing the insulating substrate with another insulating substrate, the front probe (11) and the extension electrode front probe (17) are also interchangeable with another front probe and another extension electrode front probe, respectively. [11] Semiconductor evaluation device (1) according to one of claims 3 to 10, further comprising: a first insulating substrate (21a) fixing the front probe (11); a second insulating substrate (21b) fixing the extension electrode front probe (17); and a test head (23) electrically connected to the evaluation unit (27) and, in a case where the first insulating substrate is attached to the test head, electrically connected to the front probe, and, in a case where the second insulating substrate is attached to the test head, electrically connected to the extension electrode front probe (17), wherein by replacing the first insulating substrate with another first insulating substrate, the front-side probe and the extension electrode front-side probe are also interchangeable with another front-side probe. [12] A semiconductor evaluation device (1) according to any one of claims 3 to 11, wherein the extension electrode front side probe (17) comprises a spring probe having a built-in spring. [13] Semiconductor evaluation device (1) according to one of the preceding claims, further comprising: a test head (23) electrically connected to the front probe (11), wherein the backside connection region (6, 14a, 34) is formed from the semiconductor wafer holding region (6) which is in contact with the backside of the semiconductor wafer (51) in order to be electrically connectable to the backside of the semiconductor wafer, and a direction of a conductive path of an element electrically connecting the front probe and the test head is parallel to a direction of a conductive path of the semiconductor wafer holding region. [14] Semiconductor evaluation device (1) according to one of the preceding claims, wherein the semiconductor wafer holding section (6) is arranged to rotate the semiconductor wafer (51) by 180 degrees in a plan view of the semiconductor wafer. [15] A semiconductor evaluation method for evaluating a plurality of vertical semiconductor devices (52) provided in a semiconductor wafer (51), the vertical semiconductor devices each comprising a front-side electrode (52a) and a back-side electrode (52b) provided on a front side and a back side of the semiconductor wafer, respectively, the semiconductor evaluation method comprising the steps of: (a) holding the semiconductor wafer by a semiconductor wafer holding area (6); (b) bringing a front-side probe (11) into contact with the front-side electrode on the semiconductor wafer held by the semiconductor wafer holding portion to electrically connect the front-side probe and the front-side electrode; (c) bringing a backside connection region (6, 14, 34) into contact with the backside electrode on the semiconductor wafer held by the semiconductor wafer holding region to electrically connect the backside connection region and the backside electrode; (d) arranging one end portion of a backside potential lead-out region (18) on one side of the backside of the semiconductor wafer held by the semiconductor wafer holding region, and arranging the other end portion on one side of the frontside of the semiconductor wafer held by the semiconductor wafer holding region, wherein the one end portion is electrically connected to the backside connection region, wherein the other end portion is electrically connected to the one end portion of the backside potential lead-out region (18), and (e) passing current through the front electrode and the back electrode via the front probe and the other end portion of the back potential lead-out region (18), respectively, to evaluate electrical characteristics of the vertical semiconductor devices, wherein the semiconductor wafer and the semiconductor wafer holding portion holding the semiconductor wafer, or the front-side probe, the back-side connection portion and the back-side potential lead-out portion (18) are movable in the direction of a plane of the semiconductor wafer, and In a case where the semiconductor wafer and the semiconductor wafer holding portion that holds the semiconductor wafer, or the front-side probe, the back-side connection portion, and the back-side potential-releasing portion are moved in the in-plane direction, the semiconductor wafer or a portion of the back-side potential-releasing portion located in the in-plane direction from the semiconductor wafer is fixed near the outside of one moving portion of the other.

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