Method for forming a bore for a cavern arranged within a semiconductor layer stack

Abstract

The invention relates to a method for forming a bore (38) for a cavern (22) arranged within a semiconductor layer stack (10) by forming a first partial bore (24) by means of a first laser ablation step started on an outer surface (26) of the semiconductor layer stack (10) such that the first partial bore (24) extends from the outer surface (26) with a first central extension (d1) oriented parallel to the outer surface (26) and is formed with a bottom surface (24a) of the first partial bore (24) located between the outer surface (26) and the cavern (22) and forming a second partial bore (36) by means of a second laser ablation step started from the bottom surface (24a) of the first partial bore (24) such thatthat the second partial bore (36) extends through the bottom surface (24a) into the cavern (22) or into an access channel opening into the cavern (22) or connected to the cavern (22) via a connecting channel, with a second mean extent (d2) oriented parallel to the outer surface (26) and smaller than the first mean extent (d1).

Description

[0001] The present invention relates to a method for forming a bore for a cavity arranged within a semiconductor layer stack. The invention also relates to a method for enclosing pressure and / or a medium in a cavity arranged within a semiconductor layer stack. Furthermore, the invention relates to semiconductor layer stacks. State of the art

[0002] German patent application DE 10 2011 103 516 A1 describes a method for filling a cavity with an atmosphere. The cavity, located within a semiconductor layer stack, is subsequently filled by removing material through laser ablation using a pulsed laser beam. This creates an opening with a (essentially) constant diameter that extends into the interior of the cavity. After the cavity is filled with the desired atmosphere, the opening is sealed by melting and subsequent solidification using another laser beam, which causes slow heating in the area of ​​the opening. Disclosure of the invention

[0003] The present invention provides a method for forming a bore for a cavern arranged within a semiconductor layer stack with the features of claim 1, a method for enclosing a pressure and / or a medium in a cavern arranged within a semiconductor layer stack with the features of claim 8, a semiconductor layer stack with the features of claim 9 and a semiconductor layer stack with the features of claim 10. Advantages of the invention

[0004] The present invention enables the cost-effective and simple fabrication of a variety of semiconductor devices, each of which has a cavity within a semiconductor layer stack containing a desired internal pressure and / or a defined medium. In particular, the present invention avoids problems that are conventionally encountered when performing at least one etching process to create a bore down to the cavity. Furthermore, the present invention implements an improved laser drilling technique for creating a bore down to the cavity or to an associated access channel, which allows for faster bore formation and significantly reduces the frequency of particles or soot generated in the cavity during laser drilling.By using the present invention, damage to semiconductor devices caused by particles or soot generated during laser drilling can be reduced compared to conventional techniques.

[0005] In an advantageous embodiment of the method, the first and second partial bores are drilled through a semiconductor substrate of the semiconductor layer stack that defines the cavity. This substrate substrate, on its surface facing away from the outer surface of the semiconductor layer stack, is equipped with a circuit layer containing at least one application-specific integrated circuit. The semiconductor substrate equipped with the at least one application-specific integrated circuit can also be referred to as an ASIC substrate. In particular, the outer surface of the semiconductor layer stack can be the back side of the ASIC substrate, facing away from the substrate surface containing the at least one application-specific integrated circuit.Drilling the first and second partial bores through the ASIC substrate is significantly simpler and more cost-effective than alternatively drilling access holes through a MEMS substrate, since the substrate thickness of the ASIC substrate, perpendicular to the outer surface, is generally considerably smaller than the corresponding substrate thickness of a MEMS substrate. Therefore, in the embodiment described here, the formation of the bore comprising the first and second partial bores through the ASIC substrate can be achieved within shorter process times.

[0006] Alternatively, the first and second partial bores can also be drilled through a capping substrate of the semiconductor layer stack that defines the cavity. Even a capping substrate thickness perpendicular to the outer surface is typically relatively thin, which is why, in this case as well, the advantages of a comparatively short process time for forming the bore comprising the first and second partial bores are ensured.

[0007] Preferably, the second partial bore is drilled into the access channel, which extends parallel to the outer surface of the semiconductor layer stack and through a portion of the semiconductor layer stack. As will become clear from the following description, in this case the access channel prevents the ingress of particles or soot into the cavity.

[0008] In a further advantageous embodiment of the method, the first partial bore and the second partial bore are aligned with each other such that a common central longitudinal axis can be defined for both. Preferably, in this case, the first length of the first partial bore along the common central longitudinal axis is at least twice as long as the second length of the second partial bore along the common central longitudinal axis. As will become clear from the following description, this allows the bore comprising both the first and second partial bores to be formed relatively quickly, even with a comparatively large sum of the first and second lengths.

[0009] It is advantageous if the first partial bore is formed with a first mean dimension oriented parallel to the outer surface, which is at least twice the size of the second mean dimension with which the second partial bore is formed parallel to the outer surface. The first laser ablation step can thus be performed at a high ablation rate, while the second laser ablation step can be performed at a significantly reduced ablation rate.

[0010] The advantages described above are also guaranteed when carrying out a method for enclosing pressure and / or a medium in a cavern arranged within a semiconductor layer stack, comprising the steps of: forming a bore for the cavern arranged within the semiconductor layer stack according to an embodiment of the method described above, and closing the bore when pressure and / or the medium is present in the cavern by melting a wall area of ​​the first partial bore and / or the second partial bore adjacent to the bottom surface of the first partial bore of the bore using a laser beam. Brief description of the drawings

[0011] Further features and advantages of the present invention are explained below with reference to the figures. They show: Fig. 1 A to 1 C schematic representations of intermediate or final products to explain a first embodiment of the method for forming a bore for a cavern arranged within a semiconductor layer stack; Fig. 2A and Fig. 2B Schematic representations of intermediate or final products to illustrate a second embodiment of the method for forming a bore for a cavern arranged within a semiconductor layer stack; Fig. 3A and Fig. 3B Schematic representations of intermediate or final products to illustrate a third embodiment of the method for forming a bore for a cavern arranged within a semiconductor layer stack; and Fig. 4 A schematic representation of an end product to illustrate a fourth embodiment of the method for forming a bore for a cavern arranged within a semiconductor layer stack. Embodiments of the invention

[0012] Fig. Figures 1A to 1C show schematic representations of intermediate or final products to illustrate a first embodiment of the method for forming a bore for a cavern arranged within a semiconductor layer stack.

[0013] In the embodiment described here, the semiconductor layer stack 10 comprises, for example, a so-called ASIC substrate 12, the substrate surface 12a of which is equipped with a circuit layer 14 comprising at least one application-specific integrated circuit, and a so-called MEMS substrate 16 with at least one MEMS component 18a and 18b attached to / connected to a substrate surface 16a of the MEMS substrate 16. The circuit layer 14 can, for example, be configured as a CMOS layer 14. The at least one MEMS component 18a and 18b can be understood to be at least one MEMS sensor 18a and 18b and / or at least one MEMS actuator. The at least one MEMS sensor 18a and 18b can, for example, be a gyroscope 18a, an accelerometer 18b, and / or a pressure sensor. However, the sensor types listed here are only examples.In the embodiment described here, the ASIC substrate 12 and the MEMS substrate 16 are connected to each other via at least one bond connection 20 such that the substrate surfaces 12a and 16a are aligned with each other and a cavity 22 is enclosed between the circuit layer 14 and the substrate surface 16a of the MEMS substrate 16. It should be noted, however, that this semiconductor layer stack 10 is only an example. The method described below can be carried out with a plurality of further semiconductor layer stacks, each with a cavity 22 arranged within the respective semiconductor layer stack.

[0014] As in Fig. As illustrated in Figure 1A, when carrying out the process described here, a first partial bore 24 is formed by means of a first laser ablation step initiated at an outer surface 26 of the semiconductor layer stack 10. The first laser ablation step can also be understood as a laser removal step or a laser vaporization step. For clarity, the outer surface 26 of the semiconductor layer stack 10, where the formation of the first partial bore 24 by means of the first laser ablation step begins, is hereinafter referred to as the bore origin surface 26. By means of the first laser ablation step, the first partial bore 24 is formed such that the first partial bore 24 extends partially through the semiconductor layer stack 10 from the bore origin surface 26 with a first mean extent d1 oriented parallel to the bore origin surface 26.Furthermore, the first partial bore 24 is formed by means of the first laser ablation step on a side facing away from the bore exit surface 26 with a bottom surface 24a of the first partial bore 24 located between the bore exit surface 26 and the cavern 22.

[0015] The first laser ablation step can be performed with a first laser optimized for high ablation, which is why the first laser ablation step can be carried out relatively quickly in relation to the first length l1 of the first sub-bore 24 extending along a central longitudinal axis 28 of the first sub-bore 24. In particular, the first laser ablation step is significantly faster and much easier to perform than an etching step to achieve the same first length l1 of the first sub-bore 24. Since the first laser ablation step is stopped before the bottom surface 24a of the first sub-bore 24 reaches the cavern 22, even when using the first laser with high ablation to perform the first laser ablation step, there is no risk of particles penetrating the cavern 22 during the first laser ablation step.

[0016] As in Fig. As can be seen in Figure 1A, the first partial bore 24 can be shaped as a blind hole or a cup-shaped trench, in particular such that the opening diameter of the first partial bore 24 at the bore exit surface 26 is comparatively large. However, the opening diameter of the first partial bore 24 at the bore exit surface 26 is generally still smaller than the first length l1 of the first partial bore 24 extending along the central longitudinal axis 28 of the first partial bore 24. The central longitudinal axis 28 of the first partial bore 24 can, in particular, be oriented perpendicular to the bore exit surface 26.

[0017] The bore exit surface 26 can also be understood to be, in particular, an outer surface 26 of a passivation layer 30. It is expressly pointed out here that the formation of the first partial bore 24 can only begin when at least one through-hole 32 (TSV) adjacent to the future first partial bore 24 extends from the bore exit surface 26 towards the cavity 22, partially through the semiconductor layer stack 10, and / or when at least one solder ball 34 is attached to the semiconductor layer stack 10 adjacent to and / or on the bore exit surface 26. This is recognizable from the Fig. 1A also states that the formation of the first partial bore 24 can only take place after an advanced packaging process.

[0018] As in Fig. As shown in Figure 1B, after the formation of the first partial bore 24, a second partial bore 36 is formed by means of a second laser ablation step initiated from the bottom surface 24a of the first partial bore 24. The second laser ablation step can also be a laser removal step or a laser vaporization step. The second partial bore 36 is shaped such that it extends through the bottom surface 24a of the first partial bore 24 into the cavern 22 or into an access channel (not shown) that opens into the cavern 22 or is connected to the cavern 22 via a connecting channel. This second intermediate dimension d2 is smaller than the first intermediate dimension d1 and is aligned parallel to the bore exit surface 26.The first partial bore 24 and the second partial bore 36 thus together form a bore 38, which extends from the bore exit surface 26 (at least) into the cavern 22 or into the access channel which opens into the cavern 22 or is connected to the cavern 22 via the connecting channel.

[0019] The two laser ablation steps are preferably performed with two different laser configurations. Preferably, a second laser with a lower ablation rate compared to the first laser is used for the second laser ablation step, e.g., because the second laser emits a shorter wavelength than the first laser. In this way, the first partial bore 24 can easily be formed with the first mean dimension d1, which is aligned parallel to the bore exit surface 26 and is at least a factor of 2 larger than the second mean dimension d2, with which the second partial bore 36 is formed parallel to the bore exit surface 26. Preferably, the second mean dimension d2 is less than or equal to 20 µm (micrometers), in particular less than or equal to 15 µm (micrometers), and especially less than or equal to 10 µm (micrometers).

[0020] Due to the design of the second sub-bore 36 with its smaller second mean dimension d2 (compared to the first mean dimension d1 of the first sub-bore 24), despite the penetration of a wall surface of cavern 22 or the access channel (opening into cavern 22 or connected to cavern 22 via the connecting channel) during the drilling of the second sub-bore 36, little to no ingress of particles or soot into cavern 22 is to be expected. This is a significant advantage of the method described here compared to the prior art explained above.

[0021] The first partial bore 24 and the second partial bore 36 can be aligned with each other such that the central longitudinal axis 28 of the first partial bore 24 can be defined as the common central longitudinal axis 28 of the first partial bore 24 and the second partial bore 36. Furthermore, it is advantageous if the first length l1 of the first partial bore 24 along the common central longitudinal axis 28 is at least a factor of 2 greater than a second length l2 of the second bore 36 along the common central longitudinal axis 28, because, if necessary, even if the second laser has a relatively low ablation rate, the total time for performing the two laser ablation steps is comparatively short. In particular, the two laser ablation steps can be performed within a shorter total time than an etching step to create a reference bore with a length equal to the sum of the lengths l1 and l2.Furthermore, performing the first laser ablation step and the second laser ablation step is extremely cost-effective compared to performing conventional etching processes.

[0022] In an advantageous embodiment of the method described here, the first partial bore 24 and the second partial bore 36 are drilled through the ASIC substrate 12 of the semiconductor layer stack 10, which bounds the cavity 22, wherein the substrate surface 12a with the circuit layer 14 is oriented away from the bore exit surface 26. The ASIC substrate 12 can have a substrate thickness perpendicular to the bore exit surface 26 of less than 150 µm (micrometers), specifically less than 80 µm (micrometers), and particularly less than 50 µm (micrometers). As can be seen from the Fig. As can also be seen in Figure 1B, the bore 38 can extend through the circuit layer 14 within a sealing ring 40, thereby limiting crack formation in the circuit layer 14. In an alternative embodiment, the first partial bore 24 and the second partial bore 36 can also extend through a capping substrate (not shown) of the semiconductor layer stack 10 that defines the cavity 22. Optionally, the substrate thickness of the capping substrate is preferably less than 150 µm (micrometers), specifically less than 80 µm (micrometers), and particularly less than 50 µm (micrometers). In both cases, the total time for performing the first laser ablation step and the second laser ablation step is comparatively short. Alternatively, the bore 38 can also be formed through the MEMS substrate 16, whereby, if necessary, the entire volume of the circuit layer 14 can be used for application-specific integrated circuit elements.

[0023] A semiconductor layer stack 10 produced by the preceding process steps is identifiable by a cavity 22 arranged within the semiconductor layer stack 10 and a bore 38, if the bore 38 comprises a first partial bore 24 with laser ablation traces and a second partial bore 36 with laser ablation traces, wherein the first partial bore 24 extends partially through the semiconductor layer stack 10 with a first mean extension d1 oriented parallel to an outer surface 26 of the semiconductor layer stack 10 from the outer surface 26 and has at least remnants of a bottom surface 24a of the first partial bore 24 on a side facing away from the outer surface 26,and wherein the second partial bore 36 extends with a second mean extent d2 oriented parallel to the outer surface 26 and smaller than the first mean extent d1 through the bottom surface 24a of the first partial bore 24 into the cavern 22 or into an access channel opening into the cavern 22 or connected to the cavern 22 via a connecting channel (see , Fig. 1B).

[0024] The method described here can be (optionally) part of a method for enclosing pressure and / or a medium in the cavity 22 arranged within the semiconductor layer stack 10. If necessary, as in Fig. As shown in Figure 1C, after the formation of bore 38, this bore 38 is closed when the preferred pressure and / or the desired medium is present in the cavern 22. The closing of bore 38 is achieved by melting a wall section of the first partial bore 24 and / or the second partial bore 36, located adjacent to the bottom surface 24a of the first partial bore 24, using a laser beam. The remaining remnants of the partial bores 24 and 36 are generally not critical for any further processing of the material in the Fig. 1C pictorial representation of the final product.

[0025] The method described here can therefore be used to produce a large number of semiconductor devices with a cavity 22 arranged within their respective semiconductor layer stack 10, with a preferred pressure and / or a desired medium, at favorable costs. That the respective semiconductor device has been produced by carrying out the method described here is evident from its semiconductor layer stack 10 with a cavity 22 arranged within the semiconductor layer stack 10 and a bore plug 42 made of a molten and solidified portion of the semiconductor layer stack 22, which lies between a first partial bore 24 with laser ablation traces and a second partial bore 38 with laser ablation traces.wherein the first partial bore 24 extends with a first mean extent d1 oriented parallel to an outer surface 26 of the semiconductor layer stack 10 partially through the semiconductor layer stack 10 starting from the outer surface 26 and the second partial bore 36 extends with a second mean extent d2 oriented parallel to the outer surface 26, smaller than the first mean extent d2, into the cavern 22 or into an access channel opening into the cavern 22 or connected to the cavern 22 via a connecting channel (see , ). Fig. 1C).

[0026] Fig. 2A and Fig. Figure 2B shows schematic representations of intermediate or final products to illustrate a second embodiment of the method for forming a bore for a cavern arranged within a semiconductor layer stack.

[0027] In the method described here, the second partial bore 36 is drilled into an access channel 44 extending parallel to the bore exit surface 26 through a portion of the semiconductor layer stack 10. This access channel opens into the cavity 22 or is connected to the cavity 22 via a connecting channel 44a. Due to its orientation, the access channel 44 can also be described as a lateral access channel 44. The orientation of the access channel 44 ensures that particles or soot released during the drilling of the second partial bore 36 are unlikely to enter the cavity 22. In particular, this effectively prevents damage to the at least one MEMS component 18a and 18b in the cavity 22 caused by particles and soot.Thus, a preferred pressure and / or a desired medium can be ensured in the cavern 22 via the access channel 44, while at the same time an unwanted ingress of particles and soot into the cavern 22 is (essentially) prevented.

[0028] As in Fig. As can be seen in Figure 2A, the access channel 44, extending parallel to the bore exit surface 26 through the portion of the semiconductor layer stack 10, can be formed in a substrate 16 which lies on a side of the cavern 22 oriented towards the bore exit surface 26, and in particular adjoins the cavern 22. This is shown in the example only by way of example. Fig. 2A the corresponding substrate 16 the MEMS substrate 16.

[0029] As in Fig. As shown in Figure 2B, in the method described here, after completion of the bore 38 comprising the first partial bore 24 and the second partial bore 36, a desired pressure and / or a preferred medium can be enclosed in the cavern 22 by subsequently melting a wall region of the first partial bore 24 and / or the second partial bore 36 adjacent to the bottom surface 24a of the first partial bore 24 using a laser beam, so that the molten material solidifies to form a bore plug 42 sealing the bore 38. This can be seen in Figure 2B. Fig. 2B also that in the method described here the bore 38 is stopped so far away from the cavern 22 that no damage to the at least one MEMS component 18a and 18b arranged in the cavern 22 and / or an application-specific integrated circuit formed adjacent to the cavern 22 is to be feared.

[0030] Regarding further features of the procedure of Fig. 2A and Fig. 2B and its advantages will be discussed in the explanations regarding the Fig. Refer to 1A to 1C.

[0031] Fig. 3A and Fig. Figure 3B shows schematic representations of intermediate or final products to illustrate a third embodiment of the method for forming a bore for a cavern arranged within a semiconductor layer stack.

[0032] In contrast to the embodiment described above, the method of Fig. 3A and Fig. 3B the bore 38 is drilled into the access channel 44 extending parallel to the bore exit surface 26 through the part of the semiconductor layer stack 10, which is formed in a substrate 16 located on a side of the cavern 22 facing away from the bore exit surface 26 (see Fig. 3A). As in Fig. As can be seen in Figure 3B, the bore 38 also extends through a cavity 46 surrounded by the semiconductor layer stack 10 (even before the formation of the first partial bore 24). Preferably, the cavity 46 lies together with the cavern 22 in a common plane 48 of the semiconductor layer stack 10, but is sealed within the common plane from the cavern 22 by means of at least one partition component 50 in a particle- or airtight manner. The penetration of particles or soot generated by laser drilling into the cavern 22 via the cavity 46 is therefore not / hardly a concern. The plane 48 formed by the cavity 46 and the cavern 22 can be understood, in particular, as a plane 48 of the semiconductor layer stack 10 lying between two substrates 12 and 16, such as, specifically, the ASIC substrate 12 and the MEMS substrate 16.

[0033] Regarding further features of the procedure of Fig. 3A and Fig. 3B and its advantages will be discussed in the explanations regarding the Fig. 1 and Fig. 2 referred.

[0034] Fig. Figure 4 shows a schematic representation of an end product to illustrate a fourth embodiment of the method for forming a bore for a cavern arranged within a semiconductor layer stack.

[0035] In the embodiment described here, the bore 38 is drilled into the access channel 44, which extends parallel to the bore exit surface 26 and is framed by the cavern 22. In particular, the access channel 44 can be formed between a first material layer 52 and a second material layer 54, wherein the at least one MEMS component 18a and 18b is formed at least partially from the first material layer 52 and / or the second material layer 54.

[0036] Similarly, the access channel 44 can be formed within a (not shown) material layer from which the at least one MEMS component 18a and 18b are also at least partially formed. In these cases as well, the access channel 44 prevents unwanted ingress of particles and soot into the cavern 22.

[0037] Regarding further features of the procedure of Fig. 4 and their advantages will be discussed in the explanations regarding the Fig. 1 and Fig. 2 referred.

[0038] Although the intermediate and final products are shown as individual components in the figures above, the process steps described can also be carried out at the wafer level.

[0039] The semiconductor devices realizable by means of the present invention can be used in connection with smartphones and tablets, wearables, hearables, AR and VR, drones, gaming and toys, robots, smart homes, and in industrial contexts. Possible applications for such semiconductor devices include wake-up functions for selected device modules, detection of device orientation, screen orientation, and display orientation, detection of significant movement, shock and free-fall detection, and HMI (human-machine interface) functionality, such as...Multi-tap recognition, activity recognition, gesture recognition, context recognition and user recognition, motion control, gimbal system, altitude and attitude stabilization, flight control, image stabilization, indoor and outdoor navigation, floor detection, position tracking and route recording, PDR (pedestrian dead reckoning), dynamic route planning, boundary and obstacle detection, indoor SLAM (simultaneous localization and mapping), intrusion monitoring, real-time motion detection, real-time motion tracking, activity tracking, pedometer, calorie counter, sleep monitoring. Hearable status detection (in-ear / out-of-ear detection), head orientation and / or head movement determination, audio applications, speech recognition, keyword recognition, user recognition, active noise cancellation, logistics, part tracking, energy management, energy saving.

[0040] These applications include measurement, predictive maintenance, air quality and climate monitoring, mold detection, water level detection, and / or sensor data fusion. The semiconductor devices can also be used in connection with automotive applications. Examples include crash detection, e.g., in airbag systems, electronic stability control (ESP), vehicle dynamics control (VDC), hill start assist, hill hold control (preventing rolling backward when starting on inclines), adaptive chassis control, smart tires (e.g., road condition monitoring), road noise cancellation, navigation applications, autonomous driving, theft detection, alarm functions, tailgate tilt control, engine control optimization, and / or combustion process optimization in gasoline or diesel engines. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] DE 10 2011 103 516 A1

[0002]

Claims

[1] Method for forming a bore (38) for a cavity (22) arranged within a semiconductor layer stack (10), comprising the steps: Forming a first partial bore (24) by means of a first laser ablation step initiated on an outer surface (26) of the semiconductor layer stack (10) such that the first partial bore (24) extends, with a first mean extent (d1) aligned parallel to the outer surface (26), partially through the semiconductor layer stack (10) from the outer surface (26) and is formed on a side directed away from the outer surface (26) with a bottom surface (24a) of the first partial bore (24) lying between the outer surface (26) and the cavity (22); and Forming a second partial bore (36) by means of a second laser ablation step starting from the bottom surface (24a) of the first partial bore (24) such that the second partial bore (36) extends with a second mean extent (d2) aligned parallel to the outer surface (26) and smaller than the first mean extent (d1) through the bottom surface (24a) of the first partial bore (24) into the cavern (22) or into an access channel (44) opening at the cavern (22) or connected to the cavern (22) via a connecting channel (44a). [2] Method according to claim 1, wherein the first partial bore (24) and the second partial bore (36) are drilled through a semiconductor substrate (12) of the semiconductor layer stack (10) which delimits the cavity (22) and which is equipped with a circuit layer (14) of at least one application-specific integrated circuit on its substrate surface (12a) directed away from the outer surface (26) of the semiconductor layer stack (10). [3] Method according to claim 1, wherein the first partial bore (24) and the second partial bore (36) are drilled through a capping substrate of the semiconductor layer stack (10) delimiting the cavity (22). [4] Method according to one of the preceding claims, wherein the second partial bore (36) is drilled into the access channel (44) extending parallel to the outer surface (26) of the semiconductor layer stack (10) through a part of the semiconductor layer stack (10). [5] Method according to one of the preceding claims, wherein the first partial bore (24) and the second partial bore (36) are aligned with each other in such a way that a common central longitudinal axis (28) can be defined for the first partial bore (24) and the second partial bore (36). [6] Method according to claim 5, wherein a first length (11) of the first partial bore (24) along the common central longitudinal axis (28) is at least a factor of 2 greater than a second length (l1) of the second partial bore (36) along the common central longitudinal axis (28). [7] Method according to one of the preceding claims, wherein the first partial bore (24) is formed with the first mean extension (d1) aligned parallel to the outer surface (26), which is at least a factor of 2 greater than the second mean extension (d2) with which the second partial bore (36) is formed parallel to the outer surface (26). [8] Method for enclosing a pressure and / or a medium in a cavity (22) arranged within a semiconductor layer stack (10), comprising the steps of: Forming a bore (38) for the cavity (22) arranged within the semiconductor layer stack (10) according to the method according to one of the preceding claims; and Closing the bore (38) when the pressure and / or the medium are present in the cavern (22) by melting a wall region of the first partial bore (24) and / or the second partial bore (36) of the bore (38) adjacent to the bottom surface (24a) of the first partial bore (24) of the bore (38) by means of a laser beam. [9] Semiconductor layer stack (10) with: a cavity (22) arranged within the semiconductor layer stack (10); and a bore (38) comprising: - a first partial bore (24) with laser ablation tracks, which extends with a first mean extent (d1) aligned parallel to an outer surface (26) of the semiconductor layer stack (10) starting from the outer surface (26) partially through the semiconductor layer stack (10) and has, on a side directed away from the outer surface (26), at least remnants of a bottom surface (24a) of the first partial bore (24) lying between the outer surface (26) and the cavity (22); and - a second partial bore (36) with laser ablation tracks, which extends with a second mean extent (d2) aligned parallel to the outer surface (26) and smaller than the first mean extent (d1) through the bottom surface (24a) of the first partial bore (24) into the cavern (22) or into an access channel (44) opening into the cavern (22) or connected to the cavern (22) via a connecting channel (44a). [10] Semiconductor layer stack (10) with: a cavity (22) arranged within the semiconductor layer stack (10); and a bore closure (42) made of a melted and solidified partial material of the semiconductor layer stack (10), which lies between a first partial bore (24) with laser ablation tracks and a second partial bore (36) with laser ablation tracks; wherein the first partial bore (24) extends from the outer surface (26) with a first average extent (d1) aligned parallel to an outer surface (26) of the semiconductor layer stack (10) partially through the semiconductor layer stack (10), and the second partial bore (36) extends with a second average extent (d2) aligned parallel to the outer surface (26) and smaller than the first average extent (d1) into the cavern (22) or into an access channel (44) opening at the cavern (22) or connected to the cavern (22) via a connecting channel (44a).

Images