Semiconductor storage device

Abstract

To provide a semiconductor storage device that improves reliability of operations.SOLUTION: A memory cell array includes a laminate SST that is arranged above a substrate and in which a plurality of conductive layers 6 are laminated with an insulating layer 7 interposed therebetween, and a columnar body 40 including a first polycrystalline semiconductor film 42 extending in a lamination direction inside the laminate and a first insulating film 43 extending in the lamination direction between the plurality of conductive layers 6 and the first polycrystalline semiconductor film inside the laminate. The first polycrystalline semiconductor film includes a first portion 42a and a second portion 42b, the first portion corresponding to a first conductive layer which is a conductive layer farthest from the substrate, and the second portion corresponding to two or more conductive layers arranged between the substrate and the first conductive layer. The height of the boundary between the first portion and the second portion from the substrate is between the height of the upper surface of the first conductive layer from the substrate and the height of the upper surface of the second conductive layer from the substrate, the second conductive layer being the conductive layer farthest from the substrate among the two or more conductive layers. The average grain size of the first portion is smaller than the average grain size of the second portion.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] In a semiconductor memory device having a stack in which a plurality of conductive layers are stacked with an insulating layer interposed therebetween and a polycrystalline semiconductor film extending in the stacking direction within the stack, a plurality of memory cells are provided at a plurality of intersections where the plurality of conductive layers and the polycrystalline semiconductor film intersect. It is desirable to improve the operational reliability of the semiconductor memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-136540 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor memory device suitable for improving operational reliability. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor memory device is provided that includes a substrate, a stack, a first polycrystalline semiconductor film, and a first insulating film. The stack is disposed above the substrate. In the stack, a plurality of conductive layers are stacked with an insulating layer interposed therebetween. The first polycrystalline semiconductor film extends in the stack in the stack direction. The first insulating film extends in the stack in the stack direction between the plurality of conductive layers and the first polycrystalline semiconductor film. The first polycrystalline semiconductor film includes a first portion and a second portion. The first portion corresponds to the first conductive layer. The first conductive layer is a conductive layer farthest from the substrate among the plurality of conductive layers. The second portion corresponds to two or more conductive layers. The two or more conductive layers are disposed between the substrate and the first conductive layer among the plurality of conductive layers. The height from the substrate of the boundary between the first portion and the second portion is between the height from the substrate of the upper surface of the first conductive layer and the height from the substrate of the upper surface of the second conductive layer. The second conductive layer is a conductive layer farthest from the substrate among the two or more conductive layers. The particle size of the first portion is smaller than the particle size of the second portion. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing a configuration of a semiconductor memory device according to an embodiment. [Diagram 2] FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment. [Diagram 3] FIG. 2 is a circuit diagram showing a configuration of a memory cell array according to the embodiment. [Figure 4] 1 is a cross-sectional view showing a configuration of a memory cell array according to an embodiment. [Diagram 5] 1 is a cross-sectional view showing a configuration of a memory cell according to an embodiment. [Figure 6] 5A and 5B are diagrams showing the distribution of impurity concentrations in a semiconductor film according to an embodiment. [Figure 7] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 8] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 10]1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 11] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 12] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 13] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 14] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 15] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 16] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 17] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to a modified example of the embodiment. [Figure 18] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, a semiconductor memory device according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

[0008] (Embodiment) The semiconductor memory device according to the embodiment has a stack in which a plurality of conductive layers are stacked with an insulating layer interposed therebetween, and a polycrystalline semiconductor film extending in the stacking direction within the stack, and a plurality of memory cells are provided at a plurality of intersections where the plurality of conductive layers and the polycrystalline semiconductor film intersect. The semiconductor memory device is devised to improve the reliability of its operation.

[0009] The semiconductor memory device 1 is configured as shown in Fig. 1. Fig. 1 is a cross-sectional view showing a schematic configuration of the semiconductor memory device 1.

[0010] In the following description, the directions perpendicular to each other in a plane parallel to the surface of the substrate SUB are defined as the X-direction and the Y-direction. More specifically, the X-direction is the direction in which the word lines WL extend, and the Y-direction is the direction in which the bit lines BL extend. The Z-direction is the direction perpendicular to the surface of the substrate SUB. Therefore, the Z-direction is perpendicular to the X-direction and the Y-direction.

[0011] As shown in FIG. 1, the semiconductor memory device 1 includes select gates SGS and SGSB, word lines WL, and select gates SGDT and SGD. The select gates SGS are stacked on the source lines SL via an insulating layer 7. In the example of FIG. 1, four layers of select gates SGSB are provided, and three layers of select gates SGS are provided. The word lines WL are stacked on the top select gate SGS via the insulating layer 7. In the example of FIG. 1, the word lines WL are provided in multiple layers alternately with the insulating layers 7 along the Z direction. The select gates SGD and SGDT are stacked on the top word line WL via the insulating layer 7. In the example of FIG. 1, two layers of select gates SGD are provided, and two layers of select gates SGDT are provided. The select gates SGSB and SGS, the word lines WL, and the select gates SGD and SGDT are plate-shaped extending in the X and Y directions, respectively.

[0012] In the example of FIG. 1, the select gates SGDT, SGD, word line WL, and select gates SGS, SGSB are divided and insulated in the Y direction by slits ST. The source line may have a two-layer structure. The two-layer structure includes a stack of source lines BSL and SL. The source lines BSL and SL are stacked in order on the +Z side of the substrate SUB via an interlayer insulating film 81. The source line BSL is in contact with the -Z side surface of the source line SL to reduce the resistance of the source line SL. The slits ST are provided on the +Z side of the source line SL and extend in the X and Z directions.

[0013] The selection gate SGD is divided in the Y direction, for example, by a dividing film SHE (not shown). The dividing film SHE is provided above (on the +Z side of) the word line WL, and extends in the X and Z directions.

[0014] The substrate SUB is, for example, a silicon substrate. The select gate SGS, the word line WL, and the select gate SGD are, for example, metal layers containing tungsten (W). The insulating layer 7 and the interlayer insulating film 81 are, for example, insulators containing silicon oxide.

[0015] The semiconductor memory device 1 further includes a plurality of pillars 40. The pillars 40 extend in the Z direction, which is the stacking direction of the select gate SGS, the word line WL, and the select gate SGD. The semiconductor memory device 1 further includes a plurality of bit lines BL provided above the select gate SGD.

[0016] The pillars 40 are each electrically connected to a bit line BL via a contact plug 31. For example, one of the pillars 40 sharing the select gate SGD0 and one of the pillars 40 sharing the select gate SGD1 are electrically connected to one bit line BL.

[0017] An interlayer insulating film 83 is provided between the pillar 40 and the bit line BL. An interlayer insulating film 82 is provided between the interlayer insulating film 83 and the selection gate SGD. The contact plug 31 penetrates the interlayer insulating film 83. The -Z side end of the contact plug 31 is connected to the semiconductor film of the pillar 40, and the +Z side end is connected to the bit line BL.

[0018] In the semiconductor memory device 1, the select gate SGD, the word line WL, and the select gate SGS are each composed of a conductive layer. A stacked body SST in which conductive layers and insulating layers 7 are alternately stacked is composed on the +Z side of the source line SL. The stacked body SST is penetrated by pillars 40 to form a three-dimensional arrangement of memory cells (a memory cell array).

[0019] That is, in the semiconductor memory device 1, the portions where the word lines WL and the pillars 40 intersect are configured to function as memory cells, and a memory cell array 2 is configured in which a plurality of memory cells are arranged three-dimensionally. Also, the portions where the select gates SGS and the pillars 40 intersect function as source-side select gates, and the portions where the select gates SGD and the pillars 40 intersect function as drain-side select gates. In the semiconductor memory device 1, by increasing the number of word lines WL in the stack SST, it is possible to increase the memory capacity without using finer patterning technology.

[0020] FIG. 2 is a block diagram showing a schematic configuration of the semiconductor memory device 1. As shown in FIG.

[0021] 2, the semiconductor memory device 1 includes a memory cell array 2, a peripheral circuit 100, and an interface 200. The peripheral circuit 100 includes a WL driving circuit 110, an SGS driving circuit 120, an SGD driving circuit 130, a SL driving circuit 140, and a sense amplifier circuit 150.

[0022] The WL driving circuit 110 is a circuit that controls the voltage applied to the word line WL, the SGS driving circuit 120 is a circuit that controls the voltage applied to the select gates SGS and SGSB, the SGD driving circuit 130 is a circuit that controls the voltage applied to the select gates SGD and SGDT, and the SL driving circuit 140 is a circuit that controls the voltage applied to the source line SL, and the sense amplifier circuit 150 is a circuit that controls the voltage applied to the bit line BL and is also a circuit that determines the data read out in response to a signal from a selected memory cell.

[0023] The peripheral circuit 100 controls the operation of the semiconductor memory device 1 based on an instruction input via the interface 200 from the outside (for example, a memory controller of a memory system to which the semiconductor memory device 1 is applied).

[0024] Next, the circuit configuration of the memory cell array 2 will be described with reference to Fig. 3. Fig. 3 is a circuit diagram showing the configuration of the memory cell array 2.

[0025] The memory cell array 2 has a plurality of blocks BLK, each of which is a collection of a plurality of memory cell transistors MT. Hereinafter, the memory cell transistors MT will be simply referred to as memory cells MT.

[0026] Each block BLK has multiple string units SU0, SU1, SU2, and SU3, which are a set of memory cells MT associated with word lines WL and bit lines BL. Each string unit SU0 to SU3 has multiple memory strings MST in which memory cells MT are connected in series. The number of memory strings MST in the string units SU0 to SU3 is arbitrary.

[0027] The string units SU0, SU1, SU2, and SU3 correspond to the select gates SGD0, SGD1, SGD2, and SGD3, share the select gate SGS, and function as drive units in the block BLK. Each string unit SU can be driven by its corresponding select gate SGD and select gate SGS. Each string unit SU includes a plurality of memory strings MST.

[0028] Each memory string MST includes, for example, eleven memory cells MT (MT0 to MT10) and select transistors DGT and SGT. The memory cells MT have a control gate and a charge storage film, and retain and store data in a non-volatile manner. The eleven memory cells MT are connected in series between the source of the select transistor DGT and the drain of the select transistor SGT. The number of memory cells MT in the memory string MST is not limited to eleven.

[0029] The gates of the selection transistors DGTb in the string units SU0 to SU3 are connected to the selection gates SGD0T to SGD3T, respectively. The gates of the selection transistors DGTa in the string units SU0 to SU3 are connected to the selection gates SGD0 to SGD3, respectively. In contrast, the gates of the selection transistors SGTa in each string unit SU are commonly connected to, for example, the selection gate SGS. The gates of the selection transistors SGTb in each string unit SU are commonly connected to, for example, the selection gate SGSB.

[0030] The drains of the select transistors DGT of each memory string MST in each string unit SU are connected to different bit lines BL0 to BLk (k is any integer equal to or greater than 2). The bit lines BL0 to BLk commonly connect one memory string MST in each string unit SU across multiple blocks BLK. Furthermore, the sources of the select transistors SGT are commonly connected to a source line SL.

[0031] That is, the string unit SU is a set of memory strings MST connected to different bit lines BL0 to BLk and connected to the same select gate SGD. Each block BLK is a set of multiple string units SU0 to SU3 that share a word line WL. The memory cell array 2 is a set of multiple blocks BLK that share the bit lines BL0 to BLk.

[0032] Furthermore, if a group of memory cells MT sharing a word line WL is referred to as a "memory cell group MCG," the memory cell group MCG is the smallest unit of a collection of memory cells MT to which a predetermined voltage (e.g., a write voltage, a read voltage) can be applied collectively via the word line WL.

[0033] Next, the cross-sectional configuration of the memory cell array 2 will be described with reference to Fig. 4. Fig. 4 is a YZ cross-sectional view showing the configuration of the memory cell array 2, and is an enlarged cross-sectional view of a portion A in Fig. 1.

[0034] In the semiconductor memory device 1, a source line SL (see FIG. 1) is disposed on the +Z side of the substrate SUB. A plurality of columns 40 are arranged in the XY direction. Each column 40 extends in the Z direction and penetrates the stacked body SST.

[0035] The columnar body 40 shown in FIG. 4 has a columnar shape having a central axis CA along the Z direction, for example, a substantially cylindrical shape. FIG. 4 illustrates a portion of the columnar body 40 near the -Z side end. The columnar body 40 may have a tapered shape in which the diameter of the -Z side end is narrower than the diameter of the +Z side end. The columnar body 40 may have a bowing shape in which the diameter of the -Z side end is narrower than the diameter of the +Z side end and the diameter is wider at a predetermined Z position between the +Z side end and the -Z side end. The diameter of the -Z side end of the columnar body 40 is smaller than the diameter of the +Z side end of the columnar body 40.

[0036] 4 and 5, the columnar body 40 has, in order from the central axis CA side, a core member 41, a polycrystalline semiconductor film 42, and an insulating film 43. The insulating film 43 is a multilayer film including, in order from the central axis CA side, an insulating film 43a, a charge storage film 43b, and an insulating film 43c. Fig. 5 is an XY cross-sectional view showing the configuration of a memory cell, showing a cross section when Fig. 4 is cut along line BB.

[0037] The core member 41 has a generally cylindrical shape disposed in the vicinity of the central axis CA of the columnar body 40 and extending along the central axis CA of the columnar body 40. The core member 41 may be formed of a material containing an insulator (for example, a semiconductor oxide such as silicon oxide) as a main component.

[0038] The polycrystalline semiconductor film 42 is disposed so as to surround the core member 41 from the outside, and has a generally cylindrical shape extending along the central axis CA of the columnar body 40. The polycrystalline semiconductor film 42 may be formed of a material mainly composed of a semiconductor (e.g., polysilicon) that does not substantially contain impurities.

[0039] The insulating film 43a is disposed so as to surround the polycrystalline semiconductor film 42 from the outside, and has a generally cylindrical shape extending along the central axis CA of the columnar body 40. The insulating film 43a may be made of a material containing an oxide (e.g., silicon oxide or silicon oxynitride) as a main component.

[0040] The charge storage film 43b is disposed so as to surround the insulating film 43a from the outside and has a substantially cylindrical shape extending along the central axis CA of the columnar body 40. The charge storage film 43b may be formed of a material containing nitride (for example, silicon nitride) as a main component.

[0041] The insulating film 43c is disposed so as to surround the charge storage film 43b from the outside and has a generally cylindrical shape extending along the central axis CA of the columnar body 40. The insulating film 43c may be formed of a material mainly composed of an oxide (e.g., silicon oxide, metal oxide, or a laminate of these). This may form an ONO-type three-layer structure in which the charge storage film 43b is sandwiched between a pair of insulating films 43a and 43c.

[0042] The insulating film 8 covers the insulating film 43c from the outside in the XY directions, and extends to cover the +Z side surface of the conductive layer 6, the surface on the columnar body 40 side, and the -Z side surface of the conductive layer 6, forming a substantially hollow disk shape having an axis along the Z direction. The insulating film 8 may be made of an insulating material such as aluminum oxide. In the following, for simplification, illustration and description of the insulating film 8 may be omitted.

[0043] As shown in FIG. 4, the pillar 40 further includes a polycrystalline semiconductor film 44.

[0044] The polycrystalline semiconductor film 44 has a generally cylindrical shape disposed near the central axis CA of the columnar body 40 and extending along the central axis CA of the columnar body 40. The outer diameter of the polycrystalline semiconductor film 44 corresponds to the outer diameter of the polycrystalline semiconductor film 42. The polycrystalline semiconductor film 44 is disposed between the core member 41 and the polycrystalline semiconductor film 42 and the contact plug 31. The -Z side end face of the polycrystalline semiconductor film 44 covers the -Z side end of the core member 41 and the -Z side end of the polycrystalline semiconductor film 42, and the +Z side end face contacts the contact plug 31.

[0045] The polycrystalline semiconductor film 42 of the pillar 40 is connected to the source line SL (see FIG. 1) on the -Z side, and is connected to the bit line BL (see FIG. 1) on the +Z side via the polycrystalline semiconductor film 44 and the contact plug 31. That is, the polycrystalline semiconductor film 42 of the pillar 40 includes a channel region (active region) in the memory string MST.

[0046] In the laminate SST, conductive layers 6 and insulating layers 7 are alternately and repeatedly laminated. Each conductive layer 6 extends in a plate shape in the XY direction. Each conductive layer 6 may be formed of a material mainly composed of a conductive material (e.g., a metal such as tungsten). Each conductive layer 6 may be covered with an insulating film 8 on the +Z side surface, the -Z side surface, and the surface facing the columnar body 40. The insulating film 8 may have a different composition from the insulating film 43c. The insulating film 8 may be formed of a material mainly composed of an insulator (e.g., a metal oxide such as aluminum oxide, zirconium oxide, or hafnium oxide). Each insulating layer 7 extends in a plate shape in the XY direction. Each insulating layer 7 may be formed of a material mainly composed of an insulator (e.g., a semiconductor oxide such as silicon oxide).

[0047] In the stacked body SST, of the multiple conductive layers 6 arranged spaced apart from each other in the Z direction, the conductive layer 6 on the -Z side functions as select gates SGSB and SGS (see FIG. 1), the conductive layer 6 on the +Z side functions as select gates SGDT and SGD (see FIG. 1), and the conductive layer 6 therebetween functions as a word line WL. In FIG. 4, a configuration is illustrated in which, from the -Z side, the conductive layer 6 of the select gate SGSB1, the conductive layer 6 of the select gate SGSB2, the conductive layer 6 of the select gate SGSB3, the conductive layer 6 of the select gate SGSB4, the conductive layer 6 of the select gate SGS1, the conductive layer 6 of the select gate SGS2, and the conductive layer 6 of the select gate SGS3 are stacked.

[0048] A select transistor DGTb0 is formed at a position where the conductive layer 6 of the select gate SGDT0 intersects with the polycrystalline semiconductor film 42. A select transistor SGTb1 is formed at a position where the conductive layer 6 of the select gate SGDT1 intersects with the polycrystalline semiconductor film 42.

[0049] A select transistor DGTa0 is formed at a position where the conductive layer 6 of the select gate SGD0 intersects with the polycrystalline semiconductor film 42 and the charge storage film 43b. A select transistor DGTa1 is formed at a position where the conductive layer 6 of the select gate SGD1 intersects with the polycrystalline semiconductor film 42.

[0050] A memory cell MT0 is formed at a position where the conductive layer 6 of the word line WL0 intersects with the polycrystalline semiconductor film 42 and the charge storage film 43b. A memory cell MT1 (see FIG. 3) is formed at a position where the conductive layer 6 of the word line WL1 (see FIG. 1) intersects with the polycrystalline semiconductor film 42 and the charge storage film 43b. A memory cell MT10 is formed at a position where the conductive layer 6 of the word line WL10 intersects with the polycrystalline semiconductor film 42 and the charge storage film 43b.

[0051] At the position where the conductive layer 6 of the select gate SGS (see FIG. 1) intersects with the polycrystalline semiconductor film 42, a select transistor SGTa (see FIG. 3) is formed.

[0052] At the position where the conductive layer 6 of the select gate SGSB (see FIG. 1) intersects with the polycrystalline semiconductor film 42, a select transistor SGTb (see FIG. 3) is formed.

[0053] In addition, the charge storage film 43b and the insulating film 43c may be partially omitted from the columnar body 40 at positions where the columnar body 40 intersects with the conductive layers 6 of the selection gates SGD and SGDT.

[0054] As shown in FIG. 4, the polycrystalline semiconductor film 42 of each pillar 40 has a portion 42a and a portion 42b.

[0055] The portion 42a has a generally cylindrical shape that is disposed so as to surround the core member 41 from the outside and extends along the central axis CA of the columnar body 40.

[0056] The portion 42a corresponds to the conductive layer 6 on the +Z side (for example, the conductive layer 6 of the select gate SGDT0) among the multiple conductive layers 6 in the stack SST. The conductive layer 6 on the +Z side among the multiple conductive layers 6 can also be rephrased as the conductive layer 6 farthest from the substrate SUB (see FIG. 1) among the multiple conductive layers 6.

[0057] Portion 42a is a portion from the +Z side end of polycrystalline semiconductor film 42 to a Z position corresponding to the most +Z conductive layer 6. The Z position corresponding to the most +Z conductive layer 6 may be a Z position between the Z position of the +Z side surface of the most +Z conductive layer 6 and the Z position of the +Z side surface of the conductive layer 6 that is second most +Z side.

[0058] The portion 42a contacts the polycrystalline semiconductor film 44 on the +Z side, and contacts the portion 42b on the -Z side. The portion 42a may be integrally continuous with the portion 42b on the -Z side.

[0059] The portion 42b corresponds to the remaining conductive layer 6 other than the one on the +Z side among the multiple conductive layers 6 in the stack SST (for example, the conductive layer 6 of the selection gate SGDT1 to the conductive layer 6 of the selection SGSB). The remaining conductive layer 6 other than the one on the +Z side among the multiple conductive layers 6 can also be rephrased as two or more conductive layers 6 arranged between the substrate SUB (see FIG. 1) and the conductive layer 6 on the +Z side among the multiple conductive layers 6.

[0060] The portion 42b is a portion of the polycrystalline semiconductor film 42 from the Z position corresponding to the conductive layer 6 on the most +Z side to the -Z end.

[0061] The portion 42b contacts the portion 42a on the +Z side. The portion 42b may be integrally continuous with the portion 42a on the +Z side.

[0062] The Z height from the substrate SUB of the boundary between portions 42a and 42b may be between the Z height from the substrate SUB of the upper surface (+Z side surface) of the conductive layer 6 that is most +Z side among the multiple conductive layers 6 and the Z height from the substrate SUB of the upper surface (+Z side surface) of the conductive layer 6 that is second most +Z side.

[0063] For example, the Z height from the substrate SUB of the boundary between the portion 42a and the portion 42b may be equal to the Z height from the substrate SUB of the lower surface (-Z side surface) of the conductive layer 6 on the most +Z side among the multiple conductive layers 6.

[0064] The portions 42a and 42b may each be formed of a material containing a polycrystalline semiconductor (eg, polysilicon) as a main component. The average grain size d1 of the portion 42a is smaller than the average grain size d2 of the portion 42b.

[0065] The method for determining the average particle size is not particularly limited, and may be, for example, the average particle size measured using a flow-type particle image analyzer, a particle size distribution measuring device using a laser diffraction / scattering method, etc. Alternatively, the average particle size may be calculated from a transmission electron microscope (TEM) image using the Intercept method (also called the Heyn method) or the Planimetric method (also called the Jeffries method).

[0066] Alternatively, the average grain size may be calculated using ACOM-TEM (Automated Crystal Orientation Mapping in TEM) analysis. In ACOM-TEM analysis, the polycrystalline semiconductor film 42 is sliced ​​in a direction perpendicular to the central axis CA to create a semicircular sample, which is then analyzed in a field of view of about 5 nm x 5 nm, and an azimuth angle difference of less than 5° is determined to be the same grain size. The in-plane average grain size obtained by ACOM-TEM analysis under these conditions is used. The average grain size is calculated using the grain size averaged within a field of view of about 5 nm x 5 nm.

[0067] For example, the crystal grains included in the polycrystalline semiconductor film 42 may have twin crystals. When the twin boundary is not regarded as a grain boundary, the total number of grains is N, and the grain diameter (circle equivalent diameter) of each grain is d i Then, d calculated by the following formula 1 may be defined as the average particle size. In this case, the average particle size of portion 42a may be less than 80 nm, and the average particle size of portion 42b may be 80 nm or more.

number

[0068] When twin boundaries are considered as grain boundaries, the total number of grains is N, and the grain diameter (circle equivalent diameter) of each grain is d i When d′ is used, the average particle diameter may be calculated by the following formula 2: In this case, the average particle diameter of portion 42a may be less than 30 nm, and the average particle diameter of portion 42b may be 30 nm or more.

number

[0069] The average grain size d3 of the polycrystalline semiconductor film 44 may be larger than the average grain size d1 of the portion 42a. The average grain size d3 of the polycrystalline semiconductor film 44 may be larger than the average grain size d2 of the portion 42b.

[0070] In a process of writing information to a memory cell MT, a write voltage is applied to the conductive layer 6 of a selected word line WL, a transfer voltage is applied to the conductive layer 6 of an unselected word line WL, a reference voltage is applied to the polycrystalline semiconductor film 42, a selection voltage is applied to the select gate lines SGD and SGDT of a selected string, and a reference voltage is applied to the select gate lines SGS and SGSB. The write voltage has a potential (e.g., 20 V) for injecting charges (electrons) of the polycrystalline semiconductor film 42 into the charge storage film 43b. The transfer voltage has a potential (e.g., 10 V) between the write voltage and the reference voltage. The reference voltage has a reference potential (e.g., 0 V). The selection voltage has a potential (e.g., 2.5 V) that turns on the select transistors DGTa and DGTb, and the reference voltage has a potential that turns off the select transistors SGTa and SGTb. As a result, charges are stored in the charge storage film 43b of the selected memory cell MT at the position where the conductive layer 6 of the selected word line WL intersects with the polycrystalline semiconductor film 42, and information is written to the selected memory cell MT.

[0071] In the process of erasing information from the memory cell MT, a reference voltage is applied to the conductive layer 6 of each word line WL, an erase voltage is applied to the polycrystalline semiconductor film 42, a select voltage is applied to the select gates SGS and SGSB, and an intermediate voltage between the two is applied to the select gates SGD and SGDT. The erase voltage has a potential (e.g., 20V) for injecting opposite charges (holes) of the polycrystalline semiconductor film 42 into the charge storage film 43b. The reference voltage has a reference potential (e.g., 0V). The select voltage has a potential (e.g., 20V) that turns off the select transistors SGTa and SGTb, and the intermediate voltage has a potential (e.g., 5V) between the erase process and the reference voltage. By such control, electron-hole pairs are generated by GIDL (Gate Induced Drain Leakage) near the drain of the select transistor SGTb, and the opposite charges (holes) are injected from the polycrystalline semiconductor film 42 into the charge storage film 43b. This erases the charge stored in the charge storage film 43b, and the information in the memory cell MT can be erased.

[0072] In the erase process, the select transistor DGTb corresponding to the select gate SGDT has the function of generating GIDL, and the select transistor DGTa corresponding to the select gate SGD has the function of electrically connecting / disconnecting the polycrystalline semiconductor film 42 and the bit line BL.

[0073] During the manufacture of the semiconductor memory device 1, the N-type impurities (e.g., phosphorus) contained in the polycrystalline semiconductor film 44 diffuse into the polycrystalline semiconductor film 42. Accordingly, the concentration of the N-type impurities in the polycrystalline semiconductor film 42 is relatively high in the portion 42a as shown by the solid line in FIG. 6(a), but tends to decrease toward the Z position Zb at the boundary between the portion 42a and the portion 42b.

[0074] Fig. 6 is a diagram showing the distribution of impurity concentration in the polycrystalline semiconductor film 42. Fig. 6(a) shows the distribution of the N-type impurity concentration in the polycrystalline semiconductor film 42 in the Z direction, with the vertical axis showing the N-type impurity concentration and the horizontal axis showing the Z position. Fig. 6(b) shows the YZ cross section of the polycrystalline semiconductor film 42 corresponding to the horizontal axis (Z position) in Fig. 6(a).

[0075] At this time, as described above, the average grain size of the portion 42a in the polycrystalline semiconductor film 42 is smaller than the average grain size of the portion 42b. This allows the amount of N-type impurity diffusion from the polycrystalline semiconductor film 44 to the portion 42a and the portion 42b to be appropriately controlled. The diffusion distance in the Z direction of the N-type impurity from the polycrystalline semiconductor film 44 in the polycrystalline semiconductor film 42 is equal to the distance in the Z direction from the interface between the polycrystalline semiconductor film 44 and the polycrystalline semiconductor film 42 to the boundary (Z position Zb).

[0076] 6(a), in the polycrystalline semiconductor film 42, the channel region of the select gate SGDT may contain N-type impurities at a concentration equal to or higher than the threshold concentration Cth, but the channel region of the select gate SGD has N-type impurities suppressed to a concentration less than the threshold concentration Cth. This makes it possible to efficiently generate GIDL in the select gate SGDT during the erase process, and also allows the select gate SGD to be turned on and off appropriately.

[0077] The method for determining the impurity concentration is not particularly limited, but may be, for example, a concentration measured using a SIMS (Secondary Ion Mass Spectrometry) device.

[0078] Next, a method for manufacturing the semiconductor memory device 1 will be described with reference to Figures 7 to 16 and Figure 4. Figures 7 to 16 are YZ cross-sectional views showing a method for manufacturing the semiconductor memory device 1. Figure 4 is a YZ cross-sectional view showing the structure of the semiconductor memory device 1, but is also used as a cross-sectional view showing the manufacturing method.

[0079] 7, a transistor is formed in a substrate SUB (see FIG. 1), and contact plugs, wiring films, via plugs, etc. are formed on the substrate SUB, and an interlayer insulating film 81 is formed around them. This forms the peripheral circuit 100. The interlayer insulating film 81 can be formed by depositing a material mainly composed of an insulator (for example, a semiconductor oxide such as silicon oxide) on the +Z side of the substrate SUB.

[0080] A layer of the source line BSL is deposited on the +Z side of the interlayer insulating film 81. The layer of the source line BSL may be formed of a material mainly composed of a semiconductor (e.g., silicon) containing N-type impurities (e.g., phosphorus or arsenic).

[0081] A layer of the source line SL is deposited on the +Z side of the layer of the source line BSL. The layer of the source line SL may be formed of a material mainly composed of a semiconductor (e.g., silicon) containing an N-type impurity (e.g., phosphorus or arsenic).

[0082] On the +Z side of the layer of the source line SL, the insulating layer 7i and the sacrificial layer 13i are alternately deposited multiple times to form a stacked body SSTi. The insulating layer 7i may be formed of a material mainly composed of an oxide (e.g., silicon oxide). The sacrificial layer 13i may be formed of a material mainly composed of a nitride (e.g., silicon nitride). Each insulating layer 7i and each sacrificial layer 13i may be deposited to have approximately the same film thickness.

[0083] An interlayer insulating film 82i is deposited on the +Z side of the sacrificial layer 13i on the most +Z side in the stacked body SSTi. The interlayer insulating film 82i may be made of a material containing an oxide (for example, silicon oxide) as a main component.

[0084] 8, a resist pattern having an opening corresponding to the position for forming the memory hole 26 is formed on the stacked body. Using the resist pattern as a mask, anisotropic etching such as RIE (Reactive Ion Etching) is performed to form the memory hole 26 that penetrates the interlayer insulating film 82, the stacked body SSTj, and the layer of the source line SL (see FIG. 1) and reaches the layer of the source line BSL.

[0085] In the process shown in FIG. 9, an insulating film 43ci, a charge storage film 43bi, and an insulating film 43ai (see FIG. 4) are sequentially deposited on the side surface and the bottom surface of the memory hole 26. The insulating film 43ci can be formed of a material mainly composed of an oxide (for example, silicon oxide, metal oxide, or a laminate thereof). The charge storage film 43bi can be formed of a material mainly composed of a nitride (for example, silicon nitride). The insulating film 43ai can be formed of a material mainly composed of an oxide (for example, silicon oxide or silicon oxynitride).

[0086] In the process shown in FIG. 10, a polycrystalline semiconductor film 42i is deposited on the side surface and the bottom surface of the memory hole 26. The polycrystalline semiconductor film 42i can be formed of a material mainly composed of a substantially impurity-free polycrystalline semiconductor (for example, polysilicon). The film thickness of the polycrystalline semiconductor film 42i is controlled by film formation conditions and the like.

[0087] For example, the polycrystalline semiconductor film 42i is deposited under film formation conditions (for example, gas flow rate, film formation time) such that the film thickness in a YZ cross-sectional view including the central axis CA is D42i.

[0088] Note that there is a correlation between the film thickness of the polycrystalline semiconductor film and its average grain size. The larger the film thickness of the polycrystalline semiconductor film, the larger the average grain size tends to be. The film thickness D42i of the polycrystalline semiconductor film 42i shown in FIG. 10 corresponds to the average grain size d2. The average grain size d2 is the average grain size of a portion 42b (see FIG. 4) formed in a later process.

[0089] In the process shown in FIG. 11, the polycrystalline semiconductor film 42i is thinned by isotropic etching such as wet etching to form a polycrystalline semiconductor film 42j. The etching amount of the isotropic etching is controlled by etching conditions and the like.

[0090] For example, the polycrystalline semiconductor film 42j is etched under etching conditions (for example, etching time) such that the film thickness in a YZ cross-sectional view including the central axis CA is D42j (<D42i).

[0091] Note that the film thickness D42j of the polycrystalline semiconductor film 42i shown in FIG. 11 corresponds to the average particle diameter d1 (<d2). The average particle diameter d1 is the average particle diameter of the portion 42a (see FIG. 4) formed in a later process.

[0092] In the process shown in FIG. 12, the core member 41 is embedded in the memory hole 26. The core member 41 can be formed of a material mainly composed of an insulator (for example, a semiconductor oxide such as silicon oxide). Thereby, a columnar body 40i (see FIG. 1) that penetrates the stacked body SSTj and the layer of the source line SL and reaches the layer of the source line BSL is formed.

[0093] Note that the core member 41 may be embedded in the memory hole 26 such that the Z height of the +Z side end of the core member 41 is lower than the Z height of the +Z side ends of the insulating film 43ci, the charge storage film 43bi, the insulating film 43ai, and the polycrystalline semiconductor film 42j. Thereby, a recess 261 surrounded by the inner surface of the polycrystalline semiconductor film 42j and the +Z side surface of the core member 41 is formed. The recess 261 is a space on a substantially cylinder.

[0094] In the process shown in FIG. 13, the polycrystalline semiconductor film 44i is embedded in the recess 261. The polycrystalline semiconductor film 44i can be formed of a material mainly composed of a polycrystalline semiconductor (for example, polysilicon) containing an impurity (for example, phosphorus).

[0095] Note that the XY direction width D44i of the polycrystalline semiconductor film 44i corresponds to the average particle diameter d3. The XY direction width D44i is larger than the film thickness D42j (see FIG. 11) and larger than the film thickness D42i (see FIG. 10). Accordingly, the average particle diameter d3 is larger than the average particle diameter d1 and larger than the average particle diameter d2.

[0096] In the process shown in FIG. 14, by a particle implantation method or the like, predetermined particles are introduced to a predetermined Z position in the polycrystalline semiconductor film 42j, a portion 42ak up to the predetermined Z position in the polycrystalline semiconductor film 42k is amorphized, and a portion 42bk deeper than the predetermined Z position remains in a polycrystalline state without being amorphized.

[0097] The predetermined particles include any particles suitable for amorphization. The predetermined particles may be arsenic ions or argon molecules. The predetermined Z position may be a Z position between the Z position of the +Z side surface of the sacrificial layer 13 on the most +Z side and the Z position of the +Z side surface of the sacrificial layer 13 on the second most +Z side. When a particle implantation method is used, the predetermined Z position may be controlled by the acceleration voltage of the particle implantation.

[0098] 15, the columnar body 40i is heat-treated. As a result, the amorphous portion 42ak of the polycrystalline semiconductor film 42i is crystallized to become the side portion of the polycrystalline semiconductor film 44 and the polycrystalline portion 42a of the polycrystalline semiconductor film 42. The polycrystalline portion 42bk of the polycrystalline semiconductor film 42i becomes the polycrystalline portion 42b of the polycrystalline semiconductor film 42 almost as it is.

[0099] Here, when the portion 42a is crystallized, the average grain size becomes d1 according to the film thickness D42j (see FIG. 11). The portion 42b remains almost the same, and the average grain size remains d2. The film thickness D42j is thinner than the film thickness D42i (see FIG. 10). Accordingly, the average grain size d1 of the portion 42a becomes smaller than the average grain size d2 of the portion 42b.

[0100] The average grain size d3 of the polycrystalline semiconductor film 44 is larger than the average grain size d1 of the portion 42a and larger than the average grain size d2 of the portion 42b.

[0101] 16, the sacrificial layer 13 in the stacked body SSTj is removed by isotropic etching such as wet etching, and a void 28 is formed. Then, an insulating film 8 (see FIG. 4) is formed to cover the exposed surface of the void 28. The insulating film 8 can be made of an insulator such as aluminum oxide.

[0102] 4, a conductive material is embedded in the gap 28 to form a conductive layer 6. The conductive layer 6 is made of a material mainly composed of a metal such as tungsten. This forms a stacked body SST in which insulating layers 7 and conductive films 6 are alternately stacked. That is, a semiconductor memory device 1 including the stacked body SST is formed.

[0103] As described above, in the embodiment, the polycrystalline semiconductor film 42 is provided in the semiconductor memory device 1, extending in the Z direction in the stacked body SST in which the conductive layers 6 and the insulating layers 7 are alternately and repeatedly stacked. In the polycrystalline semiconductor film 42, the average grain size d1 of the portion 42a corresponding to the conductive layer 6 on the most +Z side (e.g., the conductive layer 6 of the select gate SGDT0) is smaller than the average grain size d2 of the portion 42b corresponding to the remaining conductive layers 6 other than the most +Z side (e.g., the conductive layer 6 of the select gate SGDT1, the conductive layer 6 of the select gate SGD0, the conductive layer 6 of the select gate SGD1, . . . , the conductive layer 6 of the select gate SGSB). This allows the amount of diffusion of N-type impurities from the polycrystalline semiconductor film 44 to the portion 42a and the portion 42b to be appropriately controlled. As a result, the GIDL generation in the select gate SGDT during the erase process can be made more efficient, and the select gate SGD can be appropriately turned on and off, thereby improving the reliability of the operation of the semiconductor memory device 1.

[0104] For example, when the average grain size of the polycrystalline semiconductor film 42 is uniformly relatively large from the +Z end to the -Z end (for example, the average grain size is d2), the diffusion length of the N-type impurity from the polycrystalline semiconductor film 44 to the polycrystalline semiconductor film 42 tends to vary greatly.

[0105] In the polycrystalline semiconductor film 42, the diffusion length of N-type impurities diffusing through grain boundaries tends to be long, whereas the diffusion length of N-type impurities diffusing through grain interiors tends to be short. If the average grain size of the polycrystalline semiconductor film 42 is uniformly relatively large, the effect of variations in diffusion paths tends to be large. In other words, the ratio of N-type impurities diffusing through grain interiors to N-type impurities diffusing through grain boundaries tends to be large, and the variation in diffusion length of N-type impurities due to differences in diffusion paths tends to be large.

[0106] This tendency can become more pronounced due to the influence of variations in the Z height of the core member 19. For example, when the Z height of the core member 19 is relatively high, the Z distance from the +Z side end of the core member 19 to the desired Z position Zb (see FIG. 6(a)) becomes longer, making it difficult to diffuse to the desired Z position Zb. When the Z height of the core member 19 is relatively low, the Z distance from the +Z side end of the core member 19 to the desired Z position Zb (see FIG. 6(a)) becomes shorter, making it easier to diffuse to the desired Z position Zb.

[0107] Due to the variation in the diffusion length of the N-type impurities, the amount of N-type impurities diffused from the polycrystalline semiconductor film 44 to the polycrystalline semiconductor film 42 may become excessive.

[0108] 6(a), N-type impurities are contained at a threshold concentration Cth or more in the channel region of the select gate SGD in the polycrystalline semiconductor film 42. This may cause the select gate SGD to be turned on when not selected, making it difficult to properly turn the select gate SGD on and off, and thus deteriorating the reliability of the operation of the semiconductor memory device 1.

[0109] Alternatively, the amount of N-type impurities diffused from the polycrystalline semiconductor film 44 to the polycrystalline semiconductor film 42 may be insufficient due to variations in the diffusion length of the N-type impurities.

[0110] 6(a), in the polycrystalline semiconductor film 42, the N-type impurity is suppressed to a threshold concentration Cth or less in the channel region of the select gate SGDT. This may result in insufficient GIDL generation in the select gate SGDT during the erase process, leading to erase failures and other problems that make it difficult to properly perform the erase process, and may degrade the reliability of the operation of the semiconductor memory device 1.

[0111] On the other hand, in the embodiment, the average grain size d1 of the portion 42a in the polycrystalline semiconductor film 42 is smaller than the average grain size d2 of the portion 42b. This allows the amounts of N-type impurities diffused from the polycrystalline semiconductor film 44 to the portion 42a and the portion 42b to be appropriately controlled.

[0112] In the polycrystalline semiconductor film 42, the influence of the variation in the diffusion path can be reduced. That is, the ratio of the N-type impurities diffusing through the grain interior to the N-type impurities diffusing through the grain boundaries becomes smaller, and the variation in the diffusion length of the N-type impurities due to the difference in the diffusion path can be reduced. This reduces the influence of the variation in the Z height of the core member 19.

[0113] 6(a), in the polycrystalline semiconductor film 42, the channel region of the select gate SGDT contains N-type impurities at a concentration equal to or higher than the threshold concentration Cth, but the channel region of the select gate SGD contains N-type impurities at a concentration less than the threshold concentration Cth. As a result, the generation of GIDL in the select gate SGDT during the erase process can be made more efficient, and the select gate SGD can be turned on and off appropriately, thereby improving the reliability of the operation of the semiconductor memory device 1.

[0114] As a modification of the embodiment, in the method for manufacturing the semiconductor memory device 1, the order of the step of partially amorphizing the polycrystalline semiconductor film 42j and the step of filling the recesses 261 with the polycrystalline semiconductor film 44i may be interchanged.

[0115] For example, instead of the steps shown in Figures 13 and 14, steps shown in Figures 17 to 18 may be performed. Figures 17 to 18 are YZ cross-sectional views showing a manufacturing method of a semiconductor memory device 1 according to a modification of the embodiment.

[0116] 7 to 12 are performed in the same manner as in the embodiment, and then the process shown in Fig. 17 is performed. In the process shown in Fig. 17, predetermined particles are introduced into the polycrystalline semiconductor film 42j up to a predetermined Z position by a particle injection method or the like, a portion 42ak of the polycrystalline semiconductor film 42k up to the predetermined Z position is made amorphous, and a portion 42bk deeper than the predetermined Z position is left in a polycrystalline state without being made amorphous.

[0117] The predetermined particles include any particles suitable for amorphization. The predetermined particles may be arsenic ions or argon molecules. The predetermined Z position may be a Z position between the Z position of the +Z side surface of the sacrificial layer 13 on the most +Z side and the Z position of the +Z side surface of the sacrificial layer 13 on the second most +Z side. When a particle implantation method is used, the predetermined Z position may be controlled by the acceleration voltage of the particle implantation.

[0118] 18, a polycrystalline semiconductor film 44i is filled into the recess 261. The polycrystalline semiconductor film 44i may be made of a material containing, as a main component, a polycrystalline semiconductor (eg, polysilicon) containing impurities (eg, phosphorus).

[0119] The width D44i in the XY direction of the polycrystalline semiconductor film 44i corresponds to the average grain size d3. The width D44i in the XY direction is larger than the film thickness D42j (see FIG. 11) and larger than the film thickness D42i (see FIG. 10). Accordingly, the average grain size d3 is larger than the average grain size d1 and larger than the average grain size d2.

[0120] Thereafter, the steps shown in FIG. 15 and subsequent steps are carried out.

[0121] This manufacturing method also makes it possible to manufacture the semiconductor memory device 1 including the polycrystalline semiconductor film 42 in which the average grain size d1 of the portion 42a is smaller than the average grain size d2 of the portion 42b.

[0122] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0123] 1 semiconductor memory device, 6 conductive layer, 7 insulating layer, 42, 42i, 42j, 44, 44i polycrystalline semiconductor film, 43 insulating film, SST, SSTi, SSTj laminate, SUB substrate.

Claims

1. A substrate; a laminate disposed above the substrate, the laminate including a plurality of conductive layers laminated with insulating layers interposed therebetween; a first polycrystalline semiconductor film extending in a stacking direction within the stack; a first insulating film extending in the stacking direction between the plurality of conductive layers and the first polycrystalline semiconductor film within the stack; Equipped with The first polycrystalline semiconductor film is a first portion corresponding to a first conductive layer of the plurality of conductive layers that is farthest from the substrate; a second portion corresponding to two or more conductive layers among the plurality of conductive layers disposed between the substrate and the first conductive layer; Including, a height from the substrate of a boundary between the first portion and the second portion is between a height from the substrate of an upper surface of the first conductive layer and a height from the substrate of an upper surface of a second conductive layer, which is furthest from the substrate, in the two or more conductive layers; The average grain size of the first portion is smaller than the average grain size of the second portion. Semiconductor memory device.

2. The height of the boundary between the first portion and the second portion from the substrate is equal to the height of the lower surface of the first conductive layer from the substrate.

2. The semiconductor memory device according to claim 1.

3. a second insulating film extending in the stacking direction on an opposite side of the plurality of conductive layers with respect to the first polycrystalline semiconductor film; a second polycrystalline semiconductor film covering an end portion of the first polycrystalline semiconductor film and an end portion of the second insulating film and containing an impurity; Further equipped 2. The semiconductor memory device according to claim 1.

4. The grain size of the first portion is smaller than the grain size of the second polycrystalline semiconductor film.

4. The semiconductor memory device according to claim 3.

5. A diffusion distance of the impurity from the second polycrystalline semiconductor film to the first polycrystalline semiconductor film in the stacking direction is equal to a distance in the stacking direction from an interface between the second polycrystalline semiconductor film and the first polycrystalline semiconductor film to the boundary.

4. The semiconductor memory device according to claim 3.

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