Light detection device and light detection system

Abstract

To solve the problem in which: electric charges generated by a tunnel effect increase in proportion to the area of a region where the electric charges are detected; and when the area of the region where the electric charges are detected is reduced, light detection efficiency may be reduced.SOLUTION: The magnitude of the potential of a fourth semiconductor region is lower than the magnitude of the potential of a portion between the fourth semiconductor region and a third semiconductor region, and the difference between the magnitude of the potential of a first semiconductor region and the magnitude of the potential of a second semiconductor region is larger than the difference between the magnitude of the potential of the fourth semiconductor region and the magnitude of the potential of the portion between the fourth semiconductor region and the third semiconductor region. The magnitude of the potential of the third semiconductor region is lower than the magnitude of the potential of the fourth semiconductor region, and the difference between the magnitude of the potential of the first semiconductor region and the magnitude of the potential of the third semiconductor region is larger than the difference between the magnitude of the potential of the second semiconductor region and the magnitude of the potential of the fourth semiconductor region.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a photodetection device and a photodetection system that perform photoelectric conversion.

Background Art

[0002] Conventionally, a photodetection device that utilizes avalanche (electron avalanche) multiplication and can detect weak light at the single-photon level is known.

[0003] Patent Document 1 discloses a SPAD (Single Photon Avalanche Diode) in which a photoelectric charge caused by a single photon causes avalanche amplification in a PN junction region of a semiconductor region constituting a photoelectric conversion unit.

[0004] Further, in the SPAD of Patent Document 1, a P-type semiconductor region with a high impurity concentration is arranged on the surface of a semiconductor substrate, and an N-type semiconductor region is arranged below the P-type semiconductor region. The N-type semiconductor region is arranged so as to be included in an N-type epitaxial layer. The P-type semiconductor region and the N-type semiconductor region constitute a PN junction, and a high reverse bias voltage is applied to the PN junction.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In the SPAD described in Patent Document 1, the region for detecting charges is the PN junction region. Since a strong electric field is generated in the region for detecting charges, there is a possibility that the tunnel effect occurs between the PN junctions due to the strong electric field. The charges generated by the tunnel effect may be detected as false signals in the region for detecting charges and may become noise. The charges generated by this tunnel effect increase in proportion to the area of the region for detecting charges.

[0007] On the other hand, when the area of the region for detecting charges is reduced, it is possible to suppress the charges generated by the tunnel effect. However, if the area of the region for detecting charges is reduced, there is a risk that the light detection efficiency will decrease.

[0008] Therefore, an object of the present invention is to provide a light detection device capable of suppressing a decrease in light detection efficiency while suppressing noise.

Means for Solving the Problems

[0009] The present invention is a light detection device having a semiconductor substrate having a first surface and a second surface facing the first surface, and a pixel portion in which a plurality of pixels including avalanche diodes are arranged on the semiconductor substrate, wherein the avalanche diode includes a first semiconductor region of a first conductivity type arranged at a first depth, a second semiconductor region arranged in contact with the first semiconductor region, a third semiconductor region arranged at a second depth deeper than the first depth with respect to the first surface, a fourth semiconductor region of a second conductivity type opposite to the first conductivity type arranged in contact with the third semiconductor region, and a fifth semiconductor region arranged at a third depth deeper than the second depth with respect to the first surface. In a plan view, the first semiconductor region overlaps at least a part of the third semiconductor region, the second semiconductor region overlaps at least a part of the fourth semiconductor region, the third semiconductor region and the fourth semiconductor region overlap the fifth semiconductor region, the height of the potential of the third semiconductor region with respect to the charge of the first conductivity type is lower than the height of the potential of the fourth semiconductor region with respect to the charge of the first conductivity type, and the difference between the height of the potential of the first semiconductor region with respect to the charge of the first conductivity type and the height of the potential of the third semiconductor region with respect to the charge of the first conductivity type is larger than the difference between the height of the potential of the second semiconductor region with respect to the charge of the first conductivity type and the height of the potential of the fourth semiconductor region with respect to the charge of the first conductivity type.

Effects of the Invention

[0010] According to the present invention, it is possible to suppress a decrease in light detection efficiency while suppressing noise.

Brief Description of the Drawings

[0011]

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Modes for Carrying Out the Invention

[0012] The photodetection device in this embodiment will be described with reference to FIGS. 1 to 3. The photodetection device of this embodiment has pixels including avalanche diodes. Among the charge pairs generated in the avalanche diode, the conductivity type of the charge used as the signal charge is referred to as the first conductivity type. Also, the conductivity type opposite to the first conductivity type is referred to as the second conductivity type.

[0013] FIG. 1 is a schematic cross-sectional view of the avalanche diode in this embodiment. The avalanche diode of this embodiment is disposed on the semiconductor substrate 15. The semiconductor substrate 15 has a first surface and a second surface facing the first surface. For example, the first surface is the surface of the semiconductor substrate 15, and the second surface is the back surface of the semiconductor substrate 15. In this embodiment, the depth direction is from the first surface to the second surface. On the surface side of the semiconductor substrate 15, the gate electrode of the transistor and the multilayer wiring structure are disposed.

[0014] In FIG. 1, a first semiconductor region 71 of the first conductivity type, a second semiconductor region 76, a third semiconductor region 74, a fourth semiconductor region 72 of the second conductivity type, and a fifth semiconductor region 75 are disposed in the region sandwiched by the separation portion 16.

[0015] At the first depth X, the first semiconductor region 71 and the second semiconductor region 76 are disposed. The first semiconductor region 71 and the second semiconductor region 76 are in contact with each other. The second semiconductor region 76 is disposed between the first semiconductor region 71 and the separation portion 16. Here, the fact that the first semiconductor region 71 and the second semiconductor region 76 are disposed at the first depth X means that, for example, the region (peak) where the implanted impurity concentration is the highest is disposed at the first depth X. However, it is not necessarily required that the peak be disposed at the first depth X, and design errors and manufacturing errors are also allowed.

[0016] At the second depth Y deeper than the first depth X with respect to the first surface, the third semiconductor region 74 and the fourth semiconductor region 72 are disposed. The third semiconductor region 74 and the fourth semiconductor region 72 are in contact with each other.

[0017] The first semiconductor region 71 overlaps at least a part of the third semiconductor region 74, and the second semiconductor region 76 overlaps at least a part of the fourth semiconductor region 72. The fourth semiconductor region 72 is disposed between the third semiconductor region 74 and the separation portion 16.

[0018] At a third depth Z deeper than the second depth Y with respect to the first surface, a fifth semiconductor region 75 is disposed. The third semiconductor region 74 and the fourth semiconductor region 72 overlap the fifth semiconductor region 75.

[0019] FIG. 2 is a plan schematic view, FIG. 2(a) is a plan schematic view at the first depth X, and FIG. 2(b) is a plan schematic view at the second depth Y.

[0020] As shown in FIG. 2(a), at the first depth X, the first semiconductor region 71 is enclosed by the second semiconductor region 76. And the second semiconductor region 76 is enclosed by the separation portion 16.

[0021] As shown in FIG. 2(b), at the second depth Y, the third semiconductor region 74 is enclosed by the fourth semiconductor region 72. And the fourth semiconductor region 72 is enclosed by the separation portion 16. As is clear from FIGS. 1 and 2, in plan view, the first semiconductor region 71 overlaps at least a part of the third semiconductor region 74, and the third semiconductor region 74 and the fourth semiconductor region 72 overlap the fifth semiconductor region 75. Further, the second semiconductor region 76 overlaps at least a part of the fourth semiconductor region 72.

[0022] FIG. 3 shows the potential diagram of the avalanche diode. FIG. 3 shows an example of the potential distribution of the line segment JK and the line segment GH in the cross-sectional view shown in FIG. 1. The dotted line 20 shows the potential distribution of the line segment GH, and the solid line 21 shows the potential distribution of the line segment JK. Here, the potential as seen from electrons which are signal charges is shown. Note that when the signal charge is a hole, the relationship of the potential high and low is reversed.

[0023] Also in FIG. 3, the depths X, Y, Z, W correspond to the respective depths shown in FIG. 1, and the depth W is an arbitrary depth between the depth Y and the depth Z.

[0024] The height of the potential at the XH level indicates the height of the potential in the fourth semiconductor region 72. The height of the potential at the H level indicates the height of the potential in the third semiconductor region 74. The height of the potential at the M level is the height of the potential in the second semiconductor region 76. The height of the potential at the L level indicates the height of the potential in the first semiconductor region 71. Here, it is assumed that the height of the potential in the second semiconductor region 76 is lower than the height of the potential in the third semiconductor region 74, but the reverse may also be true.

[0025] The dotted line 20 is the height of the potential between the XH level and the H level at the depth Z. As the depth approaches from Z to W, the potential gradually decreases. Then, as the depth approaches from W to Y, the potential gradually increases and reaches the XH level at the depth Y. As the depth approaches from Y to X, the potential gradually decreases. At the depth X, the potential becomes the M level.

[0026] The solid line 21 is the height of the potential between the XH level and the H level at the depth Z. The potential gradually decreases until approaching the depth Y from Z. When approaching the depth Y, the height of the potential starts to decrease steeply and becomes the height of the potential at the H level at the depth Y. From the depth Y to the depth X, the height of the potential decreases steeply. And at the depth X, the potential becomes the L level.

[0027] At the depth Z, the potentials of the dotted line 20 and the solid line 21 are approximately the same height, and have a gentle potential gradient that becomes gradually lower towards the side of the first surface of the semiconductor substrate 15 in the regions indicated by the line segment GH and the line segment JK. Therefore, the charges generated in the photodetection device move towards the side of the first surface due to the gentle potential gradient.

[0028] As it approaches depth Y from depth W, the solid line 21 has a gently decreasing potential gradient, and charges move toward the first surface side. On the other hand, in the dotted line 20, a potential gradient serving as a potential barrier is formed for the charges moving toward the first surface. This potential barrier (the fourth semiconductor region 72) suppresses the movement of charges from the fifth semiconductor region 75 to the second semiconductor region 76. Since the potential in the direction of moving from line segment GH to line segment JK is lower than this potential barrier, at depths W to Y, the charges existing in line segment GH are more likely to move near line segment JK in the process of moving to the first surface.

[0029] The charges that have moved near the region indicated by line segment JK are accelerated by a steep potential gradient, that is, a strong electric field, from depth Y to depth X, and the accelerated charges reach the first semiconductor region 71. Avalanche amplification occurs in the region from depth Y to X. On the other hand, in the region indicated by line segment GH, an avalanche breakdown does not occur, or the potential distribution is such that an avalanche breakdown is less likely to occur than in the region indicated by line segment JK, particularly in the region from depth Y to X of line segment JK. As an example of realizing such a structure, it is preferable to have a configuration in which the difference in the potential height between the first semiconductor region 71 and the third semiconductor region 74 is larger than the difference in the potential height between the second semiconductor region 76 and the fourth semiconductor region 72.

[0030] By adopting such a potential structure, it is possible to reduce the noise charges generated by the above-described tunnel effect as compared with a configuration in which an avalanche breakdown occurs in the entire conventional avalanche diode. In addition, according to the avalanche diode of the present embodiment, the sensitivity is not decreased. This is because the signal charges existing in the region of the fifth semiconductor region 75 that overlaps with the fourth semiconductor region 72 have a potential structure in which they are likely to move to the first semiconductor region via the third semiconductor region 74.

[0031] Specifically, this is because the potential height of the third semiconductor region 74 is lower than the potential height of the fourth semiconductor region 72. That is, the fourth semiconductor region 72 functions as a potential barrier for the signal charges existing in the fifth semiconductor region 75. As a result, charges can easily move to the first semiconductor region 71 via the third semiconductor region 74.

[0032] In FIG. 3, the potential structure when the third semiconductor region 74 is a P-type semiconductor region is shown. However, even when the third semiconductor region 74 is an N-type semiconductor region, the potential height at position Y is such that the dotted line 20 is higher than the solid line 21. Also, although the potential structure when the second semiconductor region 76 is an N-type semiconductor region is shown, even when the second semiconductor region 76 is a P-type semiconductor region, the potential height at position Y is such that the dotted line 20 is higher than the solid line 21.

[0033] Note that in a plan view, it is preferable that all regions of the first semiconductor region 71 overlap with the third semiconductor region 74. According to such a configuration, a PN junction between the first semiconductor region 71 and the fourth semiconductor region 72 is not formed. Therefore, it is possible to suppress avalanche amplification from occurring at the PN junction between the first semiconductor region 71 and the fourth semiconductor region 72 and noise due to the tunnel effect from occurring.

[0034] Hereinafter, embodiments of the present invention will be described using specific examples. In each example, a configuration in which the signal charges are electrons will be described, but it is also applicable when the signal charges are holes. In that case, the semiconductor regions and potential relationships are reversed.

[0035] (Example 1) Examples of a photodetection device applicable to the present invention will be described with reference to FIGS. 4 to 9. Also, parts having the same functions as those in FIGS. 1 to 3 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0036] FIG. 4 is a block diagram of the photodetection device 1010 of this embodiment. The photodetection device 1010 includes a pixel section 106, a control pulse generation section 109, a horizontal scanning circuit section 104, a column circuit 105, signal lines 107, and a vertical scanning circuit section 103.

[0037] In the pixel section 106, a plurality of pixels 100 are arranged in a matrix. One pixel 100 is composed of a photoelectric conversion element 101 and a pixel signal processing section 102. The photoelectric conversion element 101 converts light into an electrical signal. The pixel signal processing section 102 outputs the converted electrical signal to the column circuit 105.

[0038] The vertical scanning circuit section 103 receives the control pulse supplied from the control pulse generation section 109 and supplies the control pulse to each pixel 100. Logic circuits such as a shift register and an address decoder are used in the vertical scanning circuit section 103.

[0039] The signal lines 107 supply the signal output from the pixel 100 selected by the vertical scanning circuit section 103 to the circuit at the subsequent stage of the pixel 100 as a potential signal.

[0040] The column circuit 105 receives the signals of the respective pixels 100 via the signal lines 107 and performs predetermined processing. The predetermined processing is processing such as noise removal and amplification of the input signals and converting them into a form for output to the outside of the sensor. For example, the column circuit has a parallel-serial conversion circuit.

[0041] The horizontal scanning circuit section 104 supplies a control pulse for sequentially outputting the signals processed by the column circuit 105 to the output circuit 108 to the column circuit 105.

[0042] The output circuit 108 is composed of a buffer amplifier, a differential amplifier, etc., and outputs the signal output from the column circuit 105 to a recording section or a signal processing section outside the photodetection device 1010.

[0043] In FIG. 4, the pixels 100 in the pixel section 106 may be arranged in a one-dimensional manner or may be composed of only a single pixel. Also, the vertical scanning circuit section 103, the horizontal scanning circuit section 104, and the column circuit 105 may divide the pixel section 106 into a plurality of pixel columns as blocks and arrange them for each block. Alternatively, they may be arranged for each pixel column.

[0044] The functions of the pixel signal processing section 102 do not necessarily have to be provided one by one for all the pixels 100. For example, one pixel signal processing section 102 may be shared by a plurality of pixels 100, and signal processing may be performed sequentially. Also, the pixel signal processing section 102 may be provided on a semiconductor substrate different from that of the photoelectric conversion element 101 in order to increase the aperture ratio of the photoelectric conversion element 101. In this case, the photoelectric conversion element 101 and the pixel signal processing section 102 are electrically connected via connection wiring provided for each pixel. The vertical scanning circuit section 103, the horizontal scanning circuit section 104, the signal line 107, and the column circuit 105 may also be provided on different semiconductor substrates as described above.

[0045] FIG. 5 shows an example of a block diagram of a pixel 100 including an equivalent circuit in the present embodiment. In FIG. 5, one pixel 100 has a photoelectric conversion element 101 and a pixel signal processing section 102.

[0046] The photoelectric conversion element 101 has a photoelectric conversion section 201 and a control section 202.

[0047] The photoelectric conversion section 201 generates a pair of charges corresponding to incident light by photoelectric conversion. An avalanche diode is used for the photoelectric conversion section 201.

[0048] A potential based on a potential VH higher than the potential VL supplied to the anode is supplied to the cathode of the photoelectric conversion section 201. Then, potentials are supplied to the anode and cathode of the photoelectric conversion section 201 such that a reverse bias is applied so that the photoelectric conversion section 201 becomes an avalanche diode. By performing photoelectric conversion in a state where such a reverse bias potential is supplied, the charges generated by the incident light cause avalanche amplification and an avalanche current is generated.

[0049] In addition, when a reverse bias potential is supplied, if the potential difference between the anode and the cathode is greater than the breakdown voltage, the avalanche diode operates in Geiger mode. A photodiode that uses Geiger mode operation to detect a weak signal at the single photon level at high speed is an SPAD.

[0050] Also, when the potential difference between the anode and the cathode of the photoelectric conversion unit 201 is equal to or greater than the potential difference at which the charges generated in the photoelectric conversion unit 201 cause avalanche amplification and less than or equal to the breakdown voltage, the avalanche diode operates in linear mode. An avalanche diode that performs optical detection in linear mode is called an avalanche photodiode (APD). In this embodiment, the photoelectric conversion unit 201 may operate as either avalanche diode. Note that the potential difference at which avalanche amplification occurs will be described later.

[0051] The control unit 202 is connected to a power supply voltage that supplies a high potential VH and the photoelectric conversion unit 201. The control unit 202 has a function of replacing the change in the avalanche current generated in the photoelectric conversion unit 201 with a voltage signal. Further, the control unit 202 functions as a load circuit (quench circuit) during signal amplification by avalanche amplification, and has a function of suppressing the voltage supplied to the photoelectric conversion unit 201 to suppress avalanche amplification (quench operation). As the control unit 202, for example, a resistive element or an active quench circuit that actively suppresses avalanche amplification by detecting an increase in the avalanche current and performing feedback control is used.

[0052] The pixel signal processing unit 102 includes a waveform shaping unit 203, a counter circuit 209, and a selection circuit 206. The waveform shaping unit 203 shapes the voltage change obtained when detecting a signal at the photon level and outputs a pulse signal. As the waveform shaping unit 203, for example, an inverter circuit is used. Also, although an example using a single inverter is shown as the waveform shaping unit 203, a circuit in which a plurality of inverters are connected in series may be used, or another circuit having a waveform shaping effect may be used.

[0053] The pulse signal output from the waveform shaping unit 203 is counted by the counter circuit 209. For example, in the case of an N-bit counter (N: a positive integer), the counter circuit 209 can count up to approximately 2 to the power of N pulse signals caused by single photons. The counted signal is held as the detected signal. Also, when the control pulse pRES is supplied via the drive line 207, the detected signal held in the counter circuit 209 is reset.

[0054] The selection circuit 206 is supplied with the control pulse pSEL from the vertical scanning circuit unit 103 in FIG. 4 via the drive line 208, and switches the electrical connection and disconnection between the counter circuit 209 and the signal line 107. For the selection circuit 206, for example, a transistor or a buffer circuit for outputting a signal outside the pixel is used.

[0055] Note that a switch such as a transistor may be arranged between the control unit 202 and the photoelectric conversion unit 201, or between the photoelectric conversion element 101 and the pixel signal processing unit 102 to switch the electrical connection. Similarly, the supply of the high potential VH supplied to the control unit 202 or the low potential VL supplied to the photoelectric conversion element 101 may be electrically switched using a switch such as a transistor.

[0056] In the pixel unit 106 where a plurality of pixels 100 are arranged in a matrix, an imaging image may be acquired by a rolling shutter operation that sequentially resets the count of the counter circuit 209 for each row and sequentially outputs the detected signal held in the counter circuit 209 for each row.

[0057] Alternatively, an imaging image may be acquired by a global electronic shutter operation that simultaneously resets the count of the counter circuit 209 for all pixel rows and sequentially outputs the detected signal held in the counter circuit 209 for each row. Note that when performing the global electronic shutter operation, it is better to provide means for switching between the case where the counter circuit 209 performs counting and the case where it does not. The switching means is, for example, the switch described above.

[0058] In this embodiment, a configuration for acquiring a captured image using the counter circuit 209 is shown. However, instead of the counter circuit 209, an optical detection device 1010 that acquires pulse detection timing using a time-to-digital converter (hereinafter referred to as TDC) and a memory may be used.

[0059] At this time, the generation timing of the pulse signal output from the waveform shaping unit 203 is converted into a digital signal by the TDC. A control pulse pREF (reference signal) is supplied to the TDC from the vertical scanning circuit unit 103 in FIG. 4 via a drive line for measuring the timing of the pulse signal. The TDC acquires, as a digital signal, a signal when the input timing of the signal output from each pixel via the waveform shaping unit 203 is a relative time with respect to the control pulse pREF.

[0060] For the circuit of the TDC, for example, a Delay Line method in which buffer circuits are connected in series to create a delay, a Looped TDC method in which a Delay Line is connected in a loop, etc. are used. Although other methods may be used, it is better to use a circuit method that can achieve a time resolution equal to or higher than the time resolution of the photoelectric conversion unit 201.

[0061] The digital signal representing the pulse detection timing obtained by the TDC is held in one or a plurality of memories. When a plurality of memories are arranged, by supplying a plurality of signals to the selection circuit 206, it is possible to control the output to the signal line 107 for each memory when outputting the digital signal held in the memory to the signal line 107.

[0062] The cross-sectional schematic diagram and the plan schematic diagram of the avalanche diode of this embodiment will be described with reference to FIGS. 6 and 7. In FIG. 6, in the region where the first semiconductor region 71 of FIG. 1 is arranged, an N-type semiconductor region 1 is arranged, and in the region where the second semiconductor region 76 of FIG. 1 is arranged, an N-type semiconductor region 6 is arranged. In FIG. 6, in the region where the third semiconductor region 74 of FIG. 1 is arranged, an N-type semiconductor region 4 is arranged, and in the region where the fourth semiconductor region 72 of FIG. 1 is arranged, a P-type semiconductor region 2 is arranged. In FIG. 6, in the region where the fifth semiconductor region 75 of FIG. 1 is arranged, an N-type semiconductor region 5 is arranged.

[0063] First, with reference to FIG. 6, the cross-sectional structure of the separation portion 16 and the photoelectric conversion region sandwiched between the separation portions 16 will be described.

[0064] On the semiconductor substrate 15 on which a plurality of pixels 100 are arranged, a separation portion 16 for separating each of the plurality of pixels 100 is arranged.

[0065] The separation portion 16 is composed of a P-type semiconductor region arranged in the depth direction from the first surface. Specifically, as the separation portion 16, a P-type semiconductor region 3 and a P-type semiconductor region 7 are arranged in this order in the depth direction from the first surface and are in contact with each other. Note that the P-type semiconductor region 3 is electrically connected to the P-type semiconductor region 7, a P-type semiconductor region 8 described later, and a P-type semiconductor region 2 described later.

[0066] The impurity concentration of the P-type semiconductor region 3 is higher than the impurity concentrations of each of the P-type semiconductor region 7, the P-type semiconductor region 8, and the P-type semiconductor region 2. Thereby, for example, it is possible to reduce the contact resistance by connecting the P-type semiconductor region 3 to the contact plug 17 rather than connecting the P-type semiconductor region 7 to the contact plug 17.

[0067] The N-type semiconductor region 1 is a region having a higher impurity concentration than the N-type semiconductor region 6, the N-type semiconductor region 4, and an N-type semiconductor region 5 described later. By setting such an impurity concentration, it is possible to strengthen the electric field of the depletion layer generated in the N-type semiconductor region 1. Note that a potential that is reverse-biased with respect to the separation portion 16 is supplied to the N-type semiconductor region 1.

[0068] The impurity concentration of the N-type semiconductor region 4 is made lower than that of the N-type semiconductor region 1. This makes it easier for the charges in the vicinity of the N-type semiconductor region 4 to move to the N-type semiconductor region 1.

[0069] The impurity concentration of the N-type semiconductor region 6 is made lower than that of the N-type semiconductor region 1. For example, when the impurity concentration of the N-type semiconductor region 1 is 6.0×10 18 [atms / cm 3 or more, the impurity concentration of the N-type semiconductor region 6 is 1.0×10 16 [atms / cm 3 or more and 1.0×10 18 [atms / cm 3 or less.

[0070] In FIG. 6, a configuration is shown in which an N-type semiconductor region 6 having no impurity concentration gradient is arranged in the second semiconductor region 76 of FIG. 1. However, in FIG. 1, the semiconductor region arranged in the region where the second semiconductor region 76 is arranged is preferably a region having an impurity concentration gradient. By making the region between the N-type semiconductor region 1 and the P-type semiconductor region 3 have a configuration with an impurity concentration gradient, the strong electric field that may occur between the N-type semiconductor region 1 and the P-type semiconductor region 3 is relaxed compared to the case where the N-type semiconductor region 6 has no impurity concentration gradient.

[0071] Two examples of the region having an impurity concentration gradient will be described. The first example is the case where an N-type semiconductor region having an impurity concentration lower than that of the N-type semiconductor region 1 is arranged in a region close to the N-type semiconductor region 1, and an N-type semiconductor region having an impurity concentration lower than that of this N-type semiconductor region is arranged in a region close to the separation part 16. The second example is the case where an N-type semiconductor region having an impurity concentration lower than that of the N-type semiconductor region 1 is arranged in a region close to the N-type semiconductor region 1, and a P-type semiconductor region having an impurity concentration lower than that of the P-type semiconductor region 3 is arranged in a region close to the separation part 16. Specifically, as shown in FIG. 20, a P-type semiconductor region 2000 having an impurity concentration lower than that of the P-type semiconductor region 3 is provided between the P-type semiconductor region 3 and the N-type semiconductor region 6.

[0072] In this way, by configuring the region between the N-type semiconductor region 1 and the P-type semiconductor region 3 to have a gradient of impurity concentration, the strong electric field that can occur between the N-type semiconductor region 1 and the P-type semiconductor region 3 is relaxed as compared with the case where the N-type semiconductor region 6 does not have a gradient of impurity concentration.

[0073] Next, the impurity concentration of the P-type semiconductor region 2 is set to be equal to or lower than the impurity concentration of the P-type semiconductor region 7. The P-type semiconductor region 2 and the N-type semiconductor region 4 form a PN junction. Due to this PN junction, all regions of the N-type semiconductor region 4 become depletion layer regions. Further, this depletion layer region extends to a part of the N-type semiconductor region 1. A strong electric field is induced in the extended depletion layer region. Due to this strong electric field, avalanche amplification occurs in the depletion layer region extending to a part of the N-type semiconductor region 1, and a current based on the amplified charges is output from the wiring 9. That is, in this embodiment, the light detection region is the depletion layer region in a part of the N-type semiconductor region 1.

[0074] In this embodiment, the N-type semiconductor region 4 is configured as an N-type region instead of a P-type region in order to enable charge acquisition from a deeper part by expanding the depletion layer deeper into the N-type semiconductor region 5.

[0075] Also, if the N-type semiconductor region 6 were a P-type semiconductor region, a depletion layer region would be formed between this P-type semiconductor region and the N-type semiconductor region 1, and avalanche amplification might occur between the P-type semiconductor region and the N-type semiconductor region 1. Since noise increases as the depletion layer region expands closer to the first surface of the P semiconductor substrate 15, the N-type semiconductor region 1 is configured as an N-type in this embodiment.

[0076] Furthermore, the impurity concentrations of the N-type semiconductor region 1, the N-type semiconductor region 4, and the P-type semiconductor region 2 are set to impurity concentrations such that when a potential difference that causes avalanche amplification is supplied in the depletion layer region generated in a part of the N-type semiconductor region 1, all regions of the N-type semiconductor region 1 do not deplete. This is because if the depletion layer region spreads closer to the first surface of the semiconductor substrate 15, there is a possibility that noise will occur on the first surface of the semiconductor substrate 15. On the other hand, the impurity concentration of all regions of the N-type semiconductor region 4 is set to an impurity concentration such that all regions deplete.

[0077] The conditions for all regions of the N-type semiconductor region 4 to deplete are shown in Equation 1. Here, the impurity concentration of the N-type semiconductor region 4 is defined as the impurity concentration Nd, the impurity concentration of the P-type semiconductor region 2 is defined as the impurity concentration Na, and the elementary charge is defined as the elementary charge q. Furthermore, the dielectric constant of the semiconductor is defined as the dielectric constant ε, the potential difference between the PN junctions of the N-type semiconductor region 4 and the P-type semiconductor region 2 is defined as the potential difference V, and the length of the N-type semiconductor region 4 sandwiched between the P-type semiconductor regions 2 is defined as the length D.

[0078]

Equation

[0079] The impurity concentration at which all regions of the N-type semiconductor region 1 do not deplete is, for example, the impurity concentration of the N-type semiconductor region 1 is 6.0×10 18 [atms / cm 3 or more. In that case, the impurity concentration that satisfies these depletion conditions is that the impurity concentration of the P-type semiconductor region 2 is 1.0×10 16 [atms / cm 3 or more. Also, the impurity concentration of the N-type semiconductor region 4 is 1.0×10 17 [atms / cm 3 or less. However, it is not limited to these impurity concentrations.

[0080] Then, the potential difference between the N-type semiconductor region 1 and the separation part 16 is set so that the electric field in the depth direction induced in the extended depletion layer becomes sufficiently large. Here, the sufficiently large potential difference is a potential difference at which charges affected by the electric field cause avalanche amplification. That is, it is the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 3 that enables the photoelectric conversion unit 201 to operate as an avalanche diode (APD or SPAD).

[0081] Specifically, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 2 is 6V or more. At this time, as described above, all regions of the N-type semiconductor region 4 electrically connected to the N-type semiconductor region 1 become depletion layer regions, and a strong electric field is generated in the depletion layer region that extends to a part of the N-type semiconductor region 1 so that avalanche amplification occurs.

[0082] Considering the impurity concentration that satisfies the above-described depletion conditions, more preferably, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 3 is 10V or more and 30V or less. At this time, for example, a potential of 10V or more is supplied to the N-type semiconductor region 1, and a potential of 0V or less is supplied to the P-type semiconductor region 3. However, as long as the potential difference is 6V or more, the values of these potentials are not limited.

[0083] Also, the depletion layer formed between the P-type semiconductor region 2 and the N-type semiconductor region 6 may spread to the N-type semiconductor region 1 and cause avalanche amplification. In this case, if all regions of the N-type semiconductor region 1 are depleted, noise may be generated. Therefore, it is preferable to set the impurity concentration of the N-type semiconductor region 1 so as not to deplete all regions of the N-type semiconductor region 1.

[0084] Incidentally, in this embodiment, charges are generated in the N-type semiconductor region 5 and collected and read in the N-type semiconductor region 1. That is, charges generated in the semiconductor region of the first conductivity type are read out from the semiconductor region of the first conductivity type.

[0085] In contrast, the device described in U.S. Patent No. 9,209,336 avalanche amplifies the charges generated in the N-type epitaxial layer 2 at the interface between the N-type epitaxial layer 2 and the p-type anode region 14, and reads out the charges from the p-type anode region 14. That is, the charges generated in the semiconductor region of the first conductivity type are read out from the semiconductor region of the second conductivity type. Also in this regard, the present embodiment is different from the device described in U.S. Patent No. 9,209,336.

[0086] In FIG. 6, it is assumed that, without providing the P-type semiconductor region 2 and the N-type semiconductor region 4, an N-type semiconductor region 5 having an impurity concentration lower than that of the N-type semiconductor region 1 is disposed immediately below the N-type semiconductor region 1 having a high impurity concentration. In this case, although it is possible to generate charges in the N-type semiconductor region 5 and read out the charges from the N-type semiconductor region 1, it is difficult to perform avalanche amplification under the same voltage conditions as in this embodiment. This is because most of the potential difference applied between the N-type semiconductor region 1 and the P-type semiconductor region 3 is applied to the depletion layer region of the N-type semiconductor region 5, so that the potential difference applied to the avalanche amplification region near the N-type semiconductor region 1 becomes small. On the other hand, in this embodiment, since the N-type semiconductor region 5 is surrounded by the P-type semiconductor region in all directions except at the location where it is in contact with the N-type semiconductor region 4, the potential of the N-type semiconductor region 5 becomes closer to the level of the surrounding P-type semiconductor region than that of the N-type semiconductor region 1. That is, by suppressing the excessive spread of the depletion layer into the deep part of the substrate in the P-type semiconductor region 2, it becomes possible to concentrate most of the applied potential difference on the avalanche amplification region near the N-type semiconductor region 1. As a result, it is possible to avalanche amplify the photo charges at a lower voltage.

[0087] Next, the impurity concentration of the N-type semiconductor region 5 is an impurity concentration equal to or lower than the impurity concentration of the N-type semiconductor region 4. For example, the impurity concentration of the N-type semiconductor region 5 is 1.0×10 17 [atms / cm 3The following applies. Since it is "the following", the impurity concentration of the N-type semiconductor region 5 and the impurity concentration of the N-type semiconductor region 4 may be the same. Further, at least, the impurity concentration of the N-type semiconductor region 5 may be less than the impurity concentration of the N-type semiconductor region 1.

[0088] In FIG. 6, the N-type semiconductor region 5 is shown as an example of a region having the same impurity concentration. However, the N-type semiconductor region 5 preferably has a gradient in impurity concentration so as to have a potential structure in which charges move to the side of the first surface of the semiconductor substrate 15. By having such a gradient in impurity concentration, it is possible to make it easier for charges to move to the N-type semiconductor region 1.

[0089] Also, when having a gradient in impurity concentration so as to have a potential structure in which charges move to the side of the first surface of the semiconductor substrate 15, the side of the first surface may be an N-type semiconductor region and the side of the second surface may be a P-type semiconductor region in the region where the N-type semiconductor region 5 is arranged.

[0090] Alternatively, a P-type semiconductor region having an impurity concentration lower than the impurity concentration of the P-type semiconductor region 2 may be arranged instead of the N-type semiconductor region 5. Also in this case, it preferably has a gradient in impurity concentration so as to have a potential structure in which charges move to the side of the first surface of the semiconductor substrate 15.

[0091] For example, this P-type semiconductor region has a first region, a second region arranged at a position deeper than the first region with respect to the first surface, and a third region arranged at a position deeper than the second region with respect to the first surface. And when the first region has a first impurity concentration, the second region has a second impurity concentration, and the third region has a third impurity concentration, the first impurity concentration < the second impurity concentration < the third impurity concentration may be satisfied. Note that the first impurity concentration is lower than the impurity concentration of the P-type semiconductor region 2. Here, the P-type semiconductor region arranged instead of the N-type semiconductor region 5 is divided into three regions, but this is not a limitation.

[0092] The P-type semiconductor region 8 is disposed at a position deeper than the N-type semiconductor region 5 and defines the depth of the photoelectric conversion region. The N-type semiconductor region 5 forms a PN junction with each of the P-type semiconductor region 2, the P-type semiconductor region 7, and the P-type semiconductor region 8. The impurity concentration of the P-type semiconductor region 8 is made higher than the impurity concentration of the P-type semiconductor region 2. Thereby, the charges generated in the vicinity of the P-type semiconductor region 8 are likely to move in the first surface direction.

[0093] A contact plug 18 is connected to the N-type semiconductor region 1, and a wiring 9 is connected to the contact plug 18. Also, a contact plug 17 is connected to the P-type semiconductor region 3, and a wiring 10 is connected to the contact plug 17. Then, the wiring 9 or the wiring 10 is connected to a control unit 202 such as a resistance element that performs a quench operation. Hereinafter, it will be described assuming that the control unit 202 is connected to the wiring 9.

[0094] In FIG. 6, it has been described that the contact plug 17 and the wiring 10 are disposed on the side of the first surface. However, the contact plug 17 and the wiring 10 may be disposed on the side of the second surface.

[0095] When the contact plug 17 and the wiring 10 are disposed on the side of the second surface, the impurity concentration of the region of the P-type semiconductor region 8 where the contact plug 17 is disposed is preferably higher than the impurity concentration of the P-type semiconductor region 7. That is, it becomes the P-type semiconductor region 3. At this time, since the contact plug 17 is not connected to the P-type semiconductor region 3 that was disposed on the first surface side, it is preferable that the impurity concentration be made approximately the same as that of the P-type semiconductor region 7. Thereby, it becomes possible to relax the electric field generated between the P-type semiconductor region 3 and the N-type semiconductor region 1.

[0096] Also, even when the separation part 16 has an insulating separation part on the first surface side, the contact plugs 17 and 10 are disposed on the second surface side. At this time, the separation part 16 is disposed in contact so as to overlap in the order of the insulating separation part, the P-type semiconductor region 7, and the P-type semiconductor region 3 in the depth direction from the first surface.

[0097] Next, with reference to FIG. 7, the separation part 16 at an arbitrary depth of the cross-sectional structure of FIG. 6 and the planar structure of the photoelectric conversion region sandwiched between the separation parts 16 will be described. In FIG. 7, the boundaries of the semiconductor regions are drawn as circular, but it is not limited thereto.

[0098] FIG. 7(a) shows a plan schematic view of the line segment AB at the depth X in FIG. 6. The N-type semiconductor region 1 is enclosed by the N-type semiconductor region 6. The N-type semiconductor region 6 is enclosed by the P-type semiconductor region 3. Also, the area of the N-type semiconductor region 6 is larger than the area of the N-type semiconductor region 1.

[0099] FIG. 7(b) shows a plan schematic view of the line segment CD at the depth Y in FIG. 6. The N-type semiconductor region 4 is enclosed by the P-type semiconductor region 2. The P-type semiconductor region 2 is enclosed by the P-type semiconductor region 3.

[0100] FIG. 7(c) shows a plan schematic view of the line segment EF at the depth Z in FIG. 6. The N-type semiconductor region 5 is enclosed by the P-type semiconductor region 7.

[0101] When FIGS. 7(b) and 7(c) are overlapped, in a plan view, the N-type semiconductor region 4 and the P-type semiconductor region 2 overlap with the N-type semiconductor region 5.

[0102] Also, when FIGS. 7(a) and 7(b) are overlapped, in a plan view, the N-type semiconductor region 1 overlaps with at least a part of the region of the N-type semiconductor region 4, and the N-type semiconductor region 6 overlaps with at least a part of the P-type semiconductor region 2.

[0103] Next, with reference to FIG. 8, the manufacturing method of the avalanche diode in the cross-sectional schematic view shown in FIG. 6 will be described. In particular, for the processes for which no description is given regarding the order, the order may be appropriately changed. Also, for the processes omitted in FIG. 8, well-known manufacturing methods can be applied.

[0104] As shown in FIG. 8(a), P-type impurity ions are implanted (hereinafter referred to as ion implantation) into the region that will become the N-type semiconductor region 5 from the normal direction with respect to the first surface of the semiconductor substrate 15. Thereby, a P-type semiconductor region 8 is formed at a deep position with respect to the first surface of the semiconductor substrate 15.

[0105] Next, as shown in FIG. 8(b), a mask 77 is formed on the first surface of the semiconductor substrate 15. The mask 77 has an opening 30. Then, by performing P-type ion implantation from the normal direction with respect to the first surface of the semiconductor substrate 15, a P-type semiconductor region 3 and a P-type semiconductor region 7 are formed so as to be arranged in this order from the first surface. At this time, a part of the P-type semiconductor region 7 and the P-type semiconductor region 8 are connected. Also, the impurity concentration of the P-type semiconductor region 3 is made higher than the impurity concentration of the P-type semiconductor region 7. Specifically, for example, there is a method of performing ion implantation a plurality of times with different ion implantation energies.

[0106] Next, the mask 77 is removed and a mask 78 is disposed. The mask 78 has an opening 32. Then, as shown in FIG. 8(c), a region that will become the P-type semiconductor region 2 is formed by performing P-type ion implantation from a direction parallel to the normal direction with respect to the first surface of the semiconductor substrate 15. Thereafter, N-type ion implantation is performed at a position shallower than the position where the P-type ion implantation was performed to form the region that will become the P-type semiconductor region 2, thereby forming a region that will become the N-type semiconductor region 6. Here, after forming the region that will become the P-type semiconductor region 2, the region that will become the N-type semiconductor region 6 is formed, but the reverse may also be possible.

[0107] Next, the mask 78 is removed and a mask 73 is disposed. The mask 73 has an opening 33. As shown in FIG. 8(d), an N-type semiconductor region 4 is formed in a part of the region that will become the P-type semiconductor region 2 by performing N-type ion implantation at the depth where the region that will become the P-type semiconductor region 2 is disposed from a direction parallel to the normal direction with respect to the first surface of the semiconductor substrate 15.

[0108] Thereafter, an N-type semiconductor region 1 is formed by performing N-type ion implantation from a direction parallel to the normal direction with respect to the first surface of the semiconductor substrate 15, on the side of the first surface of the semiconductor substrate 15. Here, the N-type semiconductor region 4 was formed first, but the N-type semiconductor region 1 may be formed first.

[0109] Thus, when ion implantation is performed using impurity ions of the same conductivity type, the diffusion of the impurity ions in the direction parallel to the first surface is greater when the ions are implanted at a deeper position with respect to the first surface than when they are implanted at a shallower position with respect to the first surface. That is, when ion implantation is performed using the same mask, the N-type semiconductor region 1 is included in the N-type semiconductor region 4 in a plan view.

[0110] Note that, as the impurity ions implanted to form the N-type semiconductor region 1 and the N-type semiconductor region 4, impurity ions having different thermal diffusion coefficients may be used. According to such a configuration, the degree of freedom in potential design in the region where the N-type semiconductor region 1 and the N-type semiconductor region 4 are arranged is improved.

[0111] In FIG. 8(d), when ion implantation is performed using different masks when forming the N-type semiconductor region 1 and the N-type semiconductor region 4, a misalignment occurs, and an asymmetric electric field distribution occurs, which may cause a tunneling effect. On the other hand, according to the manufacturing method of the present embodiment, since the N-type semiconductor region 1 and the N-type semiconductor region 4 are formed using the same mask, it is possible to suppress the misalignment between the two semiconductor regions, and it is possible to suppress the tunneling effect that may occur due to the misalignment.

[0112] Next, the control unit 202 of the present embodiment will be described with reference to FIG. 9. In the present embodiment, the control unit 202 has two configurations. The first configuration is a configuration in which the control unit 202 is arranged on the cathode side to which the high potential VH of the photoelectric conversion unit 201 is supplied, as shown in FIG. 9(a). The second configuration is a configuration in which the control unit 202 is arranged on the anode side to which the low potential VL of the photoelectric conversion unit 201 is supplied, as shown in FIG. 9(b).

[0113] In the configurations of FIGS. 9(a) and 9(b), after the input potential of the waveform shaping unit 203 changes due to the avalanche current, a certain amount of time is required for the voltage drop by the control unit 202 to return the bias of the photoelectric conversion unit 201 to its initial state. Thus, the period from when the charge is detected once until it returns to the bias state where the charge can be detected next is called the Dead time. The shorter this Dead time is, the larger the number of charges that can be counted per unit time, and the larger the dynamic range as a photodetection device becomes.

[0114] As an example, when the control unit 202 is a resistive element, the Dead time (τd [s]) of the avalanche diode of this embodiment is determined by the product of the resistance (R [Ω]) and the capacitance (C [F]) of the input terminal. In the following formula, the PN junction capacitance of the photoelectric conversion unit 201 is represented by Cpd, the capacitance of the well of the photoelectric conversion unit 201 is represented by Cw, and the parasitic capacitance of the wiring / diffusion layer is represented by C.

[0115] In the case of FIG. 9(a), the Dead time is obtained by Formula 2. τd = R(Cpd + C) …(Formula 2) In the case of FIG. 9(b), the Dead time is obtained by Formula 3. τd = R(Cpd + Cw + C) …(Formula 3)

[0116] The PN junction capacitance Cpd of the photoelectric conversion unit 201 is the PN junction capacitance of the photodetection region that induces a strong electric field to cause avalanche amplification. Therefore, the PN junction capacitance Cpd changes in proportion to the area of the photodetection region. That is, when the area of the photodetection region increases to increase the photodetection efficiency, the PN junction capacitance Cpd increases, and the Dead time increases. As a result, the dynamic range decreases.

[0117] That is, there is a trade-off between photodetection efficiency and dynamic range. On the other hand, according to the pixel structure of this embodiment, it is possible to reduce the area of ​​the photodetection region while ensuring a large area of ​​the photoelectric conversion region. Therefore, it is possible to reduce Cpd and dead time. As a result, it is possible to achieve both high photodetection efficiency and a high dynamic range.

[0118] The effect of improving the dynamic range by the pixel structure of this embodiment is more noticeable in the configuration of FIG. 9(a) than in FIG. 9(b). For example, when the ratio of Cpd of the SPAD structure of this embodiment to the conventional SPAD structure is A(0 <A<1)とすると、図9(a)と図9(b)のそれぞれの回路方式におけるダイナミックレンジの向上率Δはそれぞれ数式4、数式5で表される。 Δ1=(1-A)Cpd / (ACpd+C) ... (Formula 4) Δ2=(1-A)Cpd / (ACpd+Cw+C) ... (Formula 5)

[0119] In Equation 4 and Equation 5, the dynamic range is calculated by utilizing the fact that it is inversely proportional to the dead time. From the above equations, it can be seen that Δ1>Δ2 is always satisfied.

[0120] From the above, when FIGS. 9(a) and 9(b) are applied to the configuration of this embodiment, the improvement rate of the dynamic range is, in principle, higher in FIG. 9(a) than in FIG. 9(b).

[0121] Up to this point, the control section 202 has been described as a resistive element, but the same is true in the case of an active quench circuit.

[0122] From the above, it is possible to achieve a greater effect of improving the dynamic range when the control unit 202 for the pixel in this embodiment is disposed on the cathode side of the photoelectric conversion unit 201 than when it is disposed on the anode side.

[0123] According to the configuration of this embodiment, it is possible to suppress a decrease in photodetection efficiency by forming a path through which charges move. That is, it is possible to reduce noise while suppressing a decrease in photodetection efficiency.

[0124] (Embodiment 2) FIG. 10 is a schematic cross-sectional view of an avalanche diode in this embodiment. FIGS. 4, 5, 8, and 9 are the same as those in Embodiment 1. Also, parts having the same functions as those in FIGS. 1 to 9 are denoted by the same reference numerals, and detailed descriptions thereof are omitted. FIG. 10 is different in that a P-type semiconductor region 24 is arranged in a region where the N-type semiconductor region 4 is arranged in FIG. 6.

[0125] In FIG. 10, the N-type semiconductor region 1 and the P-type semiconductor region 24 form a PN junction. Also, the P-type semiconductor region 24 is electrically connected to the P-type semiconductor region 3 via the P-type semiconductor region 2. Therefore, the potential of the P-type semiconductor region 24 becomes a potential reverse-biased with respect to the N-type semiconductor region 1. Then, a strong electric field is induced in the PN junction region between the N-type semiconductor region 1 and the P-type semiconductor region 24. Due to this strong electric field, avalanche amplification occurs in the PN junction region, and a current based on the amplified charges is output from the wiring 9 or 10. That is, in this embodiment, the photodetection region is the PN junction region between the N-type semiconductor region 1 and the P-type semiconductor region 24. With such a configuration, the potential difference required to cause avalanche amplification can be made smaller than in Embodiment 1. That is, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 3 in this embodiment can be made smaller than the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 3 in Embodiment 1.

[0126] In FIG. 10, the impurity concentration of the P-type semiconductor region 24 is lower than the impurity concentrations of the P-type semiconductor region 2 and the P-type semiconductor region 7. Therefore, the potential relationship as shown in FIG. 3 described above also holds in this embodiment.

[0127] The impurity concentration of the N-type semiconductor region 1 is set to an impurity concentration at which not all regions of the N-type semiconductor region 1 are depleted when a potential that causes avalanche amplification is supplied between the PN junctions, as described above.

[0128] In this embodiment, the impurity concentration at which not all regions of the N-type semiconductor region 1 are depleted means, for example, that the impurity concentration of the N-type semiconductor region 1 is 6.0×10 18 [atms / cm 3 or more. And the impurity concentration of the P-type semiconductor region 24 is 1.0×10 17 [atms / cm 3 or less. This is because if the depletion layer region spreads closer to the first surface of the semiconductor substrate 15, there is a risk of noise occurring on the first surface of the semiconductor substrate 15. However, it is not limited to these impurity concentrations.

[0129] Note that when the above-described photoelectric conversion unit 201 operates as an avalanche diode (APD or SPAD), the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 24 is specifically 6V or more.

[0130] Considering the above-described impurity concentration relationship, more preferably, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 24 is 10V or more. At this time, for example, a potential of 10V or more is supplied to the N-type semiconductor region 1, and a potential of 0V or less is supplied to the P-type semiconductor region 24 via the P-type semiconductor region 2. However, as long as the potential difference is 6V or more, these potentials are not limited.

[0131] Note that in this embodiment, when applying the manufacturing method shown in FIG. 8, in FIG. 8(d), the P-type semiconductor region 24 is formed by performing N-type ion implantation to locally reduce the impurity concentration in a part of the region that becomes the P-type semiconductor region 2.

[0132] Also in this embodiment, it has the same effect as in the first embodiment.

[0133] (Embodiment 3) FIG. 11 is a schematic cross-sectional view of an avalanche diode in this embodiment. Parts having the same functions as those in FIGS. 1 to 10 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0134] In FIG. 11, in the direction parallel to the first surface, the potential height of the region far from the separation portion 16 is lower than the potential height of the region close to the separation portion 16, which is different from the potential of the region where the N-type semiconductor region 5 in FIG. 6 is arranged.

[0135] In FIG. 11, in the direction parallel to the first surface, an N-type semiconductor region 28 is arranged in a region close to the separation portion 16, and an N-type semiconductor region 27 is arranged in a region far from the separation portion 16.

[0136] In this embodiment, by setting the impurity concentration relationship such that the potential height of the N-type semiconductor region 27 is lower than the potential height of the N-type semiconductor region 28, charges can easily move from the N-type semiconductor region 28 to the N-type semiconductor region 27.

[0137] That is, in the direction parallel to the first surface, the potential height of the region (N-type semiconductor region 27) far from the separation portion 16 is lower than the potential height of the region (N-type semiconductor region 28) close to the separation portion 16.

[0138] Therefore, the impurity concentration of the N-type semiconductor region 28 is preferably lower than the impurity concentration of the N-type semiconductor region 27. And in order to form a potential gradient to the light detection region, the impurity concentration of the N-type semiconductor region 27 is made lower than the impurity concentration of the N-type semiconductor region 4.

[0139] When a P-type semiconductor region is arranged instead of the N-type semiconductor region 27, a P-type semiconductor region having an impurity concentration higher than the impurity concentration of the arranged P-type semiconductor region is arranged instead of the N-type semiconductor region 28.

[0140] According to such a configuration, when the direction from the position where the separation part 16 is arranged to the position where the N-type semiconductor region 27 is arranged is defined as the in-plane direction, by setting the impurity distribution such that charges move in the in-plane direction, an electric field in the in-plane direction is induced. Due to this electric field, the charges generated deep in the semiconductor substrate 15 move in the in-plane direction.

[0141] According to such a configuration, for example, it is possible to shorten the time required for the charges generated at a deep position in the semiconductor substrate 15 to move to the light detection region.

[0142] Furthermore, as described above, it is preferable to set the potential such that charges easily move from a deep position to a shallow position on the first surface of the semiconductor substrate 15. By setting such a potential relationship, it is possible to further reduce the time required for the charges to move to the light detection region.

[0143] This embodiment is applicable to all embodiments.

[0144] (Embodiment 4) FIG. 12 is a cross-sectional schematic view of the avalanche diode in this embodiment. Parts having the same functions as those in FIGS. 1 to 11 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0145] FIG. 12 is different from the P-type semiconductor region 2 in FIG. 6 in that it is composed of a P-type semiconductor region 2B and a P-type semiconductor region 2A having different depths.

[0146] In FIG. 12, the P-type semiconductor region 2 has a P-type semiconductor region 2A and a P-type semiconductor region 2B. The P-type semiconductor region 2A is arranged between the N-type semiconductor region 6 and the P-type semiconductor region 3 constituting the separation part 16 at the first depth X. The P-type semiconductor region 2B is arranged between the N-type semiconductor region 5 and the N-type semiconductor region 4 at the second depth Y. A part of the P-type semiconductor region 2A is in contact with the N-type semiconductor region 5, and the other region of the P-type semiconductor region 2A is in contact with the P-type semiconductor region 2B.

[0147] Next, with reference to FIG. 13, the separation portion 16 at an arbitrary depth of the cross-sectional structure of FIG. 12 and the planar structure of the photoelectric conversion region sandwiched between the separation portions 16 will be described. In FIG. 13, the boundaries of the semiconductor regions are drawn as circles, but it is not limited to this. Note that the planar schematic view of the line segment EF at the depth Z is the same as that in FIG. 7(c), so it is omitted.

[0148] FIG. 13(a) shows a planar schematic view of the line segment AB at the first depth X of FIG. 12. The N-type semiconductor region 1 is enclosed by the N-type semiconductor region 6. The N-type semiconductor region 6 is enclosed by the P-type semiconductor region 2A. The P-type semiconductor region 2A is enclosed by the P-type semiconductor region 3.

[0149] FIG. 13(b) shows a planar schematic view of the line segment CD at the second depth Y of FIG. 12. The N-type semiconductor region 4 is enclosed by the P-type semiconductor region 2B. The P-type semiconductor region 2B is enclosed by the N-type semiconductor region 5. The N-type semiconductor region 5 is enclosed by the P-type semiconductor region 3.

[0150] When FIGS. 13(a) and 13(b) are overlapped, the P-type semiconductor region 2A overlaps with the P-type semiconductor region 2B and the N-type semiconductor region 5.

[0151] According to the configuration of this embodiment, it is possible to make a part of the region where the P-type semiconductor region 2 is arranged at the second depth Y in FIG. 6 into the N-type semiconductor region 5. Thereby, it is possible to increase the light detection efficiency of short wavelengths, particularly when it is a surface irradiation type.

[0152] This embodiment is applicable to all embodiments.

[0153] (Embodiment 5) FIG. 14 is a cross-sectional schematic view of the photodiode in this embodiment. The parts having the same functions as those in FIGS. 1 to 13 are denoted by the same reference numerals, and detailed descriptions thereof are omitted. FIG. 14 is different from FIG. 6 in that a plurality of N-type semiconductor regions 1 and N-type semiconductor regions 4 are arranged.

[0154] In FIG. 14, a configuration is shown in which two N-type semiconductor regions 1 and two N-type semiconductor regions 4 are arranged respectively, but if a plurality of them are arranged, it is not limited to two.

[0155] N-type semiconductor region 1A is sandwiched between N-type semiconductor regions 6. Similarly, N-type semiconductor region 1B is sandwiched between N-type semiconductor regions 6.

[0156] N-type semiconductor region 4A is sandwiched between P-type semiconductor regions 2. Similarly, N-type semiconductor region 4B is sandwiched between P-type semiconductor regions 2.

[0157] Next, with reference to FIG. 15, the separation portion 16 at an arbitrary depth of the cross-sectional structure of FIG. 14 and the planar structure of the photoelectric conversion region sandwiched between the separation portions 16 will be described. In FIG. 15, the boundaries of the semiconductor regions are drawn as circles, but it is not limited to this. Note that since the planar schematic diagram of the line segment EF at the depth Z is the same as that in FIG. 7(c), it is omitted.

[0158] FIG. 15(a) shows a planar schematic diagram of the line segment AB at the depth X of FIG. 14. N-type semiconductor regions 1A and 1B are respectively included in N-type semiconductor region 6. N-type semiconductor region 6 is included in P-type semiconductor region 3. The area of N-type semiconductor region 6 is larger than the areas of N-type semiconductor regions 1A and 1B.

[0159] FIG. 15(b) shows a planar schematic diagram of the line segment CD at the depth Y of FIG. 14. N-type semiconductor regions 4A and 4B are respectively included in P-type semiconductor region 2. P-type semiconductor region 2 is included in P-type semiconductor region 7.

[0160] When FIG. 15(b) and FIG. 7(c) are overlapped, N-type semiconductor regions 4A, 4B and P-type semiconductor region 2 overlap with N-type semiconductor region 5.

[0161] When FIGS. 15(a) and 15(b) are overlaid, in a plan view, the N-type semiconductor region 1A overlaps at least a part of the N-type semiconductor region 4A. In a plan view, the N-type semiconductor region 1B overlaps at least a part of the N-type semiconductor region 4B. As described above, in a plan view, it is preferable that all regions of the N-type semiconductor region 1 overlap so as to be included in the N-type semiconductor region 4 in the plan view.

[0162] Note that when FIGS. 15(a) and 15(b) are overlaid, the N-type semiconductor region 6 overlaps at least a part of the P-type semiconductor region 2.

[0163] According to the configuration of this embodiment, the average migration distance of the charges generated in the photoelectric conversion region to the light detection region can be shortened by the N-type semiconductor regions 1 and the N-type semiconductor regions 4 arranged at a plurality of locations. Therefore, it is possible to shorten the time required for charge detection of the charges generated at a deep position in the photoelectric conversion region.

[0164] This embodiment is applicable to all embodiments.

[0165] (Embodiment 6) FIG. 16 is a cross-sectional schematic view of the avalanche diode and the control unit in this embodiment. Parts having the same functions as those in FIGS. 1 to 15 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0166] In FIG. 16, the photoelectric conversion unit 201 and the control unit 202 are arranged on different semiconductor substrates. The configuration of the avalanche diode constituting the photoelectric conversion unit 201 is the same as that in Embodiment 1. A plurality of photoelectric conversion units 201 are arranged on the semiconductor substrate 15, and here, a configuration in which two avalanche diodes are arranged as an example is shown. On the semiconductor substrate 1102, a control unit 202 and a wiring 1107 connected to the control unit 202 are arranged. Here, a configuration in which the control unit 202 and the wiring 1107 are arranged on the semiconductor substrate 1102 is shown, but other circuits may be arranged.

[0167] The avalanche diode of this embodiment has a back-illuminated structure. Also, light is incident in a direction from the N-type semiconductor region 5 toward the N-type semiconductor region 1. At this time, the light is incident on the N-type semiconductor region 5 through the microlens 1103 and the color filter 1104.

[0168] As described above, photoelectric conversion occurs in the N-type semiconductor region 5, and the generated charges pass through the N-type semiconductor region 4 and move to the N-type semiconductor region 1. Avalanche amplification occurs due to the electric field between the depletion layer formed between the N-type semiconductor region 1, the P-type semiconductor region 2, and the N-type semiconductor region 4, and a current flows through the wiring 9.

[0169] The wiring 9 is connected to the control unit 202 provided on the separately fabricated semiconductor substrate 1102 via the connection portion 1105.

[0170] The signals detected for each avalanche diode are processed by a scanning circuit or the like provided around the pixel region of the semiconductor substrate 1102. Note that the scanning circuit may be arranged on a semiconductor substrate different from the semiconductor substrates 15 and 1102.

[0171] According to the configuration of this embodiment, a different semiconductor substrate 1102 is laminated on the semiconductor substrate 15 on which the avalanche diode is arranged. By arranging a processing circuit such as the control unit 202 on the laminated semiconductor substrate 1102, it is possible to increase the aperture ratio of the avalanche diode and improve the light detection efficiency.

[0172] In this embodiment, when the microlens 1103 is arranged for each avalanche diode, it is preferable that the optical axis of the microlens 1103 has a positional relationship such that it is included in the N-type semiconductor region 4 in plan view. For example, when vertical light is incident at the center of the photoelectric conversion element 101, the distribution of the generation probability of signal charges inside the N-type semiconductor region 5 is maximum near the optical axis of the microlens 1103. Here, the optical axis of the microlens is an axis perpendicular to the semiconductor substrate 15 passing through the center of the microlens in plan view.

[0173] As in the configuration of this embodiment, if the optical axis of the microlens 1103 is planar-ly included in the N-type semiconductor region 4, in the N-type semiconductor region 5, charges are likely to be generated at a position close to the N-type semiconductor region 4 in plan view. Then, it is possible to reduce the generation probability of charges generated at a planar-ly distant position, and it is possible to suppress a decrease in the time resolution until charge detection in the light detection region between the charges generated at a shallow position with respect to the first surface of the semiconductor substrate 15 and the charges generated at a deep position.

[0174] Note that, in this embodiment, a back-illuminated photodiode configuration is adopted, but even in the case of a front-illuminated type, the effects according to this embodiment, that is, both high light detection efficiency and low DCR can be realized. However, in this embodiment, since the configuration is such that the photoelectric conversion unit is formed on the back side, compared with the case of the front-illuminated type, in the case of the back-illuminated type, charges generated near the outermost surface of the substrate (the light incident side) can be detected with high efficiency. That is, from the viewpoint that high light detection efficiency can be realized in a broad wavelength band from short wavelength to long wavelength, the photoelectric conversion unit 201 of this embodiment is preferably of the back-illuminated type.

[0175] This embodiment is applicable to all embodiments.

[0176] (Embodiment 7) In this embodiment, an example of a light detection system using the light detection device 1010 of each embodiment will be described. An example of an invisible light detection system and a medical diagnosis system such as PET, which are examples of the light detection system, will be described with reference to FIG. 17. Parts having the same functions as those in FIGS. 1 to 16 are denoted by the same reference numerals, and detailed descriptions thereof are omitted. Note that the pixel 100 of this embodiment has a TDC and a memory instead of the counter circuit 209 in FIG. 5. Here, the TDC will be described as TDC204 and the memory as memory 205.

[0177] FIG. 17 is a block diagram for explaining the configuration of the invisible light detection system. The invisible light detection system includes a wavelength conversion unit 1201 and a data processing unit 1207, and includes a plurality of light detection devices 1010.

[0178] The irradiator 1200 irradiates light in a wavelength band that becomes invisible light. The wavelength conversion unit 1201 receives the light in the wavelength band that becomes invisible light irradiated from the irradiator 1200 and irradiates visible light.

[0179] The photoelectric conversion unit 201 into which the visible light irradiated from the wavelength conversion unit 1201 is incident performs photoelectric conversion, and based on the signal based on the charge obtained by the photoelectric conversion, the light detection device 1010 holds a digital signal in the memory 205 via the control unit 202, the waveform shaping unit 203, and the TDC 204. The plurality of light detection devices 1010 may be formed as one device or may be formed by arranging a plurality of devices.

[0180] The plurality of digital signals held in the memories 205 of the plurality of light detection devices 1010 are signal-processed by the data processing unit 1207. Here, as the signal processing means, composite processing of a plurality of images obtained from the plurality of digital signals is performed.

[0181] Next, as a specific example of the invisible light detection system, the configuration of a medical diagnosis system such as PET will be described.

[0182] The subject, which is the irradiator 1200, emits a pair of radiations from within the living body. The wavelength conversion unit 1201 constitutes a scintillator, and when a pair of radiations emitted from the subject is incident, the scintillator irradiates visible light.

[0183] The photoelectric conversion unit 201 into which the visible light irradiated from the scintillator is incident performs photoelectric conversion, and based on the signal based on the charge obtained by the photoelectric conversion, the light detection device 1010 holds a digital signal in the memory 205 via the control unit 202, the waveform shaping unit 203, and the TDC 204. That is, the light detection device 1010 is arranged to detect the arrival time of the pair of radiations emitted from the subject, detects the visible light irradiated from the scintillator, and holds a digital signal in the memory 205.

[0184] The digital signals held in the memory 205 of the plurality of photodetection devices 1010 are signal - processed in the data processing unit 1207. Here, as signal - processing means, synthesis processing such as image reconstruction is performed using a plurality of images obtained from the plurality of digital signals, and an image of the subject's living body is formed.

[0185] (Example 8) In this example, an example of an optical detection system using the photodetection device 1010 of each example will be described. Parts having the same functions as those in FIGS. 1 to 16 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0186] In FIG. 18, a distance detection system which is an example of an optical detection system will be described. Note that the pixel 100 of this example has a TDC and a memory instead of the counter circuit 209 in FIG. 5. Here, the TDC will be described as TDC204 and the memory as memory 205.

[0187] Using FIG. 18, an example of a block diagram of the distance detection system of this example will be described. The distance detection system includes a light source control unit 1301, a light emitting unit 1302, an optical member 1303, a photodetection device 1010, and a distance calculation unit 1309.

[0188] The light source control unit 1301 controls the driving of the light emitting unit 1302. When the light emitting unit 1302 receives a signal from the light source control unit 1301, it irradiates light in short pulses (series) in the shooting direction.

[0189] The light irradiated from the light emitting unit 1302 is reflected by the subject 1304. The reflected light is received by the photoelectric conversion unit 201 of the photodetection device 1010 through the optical member 1303, and a signal based on the photoelectrically - converted charge is input to the TDC204 via the waveform shaping unit 203.

[0190] TDC204 compares the signal obtained from the light source control unit 1301 with the signal input from the waveform shaping unit 203. Then, it digitally converts with high precision the time from when the light emitting unit 1302 emits pulsed light until the reflected light reflected by the subject 1304 is received. The digital signal output from TDC204 is held in the memory 205.

[0191] Based on the digital signals for multiple measurements held in the memory 205, the distance calculation unit 1309 calculates the distance from the light detection device to the subject. This distance detection system can be applied, for example, to in-vehicle use.

[0192] Next, FIG. 19 shows an example of a light detection system when using the counter circuit 209 in FIG. 5. In FIG. 19, a light detection system for an in-vehicle camera, which is an example of a light detection system, will be described.

[0193] The light detection system 1000 is a light detection system including the distance measurement pixel and the imaging pixel according to the present invention. The light detection system 1000 has an image processing unit 1030 that performs image processing on a plurality of digital signals acquired by the light detection device 1010. Further, the light detection system 1000 has a parallax calculation unit 1040 that calculates parallax (phase difference of the parallax image) from a plurality of image data acquired by the image processing unit 1030.

[0194] Also, the light detection system 1000 has a distance measurement unit 1050 that calculates the distance to the object based on the calculated parallax, and a collision determination unit 1060 that determines whether there is a possibility of collision based on the calculated distance. Here, the parallax calculation unit 1040 and the distance measurement unit 1050 are examples of distance information acquisition means for acquiring distance information to the object. That is, the distance information is information regarding parallax, defocus amount, distance to the object, and the like.

[0195] The collision determination unit 1060 may determine the possibility of collision using any of these distance information. The distance information acquisition means may be realized by dedicatedly designed hardware, may be realized by a software module, or may be realized by a combination of these. Further, it may be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or the like. Furthermore, it may be realized by a combination of these.

[0196] The light detection system 1000 is connected to the vehicle information acquisition device 1310 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Further, the light detection system 1000 is connected to a control ECU 1410, which is a control device that outputs a control signal for generating a braking force for the vehicle based on the determination result of the collision determination unit 1060.

[0197] Also, the light detection system 1000 is also connected to an alarm device 1420 that issues an alarm to the driver based on the determination result of the collision determination unit 1060. For example, when the possibility of collision is high as a determination result of the collision determination unit 1060, the control ECU 1410 performs vehicle control to avoid collision and reduce damage, such as applying brakes, returning the accelerator, and suppressing engine output. The alarm device 1420 warns the user by sounding an alarm such as a sound, displaying alarm information on a screen of a car navigation system, or applying vibration to a seat belt or a steering wheel.

[0198] In this embodiment, the light detection system 1000 images the surroundings of the vehicle, for example, the front or the rear. FIG. 19(B) shows the light detection system when imaging the front of the vehicle. In addition, although the control that does not collide with other vehicles has been described above, it is also applicable to the control of automatically driving while following other vehicles and the control of automatically driving so as not to deviate from the lane. Furthermore, the light detection system is not limited to vehicles such as the host vehicle, and can be applied to moving bodies (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to moving bodies but also to devices that widely use object recognition, such as an advanced road traffic system (ITS).

Explanation of Reference Numerals

[0199] 1 N-type semiconductor region 2 P-type semiconductor region 4 N-type semiconductor region 5 N-type semiconductor region 6 N-type semiconductor region 15 Semiconductor substrate 16 Separation part

Claims

[Claim 1] a semiconductor substrate having a first surface and a second surface opposite to the first surface; a region in which a plurality of avalanche diodes are arranged on the semiconductor substrate, The avalanche diode is a first semiconductor region of a first conductivity type disposed at a first depth relative to the first surface; a second semiconductor region of a second conductivity type opposite to the first conductivity type and disposed at a second depth relative to the first surface that is deeper than the first depth; a third semiconductor region disposed at a third depth relative to the first surface that is deeper than the second depth; a fourth semiconductor region disposed at the first depth and adjacent to the first semiconductor region; an isolation portion provided between the third semiconductor regions of each of the plurality of avalanche diodes; the first semiconductor region and the second semiconductor region are configured to form a region in which avalanche amplification occurs; a potential level for the first conductive type charge in the fourth semiconductor region is lower than a potential level for the first conductive type charge in a portion between the fourth semiconductor region and the third semiconductor region; A photodetection device characterized in that a difference between a potential height for the first conductivity type charge in the first semiconductor region and a potential height for the first conductivity type charge in the second semiconductor region is greater than a difference between a potential height for the first conductivity type charge in the fourth semiconductor region and a potential height for the first conductivity type charge in a portion between the fourth semiconductor region and the third semiconductor region.

Images