Trench power rails in cell circuits to reduce resistance and associated power distribution networks and methods of manufacture - Patents.com

Abstract

The integrated circuit includes a trench power rail to reduce resistance in the power rail or avoid an increase in resistance of the power rail as a result of the size of the metal tracks being reduced as technology node sizes are reduced. The trench power rail is formed in an isolation region between cell circuits. The cell isolation trench in the isolation region provides additional volume for placing additional metal material to form the trench power rail and increase its cross-sectional area. The trench power rail extends through a via layer to a metal layer that includes signal interconnects. The trench power rail extends widthwise from the cell isolation trench in the via layer to couple to the trench contact of an adjacent cell circuit without a vertical interconnect access (via). A high-k dielectric layer can selectively isolate the trench power rail from the cell circuit.

Description

[Technical field]

[0001] Priority Application

[0001] This application claims priority to U.S. patent application Ser. No. 17 / 648,981, entitled "TRENCH POWER RAIL IN CELL CIRCUITS TO REDUCE RESISTANCE AND RELATED POWER DISTRIBUTION NETWORKS AND FABRICATION METHODS," filed on January 26, 2022, the entire contents of which are incorporated by reference into this specification.

[0002] I. Field of Disclosure The field of this disclosure relates generally to power rails in integrated circuits (ICs), and specifically to the distribution of supply voltage and ground connections to standard cell circuits. [Background technology]

[0003] II. Background

[0003] Integrated circuits (ICs) used in electronic devices are constantly becoming smaller in size to fit more functions into smaller volumes, reduce power consumption, and reduce cost. A circuit integrated on a single die can contain millions of transistors on a semiconductor surface. The transistors in an IC are implemented as standard cell circuits in standard cells with a uniform layout on the semiconductor surface to increase area efficiency. The transistors are interconnected by signal interconnects provided in metal layers above the semiconductor surface to form the desired circuit. Each metal layer is vertically separated from each other by a via layer. Vertical interconnect accesses (vias) in the via layer provide vertical connections between the metal interconnects in each metal layer.

[0004]

[0004] Power is supplied by a supply voltage (e.g., V DD ) and the ground voltage on the power rail (for example, V SS) to the standard cell circuits. Supply and ground voltage power rails are formed in a metallization layer that also includes signal interconnects that carry signals between the standard cells. The power rails extend beyond a given cell circuit and to multiple adjacent cell circuits to provide power to such circuits. Thus, the total current flowing through the power rails is greater than the current levels at the signal interconnects as a result of current division. Power loss in the power rails due to Joule heating (e.g., "I 2 To reduce the "R drop" (cross-sectional area), power rails are made larger in cross section than the signal interconnects. Because the metallization layer on which the power rails are formed has a uniform thickness, making the power rails wider than the signal interconnects results in a larger cross section. However, the width of the power rails contributes to the total area of ​​the IC.

[0005]

[0005] Voltage variations between a supply voltage on a supply voltage power rail and a ground voltage on a ground voltage power rail are distributed to the standard cells. Such variations (e.g., noise) in the voltage between the power supply and ground can cause the standard cell circuit to operate improperly, resulting in soft errors in the IC. To reduce such noise, decoupling capacitors are provided between the supply voltage power rail and the ground voltage power rail in the power distribution network. The frequency of the noise protection provided by the decoupling capacitor decreases with increasing resistance in the rail, and since protection from high frequency noise is required in wireless devices, decoupling capacitors with large capacitance (e.g., with lower series resistance) with a high quality factor are preferred. However, the decoupling capacitor may require a larger area to achieve a larger capacitance, which also contributes to the total area of ​​the IC. Summary of the Invention

[0006]

[0006] Exemplary aspects disclosed in the Detailed Description include trench power rails in cell circuits to reduce resistance and associated power distribution networks. Related methods of making trench power rails are also disclosed. An integrated circuit (IC) includes cell circuits (also referred to as "cells") formed in cell regions in circuit cells on a semiconductor substrate. The circuit cells may be standard cells including P-type and N-type material diffusion regions to form P-type metal-oxide-semiconductor (PMOS) and N-type metal-oxide-semiconductor (NMOS) transistors to form logic circuits. The cell circuits in the circuit cells are isolated from one another by cell isolation trenches in isolation regions between adjacent circuit cells, while the cell circuits are coupled to one another by signal interconnects that run horizontally in metal tracks in a metal layer above the semiconductor substrate. The metal layer also includes power rails for providing power to the cell circuits. In exemplary embodiments, to reduce the resistance of the power rail in the circuit cell or to avoid an increase in the resistance of the power rail as a result of the size of the metal track being reduced as technology node sizes are reduced, the power rail is formed as a trench power rail in the power rail track and cell isolation trench. The cell isolation trench provides additional volume for disposing additional metal material to form the power rail to increase its cross-sectional area, thereby reducing its resistance. The trench power rail also extends through the via layer between the power rail track and the cell isolation trench. The power rail extends from the cell isolation trench in the via layer to couple to the trench contact of an adjacent circuit cell. As a result, a vertical interconnect access (via) is not required in the via layer between the first metal layer and the trench contact to couple the power rail to the trench contact. In some exemplary embodiments, a high-k dielectric layer, such as hafnium oxide, zirconium oxide, or aluminum oxide, is disposed in the cell isolation trench between the trench contact(s) and the power rail to isolate the power rail from one or both of the circuit cells on either side of the cell isolation trench.

[0007]

[0007] In another exemplary aspect, a trench decoupling capacitor in a power distribution network of an IC includes at least a first trench rail coupled to a supply voltage and at least a second trench rail coupled to a ground voltage. The first trench rail and the second trench rail are separated from each other by a high-k dielectric layer. In some embodiments, the trench rail of the decoupling capacitor extends through a first metal layer, a via layer, and into a cell isolation trench layer on a semiconductor substrate. One or more of the trench decoupling capacitors disposed between the circuit cells reduce noise in the power distribution network.

[0008]

[0008] In an exemplary aspect, an integrated circuit (IC) is disclosed herein. The IC comprises a first cell circuit comprising a first trench contact disposed in a first metal layer, the first trench contact extending in a first direction along a first longitudinal axis. The IC comprises a second cell circuit comprising a second trench contact disposed in the first metal layer, the second trench contact extending in the first direction along a second longitudinal axis. The IC also comprises a cell isolation trench in an isolation region between a first end of the first trench contact and a second end of the second trench contact. The IC comprises a second metal layer adjacent to the first metal layer in the second direction, the first thickness of the second metal layer extending in the second direction. The IC further comprises a via layer between the first metal layer and the second metal layer, the second thickness of the via layer extending in the second direction. The IC also includes a trench power rail in the cell isolation trench, the trench power rail extending in a third direction along a third longitudinal axis, and a thickness of the trench power rail including a first thickness of the second metal layer, a second thickness of the via layer, and a third thickness of the first metal layer.

[0009]

[0009] In another exemplary aspect, an IC is disclosed. The IC comprises a first power rail and a second power rail, the first power rail and the second power rail extending in a first direction within a first metal layer. The IC also comprises a decoupling capacitor comprising a first trench capacitor rail extending in the first direction. The decoupling capacitor also comprises a second trench capacitor rail extending in the first direction adjacent to the first trench capacitor rail. The decoupling capacitor also comprises a first dielectric layer disposed between the first trench capacitor rail and the second trench capacitor rail. The decoupling capacitor also comprises a first trench contact extending in the second direction within the first metal layer and coupling the first trench capacitor rail to the first power rail. The decoupling capacitor further comprises a second trench contact extending in the second direction within the first metal layer and coupling the second trench capacitor rail to the second power rail.

[0010] In another exemplary aspect, a method of manufacturing an integrated circuit (IC) is disclosed. The method includes forming a first cell circuit including a first trench contact disposed in a first metal layer, the first trench contact extending in a first direction along a first longitudinal axis, and forming a second cell circuit including a second trench contact disposed in the first metal layer, the second trench contact extending in the first direction along a second longitudinal axis. The method also includes forming a cell isolation trench in an isolation region between a first end of the first trench contact and a second end of the second trench contact, and forming a second metal layer adjacent to the first metal layer in a second direction, the second metal layer having a first thickness extending in the second direction. The method further includes forming a via layer between the first metal layer and the second metal layer, where a second thickness of the via layer extends in the second direction, and forming a trench power rail in the cell isolation trench, where the trench power rail extends in the third direction along a third longitudinal axis, where a thickness of the trench power rail includes the first thickness of the second metal layer, the second thickness of the via layer, and a third thickness of the first metal layer. [Brief description of the drawings]

[0011] [Figure 1A]

[0011] These are a layout diagram and a cross-sectional side view showing signal interconnects in metal tracks in metal layers within a cell circuit (e.g., a standard cell) and power rail tracks in metal layers that overlap isolation areas between circuit cells. [Figure 1B] 1A and 1B are a layout diagram and a cross-sectional side view, respectively, showing signal interconnects in metal tracks in metal layers within a cell circuit (e.g., a standard cell) and power rail tracks in metal layers that overlap isolation areas between circuit cells. [Figure 2A]

[0012] 1A and 1B are a layout diagram and a cross-sectional side view, respectively, of an integrated circuit (IC) including circuit cells including diffusion regions coupled to signal interconnects disposed in a metal layer, and an exemplary trench power rail extending across isolation regions between adjacent circuit cells to reduce resistance and couple to the cell circuitry without vias. [Figure 2B] 1A and 1B are a layout diagram and a cross-sectional side view, respectively, of an integrated circuit (IC) including circuit cells including diffusion regions coupled to signal interconnects disposed in a metal layer, and an exemplary trench power rail extending across isolation regions between adjacent circuit cells to reduce resistance and couple to the cell circuitry without vias. [Diagram 3]

[0013] 13 is a cross-sectional side view of a trench power rail in an isolation region between circuit cells coupled to cell circuitry on a second side of the trench power rail. [Figure 4]

[0014] FIG. 13 is a cross-sectional side view of a trench power rail in an isolation region between circuit cells, coupled to cell circuitry on either side of the trench power rail. [Diagram 5]

[0015] FIG. 13 is a cross-sectional side view of a trench power rail in an isolation region between circuit cells where the cell circuitry is not coupled to the trench power rail. [Figure 6]

[0016] 2C is a cross-sectional side view of an IC corresponding to FIG. 2B but including a trench power rail and a trench contact coupled to a planar diffusion region. [Figure 7]

[0017] 2C corresponds to FIG. 2B, but is a cross-sectional side view of an IC including a trench power rail and a trench contact coupled to a gate-all-around (GAA) diffusion region. [Figure 8]

[0018] FIG. 1 is a top view layout diagram of an integrated circuit including a trench power rail disposed in an isolation region between circuit cells and a decoupling capacitor coupled to the trench power rail to reduce noise in the supply voltage, the decoupling capacitor comprising multiple adjacent trench rails within the circuit cell area. [Figure 9]

[0019] 1 is a side cross-sectional view of an IC including a decoupling capacitor including a trench power rail in an isolation region between circuit cells and an adjacent trench rail disposed in the circuit cell area. [Figure 10]

[0020] 1 is a side cross-sectional view of an IC including a decoupling capacitor including multiple adjacent trench capacitor rails within a circuit cell area and an isolation region between the circuit cells. [Figure 11]

[0021] 2C is a flowchart illustrating a method for manufacturing the IC shown in FIG. 2B. [Figure 12A]

[0022] 1 is a cross-sectional side view of a circuit cell at a first stage in the fabrication of the cell, showing a sacrificial placeholder for a signal interconnect in a metal layer. [Figure 12B]

[0023] 1 is a cross-sectional side view at a second stage of fabrication in which trenches are formed for trench power rails in the isolation regions between the circuit cells and a high-k dielectric layer is formed in the trenches. [Figure 12C]

[0024] FIG. 13 is a cross-sectional side view at a third stage of fabrication where the sacrificial placeholder has been removed. [Figure 12D]

[0025] FIG. 13 is a cross-sectional side view at a fourth stage of fabrication in which the high-K dielectric is patterned. [Figure 12E]

[0026] FIG. 13 is a cross-sectional side view at a fifth stage of fabrication, in which signal interconnects and trench power rails are formed in a metallization process. [Figure 13A] 4 is a first block of a flow chart illustrating the corresponding stages of manufacture. [Figure 13B] 4 is a first block of a flow chart illustrating the corresponding stages of manufacture. [Figure 13C] 4 is a first block of a flow chart illustrating the corresponding stages of manufacture. [Figure 13D] 4 is a first block of a flow chart illustrating the corresponding stages of manufacture. [Figure 13E]4 is a first block of a flow chart illustrating the corresponding stages of manufacture. [Figure 14]

[0027] As shown in FIGS. 2A-7 and 12E, a block diagram of an exemplary wireless communication device including a radio frequency (RF) module including an IC that includes a trench power rail with an increased cross-section to reduce resistance and eliminate vias to the power rail. [Figure 15]

[0028] As shown in Figures 2A-7 and 12E, block diagrams of an example processor-based system that may include an IC including trench power rails with increased cross-sectional area to reduce resistance and eliminate vias according to any of the aspects disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012]

[0029] Some exemplary aspects of the present disclosure will now be described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0013]

[0030] Exemplary aspects disclosed in the Detailed Description include trench power rails in cell circuits to reduce resistance and associated power distribution networks. Related methods of fabricating trench power rails are also disclosed. An integrated circuit (IC) includes cell circuits (also referred to as "cells") formed in cell regions in circuit cells on a semiconductor substrate. The circuit cells may be standard cells including P-type and N-type material diffusion regions to form P-type metal oxide semiconductor (PMOS) and N-type metal oxide semiconductor (NMOS) transistors to form logic circuits. The cell circuits in the circuit cells are isolated from one another by cell isolation trenches in isolation regions between adjacent circuit cells, while the cell circuits are coupled to one another by signal interconnects that run horizontally in metal tracks in a metal layer above the semiconductor substrate. The metal layer may also include power rails for providing power to the cell circuits. In exemplary aspects, the power rails are formed as trench power rails in the power rail tracks and cell isolation trenches to reduce the resistance of the power rails in the circuit cells or to avoid increased resistance of the power rails as a result of the metal track sizes being reduced as technology node sizes are reduced. The cell isolation trench provides additional volume for disposing additional metal material to form the power rail to increase its cross-sectional area, thereby reducing its resistance. The trench power rail also extends through the via layer between the power rail track and the cell isolation trench. The power rail extends from the cell isolation trench in the via layer to couple to the trench contact of an adjacent circuit cell. As a result, a vertical interconnect access (via) is not required in the via layer between the first metal layer and the trench contact to couple the power rail to the trench contact. In some exemplary embodiments, a high-k dielectric layer is disposed in the cell isolation trench between the trench contact(s) and the power rail to isolate the power rail from one or both of the circuit cells on either side of the cell isolation trench.

[0014]

[0031] 2A-15, FIGS. 1A and 1B provide a top layout view and a cross-sectional side view, respectively, of an integrated circuit (IC) 100 for reference in the following description of features of a first cell circuit 102 and a second cell circuit 104 ("cell circuits 102, 104"). Here, a limited number of features of the first cell circuit 102 and the second cell circuit 104 are shown, as appropriate. The cell circuits 102, 104 may be standard cell circuits interconnected by signal interconnects 106 in a metal layer 108. The cell circuits 102, 104 are connected to a supply voltage V DD and the reference voltage V SS Each of the cell circuits 102, 104 also includes a diffusion region 112 in a semiconductor substrate 114 for forming a transistor 116. Signal interconnects 106 may be configured to couple the transistor 116 in each cell circuit 102, 104 with other cell circuits (not shown) on the IC 100 to achieve a desired circuit function.

[0015]

[0032] Diffusion region 112 may be a fin-type diffusion region 112 or a gate-all-around device such as a nanosheet on a semiconductor substrate 114. Gate 118 and gate 120 (e.g., polysilicon gates) are disposed over a channel region 122 of diffusion region 112 to control (e.g., allow or disallow) current flow through diffusion region 112 and to provide a voltage V SD may be provided to the source / drain region 124 of the diffusion region 112 through a trench contact 126. For example, the transistor 116 may receive a voltage V SD is passed to the drain / source region 128 of the diffusion region 112. GATE It can function as a switch controlled by a voltage V SD may be received at one of the signal interconnects 106 (e.g., from an external circuit) or, as in the embodiment shown in FIG. 1, a supply voltage (e.g., V DD ) or a reference voltage (e.g., VSS ) may also be used.

[0016]

[0033] 1A, the signal interconnect 106 and the power rail 110 extend in the X-axis direction in the metal layer 108. The power rail 110 overlaps an isolation region 130 between the first cell circuit 102 and the second cell circuit 104. The diffusion region 112 extends in the X-axis direction on the semiconductor substrate 114 and intersects with the gate 118 and the trench contact 126 that extend in the Y-axis direction. The gate 118 is disposed on the semiconductor substrate 114 and extends in the Z-axis direction over the diffusion region 112. The trench contact 126 in the cell circuit 102 is formed in the metal layer 132 and is coupled to the diffusion region 112. The trench contact 126 is formed by depositing a metal 134 (e.g., copper) in a trench 136 in an inter-layer dielectric (ILD) 138 on the semiconductor substrate 114. In contrast to the gate 118, which is electrically insulated from the diffusion region 112 by a gate dielectric layer 140, the trench contact 126 is directly coupled to the diffusion region 112 to provide an electrical connection to the source / drain region 124. The trench contact 126 in the metal layer 132 is coupled to the signal interconnect 106 in the metal layer 108 by a vertical interconnect access (via) 142 formed in a via layer 144 between the metal layers 108 and 132.

[0017]

[0034] As technology advances from one technology node to the next, some features of the cell circuits 102, 104 become smaller, while others become bottlenecks to such shrinkage. For example, each of the signal interconnects 106 disposed in metal layer 108 has a metal track pitch P 106 Based on the width W 106 Also, in the X-axis direction, the width W 106 Each new generation has a width W 106 As a result, the cross-sectional area A of the signal interconnect 106 106 is reduced, which increases the resistance of the signal interconnect 106. Similarly, the width W142 is reduced in both the X-axis and Y-axis directions, which increases the connection resistance between metal layer 108 and metal layer 132.

[0018]

[0035] Because the power rails 110 are used to power multiple cell circuits 102, 104 that may require significantly more current than the signals in the signal interconnects 106, the power rails 110 have a larger cross-sectional area than the signal interconnects 106 to reduce resistance. The signal interconnects 106 and the power rails 110 have a thickness T 108 Since the power rail 110 has a width W 110 is the cross-sectional area A of the power rail 110 110 In order to increase 106 However, from one technology node to the next, the width dimension W 110 Even the cross-sectional area A 110 and reduce the resistance R of the power rail 110. 110 Increase the

[0019]

[0036] As described above, the power rail 110 overlaps the isolation region 130 between the first cell circuit 102 and the second cell circuit 104. The isolation region 130 is spaced apart from the minimum tip-to-tip distance D between the end 146 of the trench contact 126 in the first cell circuit 102 and the end 148 of the trench contact 150 in the second cell circuit 104. T2T Based on the minimum tip distance D T2T is a design rule based on manufacturing tolerances to reduce short defects between the cell circuits 102 and 104. In addition, the trench contact 126 extends in the Y-axis direction from the diffusion region 112 to provide a landing area A under the power rail 110 for the via 142 to couple the power rail 110 to the trench contact 126. VIA Therefore, the isolation region 130 and the trench contact landing region A VIA is an aspect of the cell circuits 102, 104 that is difficult to reduce.

[0020]

[0037] 2A and 2B are a layout and cross-sectional side view, respectively, of an IC 200 including a first cell circuit 202 and a second cell circuit 204 ("cell circuits 202, 204") including a diffusion region 206 of a transistor 208 formed in a semiconductor substrate 210. The transistor 208 of the cell circuit 202 is coupled to the second cell circuit 204 and an external circuit (not shown) by a signal interconnect 212 and vias 216 in a metal layer 214. One of the vias 216 extends between a first trench contact 218 in a metal layer 220 and the metal layer 214. An exemplary trench power rail 222 extends along an isolation region 224 between the cell circuits 202 and 204. The trench power rail has a width W (e.g., in the Y-axis direction) that extends across the isolation region 224 to reduce resistance in the trench power rail 222 and to provide power to the cell circuits 202, 204 without the vias 216. 222B and a height H (e.g., in the Z-axis direction) extending from metal layer 214 into cell isolation trench 226. 222 As described further below, trench power rail 222 may be formed over metal layer 220 in cell isolation trench 226, via layer 230, and metal layer 214 all as a monolithic metal layer formed in a single process step. Trench power rail 222 may be part of a power distribution network (not shown) in IC 200, and may improve the quality factor (Q) of IC 200 by reducing the resistance of trench power rail 222.

[0021]

[0038] The cell circuits 202, 204 are formed in a circuit cell 231 and are separated from one another by a cell isolation trench 226 in an isolation region 224. The cell circuits 202, 204 may be coupled to one another by a signal interconnect 212 that extends horizontally (e.g., in the X-axis, Y-axis plane) in a metal track 228 in a metal layer 214 over the semiconductor substrate 210. The cell isolation trench 226 has a cross-sectional area A 222 By using the trench power rail 222 as disclosed herein, the thickness of the existing power rail (metal layer 108 thickness T108 1 (such as the power rail 110 of FIG. 1 , which is limited to 100 Å), the resistance in supplying power to the cell circuits 202, 204 can be reduced and an increase in resistance as a result of the width of the metal track 228 being reduced in new technology nodes can be avoided. The trench power rail 222 extends through a via layer 230, in which a via 216 is formed between the metal layer 214 and the metal layer 220 in which the first trench contact 218 is formed. The trench power rail 222 extends from the cell isolation trench 226 in the Y-axis direction in the via layer 230 to couple to the first trench contact 218 of the first cell circuit 202 and the second trench contact 219 of the second cell circuit 204, which are on either side of the trench power rail 222. As a result, a via 216 is not required to couple the first trench contact 218 to the trench power rail 222. A high-k dielectric layer 232 can be disposed in the cell isolation trench 226 between the trench contacts 218, 219 and the trench power rail 222 to isolate the trench power rail 222 from one or both of the trench contacts 218, 219. As shown in FIG. 2B, a high-k dielectric layer 232 can be disposed over the second trench contact 219 to electrically insulate the second trench contact 219 from the trench power rail 222, but the high-k dielectric layer 232 is not disposed over the first trench contact 218, and therefore the trench power rail 222 is not connected to the supply voltage V DD and the reference voltage V SS , one of which (eg, ground or 0 volts) can be provided to the first trench contact 218.

[0022]

[0039] 2A and 2B, the cell circuits 202, 204 correspond to the cell circuits 102, 104 of FIG. 1, except as described below. The first cell circuit 202 includes a first trench contact 218 in the metal layer 214 and extending along a first longitudinal axis A1 in the Y-axis direction. The second cell circuit 204 includes a second trench contact 219 disposed in the metal layer 220 and extending along a second longitudinal axis A2 in the Y-axis direction. The axis A1 may be collinear with the axis A2. The cell isolation trench 226 is disposed in the isolation region 224 between an end 234 of the first trench contact 218 and a second end 236 of the second trench contact 219. The metal layer 220 is adjacent to the metal layer 214 in the Z-axis direction and has a thickness T 214 The via layer 230 is between the metal layer 220 and the metal layer 214 and has a thickness T 230 The trench power rail 222 extends along a longitudinal axis A3 in the X-axis direction and has a thickness T 222 is the thickness T of the metal layer 214 214 , the thickness T of the via layer 230 230 , and the thickness T of the metal layer in the cell isolation trench 226 226 Includes.

[0023]

[0040] The trench power rail 222 is connected to, for example, a supply voltage V DD or a reference (e.g., ground) voltage V SS Extending across the isolation region 224 in the Y-axis direction and having a height H 222 The trench power rail 222 having a large cross-sectional area A for the current to supply power to the cell circuits 202, 204. 2222B, the trench power rail 222 extends in the Y-axis direction on a surface 238 on the side of the first trench contact 218 adjacent the via layer 230 and on a surface 240 on the side of the second trench contact 219 adjacent the via layer 230. In addition to contacting end faces 242 and 244 of the trench contacts 218, 219, respectively, the trench power rail 222 may be disposed directly on a large area of ​​one or both of the surfaces 238, 240, or on neither of them. In this manner, the trench contacts 218, 219 have a low resistance electrical contact to the trench power rail 222. Alternatively, the trench power rail 222 may be indirectly disposed on the first trench contact 218 and / or the second trench contact 219, including being disposed on a high-k dielectric layer 232 that can be selectively disposed on surfaces 238, 240, 242, and 244 of the trench contacts 218, 219.

[0024]

[0041] The trench power rail 222 can be placed directly on the end 234 of the trench contact 218, so no via landing region is required. Thus, the trench contact 218 does not need to extend in the y-axis direction from the diffusion region 206 as far as the trench contact 126 of FIG. 1. The trench power rail 222 does not need to extend as far in the y-axis direction from the diffusion region 206 ... T2T The trench power rail 222 allows for a reduction in the dimension of the first cell circuit 202 in the Y-axis direction while still maintaining a . In addition, while existing power rails may have increased resistance due to smaller via cross-sectional areas, the exemplary trench power rail 222 avoids the need for vias and therefore the corresponding resistance in new technology nodes.

[0025]

[0042] More specifically, the trench power rail 222 disposed between the end 234 of the first trench contact 218 and the end 236 of the second trench contact 219 has a tip-to-tip distance D T2T A first width W 222AHere, since the high-k dielectric layer 232 is formed on the second trench contact 219, the width W 222A is the tip distance D T2T As the trench power rail 222 extends over the surfaces 238, 240, the width W of the trench power rail 222 in the Y-axis direction within the via layer 230 is 222B is the tip distance D T2T The trench power rail 222 also has a second width W 222B The second width W 222B is the width W of the power rail trench 246 formed in the inter-level dielectric (ILD) 248, as described further below. 306 The second width W 222B also depends on the patterning of the high-k dielectric layer 232.

[0026]

[0043] Figure 3 is a cross-sectional side view of an IC 300 including cell circuits 302 and 304 that correspond to cell circuits 202 and 204 in IC 200 of Figure 2, except that a trench power rail 306 of Figure 3 in an isolation region 308 between cell circuits 302 and 304 is coupled to cell circuit 304 and not to cell circuit 302. Figure 3 is provided to show a different pattern of high-k dielectric layer 310 than shown in Figure 2 to illustrate that trench power rail 306 can be configured to be coupled to one of cell circuits 302 and 304 on either side of isolation region 308.

[0027]

[0044] Figure 4 is a cross-sectional side view of another embodiment of an IC 400 in which a trench power rail 402 is coupled to cell circuits 404 and 406 on either side of an isolation region 408. In this regard, a high-k dielectric layer 410 may be formed (e.g., by deposition) in trench 412 and patterned to remove portions of high-k dielectric layer 410 over trench contact 414 and / or trench contact 416. Figure 4 includes a residual portion 418 of high-k dielectric layer 410 that remains in isolation region 408 after being patterned.

[0028]

[0045] 2B, 3, and 4, a trench power rail 502 is separated from a trench contact 504 by a high-k dielectric layer 506, and from a trench contact 508 by a high-k dielectric layer 506, which are on either side of an isolation region 510. FIG. 5 is provided to illustrate that the trench power rail 502, which does not rely on vias for connection to the trench contacts 504 and 508, can be routed through the isolation region 510 between the cell circuits 512 and 514 without being electrically coupled to the cell circuits 512 and 514.

[0029]

[0046] FIG. 6 is a cross-sectional side view of an IC 600 that in many respects corresponds to IC 200 of FIG. 2B, but is provided to illustrate that the trench power rail 602 described above can be used in an IC 600 that includes a trench contact 604 coupled to a planar diffusion region 606 formed on a semiconductor substrate 608.

[0030]

[0047] FIG. 7 is a cross-sectional side view of an IC 700 corresponding to FIG. 2B and is provided to illustrate that the trench power rail 702 described above can be used in an IC 700 that includes a trench contact 704 coupled to a gate-all-around (GAA) diffusion region 706 formed on a semiconductor substrate 708.

[0031]

[0048] FIG. 8 illustrates a supply voltage V DD A trench power rail 802 for providing a reference voltage V SS 8 is a top view layout diagram of an IC 800 including a cell circuit 804 and a trench power rail 806 for providing a supply voltage V DD and the reference voltage V SS8. The trench power rail 802 includes decoupling capacitors 808 and 810 coupled to the trench power rails 802 and 806 to reduce noise between the trench power rails 802 and 806. A plurality of cell circuits 804 are arranged in an array 812 of circuit cell regions 814. The trench power rail 802 extends in the X-axis direction along isolation regions 816 and 818, and the trench power rail 806 extends along isolation region 820. The cell circuits 804 may be coupled to the trench power rails 802 and 806 by trench contacts 822.

[0032]

[0049] Decoupling capacitors 808 and 810 are formed in two of the circuit cell regions 814 between trench power rail 806 and one of trench power rails 802. In some embodiments, IC 800 may include more or less decoupling capacitors than decoupling capacitors 808 and 810. Decoupling capacitors 808 and 810 are each coupled to trench power rail 806 and coupled to a reference voltage V SS The decoupling capacitors 808 and 810 each are coupled to one of the trench power rails 802 to provide a supply voltage V DD The decoupling capacitors 808 and 810 also include a second trench capacitor rail 826 providing a reference voltage V. In each of the decoupling capacitors 808 and 810, the first trench capacitor rail 824 and the second trench capacitor rail 826 are arranged in alternating order along the Y axis, with a high-k dielectric layer 828 disposed between adjacent trench power rails. Capacitance may be created between the first trench capacitor rail 824 and the second trench capacitor rail 826, and such capacitance may cause the cell circuitry 804 to operate improperly. SS Supply voltage V DDDecoupling capacitors 808, 810 located in close proximity to the cell circuitry 804 can provide a higher level of noise protection (e.g., higher Q) than decoupling capacitors external to the IC 800. Although decoupling capacitors 808, 810 each include two of the first trench capacitor rails 824 and two of the second trench capacitor rails 826, decoupling capacitors 808, 810 are not limited in this respect and may include more or fewer first trench capacitor rails 824 and second trench capacitor rails 826.

[0033]

[0050] 9 is a cross-sectional side view of an IC 900 including a decoupling capacitor 902 that includes a trench power rail 904 in an isolation region 906 between circuit cell regions 908 and 910. The decoupling capacitor 902 also includes a trench capacitor rail 912 disposed in the circuit cell region 908 adjacent to the trench power rail 904. In the cross-sectional view of FIG. 9, a trench contact 914 extends (e.g., in the Y-axis direction) from the circuit cell region 908 through the isolation region 906 to the circuit cell region 910 to couple a supply voltage V DD and the reference voltage V SS 9. The decoupling capacitor 902 couples one of the decoupling capacitor rails 912 to cell circuitry (not shown) in the circuit cell area 910. The circuit cell area 908 includes a diffusion region (e.g., a fin) 918 coupled to the trench contact 914, although since the decoupling capacitor 902 occupies the circuit cell area 908, the diffusion region 918 may or may not be used in the cell circuitry.

[0034]

[0051] Each of the trench power rail 904 and the trench capacitor rail 912 is disposed on a metal layer 922 that includes the signal interconnect 924, a via layer 926 that includes the via 928, and a metal layer 930 on which the trench contact 914 is formed (e.g., on either side of the trench contact 914 in the X-axis direction). A high-k dielectric layer 932 is disposed on a sidewall 934 of the trench power rail 904 between the sidewall 934 and the trench capacitor rail 912. Capacitance occurs in the high-k dielectric layer 932 between the sidewall 934 of the trench power rail 904 and the trench capacitor rail 912. The capacitance of the decoupling capacitor 902 is determined by the height H of the sidewall 934. 934 and the length (not shown) of the trench capacitor rail 912 and the trench power rail 904. In addition, a high-k dielectric layer 932 extends between the trench power rail 904 and the trench contact 914, increasing the capacitance of the decoupling capacitor 902.

[0035]

[0052] Figure 10 shows the supply voltage V DD and the reference voltage V SS a first trench capacitor rail 1006 coupled to a first one of the SS and the supply voltage V DD1 is a side cross-sectional view of an IC 1000 including a decoupling capacitor 1002 including a first trench capacitor rail 1006 and a second trench capacitor rail 1008 coupled to the other of the first and second trench capacitor rails 1006 and 1008. The first trench capacitor rail 1006 and the second trench capacitor rail 1008 are interleaved, with a high-k dielectric layer 1010 disposed between adjacent rails to provide high capacitance to the decoupling capacitor 1002. The first trench capacitor rail 1006 and the second trench capacitor rail 1008 are formed in a circuit cell region 1012 and an isolation region 1014 between the circuit cell region 1012 and the circuit cell region 1016. The first trench capacitor rail 1006 and the second trench capacitor rail 1008 are disposed in a metal layer 1022, a via layer 1024, and a metal layer 1026 in which a trench contact 1028 is formed. Forming the first and second trench capacitor rails 1006, 1008 with a large Z-axis dimension increases the surface area between adjacent rails, thereby increasing capacitance. In addition, the larger Z-axis dimension increases the cross-sectional area of ​​the first and second trench capacitor rails 1006, 1008 for lower resistance (e.g., to achieve a high Q factor). The decoupling capacitor 1002 is not limited to the first and second trench capacitor rails 1006, 1008 shown in FIG. 10 and may include more or less than those shown.

[0036]

[0053] 10, decoupling capacitor 1002 includes a first trench capacitor rail 1006(1) extending in the X-axis direction. First trench capacitor rail 1006 has a rail thickness T 1006 The decoupling capacitor 1002 includes a second trench capacitor rail 1008(1), which also extends in the X-axis direction and has a Z-axis thickness T 1008The decoupling capacitor 1002 includes a metal layer 1022, a via layer 1024, and a high-k dielectric layer 1027 in metal layer 1026 between a first trench capacitor rail 1006(1) and a second trench capacitor rail 1008(1). A trench contact 1028 extends in the metal layer 1026 along the y-axis and couples the first trench capacitor rail 1006(1) to a supply voltage V DD and the reference voltage V SS 8. A second trench contact (not shown in FIG. 10, but can be understood in view of FIG. 8) also extends in the y-axis direction within metal layer 1026 and couples second trench capacitor rail 1008(1) to a first trench power rail that provides one of the supply voltages V DD and the reference voltage V SS The other of the two is coupled to a trench power rail.

[0037]

[0054] In some embodiments, the decoupling capacitor 1002 further includes another first trench capacitor rail 1006(2) between the first trench capacitor rail 1006(1) and the second trench capacitor rail 1008(1). The first trench capacitor rail 1006(2) is coupled to a second trench contact (not shown). The decoupling capacitor 1002 also includes another second trench capacitor rail 1008(2) between the first trench capacitor rail 1006(1) and the other first trench capacitor rail 1006(2). The other second trench capacitor rail 1008(2) is coupled to a trench contact 1028. A high-k dielectric layer 1030 is disposed between the other first trench capacitor rail 1006(2) and the second trench capacitor rail 1008(2), and a high-k dielectric layer 1032 is disposed between the other first trench capacitor rail 1006(2) and the second trench capacitor rail 1008(1). In these examples, a high-k dielectric layer 1027 is disposed between the first trench capacitor rail 1006(1) and the other second trench capacitor rail 1008(2). In addition, a high-k dielectric layer 1034 is disposed between the other first trench capacitor rail 1006(1) and a second trench contact (not shown), and a high-k dielectric layer 1036 is disposed between the other second trench capacitor rail 1008(1) and the trench contact 1028.

[0038]

[0055] 11 is a flow chart illustrating a method of fabricating the IC 200 of FIGs. 2A and 2B. The method includes forming a first cell circuit 202 including a first trench contact 218 disposed in a first metal layer 220, the first trench contact 218 extending in a first direction (Y-axis direction) along a first longitudinal axis A1 (block 1102). The method further includes forming a second cell circuit 204 including a second trench contact 219 disposed in the first metal layer 220, the second trench contact 219 extending in a first direction along a second longitudinal axis A2 (block 1104). The method further includes forming a cell isolation trench 226 in an isolation region 224 between a first end 234 of the first trench contact 218 and a second end 236 of the second trench contact 219 (block 1106). The method further comprises: forming a second metal layer 214 adjacent to the first metal layer 220 in a second direction (Z-axis direction), the second metal layer 214 having a first thickness T 214 The method further includes forming a second metal layer 214 extending in a second direction (Z-axis direction) (block 1108). The method further includes forming a via layer 230 between the first metal layer 220 and the second metal layer 214, the via layer 230 having a second thickness T 230 The method also includes forming a via layer 230 extending in a second direction (Z-axis direction) (Block 1110). The method also includes forming a trench power rail 222 extending along a third longitudinal axis A3 in a third direction (X-axis) and having a trench power rail thickness T 222 is the first thickness T of the second metal layer 214. 214 , the second thickness T of the via layer 230 230 , and a third thickness T of the first metal layer 220 in the isolation region 224 220 The method further includes forming a trench power rail 222, the trench power rail 222 including:

[0039]

[0056] Figures 12A-12E are cross-sectional side views of IC 200 of Figure 2 at stages in its manufacture, and Figures 13A-13E are corresponding blocks of a flowchart illustrating a method corresponding to the stages in its manufacture shown in Figures 12A-12E. Where features of Figures 12A-12E correspond to features of Figures 2A and 2B, such features in Figures 12A-12E are labeled as such.

[0040]

[0057] 12A is a cross-sectional side view of a first stage of fabrication of the cell circuits 202, 204 showing sacrificial placeholders 1202 for the signal interconnects 212 and vias 216 in the metal layer 214. The process for forming the first cell circuit 202 and the second cell circuit 204 includes forming at least one of the diffusion regions 206 on the semiconductor substrate 210 in the first circuit cell 202 and at least one of the diffusion regions on the semiconductor substrate 210 in the second circuit cell 204. The process further includes forming a first trench contact 218 on the diffusion region 206 in the first cell circuit 202 and forming a second trench contact 219 on the diffusion region 206 in the second cell circuit 204. The process further includes forming an ILD 248 on the semiconductor substrate 210, the first trench contact 218, and the second trench contact 219, the thickness of the ILD 248 being less than the thickness T of the metal layer 214. 214 and the thickness T of the via layer 230 230 In Figure 13A, a method of forming a sacrificial placeholder 1202 as shown in Figure 12A includes forming a trench pattern 1204 in an ILD 248 that corresponds to a via 216 in a via layer 230 and a signal interconnect 212 in a metal layer 214 (block 1302). The method further includes filling the trench pattern 1204 with a sacrificial material 1206 (block 1304). The sacrificial material may be a soft mask such as amorphous silicon, spin-on carbon, or spin-on glass. The cell circuitry 202, 204 includes a diffusion region 206 and trench contacts 218, 219.

[0041]

[0058] 12B is a cross-sectional side view of a second stage of fabrication in which a power rail trench 246 is formed for the trench power rail 222 in the isolation region 224 between the cell circuits 202 and 204, and a high-k dielectric layer 232 is formed in the power rail trench 246. In FIG. 13B, the method of forming the trench power rail 222 as shown in FIG. 12B further includes forming the power rail trench 246 in the ILD 248, which includes removing the ILD 248 in the cell isolation trench 226 in the second metal layer 220 between the end 234 of the first trench contact 218 and the end 236 of the second trench contact 219 (block 1306). The method further includes removing the ILD 248 in the via layer 230 and the first metal layer 214 in the isolation region to expose the first surface 238 of the first trench contact 218 and the second surface 240 of the second trench contact 219 (block 1308). The method further includes forming a high-k dielectric layer 232 in the power rail trench 246 (block 1310).

[0042]

[0059] Figure 12C is a cross-sectional side view at a third stage of fabrication where the sacrificial placeholder 1202 has been removed. In Figure 13C, the method of forming the trench power rail 222 further includes removing the sacrificial material 1206 from the trench pattern 1204 in the ILD 248 (block 1312), as shown in Figure 12C.

[0043]

[0060] 12D is a cross-sectional side view of a fourth stage of fabrication in which the high-k dielectric layer is patterned. In FIG. 13D, the method at the stage shown in FIG. 12D includes selectively removing the high-k dielectric layer 232 from the first surface 238 of the first trench contact 218 and the second surface 240 of the second trench contact 219 (block 1314). Selectively removing the high-k dielectric layer 232 from the first surface 238 of the first trench contact 218 and the second surface 240 of the second trench contact 219 can include any of the following:

[0061] 1) removing the high-k dielectric layer 232 from the first surface 238 of the first trench contact 218, but not removing the high-k dielectric layer 232 from the second surface 240 of the second trench contact 219;

[0062] 2) removing the high-k dielectric layer 232 from a first surface 238 of the first trench contact 218 and removing the high-k dielectric layer 232 from a second surface 240 of the second trench contact 219; and

[0063] 3) not removing the high-k dielectric layer 232 from the first surface 238 of the first trench contact 218 and not removing the high-k dielectric layer 232 from the second surface 240 of the second trench contact 219.

[0044]

[0064] Selectively removing the high-k dielectric layer 232 may include applying a mask (not shown) and removing portions of the high-k dielectric layer 232 that are not covered by the mask.

[0045]

[0065] Figure 12E is a cross-sectional side view at a fifth stage of fabrication in which signal interconnect 212 and trench power rail 222 are formed. In Figure 13E, as shown in Figure 12E, the method of forming trench power rail 222, forming via layer 230, and forming a second metal layer includes disposing metal 1208 in each of power rail trench 246 and trench pattern 1204 in ILD 248 (block 1316). Disposing metal 1208 can involve applying a mask and performing metallization in which metal (e.g., copper) is formed or deposited in power rail trench 246 and trench pattern 1204.

[0046]

[0066] FIG. 14 illustrates an exemplary wireless communication device 1400 including a radio frequency (RF) component formed from one or more ICs 1402. Any of the ICs 1402 may include a trench power rail with an increased cross section to reduce resistance and eliminate vias to the power rail according to any of the aspects disclosed herein, as shown in FIGS. 2A-7 and 12E. The wireless communication device 1400 may include or be provided within any of the above devices, as examples. As shown in FIG. 14, the wireless communication device 1400 includes a transceiver 1404 and a data processor 1406. The data processor 1406 may include a memory for storing data and program code. The transceiver 1404 includes a transmitter 1408 and a receiver 1410 supporting bidirectional communication. In general, the wireless communication device 1400 may include any number of transmitters 1408 and / or receivers 1410 for any number of communication systems and frequency bands. All or a portion of the transceiver 1404 may be implemented on one or more analog ICs, RFICs, mixed-signal ICs, etc.

[0047]

[0067] The transmitter 1408 or receiver 1410 may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In a super-heterodyne architecture, a signal is frequency converted between RF and baseband in multiple stages, e.g., from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and / or have different requirements. In the wireless communication device 1400 of FIG. 14, the transmitter 1408 and receiver 1410 are implemented with a direct-conversion architecture.

[0048]

[0068] On the transmit path, the data processor 1406 processes data to be transmitted and provides I and Q analog output signals to a transmitter 1408. In the example wireless communication device 1400, the data processor 1406 includes digital-to-analog converters (DACs) 1412(1), 1412(2) to convert digital signals generated by the data processor 1406 to I and Q analog output signals, e.g., I and Q output currents, for further processing.

[0049]

[0069] Within the transmitter 1408, low pass filters 1414(1), 1414(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1416(1), 1416(2) amplify the signals from the low pass filters 1414(1), 1414(2), respectively, and provide I and Q baseband signals. An upconverter 1418 upconverts the I and Q baseband signals with an ITX LO signal and a Q TX LO signal from a transmit (TX) local oscillator (LO) signal generator 1422 via mixers 1420(1), 1420(2) to provide an upconverted signal 1424. A filter 1426 filters the upconverted signal 1424 to remove undesired signals caused by frequency upconversion as well as noise in the receive frequency band. A power amplifier (PA) 1428 obtains a desired output power level and amplifies the upconverted signal 1424 from filter 1426 to provide a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1430 and transmitted via an antenna 1432.

[0050]

[0070] In the receive path, an antenna 1432 receives a signal transmitted by a base station and provides a received RF signal that is routed through a duplexer or switch 1430 and provided to a low noise amplifier (LNA) 1434. The duplexer or switch 1430 is designed to operate at a particular RX to TX duplexer frequency separation such that the receive (RX) signal is separated from the TX signal. The received RF signal is amplified by the LNA 1434 and filtered by a filter 1436 to obtain the desired RF input signal. Downconversion mixers 1438(1), 1438(2) mix the output of the filter 1436 with I and Q RX LO signals (i.e., LO_I and LO_Q) from a RX LO signal generator 1440 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1442(1), 1442(2) and further filtered by low pass filters 1444(1), 1444(2) to obtain I and Q analog input signals, which are provided to data processor 1406. In this example, data processor 1406 includes analog-to-digital converters (ADCs) 1446(1), 1446(2) to convert the analog input signals to digital signals for further processing by data processor 1406.

[0051]

[0071] In the wireless communication device 1400 of FIG. 14, a TX LO signal generator 1422 generates I and Q TX LO signals used for frequency up-conversion, and a RX LO signal generator 1440 generates I and Q RX LO signals used for frequency down-conversion. Each LO signal is a periodic signal having a particular fundamental frequency. A TX phase-locked loop (PLL) circuit 1448 receives timing information from the data processor 1406 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 1422. Similarly, a RX PLL circuit 1450 receives timing information from the data processor 1406 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 1440.

[0052]

[0072] As shown in FIGS. 2A-7 and 12E, wireless communication devices 1400 may each include ICs including trench power rails having increased cross-sections to reduce resistance and eliminate vias to the power rails according to any of the aspects disclosed herein, and may be provided or incorporated within any processor-based device. Examples include, but are not limited to, a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter.

[0053]

[0073] In this regard, FIG. 15 illustrates an example of a processor-based system 1500 including an IC including 3D power rails with increased cross-section to reduce resistance and eliminate vias to the power rails according to any aspect disclosed herein, as shown in FIGS. 2A-7 and 12E. In this example, the processor-based system 1500 includes one or more central processor units (CPUs) 1502, sometimes referred to as CPUs or processor cores, each including one or more processors 1504. The CPU(s) 1502 may have a cache memory 1506 coupled to the processor(s) 1504 for rapid access to temporarily stored data. The CPU(s) 1502 are coupled to a system bus 1508, which may interconnect master and slave devices included within the processor-based system 1500. As is well known, the CPU(s) 1502 communicate with these other devices by exchanging address, control, and data information via a system bus 1508. For example, the CPU(s) 1502 may communicate bus transaction requests to a memory controller 1510, as an example of a slave device. Although not shown in FIG. 15, multiple system buses 1508 may be provided, with each system bus 1508 constituting a different fabric.

[0054]

[0074] Other master and slave devices may be connected to the system bus 1508. As shown in FIG. 15, these devices may include, by way of example, a memory system 1512 including a memory controller 1510 and one or more memory arrays 1514, one or more input devices 1516, one or more output devices 1518, one or more network interface devices 1520, and one or more display controllers 1522. Any of the output devices 1518 and the network interface devices 1520 may include ICs including trench power rails with increased cross-sections to reduce resistance and eliminate vias to the power rails according to any of the aspects disclosed herein, as shown in FIGS. 2A-7 and 12E. The input device(s) 1516 may include any type of input device, including, but not limited to, input keys, switches, voice processors, and the like. The output device(s) 1518 may include any type of output device, including, but not limited to, audio, video, other visual indicators, and the like. The network interface device(s) 1520 may be any device configured to enable the exchange of data to and from the network 1524. The network 1524 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s) 1520 may be configured to support any type of communication protocol desired.

[0055]

[0075] The CPU(s) 1502 may also be configured to access display controller(s) 1522 via the system bus 1508 to control information sent to one or more displays 1526. The display controller(s) 1522 send information to be displayed to the display(s) 1526 via one or more video processors 1528, which process the information to be displayed into a format suitable for the display(s) 1526. The display(s) 1526 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light-emitting diode (LED) display, etc.

[0056]

[0076] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithms described with respect to the aspects disclosed herein may be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. The master and slave devices described herein may be employed in any circuit, hardware component, IC, or IC chip, as examples. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various exemplary components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may realize the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0057]

[0077] The various example logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed using a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but alternatively the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0058]

[0078] Aspects disclosed herein may be embodied in hardware and instructions stored in the hardware and may be present in, for example, a Random Access Memory (RAM), a flash memory, a Read-Only Memory (ROM), an Electrically Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0059]

[0079] It should also be noted that the operational steps described in any of the exemplary aspects disclosed herein are described to provide examples and discussion. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, an operation described in a single operational step may actually be performed in several different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that many different modifications may be made to the operational steps shown in the flow chart diagrams, as would be readily apparent to one of ordinary skill in the art. One of ordinary skill in the art would also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0060]

[0080] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other examples. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0061]

[0081] The following numbered clauses describe example implementations. 1. a first cell circuit comprising a first trench contact disposed in a first metal layer, the first trench contact extending in a first direction along a first longitudinal axis; a second cell circuit comprising a second trench contact disposed in the first metal layer, the second trench contact extending in the first direction along a second longitudinal axis; a cell isolation trench in the isolation region between the first end of the first trench contact and the second end of the second trench contact; a second metal layer adjacent to the first metal layer in a second direction, the first thickness of the second metal layer extending in the second direction; a via layer between the first metal layer and the second metal layer, the via layer having a second thickness extending in a second direction; a trench power rail in the cell isolation trench, the trench power rail extending in a third direction along a third longitudinal axis, the trench power rail having a thickness including a first thickness of the second metal layer, a second thickness of the via layer, and a third thickness of the first metal layer; An integrated circuit (IC). 2. the first longitudinal axis is collinear with the second longitudinal axis; a trench power rail disposed between the first end of the first trench contact and the second end of the second trench contact, the trench power rail having a first width in a first direction that is less than or equal to a tip-to-tip distance between the first end of the first trench contact and the second end of the second trench contact; IC as described in clause 1. 3. a first trench contact having a first surface adjacent to the via layer; a second trench contact having a second surface adjacent the via layer; a second width of the trench power rail in the first direction in the via layer is greater than the tip-to-tip distance; a trench power rail on the first surface and on the second surface; IC as described in clause 2. 4. The IC of clause 3, wherein the trench power rail has a second width in the first direction in the second metal layer. 5. The IC of clause 3 or clause 4, wherein the trench power rail is in direct contact with the first trench contact and separated from the second trench contact by a dielectric layer. 6. The IC of clause 3 or clause 4, wherein the trench power rail is in direct contact with the first trench contact and the second trench contact. 7. The IC of clause 3 or clause 4, wherein the trench power rail is separated from the first trench contact by a dielectric layer and separated from the second trench contact by a dielectric layer. 8. The IC of any one of clauses 1 to 7, wherein the trench power rail comprises a monolithic metal layer. 9. the first cell circuit further comprises a first diffusion region of the first transistor, the first diffusion region being directly coupled to the first trench contact; the second cell circuit further comprises a second diffusion region of a second transistor, the second diffusion region being directly coupled to the second trench contact; An IC as described in any one of clauses 1 to 8. 10. a first power rail and a second power rail each extending in a first direction within a first metal layer; A decoupling capacitor, a first trench capacitor rail extending in a first direction; a second trench capacitor rail extending in a first direction adjacent to the first trench capacitor rail; a first dielectric layer disposed between the first trench capacitor rail and the second trench capacitor rail; a first trench contact extending in the second direction within the first metal layer and coupling the first trench capacitor rail to the first power rail; a second trench contact extending in a second direction within the first metal layer and coupling the second trench capacitor rail to a second power rail; a decoupling capacitor comprising: An integrated circuit (IC). 11. Decoupling capacitors are a third trench capacitor rail extending in the first direction, the third trench capacitor rail being disposed between the first trench capacitor rail and the second trench capacitor rail and coupled to the second trench contact; a fourth trench capacitor rail extending in the first direction, the fourth trench capacitor rail being disposed between the third trench capacitor rail and the second trench capacitor rail and coupled to the first trench contact; a second dielectric layer disposed between the third trench capacitor rail and the fourth trench capacitor rail; a third dielectric layer disposed between the fourth trench capacitor rail and the second trench capacitor rail; Further comprising: a first dielectric layer disposed between the first trench capacitor rail and the third trench capacitor rail; IC as described in Article 10. 12. The IC of clause 10 or clause 11, wherein a decoupling capacitor is disposed between the first power rail and the second power rail. 13. A method of manufacturing an integrated circuit (IC), comprising: forming a first cell circuitry comprising a first trench contact disposed in a first metal layer, the first trench contact extending in a first direction along a first longitudinal axis; forming a second cell circuitry comprising a second trench contact disposed in the first metal layer, the second trench contact extending in the first direction along a second longitudinal axis; forming a cell isolation trench in the isolation region between the first end of the first trench contact and the second end of the second trench contact; forming a second metal layer adjacent to the first metal layer in a second direction, the second metal layer having a first thickness extending in the second direction; forming a via layer between the first metal layer and the second metal layer, the via layer having a second thickness extending in a second direction; forming a trench power rail in the cell isolation trench, the trench power rail extending in a third direction along a third longitudinal axis, the trench power rail having a thickness including a first thickness of the second metal layer, a second thickness of the via layer, and a third thickness of the first metal layer; A method comprising: 14. Forming a first cell circuit and a second cell circuit, forming a first diffusion region on a semiconductor substrate; forming a second diffusion region on the semiconductor substrate; forming a first trench contact on the first diffusion region; forming a second trench contact on the second diffusion region; forming an inter-layer dielectric (ILD) over the semiconductor substrate, over the first trench contact, and over the second trench contact; forming a trench pattern in the ILD corresponding to vias in the via layer and signal interconnects in the second metal layer; filling the trench pattern with a sacrificial material; Further comprising: The method described in clause 13. 15. Forming a trench power rail removing the ILD in the isolation regions in the second metal layer; removing the ILD in the via layer and the first metal layer in the isolation region to expose a first surface of the first trench contact and a second surface of the second trench contact; forming a dielectric layer for a trench power rail; Further comprising: The method described in clause 14. 16. removing sacrificial material from a trench pattern in the ILD; Selectively removing the dielectric layer from the exposed first surface of the first trench contact and the exposed second surface of the second trench contact; Further comprising: The method described in clause 15. 17. The method of claim 16, wherein selectively removing the dielectric layer from the exposed first surface of the first trench contact and the exposed second surface of the second trench contact further comprises removing the dielectric layer from the exposed first surface of the first trench contact but not removing the dielectric layer from the exposed second surface of the second trench contact. 18. The method of clause 16, wherein selectively removing the dielectric layer from the exposed first surface of the first trench contact and the exposed second surface of the second trench contact further comprises removing the dielectric layer from the exposed first surface of the first trench contact and removing the dielectric layer from the exposed second surface of the second trench contact. 19. The method of clause 16, wherein selectively removing the dielectric layer from the exposed first surface of the first trench contact and the exposed second surface of the second trench contact further comprises not removing the dielectric layer from the exposed first surface of the first trench contact and not removing the dielectric layer from the exposed second surface of the second trench contact.

Claims

1. a first cell circuit comprising a first trench contact disposed in a first metal layer, the first trench contact extending in a first direction along a first longitudinal axis; second cell circuitry including a second trench contact disposed in the first metal layer, the second trench contact extending in the first direction along a second longitudinal axis; a cell isolation trench in an isolation region between a first end of the first trench contact and a second end of the second trench contact; a second metal layer adjacent to the first metal layer in a second direction, the second metal layer having a first thickness extending in the second direction; a via layer between the first metal layer and the second metal layer, the via layer having a second thickness extending in the second direction; a trench power rail in the cell isolation trench, the trench power rail extending in a third direction along a third longitudinal axis, the trench power rail having a thickness including the first thickness of the second metal layer, the second thickness of the via layer, and a third thickness of the first metal layer; An integrated circuit (IC) comprising:

2. the first longitudinal axis is collinear with the second longitudinal axis; the trench power rail disposed between the first end of the first trench contact and the second end of the second trench contact has a first width in the first direction that is less than or equal to a tip-to-tip distance between the first end of the first trench contact and the second end of the second trench contact; the first trench contact having a first surface adjacent the via layer; the second trench contact has a second surface adjacent the via layer; a second width of the trench power rail in the first direction within the via layer that is greater than the tip-to-tip distance; the trench power rails are on the first surface and the second surface; 10. The IC of claim 1.

3. 3. The IC of claim 2, wherein the trench power rail has the second width in the first direction within the second metal layer.

4. the trench power rail is in direct contact with the first trench contact and is separated from the second trench contact by a dielectric layer; or the trench power rail is in direct contact with the first trench contact and the second trench contact; or 3. The IC of claim 2, wherein the trench power rail is separated from the first trench contact by a dielectric layer and separated from the second trench contact by the dielectric layer.

5. The IC of claim 1 , wherein the trench power rail comprises a monolithic metal layer.

6. the first cell circuit further comprises a first diffusion region of a first transistor, the first diffusion region being directly coupled to the first trench contact; the second cell circuit further comprises a second diffusion region of a second transistor, the second diffusion region being directly coupled to the second trench contact; 10. The IC of claim 1.

7. A first power rail and a second power rail, the first and second power rails comprising the trench power rail, each extending in the third direction (X) within a third metal layer to provide voltages to the first and second cell circuits; A decoupling capacitor, a first trench capacitor rail extending in the third direction; a second trench capacitor rail adjacent to the first trench capacitor rail and extending in the third direction; a first dielectric layer disposed between the first trench capacitor rail and the second trench capacitor rail; a first trench capacitor contact extending in the first direction (Y) within the third metal layer and coupling the first trench capacitor rail to the first power rail; a second trench capacitor contact extending in the first direction within the third metal layer and coupling the second trench capacitor rail to the second power rail; a decoupling capacitor comprising:

7. The integrated circuit (IC) of claim 1, further comprising:

8. The decoupling capacitor a third trench capacitor rail extending in the third direction, the third trench capacitor rail being disposed between the first trench capacitor rail and the second trench capacitor rail and coupled to the second trench capacitor contact; a fourth trench capacitor rail extending in the third direction, the fourth trench capacitor rail being disposed between the first trench capacitor rail and the second trench capacitor rail and coupled to the first trench capacitor contact; a second dielectric layer disposed between the third trench capacitor rail and the fourth trench capacitor rail; a third dielectric layer disposed between the fourth trench capacitor rail and the second trench capacitor rail; Further provided with the first dielectric layer is disposed between the first trench capacitor rail and the third trench capacitor rail.

8. The IC of claim 7.

9. 8. The IC of claim 7, wherein the decoupling capacitor is disposed between the first power rail and the second power rail.

10. 1. A method of manufacturing an integrated circuit (IC), comprising: forming a first cell circuit comprising a first trench contact disposed in a first metal layer, the first trench contact extending in a first direction along a first longitudinal axis; forming a second cell circuit comprising a second trench contact disposed in the first metal layer, the second trench contact extending in the first direction along a second longitudinal axis; forming a cell isolation trench in an isolation region between a first end of the first trench contact and a second end of the second trench contact; forming a second metal layer adjacent to the first metal layer in a second direction, the second metal layer having a first thickness extending in the second direction; forming a via layer between the first metal layer and the second metal layer, the via layer having a second thickness extending in the second direction; forming a trench power rail in the cell isolation trench, the trench power rail extending in a third direction along a third longitudinal axis, the trench power rail having a thickness including the first thickness of the second metal layer, the second thickness of the via layer, and a third thickness of the first metal layer; A method comprising:

11. forming the first cell circuit and the second cell circuit; forming a first diffusion region on a semiconductor substrate; forming a second diffusion region on the semiconductor substrate; forming the first trench contact on the first diffusion region; forming the second trench contact on the second diffusion region; forming an interlayer dielectric (ILD) over the semiconductor substrate, over the first trench contact, and over the second trench contact; forming a trench pattern in the ILD corresponding to vias in the via layer and signal interconnects in the second metal layer; filling the trench pattern with a sacrificial material; Further comprising: The method of claim 10.

12. forming the trench power rail; removing the ILD in the isolation region in the second metal layer; removing the ILD in the via layer and the first metal layer in the isolation region to expose a first surface of the first trench contact and a second surface of the second trench contact; forming a dielectric layer for the trench power rail; removing the sacrificial material from the trench pattern in the ILD; selectively removing the dielectric layer from the exposed first surface of the first trench contact and the exposed second surface of the second trench contact; Further comprising: The method of claim 11.

13. 13. The method of claim 12, wherein selectively removing the dielectric layer from the exposed first surface of the first trench contact and the exposed second surface of the second trench contact further comprises removing the dielectric layer from the exposed first surface of the first trench contact but not from the exposed second surface of the second trench contact.

14. 13. The method of claim 12, wherein selectively removing the dielectric layer from the exposed first surface of the first trench contact and the exposed second surface of the second trench contact further comprises removing the dielectric layer from the exposed first surface of the first trench contact and removing the dielectric layer from the exposed second surface of the second trench contact.

15. 13. The method of claim 12, wherein selectively removing the dielectric layer from the exposed first surface of the first trench contact and the exposed second surface of the second trench contact further comprises not removing the dielectric layer from the exposed first surface of the first trench contact and not removing the dielectric layer from the exposed second surface of the second trench contact.

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