Electronic device and method for sampling its input signal

Abstract

The present invention provides a device and method for monitoring high-speed signals using low-bandwidth probe signals. [Solution] The device includes a first clock signal generator, a second clock signal generator, an input signal generation circuit, and an input signal sampling circuit. The first clock signal generator generates a first clock signal. The second clock signal generator generates a second clock signal delayed relative to the first clock signal. The input signal generation circuit includes a voltage signal generator and a function circuit. The voltage signal generator generates a voltage signal. The function circuit receives the voltage signal and performs one or more circuit functions. The input signal sampling circuit samples the value of the voltage signal at the rising or falling edge of the second clock signal and provides the sampled value as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal.

Description

[Background technology]

[0001] A sampling circuit captures (or samples) the value of an input signal at a specific time point, stores (or holds) the sampled value, and provides them together as an output signal. The sampled values ​​correspond to the instantaneous level of the input signal at those time points. In one example, the sampling circuit receives an input signal and a clock signal. The input signal is in analog form and periodic. The clock signal, on the other hand, transitions between high and low states and has rising and falling edges. The sampling circuit samples the input signal at the rising (and / or falling) edge of the clock signal, holds these values, and generates an output signal containing the sampled values. The output signal can be used for further processing, analysis, or transmission. [Overview of the project] [Problems that the invention aims to solve]

[0002] This invention provides a device for monitoring high-speed signals using low-bandwidth probes and scopes. [Means for solving the problem]

[0003] The present invention provides a device comprising a first clock signal generator, a second clock signal generator, an input signal generation circuit, and an input signal sampling circuit. The first clock signal generator is configured to generate a first clock signal. The second clock signal generator is configured to generate a second clock signal delayed relative to the first clock signal, and each of the first and second clock signals transitions between high and low states and has rising and falling edges. The input signal generation circuit includes a voltage signal generator and a function circuit. The voltage signal generator is configured to generate a voltage signal having a period defined by the rising and falling edges of the first clock signal. The function circuit is configured to receive the voltage signal and perform one or more circuit functions. The input signal sampling circuit is configured to sample the value of the voltage signal at the rising or falling edge of the second clock signal and provide the sampled value as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal.

[0004] The present invention provides another device comprising a first clock signal generator, a second clock signal generator, and an input signal sampling circuit. The first clock signal generator comprises a first clock signal selector and a first frequency divider. The first clock signal selector receives a first clock signal and a delayed version of the first clock signal and is configured to select the first clock signal as the output, but never to select the first delayed version of the first clock signal. The first frequency divider is configured to reduce the frequency of the output to generate a second clock signal. The second clock signal generator is configured to generate a third clock signal. The input signal sampling circuit is configured to sample the value of a voltage signal using the second and third clock signals and provide the sampled value as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal.

[0005] The present invention provides a method for sampling an input signal. This method includes generating a first clock signal, dividing the frequency of the first clock signal to generate a second clock signal, generating a third clock signal, introducing a delay to the third clock signal, alternately selecting the third clock signal and the delayed version of the third clock signal to generate an output, lowering the frequency of the output to generate a fourth clock signal, receiving a voltage signal, using the second and fourth clock signals to obtain a value of the voltage signal, providing that value as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal. [Effects of the Invention]

[0006] The device and method of the present invention can sample high-frequency signals without reducing the signal frequency using a low-bandwidth strobe signal. Therefore, signals can be monitored with high accuracy, and power consumption caused by the low-bandwidth strobe signal can be saved. [Brief explanation of the drawing]

[0007] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings.

[0008] [Figure 1] This is a schematic block diagram illustrating exemplary devices according to various embodiments of the present invention. [Figure 2] This is a schematic timing diagram illustrating exemplary relationships between signals in devices according to various embodiments of the present invention. [Figure 3] This is a schematic block diagram showing another exemplary device according to various embodiments of the present invention. [Figure 4] This is a schematic block diagram showing another exemplary device according to various embodiments of the present invention. [Figure 5] This is a schematic circuit / block diagram showing an exemplary clock signal generator for a device according to various embodiments of the present invention. [Figure 6]This schematic circuit / block diagram shows another exemplary clock signal generator for a device according to various embodiments of the present invention. [Figure 7] This is a schematic circuit diagram showing another exemplary clock signal generator according to various embodiments of the present invention. [Figure 8] This flowchart shows an exemplary sampling method for an input signal according to an embodiment of the present invention. [Modes for carrying out the invention]

[0009] The following disclosure provides many different embodiments or examples for carrying out different features of the subject matter provided. For the sake of simplification of the invention, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to limit the invention. For example, forming the first feature above or on top of the second feature in the following description may include embodiments in which the first and second features are formed to be in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Also, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplification and clarification and does not in itself determine the relationships between the various embodiments and / or configurations discussed.

[0010] The discrete level of an input signal (e.g., a periodic analog signal) can be obtained by sampling the input signal at a specific time point and used, for example, to evaluate its quality. The sampled value of the input signal is then held and provided as a combined output signal. This output signal can then be fed to a signal analyzer, such as an oscilloscope, to identify one or more characteristics of the input signal, such as amplitude, frequency, and waveform shape. For example, a sampling circuit receives first and second clock signals, each transitioning between high and low states and having rising and falling edges. The rising (and / or falling) edge of the first clock signal triggers or initiates sampling of the input signal. The sampling circuit obtains the value of the input signal at the rising (and / or falling) edge of the second clock signal. The second clock signal is delayed by at least a predetermined delay (Δt) relative to the first clock signal. However, the clock signal generator may not be able to generate a sufficiently small delay (Δt). If the delay (Δt) is too large, the value obtained by the sampling circuit may not accurately represent the input signal.

[0011] In the specific example described herein, the system and method include a device with a clock signal generator that produces a second clock signal by alternately switching between the original clock signal and its delayed version. This approach can generate a delay (Δt) so small that the ratio of the period of the second clock signal (e.g., 2.13 ns) to the delay (Δt) (e.g., 23 ps) is greater than 50 (e.g., reaches 92.61). As a result, the frequency of the output signal is reduced to a relatively low value (e.g., 5.1 MHz) compared to the relatively high frequency of the input signal (e.g., 469 MHz). This reduction allows the output signal to accurately represent the input signal, thus facilitating a precise analysis of the input signal.

[0012] FIG. 1 is a block diagram showing an exemplary device 100 according to various embodiments of the present invention. The exemplary device 100 uses one or more of its own clock signals, e.g., clock signals (CLK TRIG , CLK SAMP ) to acquire the value of an input signal, e.g., a voltage signal (V SENSE ) at specific time points. As shown in FIG. 1, the device 100 includes a clock signal generation circuit 110 and an input signal sampler 120. The clock signal generation circuit 110 includes a first clock signal generator 130 that generates a first (or trigger) clock signal (CLK TRIG ), and a second clock signal generator 140 that generates a second (or sampling) clock signal (CLK TRIG ) having a period longer than that of the trigger clock signal (CLK SAMP ). Each clock signal (CLK TRIG , CLK SAMP ) transitions between a high state and a low state and has rising edges and falling edges.

[0013] The input signal sampler 120 acquires the value of the voltage signal (V TRIG , CLK SAMP ) determined by the clock signals (CLK SENSE ). For example, the input signal sampler 120 includes an input signal generation circuit 150 and an input signal sampling circuit 160. The input signal generation circuit 150 generates an input signal (V TRIG ) in analog form and having a period defined by the rising and falling edges of the trigger clock signal (CLK SENSE ). For example, the period of the input signal (V SENSE ) starts and ends at the rising (or falling) edge and the falling (or rising) edge of the trigger clock signal (CLK TRIG ), respectively. In this exemplary embodiment, the input signal generation circuit 160 performs one or more circuit functions.

[0014] The input signal sampling circuit 160 receives the sampling clock signal (CLK SAMP At the rising (and / or falling) edge of the input signal (V SENSE Capture (or sample) the value of ), store (or hold) the sampled value, and output it as an output signal (V SUB The sampled values ​​are provided together as the input signal (V) at these time points. SENSE Corresponds to the instantaneous level of the output signal (V). SUB By analyzing one or more characteristics of the input signal (V) using a signal analyzer, such as an oscilloscope, spectrum analyzer, voltmeter, any other device capable of measuring voltage signals, or a combination thereof, the input signal (V) can be analyzed. SENSE ) The quality can be evaluated.

[0015] In this exemplary embodiment, the sampling clock signal (CLK SAMP ) is the trigger clock signal (CLK TRIG The signal is delayed by at least (Δt) relative to the given value. For example, Figure 2 shows a device according to various embodiments of the present invention, for example, the clock signal (CLK) of device 100. TRIG CLK SAMP ) and input signal (V SENSE , V SUB This is a schematic timing diagram illustrating an exemplary relationship between ).

[0016] As shown in Figure 2, each clock signal (CLK TRIG CLK SAMP The signal transitions between a high state and a low state, and has rising and falling edges. Input signal (V SENSE ) is in analog format and is triggered by a clock signal (CLK TRIG It has a period defined by the rising and falling edges of the input signal (V). SENSE The period of each trigger clock signal (CLK) TRIGIt starts and ends on the rising (or falling) edge and falling (or rising) edge of the input signal (V). SENSE ) is the trigger clock signal (CLK TRIG The period is twice that of the trigger clock signal (CLK). In some embodiments, the trigger clock signal (CLK) has a period twice that of the trigger clock signal (CLK). TRIG The rising edge of the input signal (V SENSE ) triggers or initiates sampling of the input signal (V SENSE ) is the sampling clock signal (CLK SAMP The sample is taken at the rising edge of the ) signal. In other embodiments, the trigger clock signal (CLK TRIG The rising and / or falling edges of the input signal (V SENSE Trigger or initiate sampling of the input signal (V SENSE ) is the sampling clock signal (CLK SAMP It is sampled at the rising and / or falling edges of the signal.

[0017] In this exemplary embodiment, the sampling clock signal (CLK SAMP ) is the trigger clock signal (CLK TRIG ) is delayed by various delays, and the delay gradually increases over multiple periods. For example, the clock signal (CLK TRIG CLK SAMP The rising edge of the ) is separated by a multiple of the delay (Δt), for example, Δt, 2Δt, 3Δt, etc. Similarly, the sampling clock signal (CLK SAMP The falling edge of the ) is also triggered by the trigger clock signal (CLK TRIG The falling edge of the input signal (V) is delayed by various delays. Due to this stepwise delay, the sampling process is delayed by various delays. SENSE The value capture can be distributed along the ) and ensure that the two sampling points are not redundant or placed too close together. As a result, the voltage signal (V SENSE Compared to the relatively high frequency of the output signal (V SUB) is the input signal (V SENSE The frequency is reduced to relatively low levels without sacrificing the accuracy of the information captured from the source.

[0018] Figure 3 is a schematic block diagram showing other exemplary devices according to various embodiments of the present invention. As shown in Figure 3, the exemplary device 300, for example, device 100, includes a clock signal generation circuit 310 and an input signal sampler 320. The clock signal generation circuit 310 generates a trigger clock signal (CLK TRIG A first clock signal generator 330 generates a trigger clock signal (CLK), and a trigger clock signal (CLK TRIG ) A sampling clock signal (CLK) with a longer period than SAMP Includes a second clock signal generator 340 that generates each clock signal (CLK). TRIG CLK SAMP ) transitions between a high state and a low state and has rising and falling edges.

[0019] In this exemplary embodiment, the trigger clock signal generator 330 includes a first clock signal source 330a and a first frequency divider 330b. The clock signal source 330a receives an enable signal (START) at its first input terminal (RST) and a first control signal (SEL1) at its second input terminal. The enable signal (START) enables the generation of a first high-frequency clock signal (CLK1) at the output terminal of the clock signal source 330a (for example, when it is high) or disables it when it is low. The frequency divider 330b receives the high-frequency clock signal (CLK1) from the clock signal source 330a, divides this high-frequency clock signal (CLK1) by a divisor (N) received at its input terminal, and generates a trigger clock signal (CLK) at its output terminal. TRIG ) generates.

[0020] In certain embodiments, the control signal (SEL1) is set to a first logic state (e.g., low) but is never set to a second logic state (e.g., high), which is an inverted version of the first logic state. In such certain embodiments, the trigger clock signal (CLK) is also set. TRIG ) has a period that remains substantially constant for a long period of time, in the manner detailed below.

[0021] The sampling clock signal generator 340 has a structure similar to that of the trigger clock signal generator 330. For example, the sampling clock signal generator 340 includes a second clock signal source 340a and a second frequency divider 340b. The clock signal source 340a receives an enable signal (START) at its first input terminal (RST) and a second control signal (SEL2) at its second input terminal. The enable signal (START) enables the generation of a second high-frequency clock signal (CLK2) at the output terminal of the clock signal source 340a (for example, when it is high) or disables it when it is low. The frequency divider 340b receives the high-frequency clock signal (CLK2) from the clock signal source 340a, divides this high-frequency clock signal (CLK2) by a divisor (N) received at its input terminal, and generates a sampling clock signal (CLK) at its output terminal. SAMP ) generates.

[0022] In a particular embodiment, the sampling clock signal (CLK SAMP ) functions as a control signal (SEL2). In such a particular embodiment, the sampling clock signal (CLK SAMP The trigger clock signal (CLK) is obtained in the manner detailed below. TRIG The delay is applied by a multiple of the delay (Δt) relative to the given time.

[0023] The input signal sampler 320 receives a clock signal (CLK TRIG CLK SAMP The voltage signal (V) determined by ) SENSE) is sampled. For example, the input signal sampler 320 includes an input signal generation circuit 350 and an input signal sampling circuit 360. The input signal generation circuit 350 includes a voltage signal generator 350a and a function circuit 350b. The voltage signal generator 350a is in analog form and also receives a trigger clock signal (CLK TRIG The input signal (V) applied to the functional circuit 350b has a period defined by the rising and falling edges of the ) SENSE ), for example, to generate a voltage signal. In a particular embodiment, the voltage signal generator 350a includes a bandgap reference voltage generator, a voltage regulator, a power supply, a digital-to-analog converter (DAC), a voltage-controlled oscillator (VCO), a charge pump, any other circuitry that generates a voltage signal, or a combination thereof. In an alternative embodiment, the voltage signal generator 350a is located outside of device 300.

[0024] Functional circuit 350b receives a voltage signal (V SENSE ) receives and performs one or more circuit functions. In a particular embodiment, the functional circuit 350b is a central processing unit (CPU), a memory device, a signal amplifier, an analog-to-digital (ADC) circuit, a logic circuit, another circuit that performs a predetermined circuit function, or a combination thereof. In an alternative embodiment, the functional circuit 350b is located outside of device 300.

[0025] The input signal sampling circuit 360 uses a sampling clock signal (CLK SAMP At the rising (and / or falling) edge of the voltage signal (V SENSE Capture (or sample) the value of ), store (or hold) the sampled value, and output it as an output signal (V SUB The sampled values ​​are provided together as voltage signals (V) at those time points. SENSECorresponds to the instantaneous voltage level of the output signal (V). SUB By analyzing one or more characteristics of the voltage signal (V) using a signal analyzer, such as an oscilloscope, spectrum analyzer, voltmeter, any other device capable of measuring a voltage signal, or a combination thereof, the voltage signal (V) can be analyzed. SENSE ) The quality can be evaluated.

[0026] From the above description, the sampling clock signal generator 340 has substantially the same structure as the trigger clock signal generator 330. This similarity simplifies the design and manufacture of device 300.

[0027] Figure 4 is a schematic block diagram showing another exemplary device according to various embodiments of the present invention. As shown in Figure 4, the exemplary device 400, for example, device 300, includes a clock signal generation circuit 410 and an input signal sampler 420. The clock signal generation circuit 410 generates a trigger clock signal (CLK TRIG A first clock signal generator 430 generates a trigger clock signal (CLK), and a trigger clock signal (CLK TRIG ) A sampling clock signal (CLK) with a longer period than SAMP Includes a second clock signal generator 440 that generates each clock signal (CLK). TRIG CLK SAMP ) transitions between a high state and a low state and has rising and falling edges.

[0028] In this exemplary embodiment, the trigger clock signal generator 430 includes an oscillator 430a, a first delay circuit 430b, a clock signal selector 430c, a frequency divider 430d, a second delay circuit 430e, and a selection signal generator 430f. The oscillator 430a outputs an oscillator signal (CLK) at its output terminal (OUT) (for example, when it is in a high state). TRIG The delay circuit 430b receives an enable signal (START) at its input terminal (RST) to enable the generation of ') or to disable it when it is in a low state. The delay circuit 430b receives the oscillator signal (CLK) from the oscillator 430a. TRIG’) receives the received oscillator signal (CLK TRIG ’) introduces a first delay to the received oscillator signal (CLK TRIG ’) to generate a first delayed version of the oscillator signal (CLK

[0029] The clock signal selector 430c receives the oscillator signal (CLK TRIG ’) from the oscillator 430a and receives a first delayed version of the oscillator signal (CLK TRIG ’) from the delay circuit 430b, and in response to the first selection signal (S1) received at its input terminal, selects one of the oscillator signal (CLK TRIG ’) and the first delayed version of the oscillator signal (CLK TRIG ’), and provides a high-frequency clock signal (CLK1) corresponding to the selected one of the oscillator signal (CLK TRIG ’) and the first delayed version of the oscillator signal (CLK TRIG ’) at its output terminal.

[0030] The frequency divider 430d receives the high-frequency clock signal (CLK1) from the clock signal selector 430c, divides it by the divisor (N) received at its input terminal, whereby the trigger clock signal generator 430 generates a trigger clock signal (CLK TRIG ). The frequency divider 430d provides a trigger clock signal (CLK TRIG ) at its output terminal.

[0031] The delay circuit 430e receives the oscillator signal (CLK TRIG ’) from the oscillator 430a, introduces a second delay to the received oscillator signal (CLK TRIG ’) to generate a second delayed version of the oscillator signal (CLK TRIG ’). The selection signal generator 430f receives the second delayed version of the oscillator signal (CLK TRIG ’) from the delay circuit 430e and receives the received oscillator signal (CLK TRIGRegardless of the second delayed version of '), it generates a selection signal (S1) in response to a control signal (SEL1) at its input terminal. In certain embodiments, the control signal (SEL1) is set to a first logic (e.g., low) state but is never set to a second logic (e.g., high) state, which is the inverted version of the first logic state. In such certain embodiments, the control signal (SEL1) controls the clock signal selector 430c to always control the oscillator signal (CLK TRIG ') is selected, but its delayed version is never selected. As a result, the trigger clock signal (CLK TRIG ) has a period that remains substantially constant for a long period of time.

[0032] The sampling clock signal generator 440 has a structure similar to that of the trigger clock signal generator 430. For example, the sampling clock signal generator 440 includes an oscillator 440a, a first delay circuit 440b, a clock signal selector 440c, a frequency divider 440d, a second delay circuit 440e, and a selection signal generator 440f. The oscillator 440a outputs an oscillator signal (CLK) at its output terminal (OUT) (for example, when it is in a high state). SAMP The input terminal (RST) receives an enable signal (START) to either enable the generation of ') or disable it when it is in a low state. The delay circuit 430b receives the oscillator signal (CLK) from the oscillator 440a. SAMP ') is received, and the received oscillator signal (CLK SAMP A first delay is introduced to '), and the oscillator signal (CLK) is output at its output terminal. SAMP Generates the first delayed version of ').

[0033] The clock signal selector 440d receives the oscillator signal (CLK) from the oscillator 440a. SAMP The oscillator signal (CLK) is received from the delay circuit 440b. SAMP The first delayed version of ') is received, and in response to the second selection signal (S2) received at its input terminal, the oscillator signal (CLK SAMP ') and oscillator signal (CLK SAMPSelect one of the first delayed versions of ') and use the oscillator signal (CLK) at its output terminal. SAMP ') and oscillator signal (CLK SAMP Provides a high-frequency clock signal (CLK2) corresponding to one of the selected first delayed versions of ').

[0034] The frequency divider 440d receives a high-frequency clock signal (CLK2) from the clock signal selector 440c, divides it by the divisor (N) received at its input terminal, and thereby the sampling clock signal generator 440 generates a sampling clock signal (CLK2). SAMP The frequency divider 440d generates a sampling clock signal (CLK) at its output terminal. SAMP ) provides.

[0035] The delay circuit 440e receives the oscillator signal (CLK) from the oscillator 440a. SAMP ') is received, and the received oscillator signal (CLK SAMP A second time delay is introduced to the oscillator signal (CLK SAMP The selection signal (S2) generator 440f generates a second delayed version of the oscillator signal (CLK) from the delay circuit 440e. SAMP The second delayed version of ') is received, and the received oscillator signal (CLK SAMP It relies on a second delayed version of ') to generate a selection signal (S2) in response to a control signal (SEL2) at its input terminal. For example, the sampling clock signal (CLK SAMP ') functions as a control signal (SEL2). Oscillator signal (CLK SAMP When the second delayed version of ') is in the high state, and the control signal (SEL2) transitions from the low state to the high state and then back to the low state, the clock signal selector 440d controls the oscillator signal (CLK SAMP Select the first delayed version of ') as the high-frequency clock signal (CLK2). Otherwise, for example, the oscillator signal (CLK SAMP When both the second delayed version of ') and the control signal (SEL2) are in the low state, the clock signal selector 440d is set to the oscillator signal (CLK SAMPSelect ') as the high-frequency clock signal (CLK2).

[0036] The clock signal selector 440c controls the oscillator signal (CLK SAMP ') and its delayed version are alternately selected as the sampling clock signal (CLK2), SAMP As mentioned above, the trigger clock signal (CLK) TRIG The delay is applied by a multiple of the delay (Δt) relative to the given time.

[0037] The input signal sampler 420 receives a clock signal (CLK TRIG CLK SAMP The voltage signal (V) determined by ) SENSE ) is sampled. For example, the input signal sampler 420 includes an input signal generation circuit 450 and an input signal sampling circuit 460. The input signal generation circuit 420a includes an input signal generator 450a and a function signal 450b. The input signal generator is in analog form and also includes a trigger clock signal (CLK TRIG An input signal (V) has a period defined by the rising and falling edges of the ) SENSE ), for example, it generates a voltage signal. Functional circuit 450b generates a voltage signal (V SENSE When a voltage is applied, it performs one or more circuit functions. In an alternative embodiment, at least one of the voltage signal generator 450a and the functional circuit 450b is located outside the device 400.

[0038] The input signal sampling circuit 420b uses a sampling clock signal (CLK SAMP At the rising (and / or falling) edge of the voltage signal (V SENSE Capture (or sample) the value of ), store (or hold) the sampled value, and output it as an output signal (V SUB The sampled values ​​are provided together as voltage signals (V) at those time points. SENSE Corresponds to the instantaneous voltage level of the output signal (V). SUB) analyzes the voltage signal (V SENSE ) The quality can be evaluated.

[0039] From the above description, the sampling clock signal generator 440 has substantially the same structure as the trigger clock signal generator 430. This similarity simplifies the design and manufacture of device 400.

[0040] Figure 5 is a schematic block / circuit diagram showing another exemplary clock signal generator according to various embodiments of the present invention. As shown in Figure 5, the exemplary clock signal generator 500, for example, trigger clock signal generators 130, 330, 430, includes an oscillator 510, a first delay circuit 520, a clock signal selector 530, a frequency divider 540, a second delay circuit 550, and a selection signal generator 560. The oscillator 510 generates an oscillator signal (CLK) at its output terminal (OUT) (for example, when it is in a high state). TRIG An enable signal (START) is received at its input terminal (RST) to enable the generation of ') or to disable it when it is low. In this exemplary embodiment, oscillator 510 includes a ring oscillator with an odd number of inverting stages connected in a feedback loop. In alternative embodiments, oscillator 510 includes a crystal oscillator, a voltage-controlled oscillator (VCO), a phase-locked loop (PLL), an LC oscillator, any other suitable oscillator, or a combination thereof.

[0041] The delay circuit 520 receives the oscillator signal (CLK) from the oscillator 510. TRIG ') is received, and the received oscillator signal (CLK TRIG A first delay is introduced to '), and the oscillator signal (CLK) is output at its output terminal. TRIG This generates a first delayed version of '). In certain embodiments, the delay circuit 520 includes one or more buffer circuits.

[0042] The clock signal selector 530 receives the oscillator signal (CLK) from the oscillator 510. TRIGThe delay circuit 520 receives the oscillator signal (CLK) after receiving the ') signal. TRIG The first delayed version of ') is received, and the oscillator signal (CLK) is always received. TRIG ') is selected, that is, never the delayed version is selected, and the oscillator signal (CLK) is output at its output terminal. TRIG ') provides the trigger clock signal (CLK). TRIG ) has a period that remains substantially constant for a long period of time. In this exemplary embodiment, the clock signal selector 530 includes a multiplexer having a first input terminal connected to the output terminal of the oscillator 510 and a second input terminal connected to the output terminal of the delay circuit 520. The multiplexer connects its first input terminal to its output terminal in response to a selection signal (S1).

[0043] The frequency divider 540 receives the oscillator signal (CLK) from the clock signal selector 530. TRIG ') receives the oscillator signal (CLK TRIG The frequency of ') is divided by the divisor (N) received at its input terminal, thereby the trigger clock signal generator 500 generates the trigger clock signal (CLK TRIG The frequency divider 540 generates a trigger clock signal (CLK) at its output terminal. TRIG ) provides.

[0044] The delay circuit 550 receives the oscillator signal (CLK) from the oscillator 510. TRIG ') is received, and the received oscillator signal (CLK TRIG A second time delay is introduced to the oscillator signal (CLK TRIG This generates a second delayed version of '). In certain embodiments, the delay circuit 550 includes one or more buffer circuits.

[0045] The selection signal generator 560 receives the oscillator signal (CLK) from the delay circuit 550. TRIG The second delayed version of ') is received, and the received oscillator signal (CLK TRIG Regardless of the second delayed version of '), it generates a selection signal (S1) in response to the control signal (SEL) at its input terminal. As a result, the trigger clock signal (CLKTRIG ) has a period that remains substantially constant for a long period of time.

[0046] Figure 6 is a schematic block / circuit diagram showing another exemplary clock signal generator according to various embodiments of the present invention. As shown in Figure 6, the exemplary clock signal generator 600, for example, the sampling clock signal generators 140, 340, 440, includes an oscillator 610, a first delay circuit 620, a clock signal selector 630, a frequency divider 640, a second delay circuit 650, and a selection signal generator 660. The oscillator 610 outputs an oscillator signal (CLK) at its output terminal (OUT) (for example, when it is in a high state). SAMP An enable signal (START) is received at its input terminal (RST) to enable the generation of ') or to disable it when it is low. In this exemplary embodiment, oscillator 610 includes a ring oscillator with an odd number of inverting stages connected in a feedback loop. In an alternative embodiment, oscillator 610 includes a crystal oscillator, VCO, PLL, LC oscillator, any other suitable oscillator, or a combination thereof.

[0047] The delay circuit 620 receives the oscillator signal (CLK) from the oscillator 610. SAMP ') is received, and the received oscillator signal (CLK SAMP A first delay is introduced to '), and the oscillator signal (CLK) is output at its output terminal. SAMP This generates a first delayed version of '). In certain embodiments, the delay circuit 520 includes one or more buffer circuits.

[0048] The clock signal selector 630 receives the oscillator signal (CLK) from the oscillator 610. SAMP The delay circuit 620 receives the oscillator signal (CLK) after receiving the ') signal. SAMP The first delayed version of ') is received, and the oscillator signal (CLK SAMP ') and oscillator signal (CLK SAMPThe first delayed version of ') is alternately selected and provided as an output at its output terminal. In this exemplary embodiment, the clock signal selector 630 includes a multiplexer having a first input terminal connected to the output terminal of the oscillator 610 and a second input terminal connected to the output terminal of the delay circuit 620. The multiplexer connects its first input terminal or its second input terminal to its output terminal in response to the selection signal (S2).

[0049] The frequency divider 640 receives the output of the clock signal selector 630 and divides (or subtracts) its frequency by the divisor (N) received at its input terminal, thereby generating the sampling clock signal (CLK) for the sampling clock signal generator 600. SAMP The frequency divider 640 generates a sampling clock signal (CLK) at its output terminal. SAMP ) provides.

[0050] The delay circuit 650 receives the oscillator signal (CLK) from the oscillator 610. SAMP ') is received, and the received oscillator signal (CLK SAMP A second time delay is introduced to the oscillator signal (CLK SAMP This generates a second delayed version of '). In this exemplary embodiment, the delay circuit 650 includes one or more buffer circuits.

[0051] The selection signal generator 660 receives the oscillator signal (CLK) from the delay circuit 650. SAMP The second time delay is received to the input terminal, and the sampling clock signal (CLK) is received. SAMP A selection signal (S2) is generated in response to the sampling clock signal (CLK). SAMP ) is the trigger clock signal (CLK TRIG The delay is applied by a multiple of the delay (Δt) relative to the given time.

[0052] Figure 7 is a schematic diagram showing another exemplary clock signal generator according to various embodiments of the present invention. As shown in Figure 7, the exemplary clock signal generator 700, for example, clock signal generators 130, 140, 330, 340, 430, and 440 include an oscillator 710, a first delay circuit 720, a clock signal selector 730, a second delay circuit 750, and a selection signal generator 760. The oscillator 710, for example, oscillators 510 and 610, includes a ring oscillator with an odd number of inverting stages connected by a feedback loop. In alternative embodiments, the oscillator 710 includes a crystal oscillator, a VCO, a PLL, an LC oscillator, any other suitable oscillator, or a combination thereof.

[0053] A delay circuit 720, for example, delay circuits 520, 620, is connected between the oscillator 710 and the first input terminal of a clock signal selector 730, for example, clock signal selector 530, 630. In this exemplary embodiment, the delay circuit 720 includes one or more buffer circuits. The clock signal selector 730 further has a second input terminal connected to the output terminal of the oscillator 710. In this exemplary embodiment, the clock signal selector 730 includes a multiplexer.

[0054] Delay circuits 750, for example, delay circuits 550, 650, are connected between the output terminal of the oscillator 710 and the selection signal generators 760, for example, selection signal generators 560, 660. In this exemplary embodiment, the delay circuit 720 includes one or more buffer circuits. The selection signal generators 760 control the operation of the clock signal generator 730. In some embodiments, the selection signal generators 760 include one or more flip-flops and one or more logic gates. In other embodiments, various structures for the selection signal generators 760 are considered.

[0055] Figure 8 is a flowchart of an exemplary method 800 for sampling an input signal according to an embodiment of the present invention. For ease of understanding, the exemplary method 800 will be described further with reference to Figures 1 to 7. It should be understood that method 800 is applicable to structures other than those shown in Figures 1 to 7. Furthermore, it should be understood that alternative embodiments of method 800 may provide additional operations before, during, and after method 800, and some of the operations described later may be replaced or omitted.

[0056] In operation 810, devices, for example, devices 100, 300-700, receive a first clock signal having a period that remains substantially constant for a long period of time, for example, a trigger clock signal (CLK). TRIG ) generates.

[0057] In operation 820, the device receives the trigger clock signal (CLK). TRIG A second clock signal delayed by a multiple of the delay (Δt) relative to the first clock signal, for example, the sampling clock signal (CLK SAMP ) generates each clock signal (CLK). TRIG CLK SAMP ) transitions between a high state and a low state and has rising and falling edges.

[0058] In operation 830, the device receives the trigger clock signal (CLK). TRIG An input signal having a period defined by the rising and falling edges of the ) voltage signal (V SENSE ) generates. In operation 840, the device generates a sampling clock signal (CLK). SAMP At the rising (and / or falling) edge of the voltage signal (V SENSE Capture (or sample) the voltage value of ), store (or hold) the sampled value, and output it as an output signal (V SUB ) will be provided as a package.

[0059] In one embodiment, the device includes a first clock signal generator, a second clock signal generator, an input signal generation circuit, and an input signal sampling circuit. The first clock signal generator generates a first clock signal. The second clock signal generator generates a second clock signal delayed relative to the first clock signal. Each clock signal transitions between high and low states and has rising and falling edges. The input signal generation circuit includes a voltage signal generator and a function circuit. The voltage signal generator generates a voltage signal having a period defined by the rising and falling edges of the first clock signal. The function circuit receives the voltage signal and performs one or more circuit functions. The input signal sampling circuit samples the value of the voltage signal at the rising or falling edge of the second clock signal and provides the sampled value as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal.

[0060] In another embodiment, the device includes a first clock signal generator, a second clock signal generator, and an input signal sampling circuit. The first clock signal generator includes a first clock signal selector and a frequency divider. The first clock signal selector receives a first clock signal and a delayed version of the first clock signal and selects the first clock signal as the output, but never selects the first delayed version of the first clock signal. The first frequency divider reduces the frequency of the output to generate a second clock signal. The second clock signal generator is configured to generate a third clock signal. The input signal sampling circuit samples the values ​​of the voltage signal using the second and third clock signals and provides the sampled values ​​as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal.

[0061] In another embodiment, the input signal sampling method includes generating a first clock signal, dividing the frequency of the first clock signal to generate a second clock signal, generating a third clock signal, introducing a delay to the third clock signal, alternately selecting the third clock signal and the delayed version of the third clock signal to generate an output, lowering the frequency of the output to generate a fourth clock signal, receiving a voltage signal, using the second and fourth clock signals to obtain a value of the voltage signal, providing that value as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal.

[0062] The above outlines some features of embodiments so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should understand that the present invention can be readily used as a basis for designing or modifying other processes and structures to perform the same objectives and / or achieve the same advantages of the embodiments presented herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention. [Industrial applicability]

[0063] The devices and methods of the present invention can be applied to semiconductor chips for performing subsampling operations to monitor high-bandwidth signals with low-bandwidth probe signals during on-wafer testing. The present invention provides a simple and cost-effective on-chip timing scheme for generating the corresponding probe signals. [Explanation of Symbols]

[0064] 100, 300, 400 devices 110, 310, 410 Clock signal generation circuit 120, 320, 420 Input Signal Sampler 130, 330, 430, 500, 600 Clock Signal Generator 140, 340, 440 Clock Signal Generator 150, 350, 450 Input Signal Generation Circuits 160, 360, 460 input signal sampling circuits 330a, 340a Clock signal source 330b, 340b frequency divider 350A voltage signal generator 350b Functional Circuit 430a, 440a, 510, 610, 710 oscillators 430b, 440b, 520, 620, 720 delay circuits 430c, 440c, 530, 630, 730 Clock Signal Selector 430d, 440d, 540, 640, 740 frequency dividers 430e, 440e, 550, 650, 750 delay circuits 430f, 440f, 560, 660, 760 Selectable Signal Generator 800 ways 810~840 operation CLK1, CLK2 High-frequency clock signals CLK TRIG CLK SAMP clock signal CLK TRIG ', CLK SAMP Oscillator signal N divisor OUT output terminal RST input terminal S1, S2 selection signals SEL1, SEL2 control signals START enable signal V SENSE Voltage signal V SUB Output signal Δt delay

Claims

1. A first clock signal generator configured to generate a first clock signal, A second clock signal generator is configured to generate a second clock signal that is delayed relative to the first clock signal, and each of the first and second clock signals transitions between a high state and a low state, and has rising and falling edges. A voltage signal generator configured to generate a voltage signal having a period defined by the rising edge and falling edge of the first clock signal, A functional circuit configured to receive the aforementioned voltage signal and perform one or more circuit functions, An input signal generation circuit including, An input signal sampling circuit is configured to sample the value of the voltage signal at the rising edge or falling edge of the second clock signal, provide the sampled value as an output signal, and thereby analyze one or more characteristics of the voltage signal based on the output signal. A device that includes this.

2. The device according to claim 1, wherein the second clock signal is delayed by a multiple of the delay relative to the first clock signal.

3. The first rising edge of the first clock signal and the first rising edge of the second clock signal are separated by a first delay. The device according to claim 2, wherein the second rising edge of the first clock signal and the second rising edge of the second clock signal are separated by a second delay that is longer than the first delay.

4. The device according to claim 2, wherein the duration of the delay gradually increases over time.

5. The device according to claim 1, wherein the voltage signal has a period twice that of the period of the first clock signal.

6. The first clock signal generator, A clock signal selector configured to receive a third clock signal and a delayed version of the third clock signal, and to select the third clock signal as an output, but never to select the delayed version of the third clock signal, A frequency divider configured to reduce the frequency of the output and generate the first clock signal, The device according to claim 1, including the following:

7. The device according to claim 6, wherein the clock signal selector is configured to select the third clock signal in response to a selection signal (S1), and the selection signal is set to a first logical state but never to a second logical state which is an inverted version of the first logical state.

8. The second clock signal generator, A clock signal selector configured to receive a fourth signal and a delayed version of the fourth clock signal, and to alternately select between the fourth signal and the delayed version of the fourth clock signal to generate an output, A frequency divider configured to reduce the frequency of the output and generate the second clock signal, The device according to claim 1, including the following:

9. The device according to claim 8, wherein the clock signal selector is configured to alternately select between the fourth signal and the delayed version of the fourth clock signal in response to the second clock signal.

10. Receiving a first clock signal and a delayed version of the first clock signal, The first clock signal is selected as the output, but the delayed version of the first clock signal is never selected. A first clock signal selector configured to perform the following: A first frequency divider configured to reduce the frequency of the output and generate a second clock signal, A first clock signal generator including, A second clock signal generator configured to generate a third clock signal, An input signal sampling circuit is configured to sample the value of a voltage signal using the second clock signal and the third clock signal, provide the sampled value as an output signal, and thereby analyze one or more characteristics of the voltage signal based on the output signal. A device that includes this.

11. The first clock signal selector is further configured to select the first clock signal in response to a selection signal. The device according to claim 10, wherein the selection signal is set to a first logic state, but is never set to a second logic state which is an inverted version of the first logic state.

12. The first clock signal generator further, An oscillator configured to generate the first clock signal, A first delay circuit is connected between the oscillator and the first clock signal selector and configured to generate the delayed version of the first clock signal, A second delay circuit configured to generate a second delayed version of the first clock signal, A selection signal generator connected between the second delay circuit and the first clock signal selector, configured to generate the selection signal independently of the second delayed version of the first clock signal, The device according to claim 11, including the following:

13. The device according to claim 10, wherein the second clock signal selector is further configured to alternately select a fourth clock signal and a delayed version of the fourth clock signal in response to the third clock signal.

14. The second clock signal generator further, An oscillator configured to generate the fourth clock signal, A first delay circuit is connected between the oscillator and the second clock signal selector and configured to generate the delayed version of the fourth clock signal, A second delay circuit configured to generate a second delayed version of the fourth clock signal, A selection signal generator connected between the second delay circuit and the second clock signal selector, configured to generate a selection signal based on the second delayed version of the fourth clock signal, The device according to claim 13, including the following:

15. A sampling method for an input signal, To generate the first clock signal, The frequency of the first clock signal is divided to generate a second clock signal, To generate a third clock signal, Introducing a delay to the third clock signal, The output is generated by alternately selecting the third clock signal and a delayed version of the third clock signal, The frequency of the aforementioned output is reduced to generate a fourth clock signal, Receiving voltage signals and The second clock signal and the fourth clock signal are used to obtain the value of the voltage signal, The aforementioned value is provided as an output signal, and therefore, one or more characteristics of the voltage signal are analyzed based on the output signal. A method that includes this.

16. The method of claim 15, further comprising: introducing a delay to the first clock signal before dividing the frequency of the first clock signal; and selecting the first clock signal as an output, but never selecting the delayed version of the first clock signal.

17. The method according to claim 15, further comprising alternately selecting the third clock signal and the delayed version of the third clock signal in response to the fourth clock signal.

18. Before dividing the frequency of the first clock signal, a delay is introduced to the first clock signal, When the selection signal is in the first logic state, the first clock signal is selected as the output in response to the selection signal, The selection signal is set to the first logical state, but never to the second logical state, which is the inverted version of the first logical state. The method according to claim 15, further comprising:

19. To generate the aforementioned voltage signal, Applying the aforementioned voltage signal to the functional circuit, The aforementioned functional circuit performs one or more circuit functions, The method according to claim 15, further comprising:

20. The method according to claim 15, further comprising introducing a delay to the third clock signal, wherein the ratio of the period of the third clock signal to the delay is 50 or more.

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