AMPLIFIER ARCHITECTURE, FRONT END MODULE AND WIRELESS DEVICE - Patent application

Abstract

To provide an amplifier for wireless communication application reducing leakage.SOLUTION: In a wireless device, a variable gain amplifier 310a including a multi-input gain stage selectively provides variable or tailored impedances at a degeneration block and / or feedback block, depending at least in part on a gain mode of the variable gain amplifier. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of an amplification process in targeted gain modes. The variable gain amplifier provides a low-loss bypass mode in a low gain mode to improve signal quality.SELECTED DRAWING: Figure 3A

Description

[Technical field]

[0001] The present disclosure relates to amplifiers for wireless communication applications.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS This application is a joint venture between the US Provisional Patent Application No. 2016-0102114 filed on August 31, 2016 and the US Provisional Patent Application No. 2016-0102114. U.S. Provisional Application No. 62 / 3 entitled "Multiple Input Amplifier with Low-Loss Bypass Capability and Circuit-Based ... No. 81,851, filed on Oct. 13, 2003, the entirety of which is hereby expressly incorporated by reference for all purposes. can be incorporated into the [Background technology]

[0003] Wireless communication devices are typically configured to amplify received radio frequency (RF) signals. The components are contained in a front-end module that is It may include multiple gain modes that provide different levels of amplification. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2010 / 0321113(A1) [Patent Document 2] US Patent Application Publication No. 2014 / 0203872(A1) Summary of the Invention

[0005] According to a number of implementations, the present disclosure provides a method for receiving an input signal and generating an amplified output signal. a variable gain stage configured to adjust a gain of the variable gain stage; and a degeneration switching block configured to provide a variable gain level. This relates to a gain signal amplifier.

[0006] In some embodiments, the signal comprises a radio frequency signal. In this case, the amplifier has a bypass path that bypasses the variable gain stage and an amplification path that passes through the variable gain stage. The optical fiber is configured to selectively provide a path.

[0007] In some embodiments, the degeneration switching block further comprises: The amplifier is configured to provide a variable gain stage with a set impedance. In the above, the customized impedance is Compared to a variable gain stage that is not coupled to a degeneration switching block, In a further embodiment, the filter is configured to provide improved linearity in the output signal. The degeneration switching block is configured to select a first gain level of a plurality of gain levels. providing a first tailored impedance to the filter and a second gain of a plurality of gain levels; The second impedance is configured to provide a second tailored impedance to the level. In a further embodiment, the first tailored impedance is the impedance is greater than the impedance obtained and the first gain level is less than the second gain level.

[0008] In some embodiments, the amplifier also includes a variable gain stage and a degeneration switch. Also included is a control circuit configured to generate an amplified control signal that controls the switching circuit. In one embodiment, the control circuit generates a plurality of amplification control signals corresponding to a plurality of gain levels. It is configured to give.

[0009] In some embodiments, the amplifier further comprises an intermediate gain stage coupled to the input of the variable gain stage. A gain mode feedback block is included. The intermediate gain mode is a part of multiple gain levels. The variable gain stage is configured to provide feedback for aggregation. In the intermediate gain mode feedback block and degeneration switching The blocks are an intermediate gain feedback block and a degeneration switching block. This provides improved linearity in the amplified output signal compared to an amplifier without a clock.

[0010] In some embodiments, the amplifier further comprises a bipolar transistor coupled to the input of the variable gain stage. A pass block is included. The bypass block provides a bypass path that does not include a variable gain stage. The gain level is configured to be activated at a low gain level of the plurality of gain levels. In a further embodiment, the bypass path includes a degeneration switching block Does not include.

[0011] In some embodiments, the amplifier further comprises a cascade coupled to the output of the variable gain stage. In some embodiments, the amplifier further comprises a variable gain stage. In a further embodiment, the amplifier includes a plurality of input nodes. The input signal is configured to receive a plurality of input signals at a plurality of input terminals, each of the received signals being a different In yet a further embodiment, the amplifiers each have a frequency within the signal frequency band. amplified at the input port of the amplifier independently of the amplification of other received signals. It is configured as follows.

[0012] According to a number of implementations, the present disclosure provides a method for providing a method for controlling a gain level by using a gain control circuit having a variety of gain levels. coupled to a signal amplifier configured to provide the various associated impedance values. a variable impedance stage operatively associated with said variable impedance stage; a switch implemented to selectively isolate the variable impedance stage from a reference potential node; The present invention relates to a degeneration switching circuit including:

[0013] In some embodiments, the signal amplifier is configured to amplify the radio frequency signal. In some embodiments, a bypass path provided in the circuit is a variable impedance Bypasses the amplifier stage.

[0014] In some embodiments, different impedance values ​​are associated with the different gain levels. A degeneration switching circuit having various impedance values ​​connected to the configured to provide improved linearity of the signal amplifier as compared to an uncombined signal amplifier. In a further embodiment, the variable impedance stage has a first gain of various gain levels. A first tailored impedance value is given for each level, and a second tailored impedance value is given for each gain level. configured to provide a second customized impedance value for a gain level of .

[0015] In some embodiments, the circuitry further controls the variable impedance stage and the switch. In a further embodiment, the amplifier further includes a control circuit configured to generate an amplification control signal for controlling the amplifier. The control circuit is configured to provide a plurality of amplification control signals corresponding to different gain levels. will be done.

[0016] According to a number of implementations, the present disclosure provides a front-end architecture that includes a variable gain signal amplifier. The variable gain signal amplifier receives an input signal and generates an amplified output signal. a variable gain stage configured to obtain a gain of 100 MHz; and a degeneration switching block configured to provide a gain level. The front-end architecture also includes a variable gain signal amplifier coupled to the variable gain Also included is a filter assembly for directing a frequency band to a selected input of the signal amplifier. The architecture also includes a variable gain signal amplifier to control the variable gain signal amplifier to provide multiple gain modes. In the low gain mode, the variable gain signal amplifier includes a variable gain stage. Direct the signal along a bypass route.

[0017] In some embodiments, the degeneration switching block further comprises: The amplifier is configured to provide a variable gain stage with a set impedance. In the above, the customized impedance is Compared to a variable gain stage that is not coupled to a degeneration switching block, In a further embodiment, the filter is configured to provide improved linearity in the output signal. The degeneration switching block is configured to select a first gain level of a plurality of gain levels. providing a first tailored impedance to the filter and a second gain of a plurality of gain levels; The second impedance is configured to provide a second tailored impedance to the level.

[0018] According to a number of implementations, the present disclosure provides a diversity antenna and a method for receiving and selecting signals. a filter coupled to the diversity antenna to direct a frequency band along the path; The wireless device also includes a filter assembly for receiving an input signal. a variable gain stage configured to generate an amplified output signal; a degeneration switch configured to provide a plurality of gain levels for said variable gain stage; The wireless device also includes a variable gain signal amplifier including a switching block. A controller is also implemented to control the variable gain signal amplifier to provide the low-interest mode. In gain mode, the variable gain signal amplifier directs the signal along a path that bypasses the variable gain stage. Aim at.

[0019] In some embodiments, the degeneration switching block further comprises: The impedance is configured to be directed to a variable gain stage. In the above, the customized impedance is Compared to a variable gain stage that is not coupled to a degeneration switching block, In a further embodiment, the filter is configured to provide improved linearity in the output signal. The degeneration switching block is configured to select a first gain level of a plurality of gain levels. providing a first tailored impedance to the filter and a second gain of a plurality of gain levels; The second impedance is configured to provide a second tailored impedance to the level.

[0020] For purposes of summarizing the disclosure, certain aspects, advantages and novel features have been described herein. Not necessarily all such advantages will be achieved in any particular embodiment. Thus, embodiments of the present disclosure may be implemented with or without the benefit or group of benefits taught herein. without necessarily achieving any other advantages taught or suggested herein. The present invention can be implemented in such a manner. [Brief description of the drawings]

[0021] [Figure 1] 1 illustrates a wireless device having a primary antenna and a diversity antenna. [Diagram 2] 1 illustrates a diversity receiver (DRx) configuration including a DRx front-end module (FEM). [Figure 3A] An example variable gain amplifier configuration is illustrated that includes a multi-input gain stage configured to receive multiple inputs and selectively amplify the received signal through the gain stages or provide a bypass path through a bypass block. [Figure 3B] 3B illustrates another example variable gain amplifier that includes the same components as the variable gain amplifier of FIG. 3A with the addition of certain elements. [Figure 3C] 3B illustrates another example variable gain amplifier similar to that of FIG. 3A in which the bypass switch is omitted. [Figure 3D] 3C illustrates another example variable gain amplifier that includes the same components as the variable gain amplifier of FIG. 3C, with the addition of certain elements. [Figure 4] 1 illustrates a variable gain signal amplifier that includes a variable gain stage configured to receive an input signal and generate an amplified output signal. [Diagram 5] 1 illustrates a degeneration switching circuit that includes a variable impedance stage coupled to a signal amplifier having various gain levels. [Figure 6] 3C illustrates an example variable gain amplifier configuration similar to that of the variable gain amplifier of FIG. 3B. [Figure 7A] 7 illustrates an example of an operating mode of the variable gain signal amplifier arrangement of FIG. 6; [Figure 7B] 7 illustrates an example of an operating mode of the variable gain signal amplifier arrangement of FIG. 6; [Figure 7C] 7 illustrates an example of an operating mode of the variable gain signal amplifier arrangement of FIG. 6; [Figure 8] 7 illustrates a variable gain signal amplifier configuration similar to that of FIG. 6, but excluding the bypass switch. [Figure 9] 7 illustrates a variable gain signal amplifier configuration similar to that of FIG. 6, but with a shutdown switch block instead of a mid-gain mode feedback module. [Figure 10] 10 illustrates a variable gain signal amplifier 1010 similar to the variable gain signal amplifier configuration of FIG. 9, but excluding the bypass switch. [Figure 11] It is noted that in some embodiments, some or all of the diversity receiver configurations may be implemented in whole or in part within a module. [Figure 12] It will be appreciated that in some embodiments, some or all of the diversity receiver configurations may be implemented in whole or in part within the architecture. [Figure 13] Illustrates an example wireless device having one or more advantageous features described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The headings provided herein, if any, are merely for convenience and should not be construed as limiting the scope of the claims. It does not necessarily affect the scope or meaning of such inventions.

[0023] overview

[0024] FIG. 1 illustrates a wireless device having a primary antenna 160 and a diversity antenna 170. 1 illustrates an example wireless device 100. The wireless device 100 includes an RF module that can be controlled by a controller 102. The transceiver 104 receives an analog signal (e.g., a radio frequency The device is configured to convert between a radio frequency (RF) signal and a digital data signal. For this purpose, the transceiver 104 may include a digital-to-analog converter, an analog-to-digital converter, A local oscillator for modulating or demodulating a baseband analog signal to or from a carrier frequency. A digital oscillator, between digital samples and data bits (e.g., voice or other types of data). It may include a baseband processor that performs the conversion, or other components.

[0025] The RF module 106 is coupled between the primary antenna 160 and the transceiver 104 . The RF module 106 provides a physical layer to the primary antenna 160 to reduce attenuation due to cable losses. Since the RF module 106 can be physically close to the front-end module (FEM), The RF module 106 provides the primary antenna for the transceiver 104. 160 or from the transceiver 104 for transmission via the primary antenna 160. The received analog signal can be processed. For this purpose, the RF module 1 06 includes filters, power amplifiers, low noise amplifiers, band select switches, attenuators, matching circuits, and other components.

[0026] When a signal is transmitted to the wireless device 100, the signal is transmitted through the primary antenna 160 and the diverse antennas 162, 164, 166, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 179, 180, 181, 182, The signal can be received by both the primary antenna 160 and the diversity antenna 170. The city antenna 170 is physically separated from the primary antenna 160 and the divergent antenna 170. The signals at the city antenna 170 are received with different characteristics. In an embodiment, the primary antenna 160 and the diversity antenna 170 have different attenuation. The transceiver 1 can receive signals with attenuation, noise, frequency response and / or phase shift. 04 uses both signals of different characteristics to determine the data bits corresponding to the signals. In some implementations, the transceiver 104 may include a primary antenna 160 and a die. Based on the characteristics, the antenna may be selected from among the various antennas 170. In some implementations, the antenna with the highest signal-to-noise ratio can be selected. The receiver 104 combines the signals from the primary antenna 160 and the diversity antenna 170. In some implementations, the transmitter and receiver The receiver 104 processes signals to provide multiple input / multiple output (MiMo) communication.

[0027] In some embodiments, the diversity antenna 170 can receive multiple cellular frequencies. Signals in several bands and / or Wireless Local Area Network (WLAN) frequency bands In such an embodiment, the wireless device 100 is configured to receive A diversity antenna 170 configured to split the city signal into different frequency ranges. a multiplexer, switching network and / or filter assembly coupled to For example, the multiplexer may pass a frequency range that includes low-band cellular frequencies. and a low-pass filter for filtering low-band WLAN signals and mid-band and high-band cellular signals. and a bandpass filter that passes a frequency range including the high-band WLAN signal. The present embodiment can be configured to include a high-pass filter that passes a range of the input and output signals. For illustrative purposes only. As another example, a multiplexer may include a high pass filter and a low pass filter. The optical amplifier may have a variety of different configurations, such as a diplexer that provides the function of a filter.

[0028] Since the diversity antenna 170 is physically separated from the primary antenna 160, The diversity antenna 170 may be attached to a cable or a printed circuit board (PCB) trace. In some implementations, the transmission line is lossy, and the signal received at the diversity antenna 170 is 4. Therefore, in some implementations, the diversity antenna A gain is applied to the signal received at the filter 170. Other analog processing (e.g., analog processing) may be applied by the diversity receiver module 108. Such a diversity receiver module 108 can receive a signal from a diversity antenna 1. 70 are physically located close to each other, so that the diversity receiver front-end module An example of this is now described in detail.

[0029] The RF module 106 and the diversity receiver module 108 are connected to the primary antenna 1. Multiple gain modes for amplifying signals from the 160 and diversity antennas 170 respectively The variable gain amplifiers 110a, 110b are configured to provide 10a, 110b each include a gain stage 120 and a variable gain amplifier 110a, 110b. A degenerator that varies the inductance based at least in part on one gain mode. and a switching block 130. The signal received at the input may be amplified using a gain stage 120 or the signal may be As will be described in detail in, it may be permissible to bypass the gain stage 120. The selected inductance, bypass path, and / or The gain modes of the variable gain amplifiers 110a and 110b are controlled by the controller 102. The degeneration switching block 130 changes the inductance. Since the performance of the variable gain amplifiers 110a, 110b can be configured to be fixed The inductance of the amplifier can be increased compared to the and / or can increase performance by reducing noise introduced during amplification The variable gain amplifiers 110a, 110b receive multiple input signals and output a single signal or multiple In some implementations, each input can be connected to an input port. To improve the input isolation between the corresponding individual degeneration switching blocks, It may have a .

[0030] Advantageously, the architecture of the variable gain amplifiers 110a, 110b uses switches. The variable gain amplifiers 110a, 110b can provide multi-input processing without using a separate amplifier. b is advantageously a switchable degenerator with a tailored inductance. Using a linearization block to achieve a target or improved linearity The variable gain amplifiers 110a and 110b can be provided with a shunt switch in the bypass path. By using The variable gain amplifiers 110a and 110b are configured to operate in a specific gain mode, such as a low gain mode. A low loss direct bypass mode can be provided.

[0031] The controller 102 may be configured to generate control signals and / or to communicate with other controllers of the wireless device 100. In some embodiments, the method may be configured to transmit the The controller 102 is a Mobile Industry Processor Interface Alliance (MIPI) The controller 1 provides a signal based at least in part on specifications provided by the IEEE Trademark Alliance. 02 receives signals from other components of the wireless device 100 and transmits the signals to the other components. The control signal received by the device can be processed to determine In this embodiment, the controller 102 analyzes the signal or data and determines whether the The control signal may be configured to be sent to other components. The control circuit 102 is adapted to generate a control signal based on the gain mode provided by the wireless device 100. For example, the controller 102 can be configured to generate a control signal to control the gain mode. The controller 102 may also transmit the signal to the variable gain amplifiers 110a, 110b. A control signal is generated to select the inductance of the generation switching block 130. The controller may be configured to configure a variable gain amplifier to provide a bypass path. The control signals can be configured to generate control signals that control the devices 110a, 110b.

[0032] In some implementations, the controller 102 may be configured to: In some implementations, the control circuit generates an amplifier control signal based on the signal quality metric. The device 102 performs a service of the received signal based on the signal received from the communication controller. Generates amplifier control signals based on the Quality of Service (QoS) metrics of the received signal. The QoS metric is at least partially determined by receiving the diversity antenna 170. The received signal may be based on a diversity signal (e.g. an input signal received at the input). The QoS metric of the received signal is further based on the signal received at the primary antenna 160. In some implementations, the controller 102 may receive a signal from a communication controller. Instead, the amplifier control signal is generated based on the QoS metric of the diversity signal. In some implementations, the QoS metric includes signal strength. The block can measure bit error rate, data throughput, transmission delay or any other QoS metric. In some implementations, the controller 102 may include variable gain amplifiers 110a, 11 0b. In some implementations, the control The control unit 102 adjusts the gain of other components of the wireless device based on the amplifier control signal. Take control.

[0033] In some implementations, the variable gain amplifiers 110a, 110b amplify the received signal. a stage configured to amplify the gain by one of a plurality of set amounts indicated by the amplifier control signal; In some implementations, the variable gain amplifiers 110a, 10b amplifies the received signal by a gain proportional to or indicated by the amplifier control signal. In some implementations, the variable gain amplifier may include a continuously variable gain amplifier configured to The amplifiers 110a, 110b draw one of a number of preset amounts of current as indicated by the amplifier control signal. a step variable current amplifier configured to amplify a received signal by In some implementations, the variable gain amplifiers 110a, 110b receive an amplifier control signal A continuous variable resistor configured to amplify a received signal by drawing a current proportional to the It may include a variable current amplifier.

[0034] FIG. 2 illustrates a diversity receiver including a DRx front-end module (FEM) 208. The DRx configuration 200 is a configuration for receiving a diversity signal. , and transmits the diversity signal to the DRx FEM 150 via the filter assembly 272. The filter assembly 27 includes a diversity antenna 170 configured to provide 2, for example, a signal within a target frequency range is fed to a degeneration switching circuit 230 to selectively direct the inputs along each path to the multi-input amplifier 220. The signal may include, for example, a cellular signal (e.g., low, medium, high and / or ultra-high band cellular frequencies), WLAN signals, BLUETOOTH (registered trademark The signals may be radio frequency (RF) signals, including but not limited to GPS signals, GPS signals, etc. .

[0035] The DRx FEM 208 receives a diversity signal from the filter assembly 272. For example, the DRx FEM 208 may be configured to process a diversity signal. one or more active frequency bands, which may include cellular and / or WLAN frequency bands. The controller 102 can be configured to filter the signal to a desired filter. To achieve this filtering, the DRx FEM208 is controlled by the As another example, the DRx FEM 208 may be configured to control the amplifier 22. 0 may be used to amplify one or more of the filtered signals. For this purpose, the DRx FEM208 includes filters, low-noise amplifiers, band-select switches, , matching circuits, and other components. DRx FEM to intelligently select the path for the diversity signal through The component at 208 may be configured to interact with the component at 208 .

[0036] The DRx FEM208 transmits and receives at least a portion of the processed diversity signal. The transceiver 104 may be controlled by the controller 102. In some implementations, the controller 102 may be implemented within the transceiver 104 .

[0037] The DRx FEM 208 can be configured to provide multiple gain modes. For several gain modes, the variable impedance of the degeneration switching circuit 230 The gain stage 232 allows different inductances to be provided. 2, the switch 234 of the variable impedance stage 232 is connected to The impedance (e.g., inductance) can be selected. Such selection can be performed, for example, to improve the linearity of the amplification process. The possible impedances can be embedded into a multiple input amplifier architecture.

[0038] In some embodiments, a selectable impedance, e.g., L, coupled to the amplifier stage. The use of NA can improve linearity and / or IIP3. 4, the variable impedance stage 232 advantageously allows for a particular gain mode and / or or coupling the amplifier 220 to a desired or targeted impedance for the signal amplitude. In some embodiments, the DRx configuration 200 may be a low gain model. It bypasses the amplification when operating in one gain mode and amplifier 220 when operating in other gain modes. This advantageously enables the DRx arrangement 200 to: The linearity in a particular gain mode can be improved.

[0039] In some embodiments, amplifier 220 receives multiple input signals and produces a single output. In certain embodiments, the amplifier 220 is configured to provide a multi-input The filter may be configured to receive a signal and provide a corresponding number of output signals. Assembly 272 routes signals corresponding to particular frequency bands to designated paths to amplifier 220. In certain implementations, the amplifier 220 may be configured to direct the light along the The variable impedance stage 232 can provide different gain modes for the received signal. 2 selects different impedances using a switch 234 coupled to the amplifier 220. The selected impedance may be determined, at least in part, by the impedance of the amplifier 220. In certain implementations, the amplifier 220 is in a bypass configuration. In an amplifier configuration, the signal is amplified. The selected impedance can be operative to pass through a path. This is advantageously provided by the DRx FEM 208. The negative impact on linearity (e.g. IIP3) and / or noise figure (NF) is Reduced compared to a configuration in which no path path and / or variable impedance is selectively provided. The amplifier 220 may provide variable gain and / or multiple gain modes while being in operation. may include any suitable amplifier circuit configured to provide a desired or targeted amplification. In some embodiments, amplifier 220 may include a low noise amplifier (LNA) circuit. This is because multiple frequency bands ( configured to amplify signals from a cellular frequency band and / or a WLAN frequency band. However, the embodiments described herein may be implemented using low noise amplifiers. It should be understood that this includes, but is not limited to, implementations using any of a variety of amplifiers.

[0040] The amplifier 220 is adapted to amplify a signal based at least in part on a plurality of gain modes. For example, the amplifier 220 can be configured to have a first amplification or gain for a second gain mode, and a second amplification or gain for a second gain mode, etc. The amplifier 220 may be controlled by the controller 102, which controls the gain provided to the amplifier 220. For example, the controller 102 may be configured to control a desired or target gain A signal indicative of can be provided to amplifier 220, which provides a target gain. The controller 102 may, for example, receive the , receiving an indication of a target gain and controlling amplifier 220 based at least in part on the indication. Similarly, the degeneration switching circuit 230 can control the amplification based at least in part on the gain mode and / or target gain of the gain adjuster 220. It is possible.

[0041] The controller 102 controls the DRx FEM to selectively provide a tailored impedance. For example, the controller 102 and the DRx FE 208 may be configured to The M208 provides a target impedance based at least in part on the gain mode. To achieve this, the variable impedance stage 232 can be controlled to configure the switch 234. As another example, the controller 102 and the DRx FEM 208 may be, at least in part, The amplifier can be controlled to provide a bypass path based on the mode. The controller 102 and the DRx FEM 208 use the amplifier 220 to provide multiple gain modes. Can be given.

[0042] Example of variable gain amplifier architecture

[0043] The front-end module generally includes a low-noise amplifier (LNA) to amplify the received signal. In wireless devices that provide various gain modes, the performance is improved. Selectively providing a variable or tailored impedance to a gain stage to improve Similarly, for at least one gain mode, improving performance (e.g. It may be advantageous to bypass the gain stage (e.g., to improve linearity).

[0044] Thus, what is provided herein is a method for at least partially controlling the gain mode of a variable gain amplifier. Depending on the degeneration block and / or the feedback block, A variable gain amplifier that selectively provides a tailored impedance. Advantageously, the performance penalty is reduced or eliminated in one or more gain modes. In addition, the variable impedance improves the linearity of the amplification process in the targeted gain mode. Similarly, a variable gain amplifier can be configured to increase or decrease the gain to improve signal quality. , can be configured to provide a low loss bypass mode in low gain mode.

[0045] FIG. 3A illustrates an example variable gain amplifier configuration 310 a that includes a multiple-input gain stage 312 . The multi-input gain stage 312 receives multiple inputs and filters the received signals through a gain stage 320. to selectively amplify or provide a bypass path through bypass block 340. The gain stage 320 is coupled to a degeneration switching block 330. The degeneration switching block 330 is connected to the variable gain amplifier configuration 310a. selectively providing a tailored impedance based at least in part on the gain mode of the In certain implementations, the multi-input gain stage 312 is configured to receive separate input ports. Each separate input port is configured to receive a number of signals at the input port. Configured to receive signals in one or more specific cellular frequency bands. For example, A signal in a first band is received at a first input port and a signal in a second band is received at a second input port. and a signal in a third band is received at a third input port.

[0046] The variable gain amplifier 310a can be used to implement multiple inputs without using a switching network. The variable gain amplifier 310a can be configured to provide degeneration and It is constructed to achieve relatively high linearity through the use of a phase switching block 330. In certain implementations, the bypass block 340 may be a shunt switch. The shunt switch provides higher input-to-output isolation compared to configurations with such switches. The variable gain amplifier 310a converts the signal from the input to a bypass buffer. 340 but not through gain stage 320. The LT850 can be configured to provide a low loss direct bypass mode. The mode can be implemented in a low gain mode, for example.

[0047] The variable gain amplifier 310a includes a multi-input gain stage 312 that provides a voltage to a current gain stage 320. The multi-input gain stage 312 can be configured to provide isolation between the inputs. In some embodiments, the variable gain amplifier 310a provides a differential input to each input. A generation switching block 330 may be included to further isolate the inputs. do.

[0048] The degeneration switching block 330 changes the impedance into the gain stage 320. In this way, it is possible to match the previous stage in the processing chain. By adding power and / or noise, performance can be improved. The motion switching block 330 provides a feedback mechanism to The gain stage 320 may be configured to improve linearity. In some embodiments, Thus, the degeneration switching block 330 selects a first inductor for the first gain mode. and configured to provide a second impedance for a second gain mode. The selected impedance provided by the degeneration switching block 330 is The gain stage 320 may also be configured to improve the linearity of the gain stage 320. In bypass mode, the degeneration switching block 330 In this way, the gain stage 320 can be bypassed. Reducing or minimizing leakage current can improve linearity performance.

[0049] The bypass block 340 is adapted to receive signals from multiple inputs and to provide a bypass to the gain stage 32. 0 or provide a path to the output that does not pass through the degeneration switching block 330. The bypass block 340 is configured to take advantage of the benefits provided by the variable gain amplifier 310a. A component that serves to separate the input section and the output section in one or more of the obtained modes. It may include.

[0050] The intermediate gain mode feedback block 350a is a feedback circuit that is provided by the variable gain amplifier 310a. The intermediate gain modes are configured to be active for a subset of the gain modes. The feedback block 350a is configured to provide a desired impedance to the input signal. This can help improve the linearity of the amplification process. Feedback block 350a controls the feedback in variable gain amplifier 310a. The intermediate gain mode feedback block 350a can also be configured as follows: The degeneration block can be configured to provide the same functionality as the This can be done.

[0051] The bypass switch 360 is a bypass block 340 that is connected from the input to the output. 320. The gain stage 320 is configured to selectively provide a path from the input to the output. The bypass switch 360 controls at least part of the gain mode of the variable gain amplifier 310a. one or more switching elements that isolate and / or select a desired path based on the It may include.

[0052] In certain embodiments, the variable gain amplifier 310a can have multiple gain modes, e.g. It can be configured to give modes G0, G1, ..., GN. G0 is the highest gain. When operating in gain mode GN, the variable gain amplifier 31 0a can be configured to direct the signal from the input to the bypass block 340. When operating in the gain modes G0 to GN-1, the variable gain amplifier 310a includes a gain stage 32 Activate the degeneration switching block 330 by directing the signal through 0. The degeneration switching block 330 can be configured to , which provides different impedance levels for individual gain modes or for groups of gain modes. Even in these gain modes, the bypass block can be configured to provide The shunt of the bypass block 340 provides isolation between the input and output. By activating the switch, it can be at least partially activated. The variable gain amplifier 310a can provide intermediate gain for one or more of the gain modes G0 to GN-1. The gain mode feedback block 350a can be configured to activate do.

[0053] The variable gain signal amplifier 310a corresponds to the intermediate gain mode feedback block 35 of the present disclosure. 0a, a bypass block 340, and a degeneration switching block 330. Achieves relatively low noise and high linearity (e.g. higher IIP3) compared to amplifiers without The variable gain signal amplifier 310a can be configured to receive the cellular signal, WL Radio frequencies such as RAN signals, BLUETOOTH (registered trademark) signals, GPS signals, etc. F) can be configured to amplify the signal. By receiving signals across multiple frequency bands at the input and processing the signals, The variable gain signal amplifier 310a can be configured to provide wideband performance. It can be configured to process the signals at each input independently. The gain signal amplifier 310a is connected to a controller (e.g., a control circuit as described herein with reference to FIGS. 1 and 2). The control circuitry may be configured to control a control circuit assembly such as a control circuit 102. The path assembly intelligently and selectively switches the path between the amplification path and the bypass path. can be selectively switched by the degeneration switching block 330. Impedance can be provided.

[0054] Although three inputs are illustrated, the variable gain amplifier 310a may have any suitable number of inputs. It should be understood that the input section may include, for example and without limitation, a variable gain amplifier 310a has at least two inputs, at least four inputs, at least eight inputs, at least 16 inputs, at least 32 inputs, at least 64 inputs, or As another example and without limitation, a variable The gain amplifier 310a may have 64 or fewer inputs, 32 or fewer inputs, 16 or fewer inputs, It may include eight or fewer inputs, four or fewer inputs, or any number within the stated range.

[0055] FIG. 3B shows a circuit diagram of a variable gain amplifier 310a having the same components as FIG. 3A, with the addition of certain elements. 3 illustrates another example variable gain amplifier 310b that includes a variable gain amplifier component. b includes matching networks 313, 318 and 345. The input matching network 313 is , configured to provide an impedance match to a signal received at the input. The output matching network 318 is similarly connected to the output load 316, the gain stage 320 and the cascode bridge. The amplifier including the buffer 314 is configured to provide impedance matching. The bypass matching network 345 also provides an impedance matching circuit for the bypass block 340. The matching networks 313, 318, and 345 are provided with a target impedance. Any suitable combination of inductors and capacitors may be used to provide the impedance. This can be done.

[0056] The variable gain amplifier 310b also includes an output load 316 and a cascade amplifier as part of the amplification chain. The cascode buffer 314 acts as a current buffer. The cascode buffer 314 can be configured to include a gain stage 320 and an output stage 322. The cascode buffer 314 is also configured to provide isolation between the variable gain amplifier The output load 316 may be configured to improve the gain of the output voltage The output load 316 is configured to provide a load to the current to generate an amplitude. tuned or tunable to each band received in The output load 316 can be adjusted by tailoring the resistance of the output load 316. It can be configured to improve return loss and / or increase bandwidth. Voltage VD D can be configured to set the gain mode of the variable gain amplifier 310b. For example, the voltage VDD is set such that the current flowing through the output load 316 is lower. The gain of amplifier 310b can be configured to accommodate this.

[0057] FIG. 3C is similar to the variable gain amplifier 310a of FIG. 3A, but includes a bypass switch 360. 3 illustrates another example variable gain amplifier 310c in which the bypass switch 360 is omitted. Therefore, the output of the bypass block 340 is coupled to the output of the output of the gain stage 320. In addition, the intermediate gain mode feedback block is connected to the shutdown switch block. 3A. However, the shutdown switch block 350c is replaced by the shutdown switch block 350c of FIG. It is not coupled to the output as in variable gain amplifier 310a. Therefore, the shutdown switch block 350c reduces leakage in the amplifier 310c. In some embodiments, the input node is configured to selectively isolate the input nodes so as to This is a switch between the input node and the reference potential node when the input is not in use. It can be activated by activating the switch. Thus, the switch can couple the input node to the reference potential node via the capacitive element. .

[0058] FIG. 3D shows a variable gain amplifier 310c having the same components as FIG. 3C, with the addition of certain elements. 3 illustrates another example of a variable gain amplifier 310d including the above-mentioned components. 0d includes matching networks 313, 318 and 345. 3 is configured to provide impedance matching to a signal received at the input. Similarly, the output matching network 318 is formed by connecting the output load 316 with the gain stage 320 and the cascode. 314 and an amplifier including a buffer 314. The bypass matching network 345 also provides an impedance matching to the bypass block 340. The matching networks 313, 318, and 345 are provided with the target impedance. Any suitable combination of inductors and capacitors may be used to provide the impedance. It is possible.

[0059] The variable gain amplifier 310d also includes an output load 316 and a cascade amplifier as part of the amplification chain. The cascode buffer 314 acts as a current buffer. The cascode buffer 314 can be configured to include a gain stage 320 and an output stage 322. The cascode buffer 314 is also configured to provide isolation between the variable gain amplifier The output load 316 may be configured to improve the gain of the output voltage The output load 316 is configured to provide a load to the current to generate an amplitude. tuned or tunable to each band received in The output load 316 can be adjusted by tailoring the resistance of the output load 316. It can be configured to improve return loss and / or increase bandwidth. Voltage VD D can be configured to set the gain mode of the variable gain amplifier 310d. For example, the voltage VDD is set such that the current flowing through the output load 316 is lower. The gain of amplifier 310d can be configured to accommodate this.

[0060] FIG. 4 illustrates a variable gain amplifier configured to receive an input signal and generate an amplified output signal. Illustrated is a variable gain signal amplifier 410 including a stage 420. The variable gain signal amplifier 410 also , and also includes a degeneration switching block 430 coupled to the variable gain stage 420. The degeneration switching block 430 controls the different gains of the variable gain stage 420. It can be configured to provide different gain levels.

[0061] FIG. 5 illustrates a variable impedance amplifier 520 coupled to a signal amplifier 520 having various gain levels. 5 illustrates a degeneration switching circuit 530 including a variable impedance stage 532. The impedance stage 532 is adapted to provide different impedance values ​​associated with different gain levels. The degeneration switching circuit 530 can be configured as follows: The switch 534 is operatively associated with the dance stage 532. The switch 534 , implemented to selectively isolate the variable impedance stage 532 from the reference potential node. .

[0062] FIG. 6 illustrates a variable gain amplifier 310b configured similarly to the variable gain amplifier 310b described herein with reference to FIG. 3B. 6 illustrates an example variable gain amplifier configuration 610. The variable gain amplifier 610 is an example implementation of an amplifier. It includes examples of electrical components to demonstrate the present invention. However, this is merely an example of an implementation. It is understood that the scope of this disclosure extends to additional implementations that encompass similar architectures. You should understand.

[0063] A variable gain amplifier arrangement 610 receives inputs A, B and C and converts the received signals into A cascode buffer 614 having a transistor Q10 in conjunction with corresponding transistors Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, and Q11. The gain stage 612 includes a multi-input gain stage 612 configured to selectively amplify inputs Q1, Q2, and Q3. The multi-input gain stage 612 also includes switching transformers for each of the inputs A, B, and C. To provide a bypass path through bypass block 340 including resistors Q6, Q7 and Q8. It is configured as follows.

[0064] The multi-input gain stage 612 is coupled to a degeneration switching block 630. The degeneration switching block 630 is Selectively providing a tailored impedance based at least in part on the gain mode. In certain implementations, the multi-input gain stage 612 is configured to receive separate input ports. Each of the separate input ports is configured to receive a number of signals at one The cellular frequency band may be configured to receive signals in one or more specific cellular frequency bands. Input A receives signals in the first band, input B receives signals in the second band, and input C receives signals in the third band. In some embodiments, transistors Q3, Q4 and Q5 receive a signal in the band. Each has a dedicated degeneration switch to increase isolation between input ports. Each of these inputs can be coupled to a switching block 630. The inductors L4, L5 and L6 are coupled to provide phase matching.

[0065] The variable gain amplifier configuration 610 provides multiple inputs without the use of a switching network. The variable gain amplifier arrangement 610 can be configured to provide power processing. To achieve relatively high linearity through the use of a phase switching block 630. In certain implementations, the bypass block 640 can be configured to A shunt switch Q can provide higher input-to-output isolation compared to a configuration with a 9. The variable gain amplifier arrangement 610 includes a bypass block 640 from the input. It can be configured to provide a low loss direct bypass mode by directing the signal to The low loss direct bypass mode can be implemented in low gain mode, for example. can.

[0066] The variable gain amplifier configuration 610 includes a multi-input gain stage that provides a voltage to a current gain stage that includes transistors Q3-Q5. 612 Includes: Multiple Input Gain Stage 612 is configured to provide a voltage to the current gain stage. 612 are configured to amplify their respective input signals in conjunction with a cascode buffer 614 including transistor Q10, which is configured to act as a current buffer to lower the input impedance and increase the output impedance.

[0067] The degeneration switching block 630 controls the gain stages of the multi-input gain stage 612. In this way, the front end of the processing chain is By providing power and / or noise matching to the stages, performance can be improved. The generation switching block 630 provides a feedback mechanism. This improves the linearity of the gain stage (for example, transistors Q3 to Q5). The degeneration switching block 630 includes transistors Q2 and The first impedance L1 is set by activating the first and second transistors Q1 and Q2. a first gain mode and a second impedance provided by L1 and L2 is provided for the second gain mode. The degeneration switching block 63 can be configured to provide The selected impedance provided by the zero is also configured to improve the linearity of the gain stage. The variable gain amplifier arrangement 610 can also be used in the bypass mode. The on-switching block 630 can be bypassed. to improve linearity performance by reducing or minimizing leakage current through the gain stage. In certain implementations, the degeneration switching block 630 may include , can be configured to provide low inductance to high gain modes. The amount of inductance provided by the ratio switching block 630 is This can be changed by changing the gain mode of the configuration 610.

[0068] The bypass block 640 is adapted to receive signals from multiple inputs and to provide a gain stage (e.g. For example, through transistors Q3 to Q5 or through the degeneration switching block 630 The bypass block 640 is configured to provide a path to the output that does not exceed the 1. The input of the amplifier is configured to provide a single path to the output via transistor Q11 and capacitor C1. Capacitor C1 can be configured to block direct current (DC) voltage from the output supply. The bypass block 640 can also be used to help isolate the input from the output. 5. The bypass block 640 is selectively coupled to the reference potential node via a transistor Q9 as shown in FIG. The bypass matching network 645 includes a shunt switch that This allows for flexibility in performance matching.

[0069] The intermediate gain mode feedback block 650 is provided by the variable gain amplifier configuration 610. The intermediate gain modes are configured to be active for a subset of the gain modes. The feedback block 650 is configured to provide a desired impedance to the input signal. This can help improve the linearity of the amplification process. To control the amount of feedback, an RC matching network 651 can be used. Additionally, the RC matching network 651 is configured to act as a block for the DC voltage. The RC matching network 651 can be configured as an amplitude and phase feedback. The RC matching network 651 can be configured to control the capacitance behavior. resistors, capacitors and resistors in series, or capacitors, resistors and other components The medium gain mode feedback block 65 may include any suitable combination of the following: 0 can also be configured to control feedback within the variable gain amplifier 610. The intermediate gain mode feedback block 650 is a second degeneration block. The blocks can be configured to provide similar functionality as those included in the circuit.

[0070] When active, the signals from inputs A, B and C are A , B and C At point D In the blog This point D output matching network 618 and bypass switch 6 60. In other words, the intermediate gain mode feedback block The inputs A, B, and C are connected to the transistors Q14 to Q16 and Q18. An additional transistor Q17 acts as a bypass block. Similar to the switch 640, the shunt switch can be configured to provide a reference potential node. Key Points D The output matching network 618 is connected to the output matching network 618. The output matching network 618 may be located within the The intermediate gain mode feedback block 650 can be used to cancel the input and output. can be constructed to generate a point D Variable gain to improve performance It may be positioned within the amplifier arrangement 610 .

[0071] The bypass switch 660 is connected to the inputs A, B, and C via the bypass block 640. The path to the output, or from inputs A, B and C to gain stage elements and amplifier elements (e.g. cascode 614 and an output matching network 618) to the output. The bypass switch 660 controls the connection between the amplification path and the output. A transistor Q12 controls the connection between the bypass path and the output. 13. The bypass switch 660 at least changes the gain mode of the variable gain amplifier 610. The control can be based in part on the

[0072] Matching networks 618 and 645 are used to provide the desired impedance. The output may include any suitable combination of inductors and capacitors. The combining network 618 is connected to the output load 616 and the gain stage (e.g., transistors Q3 to Q5) and and an amplifier including a cascode buffer 614. The bypass matching network 645 is also configured for the bypass block 640. This gives the impedance matching.

[0073] The variable gain amplifier 610 includes an output load 616 and a cascode buffer as part of the amplification path. The cascode buffer 614 is configured to act as a current buffer. The cascode buffer 614 includes a transistor Q10 that is connected between the gain stage and the output. The cascode buffer 614 is also configured to provide isolation. The output load 616 can be configured to improve the output voltage swing by The output load 616 is configured to provide a load to the current to generate a The device may be configured to be tuned or tunable for each band received. For example, the output load can be tuned for a specific cellular frequency band. The output load 616 also includes a resistor R1 of the output load 616. The present invention can be configured to improve return loss and / or increase bandwidth by incorporating a It is also possible.

[0074] The voltage VDD can be configured to set the gain mode of the variable gain amplifier 310b. For example, the voltage VDD may be lower so that the current flowing through the output load 316 is lower. The gain of the variable gain amplifier 310b can be configured to accommodate the lower gain.

[0075] 7A-7C illustrate several example modes of operation of the variable gain signal amplifier configuration 610 of FIG. FIG. 7A illustrates operation in one or more high gain modes. These high gain modes In this mode, the bypass block 640 is deactivated except for the shunt switch Q9. The signals received at the inputs A, B and C are fed to the output terminals including the transistors Q3 to Q5. 614, and through the output matching network. The output is passed through the work 618 and the bypass switch 660. In these high gain modes, Q12 is activated and Q13 is deactivated. Additionally, in these high gain modes, transistor Q2 is turned on and transistor Q1 is turned off, so the gain is The inductance presented to the stage is L1. In these high gain modes, the intermediate gain The mode feedback block 650 is also deactivated.

[0076] FIG. 7B illustrates operation in one or more intermediate gain modes. These modes also include These intermediate gain modes of operation can be referred to as low gain, high linearity modes, and low gain, high linearity modes. There are several significant differences between the high gain modes of operation. In operation block 630, transistor Q2 is turned off and transistor Q1 is turned on. 630 to the gain stage. The inductance applied is given by both L1 and L2. A higher gain mode results in increased impedance, or a higher gain mode results in decreased impedance. Second, the medium gain mode feedback block 650 is active. This reduces the circuit power consumption as if a second degeneration block had been added. This provides additional feedback to the

[0077] FIG. 7C illustrates operation in one or more low-gain modes. In these low-gain modes, In this case, the bypass block 640 is activated and the gain stage transistors Q3 to Q5 are activated. The signals received at inputs A, B and C are deactivated in bypass block 64. 0, through a bypass matching network 645 and a bypass switch 660, and In these low gain modes, the bypass switch activates Q13. and deactivate Q12. In addition, the degeneration switching block To deactivate 630, transistors Q1 and Q2 are turned off, and the gain stage transistor Reducing or minimizing the leakage current through transistors Q3-Q5 improves linearity performance. The medium gain mode feedback block 650 also controls the gain of the low gain mode. It is deactivated.

[0078] FIG. 8 illustrates a variable gain signal amplifier configuration 610 similar to that of FIG. 6, but without bypass switch 66. 8 illustrates a variable gain signal amplifier 810 with the zero removed. , so that the output of the bypass matching network 645 is instead 618. In this configuration, the selection of the amplification path or the bypass path is controlled. There is no bypass switch that controls the gain of selected transistors (e.g. transistors Q3-Q5), and selected transistors of the bypass block (e.g. Transistors Q6-Q8 are selectively active to provide a bypass path or an amplification path. are activated and deactivated.

[0079] FIG. 9 illustrates a variable gain signal amplifier configuration 610 similar to that of FIG. 6, but with an intermediate gain mode feedback. Variable gain with shutdown switch block 950 instead of feedback module 9 illustrates a signal amplifier 910. In this configuration, the output node of the output matching network 618 Since the shutdown switch block 950 is not coupled to the amplification path in the Instead, the shutdown switch block 950 is Transistors Q14 to Q16 and capacitors Q15 to Q16 are arranged to selectively isolate A, B, and C. In some embodiments, the shutdown switch block 950 does not include the capacitors C3 to C5. The shutdown switch block 950 is Switching on (e.g. using a transistor) when the corresponding input is not in use This can be configured to reduce leakage in the amplifier configuration. To reduce or eliminate this, the input can be shut off to ground. can.

[0080] FIG. 10 illustrates a variable gain signal amplifier configuration 910 similar to that of FIG. 9, but without bypass switch 6 8 illustrates a variable gain signal amplifier 1010 with 60 omitted. 10, the bypass matching network 6 is eliminated by eliminating the bypass switch. This results in the output of 45 being coupled to the input node of output matching network 618. In this configuration, there is no bypass switch to control the selection of the amplification path or the bypass path. In addition, selected transistors in the gain stage (e.g., transistors Q3 to Q5) and the bypass Selected transistors in the block (e.g., transistors Q6 to Q8) are bypassed. The amplifiers may be selectively activated and deactivated to provide a selective path or an amplification path.

[0081] Example Products and Architectures

[0082] FIG. 11 illustrates, in some embodiments, a combination of features (e.g., FIGS. 1-10). A diversity receiver configuration including some or all of the diversity receiver configurations having Some or all of the above may be implemented in whole or in part in modules. The module may be, for example, a front-end module (FEM). The module may be, for example, a diversity receiver (DRx) FEM. The module may be, for example, a multiple-input multiple-output (MiMo) module.

[0083] In the example of FIG. 11, a module 1108 includes a packaging substrate 1101. A certain number of components are attached to the package board 1101. For example, A controller 1102 (which may include a FE-PIMC) Assembly 1106, a gain stage 1120 having one or more features described herein, and a delay a variable gain amplifier assembly 1110 including a generation switching block 1130; and a filter bank 1108 (which may include one or more bandpass filters) in a package. The semiconductor device is attached and / or mounted on and / or within the package substrate 1101. Other components, such as a certain number of SMT devices 1105, can be packaged together. All of the various components can be mounted on a package board 1101. Although the device is depicted as being laid out on a printed circuit board 1101, certain components may be included. It is understood that components may also be implemented on top of other components.

[0084] FIG. 12 illustrates, in some embodiments, a combination of features (e.g., FIGS. 1-10). A diversity receiver configuration including some or all of the diversity receiver configurations having Some or all of the above may be implemented in whole or in part in the architecture. Such an architecture includes one or more modules, a diversity receiver (DRx) It can be configured to provide front-end functionality such as front-end functions.

[0085] In the example of FIG. 12, the architecture 1208 includes a front-end power management integrated circuit ( [FE-PIMC]) controller 1202, combination assembly 1206, A gain stage 1220 having one or more features described in A variable gain amplifier assembly 1210 including a gain block 1230, and A filter bank 1208 (which may include a pass filter) is mounted on the package substrate 1201 and and / or may be attached and / or mounted within a package substrate 1201. Other components, such as SMT devices 1205, may also be included in the architecture 1208. It can be implemented.

[0086] In some implementations, a device and / or device having one or more features described herein The circuitry may be included in an RF electronic device, such as a radio frequency device. The processor and / or circuitry may be integrated directly into the wireless device, in a modular form as described herein, or in a In some embodiments, such a combination may be implemented. The wireless device may be, for example, a mobile phone, a smartphone, a handheld device with or without a telephone function. These may include handheld wireless devices, wireless tablets, and the like.

[0087] FIG. 13 illustrates an example wireless device 1300 having one or more advantageous features described herein. In the context of one or more modules having one or more features described herein, Such modules are generally designated by dashed lines (eg, may be implemented as front-end modules). 1306, and a diversity 13. The signal processing unit 1302 is depicted by a receiver (DRx) module 1308.

[0088] Referring to FIG. 13, a plurality of power amplifiers (PAs) 1382 are provided in each of the transceivers 130. The transceiver 1304 can receive RF signals from the 1304 . The present invention relates to a method and apparatus for processing a received signal, the method comprising: The transceiver 1304 transmits data and / or voice signals appropriate for the user to the transceiver 1304. a baseband subsystem 130 configured to provide conversion between an RF signal suitable for 5. The transceiver 1304 is also shown to interact with the wireless device 1300. and communicating with a power management component 1307 configured to manage power for operational purposes. Such power management may also be implemented in the baseband subsystem 1305 as well as in the module 1306. The operation of modules 1306 and 1308 may also be controlled.

[0089] The baseband subsystem 1305 receives and transmits voice and audio signals to and from the user. and / or a user interface 1301 to facilitate various inputs and outputs of data. The baseband subsystem 1305 is also shown connected to the wireless device's A memory 1 configured to facilitate operation and / or provide information storage for a user. 303. The memory 1303 is configured to store data and / or instructions. will be done.

[0090] In the example wireless device 1300, the output of the PA 1382 is The amplified and filtered signals are then matched and routed to each duplexer 1386. The filtered signals are then routed through a switching network 1309 for transmission. The duplex antenna 1360 may be routed to the secondary antenna 1360. The cascade 1386 allows a common antenna (e.g., the primary antenna 1360) to be used for transmission. In FIG. 13, the received signal is Now turning to the variable gain amplifier assembly 1310a, which provides the features and benefits of the illustrated variable gain amplifier. The DRx module 1308 is also shown as being driven by a similar variable gain amplifier assembly. Includes Bri 1310b.

[0091] In the example wireless device 1300, a signal received at a primary antenna 1360 is The signal may be transmitted to a variable gain amplifier 1310a of the front end module 1306. The amplifier 1310a includes a gain stage 1320 and a degeneration switching block 1330. The variable gain amplifier 1310a receives a plurality of signals at an input 1311. and configured to receive the processed signals at the output 1319. The gain amplifier 1310a is configured to amplify the signal based at least in part on the gain mode. and a degeneration switching block based at least in part on the gain mode. 330 to provide a target impedance. It is designed to improve signal linearity compared to variable gain amplifiers that do not incorporate one or more of the features. In at least one low gain mode, the gain stage 1320 and the degenerator The rate switching block 1330 may be bypassed. In the gain mode, the gain is adjusted as described herein via the mid-gain mode feedback module. As shown in FIG. 13, additional gain amplifiers are added in the variable gain amplifier 1310a to improve the linearity of the amplification process. Can give feedback.

[0092] The wireless device also includes a diversity antenna 1370 and a diversity antenna The diversity receiver module 1308 receives signals from the diversity receiver 1370. The city receiver module 1308 is a variable gain receiver for the front-end module 1306. The diversity receiver module includes a variable gain amplifier 1310b similar to the amplifier 1310a. The module 1308 and the variable gain amplifier 1310b process the received signal and output the processed signal as a 13. The diplexer 1302 transmits the signal to the transceiver 1304. A plexer, or other multiplexer or filter assembly, may be used as described herein. Between the diversity antenna 1370 and the diversity receiver module 1370 can be included in

[0093] One or more features of the present disclosure may be implemented in conjunction with the various cellular frequency bands described herein. Examples of such bands are given in Table 1. It will be understood that At least some of the bands may be divided into sub-bands. It is understood that implementations may be made with frequency ranges that do not have the designation as in the example of 1. The terms RF and radio frequency signals include at least the frequencies listed in Table 1. It is understood that reference is made to a signal. [Table 1]

[0094] Throughout this specification and claims, unless the context clearly indicates otherwise, The words "include", "comprise" and the like are used in an inclusive sense as opposed to an exclusive or exhaustive sense. In other words, it should be interpreted as meaning "including but not limited to." The word "coupled" as used herein means connected directly or through one or more intermediate elements. In addition, the words "here," "on," " "hereinafter" and words of similar import when used in this Application shall mean "hereinafter" and " "Application" refers to the application as a whole and not to any specific portion of the Application. Where the context permits, words in the above description of certain embodiments using the singular or plural The words "or" and "single" refer to a list of two or more items. "Or" covers all of the following interpretations of the word: Any item, all items in the list, and any combination of items in the list. do.

[0095] The above detailed description of the embodiments of the present invention is not intended to be exhaustive, i.e. to limit the invention to the above disclosure. It is not intended to be limited to the precise form, and specific embodiments of the invention and its examples are illustrative. While the above is illustrative and not restrictive, those skilled in the art will recognize that various equivalents fall within the scope of the present invention. Modifications are possible. For example, although processes or blocks may be presented in a given order, alternative implementations may be used. The embodiments may be modified to perform routines having steps in a different order or to implement systems having blocks. The system can be used, and some processes or blocks can be deleted, moved, added, or subdivided. Each of these processes or blocks may be The process or blocks may be implemented in various different ways. Although these processes or blocks may be shown as being They may be performed in parallel or at different times.

[0096] The teachings of the present invention provided herein are not necessarily limited to the above-mentioned systems, but may be applied to other systems as well. The various embodiment elements and acts described above may also be applied to the system. They can be combined to give embodiments.

[0097] Although several embodiments of the present invention have been described, these embodiments are presented by way of example only. and are not intended to limit the scope of the present disclosure. Indeed, The novel methods and systems described herein may be embodied in a variety of other forms. Various omissions, substitutions and changes in the form of the methods and systems described herein are within the scope of the present disclosure. The appended claims and their equivalents are intended to cover the scope of the present disclosure. It is intended to cover such forms or modifications as come within the scope and spirit of the present invention.

Claims

1. 1. An amplifier architecture comprising: a signal amplifier having a plurality of input nodes and an output node; a bypass block coupled between the plurality of input nodes and the one output node; a degeneration switching circuit coupled to the signal amplifier; a shutdown switch block coupled to the plurality of input nodes; Including, the signal amplifier is configured to amplify an input signal received at one of the plurality of input nodes based on a selected gain mode of a plurality of gain modes and to provide an amplified output signal at the one output node; the degeneration switching circuit includes a switch operatively coupled to a variable impedance stage for selectively isolating the variable impedance stage from a reference potential node based on the selected gain mode; the plurality of gain modes includes a low gain mode that bypasses the degeneration switching circuit by directing signals from the plurality of input nodes through the bypass block; An architecture, wherein the shutdown switch block is configured to be isolated from the multiple input nodes in the low gain mode.

2. 2. The architecture of claim 1 , wherein the variable impedance stage is configured to provide an impedance based on the selected gain mode.

3. 10. The architecture of claim 1 , wherein the variable impedance stage is further configured to provide a plurality of tailored impedances.

4. 4. The architecture of claim 3 , wherein the plurality of tailored impedances are configured to provide the amplified output signal with increased linearity over a signal amplifier not coupled to the degeneration switching circuit having the plurality of tailored impedances.

5. 4. The architecture of claim 3, wherein the variable impedance stage is configured to provide a first tailored impedance for a first gain mode of the plurality of gain modes and a second tailored impedance for a second gain mode of the plurality of gain modes.

6. the first tailored impedance is greater than the second tailored impedance; The architecture of claim 5 , wherein the second gain mode provides greater amplification than the first gain mode.

7. the signal amplifier is configured to receive a plurality of input signals at the plurality of input nodes; The architecture of claim 1 , wherein each received signal has a frequency within a different signal frequency band.

8. 8. The architecture of claim 7, wherein the signal amplifiers are configured to amplify signals received at each input port independently from amplification of other received signals.

9. 2. The architecture of claim 1 , wherein the shutdown switch block is not coupled to the one output node.

10. 2. The architecture of claim 1 , wherein the shutdown switch block is configured to selectively couple an input node of the plurality of input nodes to the reference potential node while the input node is not in use.

11. 2. The architecture of claim 1 , wherein the switches of the degeneration switching circuit include a plurality of transistors configured to selectively couple different combinations of a plurality of inductors of the variable impedance stage to the signal amplifier.

12. 12. The architecture of claim 11, wherein each of the plurality of transistors is configured to be turned off in a bypass mode of the plurality of gain modes to isolate the variable impedance stage from the reference potential node.

13. A front-end module, a packaging substrate configured to receive a plurality of components; a variable gain amplifier assembly mounted on the package substrate; a filter assembly mounted on the package substrate; A controller mounted on the package substrate; Including, The variable gain amplifier assembly includes: a signal amplifier having a plurality of input nodes and an output node; a shutdown switch block coupled to the plurality of input nodes of the signal amplifier; Including, the signal amplifier is configured to amplify an input signal received at one of the plurality of input nodes based on a selected gain mode of a plurality of gain modes and to provide an amplified output signal at the one output node; the variable gain amplifier assembly also includes a degeneration switching circuit coupled to the signal amplifier and a bypass block coupled between the plurality of input nodes and the one output node; the degeneration switching circuit includes a switch operatively coupled to a variable impedance stage for selectively isolating the variable impedance stage from a reference potential node based on the selected gain mode; the plurality of gain modes includes a low gain mode that bypasses the degeneration switching circuit by directing signals from the plurality of input nodes through the bypass block; the filter assembly is coupled to the variable gain amplifier assembly for selecting a frequency band for a selected input of the plurality of input nodes; the controller controls the variable gain amplifier assembly to provide the plurality of gain modes such that in the low gain mode, the switch of the degeneration switching circuit isolates the degeneration switching circuit from the reference potential node; The front-end module, wherein the shutdown switch block is configured to be isolated from the plurality of input nodes in the low gain mode.

14. The front-end module of claim 13 , wherein the variable impedance stage is configured to provide a plurality of tailored impedances to the signal amplifier.

15. the variable gain amplifier assembly further includes an intermediate gain mode feedback block coupled to the plurality of input nodes of the signal amplifier; The front-end module of claim 13 , wherein the intermediate gain mode feedback block is configured to provide feedback to the signal amplifier for some of the multiple gain modes.

16. 1. A wireless device, comprising: A diversity antenna, a filter assembly coupled to the diversity antenna to receive signals and to select a frequency band along a selected path; a variable gain amplifier assembly; Controller and Including, The variable gain amplifier assembly includes: a signal amplifier having a plurality of input nodes and an output node; a shutdown switch block coupled to the plurality of input nodes of the signal amplifier; Including, the signal amplifier is configured to amplify an input signal received at one of the plurality of input nodes based on a selected gain mode of a plurality of gain modes and to provide an amplified output signal at the one output node; the variable gain amplifier assembly also includes a degeneration switching circuit coupled to the signal amplifier and a bypass block coupled between the plurality of input nodes and the one output node; the degeneration switching circuit includes a switch operatively coupled to a variable impedance stage for selectively isolating the variable impedance stage from a reference potential node based on the selected gain mode; the plurality of gain modes includes a low gain mode that bypasses the degeneration switching circuit by directing signals from the plurality of input nodes through the bypass block; the controller controls the variable gain amplifier assembly to provide the plurality of gain modes such that in the low gain mode, the switch of the degeneration switching circuit isolates the degeneration switching circuit from the reference potential node; The wireless device, wherein the shutdown switch block is configured to be isolated from the plurality of input nodes in the low gain mode.

17. 17. The wireless device of claim 16, wherein the variable impedance stage is configured to provide a plurality of tailored impedances to the signal amplifier.

18. 2. The architecture of claim 1 , wherein the bypass block includes a shunt switch that selectively couples the bypass block to the reference potential node.

19. The architecture of claim 1, wherein the switch is connected in series between the variable impedance stage and the reference potential node.

20. The architecture of claim 19, wherein the variable impedance stage includes multiple inductors connected in series.

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