Field effect transistor, trench mos diode, and insulated-gate bipolar transistor

Abstract

The present application belongs to the technical field of semiconductors. On the basis of structural innovation regarding a Schottky source-drain MOSFET, provided is a field effect transistor having a high on-state current carrying capability and a low off-state electric leakage capability. Taking an n-channel normally-closed MOSFET as an example, on the basis of an existing solution in which a source electrode and an n-type semiconductor region are used to form a Schottky junction to deplete electron carriers of the n-type semiconductor region from one side of the n-type semiconductor region, a Schottky gate or a p-type gate is then introduced to deplete the electron carriers of the n-type semiconductor region from the other side of the n-type semiconductor region, thereby achieving an effect of causing depletion from both sides. In this way, in terms of electric performance, the on-state current carrying capability is maintained, off-state electric leakage is further reduced, and the present application also facilitates the adjustment over a turn-on voltage; and in terms of a manufacturing process, a critical width dimension requirement can be reduced, the requirements for photoetching and etching technology and devices can be reduced, a process window can be expanded, and the yield of batch production can be increased.

Description

Field effect transistors, trench MOS diodes and insulated gate bipolar transistors Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a field effect transistor, a trench MOS diode and an insulated gate bipolar transistor. Background Art

[0002] The Schottky source-drain MOSFET structure, first proposed in the 1960s, replaces the semiconductor-doped source and drain of traditional pn-junction MOSFETs with metal sources and drains, forming a Schottky contact barrier between the metal source and drain and the semiconductor. When a positive voltage is applied between the drain and source, the Schottky barrier formed between the source and the semiconductor material is reverse-biased, widening the depletion layer and achieving shutdown. Consequently, the Schottky source-drain MOSFET is a normally-off device. Turning on a Schottky source-drain MOSFET occurs when a positive gate bias forms a conductive channel, allowing carriers at the source to tunnel directly through the barrier and into the channel.

[0003] Since the birth of Schottky source-drain MOSFET, there have been two significant disadvantages: First, the on-state current is small. When the drain-source voltage V DS When >0, the Schottky contact barrier formed by the Schottky source electrode and the semiconductor is reverse biased to widen the depletion region, so that even if a positive gate-source voltage V is applied between the gate electrode and the Schottky source electrode GS When the gate electrode is at 100 nm, a complete and high-concentration electron conduction channel cannot be formed between the drain electrode and the Schottky source electrode. There is always a certain Schottky barrier height in the area close to the Schottky source electrode. This limited Schottky barrier height inhibits the transport of electron carriers, so that only a small number of electron carriers form current through the tunneling effect. According to the conductivity calculation formula σ = nqu (where n is the concentration of electron carriers participating in conduction, q is the amount of electron charge, and u is the mobility under certain carrier concentration conditions), the lower the carrier concentration n participating in conduction, the lower the conductivity σ. According to current density J = σE (where E represents the electric field strength), the lower the conductivity σ, the lower the current density J. This is why the on-state current of a Schottky source-drain MOSFET is smaller than the on-state current of a pn junction MOSFET under the same conditions. The on-state current of a conventional pn junction MOSFET can reach tens to hundreds of amperes, while the on-state current of a Schottky source-drain MOSFET under the same conditions can only reach milliamperes or even lower. Second, the off-state leakage is large, and the leakage current includes the thermal electron emission current from the source junction transmitted through the substrate and the tunneling current from the source junction.

[0004] In the patent application number 202310325051.0, the applicant adjusts the pure Schottky source in the Schottky source-drain MOSFET to a combination of an ohmic source and a Schottky source, wherein the ohmic source is located between the gate insulating film and the Schottky source. Through the design improvement of this structural detail, the problem of low on-state current of the Schottky source-drain MOSFET is completely solved, and its on-state current capacity is comparable to that of the pn junction MOSFET under the same conditions. At the same time, in the equilibrium state (when V DS =0&V GS = 0), the normally-off function can be realized by utilizing the local depletion effect of electron carriers on the Schottky junction formed by the Schottky source and the n-type semiconductor layer.

[0005] However, in equilibrium (when V DS =0&V GS =0), the normally-off effect is achieved only by relying on the unilateral depletion effect of electron carriers in the n-type semiconductor layer between the Schottky source and the gate insulating film layer caused by the Schottky junction formed by the Schottky source and the n-type semiconductor layer. Therefore, the width of the n-type semiconductor layer between the gate insulating film and the Schottky source and the ohmic source in contact with it need to be as small as possible. Taking silicon semiconductor materials as an example, the width of the ohmic source needs to be ≤100nm to ensure a good normally-off effect. This places extremely high demands on the wafer manufacturing process, especially the lithography and etching technology and equipment. The process window is narrow and the fault tolerance is small. It is easy to exceed the width size and cause large off-state leakage of the device. Summary of the Invention

[0006] In view of this, the present invention introduces a metal material or a p-type gate electrode material that can form a Schottky barrier with the semiconductor layer into the gate electrode, so that the gate electrode has a depletion effect on the electron carriers in the semiconductor layer, thereby achieving a double-sided pinch-off effect. This can relax the precision control of the critical width dimension, reduce the requirements for lithography and etching technology and equipment, and solve the problem of large off-state leakage of the device due to the narrow process window, which easily causes the width dimension to exceed the limit.

[0007] In order to solve the above technical problems, the present invention provides a field effect transistor having:

[0008] a semiconductor layer of a first conductivity type;

[0009] Electrodes, including a drain electrode, a source electrode, and a gate electrode;

[0010] a gate insulating film interposed between the gate electrode and the first conductivity type semiconductor layer;

[0011] A Schottky barrier exists between the first portion of the source electrode and the first conductive type semiconductor layer, and the first portion of the source electrode is not in contact with the gate insulating film; and the second portion of the source electrode forms an ohmic contact with the first conductive type semiconductor layer.

[0012] The gate electrode at least includes a metal material having a Schottky barrier with the semiconductor layer of the first conductive type, and the metal material is in contact with the gate insulating film; or the gate electrode at least includes an electrode material of the second conductive type, and the electrode material of the second conductive type is in contact with the gate insulating film, wherein the conductivity types of the second conductive type and the first conductive type are different.

[0013] Preferably, the first conductivity type semiconductor layer is an n-type semiconductor layer.

[0014] Preferably, the width of the first portion of the source electrode from the gate insulating film ranges from 3 nm to 400 nm.

[0015] Furthermore, the width between the first portion of the source electrode and the gate insulating film is in a range of 3 nm to 200 nm.

[0016] Preferably, when the first conductive type semiconductor layer is an n-type semiconductor layer, the work function of the metal material is greater than the work function of a corresponding material of the first conductive type semiconductor layer.

[0017] Furthermore, the metal material is Pt, Ni, Co, or Au.

[0018] Preferably, when the first conductive type semiconductor layer is an n-type semiconductor layer, the second conductive type electrode material is p-type conductive polysilicon.

[0019] Preferably, the drain electrode is formed on the first main surface of the first conductivity type semiconductor layer, and the source electrode is located on the second main surface side of the first conductivity type semiconductor layer.

[0020] Furthermore, the field effect transistor is a vertical MOSFET.

[0021] Furthermore, the vertical MOSFET is a planar gate MOSFET, a trench gate MOSFET, a shielded gate MOSFET, or a super junction MOSFET.

[0022] Preferably, the material of the semiconductor layer is silicon, silicon carbide, gallium nitride, gallium oxide, or tin oxide.

[0023] The present invention also provides a field effect transistor having:

[0024] a first semiconductor layer comprising an n-type semiconductor region;

[0025] a second semiconductor layer comprising an n-type semiconductor region and a high-resistance semiconductor region;

[0026] Electrodes, including a drain electrode, a source electrode, and a gate electrode;

[0027] a gate insulating film, which is interposed between the gate electrode and the semiconductor layer;

[0028] the drain electrode being formed on a surface of the first semiconductor layer opposite to the second semiconductor layer;

[0029] The source electrode is formed on a surface of the second semiconductor layer opposite to the first semiconductor layer, a Schottky barrier exists between a portion of the source electrode and the n-type semiconductor region of the second semiconductor layer, a first portion of the source electrode is not in contact with the gate insulating film, and a second portion of the source electrode is in ohmic contact with the n-type semiconductor region of the second semiconductor layer;

[0030] The high-resistance semiconductor region of the second semiconductor layer is provided in a region close to a surface layer of the second semiconductor layer and is formed between the gate insulating film and the first portion of the source electrode;

[0031] The gate electrode at least includes a metal material having a Schottky barrier with the second semiconductor layer, and the metal material is in contact with the gate insulating film; or the gate electrode uses a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film.

[0032] Preferably, the first portion of the source electrode contacts the n-type semiconductor region of the second semiconductor layer to form a Schottky barrier contact.

[0033] Preferably, the work function of the metal material is greater than the work function of the corresponding material of the semiconductor layer.

[0034] Preferably, the p-type conductive electrode material is p-type conductive polysilicon.

[0035] Preferably, the material of the semiconductor layer is gallium oxide, and the material of the high-resistance semiconductor region is nitrogen (N)-doped gallium oxide.

[0036] In view of the above invention contents, the present invention has the following beneficial effects:

[0037] The present invention introduces a metal material that can generate a Schottky barrier between the gate electrode and the semiconductor layer or a semiconductor material that can deplete the carriers in the semiconductor layer into the gate electrode. Taking the n-channel enhancement MOSFET as an example, on the basis of the original use of the source electrode and the n-type semiconductor region to form a Schottky junction to deplete the electron carriers of the n-type semiconductor region from one side, a Schottky gate or a p-type gate is introduced to deplete the electron carriers of the n-type semiconductor region from the other side, thereby achieving the effect of double-sided depletion. In this way, from the perspective of electrical performance, the on-state current capacity is maintained and the off-state leakage is further reduced, which is also conducive to the regulation of the turn-on voltage. From the perspective of process technology, the key width dimension requirements can be relaxed, the requirements for photolithography and etching technology and equipment can be reduced, the process window can be expanded, and the yield of mass production can be improved.

[0038] The present invention further provides a trench MOS diode having:

[0039] An n-type semiconductor layer has a first main surface on one side and a second main surface on the other side opposite thereto, and has a trench, the trench opening inward from the first main surface of the n-type semiconductor layer;

[0040] a cathode electrode formed on the second main surface of the n-type semiconductor layer;

[0041] an anode electrode formed on the first main surface of the n-type semiconductor layer;

[0042] a trench MOS gate, buried in the trench and wrapped by the gate insulating film, separated from the n-type semiconductor layer by the gate insulating film, and in contact with the anode electrode;

[0043] The first portion of the anode electrode forms a Schottky contact with the first main surface of the n-type semiconductor layer, and the second portion of the anode electrode forms an ohmic contact with the first main surface of the n-type semiconductor layer;

[0044] The trench MOS gate at least includes a metal material with a Schottky barrier between it and the n-type semiconductor layer, and the metal material is in contact with the gate insulating film; or the trench MOS gate at least includes a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film.

[0045] The width of the first portion of the anode electrode from the gate insulating film is in the range of 3 nm to 400 nm.

[0046] Preferably, the width of the first portion of the anode electrode from the gate insulating film is in the range of 3 nm to 200 nm.

[0047] The trench MOS diode of the present invention has the following beneficial effects:

[0048] Compared with the traditional trench MOS Schottky diode, the trench MOS diode of the present invention can further reduce the turn-on voltage and conduction loss when forward conducting; and can reduce the off-state leakage when reverse blocking.

[0049] The present invention also provides an insulated gate bipolar transistor having:

[0050] p-type semiconductor layer;

[0051] an n-type semiconductor layer stacked on the p-type semiconductor layer;

[0052] an electrode including a collector electrode, an emitter electrode, and a gate electrode, wherein the collector electrode is formed on a surface of the p-type semiconductor layer opposite to the n-type semiconductor layer;

[0053] a gate insulating film, which is interposed between the gate electrode and the n-type semiconductor layer;

[0054] There is a Schottky barrier between the first portion of the emitter and the n-type semiconductor layer, the first portion of the emitter is not in contact with the gate insulating film, and the second portion of the emitter forms an ohmic contact with the n-type semiconductor layer;

[0055] The gate electrode at least includes a metal material having a Schottky barrier with the n-type semiconductor layer, and the metal material is in contact with the gate insulating film; or the gate electrode is made of a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film.

[0056] Preferably, the first portion of the emitter contacts the n-type semiconductor layer to form a Schottky barrier contact.

[0057] Preferably, the width of the first portion of the emitter from the gate insulating film ranges from 3 nm to 400 nm.

[0058] Furthermore, the width between the first portion of the emitter and the gate insulating film is in a range of 3 nm to 200 nm.

[0059] Preferably, the metal material is Pt, Ni, Au, or Co.

[0060] Preferably, the p-type conductive electrode material is p-type conductive polysilicon.

[0061] The insulated gate bipolar transistor of the present invention introduces a metal material capable of generating a Schottky barrier with the semiconductor layer or a p-type conductive electrode material capable of depleting electron carriers in the semiconductor layer into the gate electrode. The introduction of the Schottky gate or the p-type gate depletes electron carriers in the n-type semiconductor region. This can further reduce off-state leakage in terms of electrical performance; and can also expand the process window and improve the yield rate of mass production in terms of process technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solution of the present invention, the following will briefly introduce the embodiments or the drawings required in the description of the prior art. Obviously, some of the drawings described below are only illustrations of some embodiments of the present invention, and the scope of protection claimed by the present invention is not limited to the embodiments. For those skilled in the art, without making any creative efforts, they can also obtain other embodiments based on these drawings.

[0063] His attached pictures.

[0064] FIG1 is a vertical cross-sectional view of an embodiment of a conventional Schottky junction trench gate MOSFET.

[0065] FIG2 is a vertical cross-sectional view of an embodiment of a trench gate MOSFET applied for by the present applicant in patent application number 202310325051.0.

[0066] FIG. 3 a is a vertical cross-sectional view of a first example of a trench gate MOSFET according to an embodiment of the present invention.

[0067] FIG3 b is a vertical cross-sectional view of a second example of a trench gate MOSFET according to an embodiment of the present invention.

[0068] FIG3 c is a vertical cross-sectional view of a third example of a trench gate MOSFET according to an embodiment of the present invention.

[0069] FIG. 4 a is a vertical cross-sectional view of a first example of a planar gate MOSFET according to an embodiment of the present invention.

[0070] FIG4 b is a vertical cross-sectional view of a second example of a planar gate MOSFET according to an embodiment of the present invention.

[0071] FIG. 5 a is a vertical cross-sectional view of a first example of a shielded gate MOSFET according to an embodiment of the present invention.

[0072] FIG5 b is a vertical cross-sectional view of a second example of a shielded gate MOSFET according to an embodiment of the present invention.

[0073] FIG. 5 c is a vertical cross-sectional view of a third example of a shielded gate MOSFET according to an embodiment of the present invention.

[0074] FIG5 d is a vertical cross-sectional view of a fourth example of a shielded gate MOSFET according to an embodiment of the present invention.

[0075] FIG. 5 e is a vertical cross-sectional view of a fifth example of a shielded gate MOSFET according to an embodiment of the present invention.

[0076] FIG5 f is a vertical cross-sectional view of a sixth example of a shielded gate MOSFET according to an embodiment of the present invention.

[0077] FIG5g is a vertical cross-sectional view of a seventh example of a shielded gate MOSFET according to an embodiment of the present invention.

[0078] FIG. 6 a is a vertical cross-sectional view of a first example of a super junction MOSFET according to an embodiment of the present invention.

[0079] FIG6 b is a vertical cross-sectional view of a second example of a super junction MOSFET according to an embodiment of the present invention.

[0080] FIG7 a is a vertical cross-sectional view of a first example of a trench MOS diode according to an embodiment of the present invention.

[0081] FIG7 b is a vertical cross-sectional view of a second example of a trench MOS diode according to an embodiment of the present invention.

[0082] FIG8 a is a vertical cross-sectional view of a first example of an insulated gate bipolar transistor according to an embodiment of the present invention.

[0083] 8 b is a vertical cross-sectional view of a second example of an insulated gate bipolar transistor according to an embodiment of the present invention.

[0084] The technical features corresponding to the marks in the accompanying drawings are:

[0085] 11 Drain electrode (collector)

[0086] 12 Source electrode (emitter)

[0087] 12a Ohmic source electrode (ohmic emitter)

[0088] 12b Schottky source electrode (Schottky emitter)

[0089] 12c Shield source electrode

[0090] 12d p-type polysilicon

[0091] 13 Gate electrode

[0092] 13a n-type gate electrode

[0093] 13b p-type gate electrode

[0094] 13c Schottky gate electrode

[0095] 21 Semiconductor District

[0096] 21a n+ type semiconductor

[0097] 21b n-type semiconductor

[0098] 21c n+ type semiconductor

[0099] 211 First main surface

[0100] 212 Second main surface

[0101] 31a p+ type semiconductor

[0102] 31b p-type semiconductor

[0103] 41 High-resistance semiconductor

[0104] 51a Gate insulating film

[0105] 51b non-gate insulating film

[0106] 61 cathode electrode

[0107] 62 anode electrode

[0108] 62a Ohm anode

[0109] 62b Schottky anode

[0110] 63 Trench MOS Gate

[0111] 63a n-type gate

[0112] 63b p-type gate

[0113] 63c Schottky gate DETAILED DESCRIPTION

[0114] In the following description, for the purpose of illustration and not limitation, specific system structures, technologies,

[0115] Such specific details are omitted to provide a thorough understanding of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

[0116] FIG1 is a vertical cross-sectional view of an embodiment of a conventional Schottky junction trench gate MOSFET. This Schottky junction trench gate MOSFET comprises: a drain electrode 11, an n+ type semiconductor 21a, an n- type semiconductor 21b, a trench located in the n- type semiconductor 21b, a gate electrode 13 located in the trench and surrounded by a gate insulating film 51a, a Schottky source electrode 12b forming a Schottky barrier contact with the n- type semiconductor 21b, and a source electrode 12 located thereon.

[0117] The Schottky junction trench gate MOSFET shown in FIG1 , due to the presence of the Schottky junction formed between the Schottky source electrode 12 b and the n-type semiconductor layer 21 b , when only a forward voltage is applied between the drain electrode 11 and the source electrode 12 , the Schottky junction is reverse biased, causing the depletion region to widen. As a result, a complete electron conduction channel is not formed between the drain electrode 11 and the source electrode 12 , and no current flows between the drain and the source. Based on this principle, the Schottky junction trench gate MOSFET shown in FIG1 is a normally-off device.

[0118] When a positive voltage is applied between the gate electrode 13 and the source electrode 12, due to the presence of the Schottky barrier between the Schottky source electrode 12b and the n-type semiconductor 21b, a complete and high-concentration electron conduction channel cannot be formed between the drain electrode 11 and the Schottky source electrode 12b. At this time, even when a positive voltage is applied between the drain electrode 11 and the source electrode 12, the reverse-biased depletion layer of the Schottky barrier formed between the Schottky source electrode 12b and the n-type semiconductor 21b is widened, which inhibits the transport of electron carriers. As a result, only a small number of electron carriers between the drain and the source form current through the tunneling effect, resulting in poor on-state current conduction capability of existing Schottky junction trench gate MOSFETs. Their on-state current is much smaller than that of pn junction MOSFETs under the same conditions. As a result, Schottky junction trench gate MOSFETs have not yet been commercialized.

[0119] FIG2 is a vertical cross-sectional view of an embodiment of a trench-gate MOSFET applied for by the present applicant in patent application number 202310325051.0. The trench-gate MOSFET in this embodiment is based on the Schottky junction trench-gate MOSFET shown in FIG1 , except that the Schottky source electrode 12b, which contacts the n-type semiconductor 21b, is modified to an ohmic source electrode 12a and a Schottky source electrode 12b. In FIG2 , the ohmic source electrode 12a forms an ohmic contact with the n-type semiconductor 21b, while the Schottky source electrode 12b forms a Schottky contact with the n-type semiconductor 21b.

[0120] In the MOSFET shown in FIG. 2 , when the voltage V between the drain electrode 11 and the source electrode 12 DS=0 and the voltage V between the gate electrode 13 and the source electrode 12 GS = 0, since the Schottky junction formed by the contact between the Schottky source electrode 12b and the n-type semiconductor 21b will deplete the electron carriers in the n-type semiconductor 21b located between the gate insulating film 51a and the Schottky source electrode 12b, when the width of the n-type semiconductor 21b located between the gate insulating film 51a and the Schottky source electrode 12b is in the range of 3nm to 250nm, the MOSFET shown in FIG2 can achieve the normally-off function; when the voltage V between the drain electrode 11 and the source electrode 12 DS >0 and the voltage V between the gate electrode 13 and the source electrode 12 GS = 0, the depletion region continues to widen due to the reverse bias of the Schottky junction formed by the Schottky source electrode 12b and the n-type semiconductor 21b in contact therewith. At this time, the MOSFET is in the off state; when the voltage V between the drain electrode 11 and the source electrode 12 DS >0, and a voltage V is applied between the gate electrode 13 and the source electrode 12 GS >0, as V GS > increases, reaching the turn-on voltage V GS（th） When the turn-on voltage V GS（th） Due to the effect of the gate insulating film 51a, a high-concentration electron conduction channel is formed in the region of the n-type semiconductor 21b adjacent to the gate insulating film 51a. At this time, current flows between the drain electrode 11 and the source electrode 12, and the device is turned on. In this way, the MOSFET shown in FIG. 2 can be designed as a normally-off device with a large current-carrying capacity.

[0121] FIG3a is a vertical cross-sectional view of a first embodiment of a trench gate MOSFET according to an embodiment of the present invention. This MOSFET includes: a drain electrode 11, an n+ type semiconductor 21a stacked on the drain electrode 11, an n- type semiconductor 21b stacked on the n+ type semiconductor 21a (the n+ type semiconductor 21a and the n- type semiconductor 21b are both semiconductor layers of the first conductivity type), a trench located in the n- type semiconductor 21b, a gate electrode 13 located in the trench and surrounded by a gate insulating film 51a, a semiconductor region 21 located between the gate insulating film 51a and the Schottky source electrode 12b (the semiconductor region 21 may be an n- type semiconductor). conductor 21b, which may also be a high-resistance semiconductor 41), a Schottky source electrode 12b forming a Schottky barrier contact with the n-type semiconductor 21b, an ohmic source electrode 12a forming an ohmic contact with the semiconductor region 21, and a source electrode 12 located thereon; wherein the gate electrode 13 includes a Schottky gate electrode 13c and an n-type gate electrode 13a, and the n-type gate electrode 13a may be phosphorus-doped n-type conductive polysilicon; the Schottky gate electrode 13c is in contact with the gate insulating film 51a, and the Schottky gate electrode 13c is composed of a metal material.

[0122] In the MOSFET shown in FIG3a , a Schottky gate electrode 13c with a Schottky barrier between the gate electrode 13 and the semiconductor region 21 is introduced. The MIS (metal insulator semiconductor) junction formed by the Schottky gate electrode 13c, the gate insulating film 51a, and the semiconductor region 21 will deplete the electron carriers in the semiconductor region 21 between the gate insulating film 51a and the Schottky source electrode 12b. In addition, the Schottky junction formed by the Schottky source electrode 12b and the semiconductor region 21 will also deplete the electron carriers in the semiconductor region 21 between the gate insulating film 51a and the Schottky source electrode 12b. When the width of the Schottky source electrode 12b from the gate insulating film 51a ranges from 3nm to 250nm, under the combined action of these two depletion effects, , completely depleting the electron carriers in the semiconductor 21 located between the gate insulating film 51a and the Schottky source electrode 12b, thereby blocking the electron conduction channel between the drain electrode 11 and the source electrode 12. Therefore, the MOSFET shown in FIG3a can be normally off, and compared with the MOSFET shown in FIG2, when the width of the semiconductor region 21 is the same, the MOSFET shown in FIG3a has lower off-state leakage in terms of electrical performance; from the process technology, to produce a normally-off MOSFET, in FIG3a, the width of the semiconductor region 21 located between the gate insulating film 51a and the Schottky source electrode 12b can be relatively wider than that designed in FIG2, thereby reducing the requirements for photolithography & etching technology and equipment, expanding the process window, and improving the yield of mass production.

[0123] FIG3 b is a vertical cross-sectional view of a second embodiment of a trench gate MOSFET according to an embodiment of the present invention. The difference between the MOSFET in this embodiment and the MOSFET shown in FIG3 a is that the gate electrode 13 in this embodiment comprises a P-type conductive electrode material (electrode material of the second conductive type), that is, the gate electrode 13 comprises a p-type gate electrode 13 b, which can be boron-doped p-type conductive polysilicon. The p-type gate electrode 13 b also depletes the electron carriers in the semiconductor region 21. In addition, the Schottky junction formed by the Schottky source electrode 12 b and the semiconductor region 21 also depletes the electron carriers in the semiconductor region 21 between the gate insulating film 51 a and the Schottky source electrode 12 b. When the width of the Schottky source electrode 12 b from the gate insulating film 51 a is in the range of 3 nm to 250 nm, the gate electrode 13 b is depleted. In the nm range, under the combined action of these two depletion effects, the electron carriers in the semiconductor 21 located between the gate insulating film 51a and the Schottky source electrode 12b are completely depleted, thereby blocking the electron conduction channel between the drain electrode 11 and the source electrode 12. Therefore, the MOSFET shown in FIG3b can be normally off, and compared with the MOSFET shown in FIG2, when the width of the semiconductor region 21 is the same, the MOSFET shown in FIG3a has lower off-state leakage in terms of electrical performance; from the process technology, to produce a normally-off MOSFET, in FIG3b, the width of the semiconductor 21 located between the gate insulating film 51a and the Schottky source electrode 12b can be relatively wider than the design in FIG2, thereby reducing the requirements for photolithography & etching technology and equipment, expanding the process window, and improving the yield of mass production.

[0124] FIG3c is a vertical cross-sectional view of a third embodiment of a trench-gate MOSFET according to an embodiment of the present invention. The MOSFET shown in FIG3c builds upon the MOSFET structure shown in FIG3a, with the addition of an n+-type semiconductor 21c between semiconductor region 21 and ohmic source electrode 12a. This design enhances the ohmic contact effect and reduces the contact resistance between ohmic source electrode 12a and the semiconductor.

[0125] FIG4a is a vertical cross-sectional view of a first example of a planar gate MOSFET according to an embodiment of the present invention. This MOSFET includes a drain electrode 11, an n+-type semiconductor 21a, an n-type semiconductor 21b, and a semiconductor region 21; a Schottky source electrode 12b; an ohmic source electrode 12a and a source electrode 12 thereon; a gate insulating film 51a and a gate electrode 13 thereon; the gate electrode 13 includes a Schottky gate electrode 13c, which is formed of a metal material.

[0126] Figure 4b is a vertical cross-sectional view of a second embodiment of a planar gate MOSFET according to an embodiment of the present invention. The difference between the MOSFET in this embodiment and the MOSFET shown in Figure 4a is that the gate electrode 13 in this embodiment includes a P-type conductive electrode material, that is, the gate electrode 13 includes a p-type gate electrode 13b, and the p-type gate electrode 13b can be boron-doped p-type conductive polysilicon.

[0127] Similarly, for the MOSFETs shown in FIG4a and FIG4b, the gate electrode 13 and the Schottky source electrode 12b jointly deplete electron carriers in the semiconductor region 21, thereby forming a normally-off device with large on-state current capability and low off-state leakage.

[0128] FIG5a is a vertical cross-sectional view of a first embodiment of a shielded gate MOSFET according to an embodiment of the present invention. The MOSFET shown in FIG5a has a top-and-bottom gate structure and comprises: a drain electrode 11, an n+-type semiconductor 21a, an n-type semiconductor 21b, a semiconductor region 21 (the semiconductor region 21 can be either an n-type semiconductor 21b or a high-resistance semiconductor 41), a trench within the n-type semiconductor 21b, a gate electrode 13 and a shield source electrode 12c within the trench and surrounded by a gate insulating film 51a, a Schottky source electrode 12b forming a Schottky barrier contact with the n-type semiconductor 21b, an ohmic source electrode 12a forming an ohmic contact with the semiconductor region 21, and a source electrode 12 located thereon. The gate electrode 13 includes a Schottky gate electrode 13c and an n-type gate electrode 13a. The n-type gate electrode 13a can be phosphorus-doped n-type conductive polysilicon; the Schottky gate electrode 13c is composed of a metal material.

[0129] FIG5 b is a vertical cross-sectional view of a second embodiment of a shielded gate MOSFET according to an embodiment of the present invention. The MOSFET in this embodiment differs from the MOSFET shown in FIG5 a in that, in this embodiment, gate electrode 13 comprises a p-type conductive electrode material, i.e., gate electrode 13 comprises a p-type gate electrode 13 b, which may be boron-doped p-type conductive polysilicon.

[0130] FIG5c is a vertical cross-sectional view of a third embodiment of a shielded gate MOSFET according to an embodiment of the present invention. The MOSFET shown in FIG5c is a shielded gate MOSFET with a left-right split-gate structure. This is based on the shielded gate MOSFET with a top-bottom gate structure shown in FIG5a, with the structure of the shield gate region modified.

[0131] FIG5 d is a vertical cross-sectional view of a fourth embodiment of a shielded gate MOSFET according to an embodiment of the present invention. The MOSFET in this embodiment is a shielded gate MOSFET with a left-right split-gate structure. It differs from the shielded gate MOSFET with a left-right split-gate structure shown in FIG5 c in that, in this embodiment, gate electrode 13 comprises a p-type conductive electrode material, i.e., gate electrode 13 comprises a p-type gate electrode 13 b, which can be boron-doped p-type conductive polysilicon.

[0132] FIG5e is a vertical cross-sectional view of a fifth embodiment of a shielded gate MOSFET according to an embodiment of the present invention. The MOSFET shown in FIG5e is another shielded gate MOSFET with a left-right split-gate structure. This MOSFET is based on the shielded gate MOSFET with a left-right split-gate structure shown in FIG5c , but with structural adjustments made to the shield gate region.

[0133] FIG5 f is a vertical cross-sectional view of a sixth embodiment of a shielded gate MOSFET according to an embodiment of the present invention. The MOSFET shown in FIG5 e is another shielded gate MOSFET with a left-right split-gate structure. The MOSFET in this embodiment differs from the MOSFET shown in FIG5 e in that gate electrode 13 in this embodiment comprises a p-type conductive electrode material, i.e., gate electrode 13 comprises a p-type gate electrode 13 b, which can be boron-doped p-type conductive polysilicon.

[0134] FIG5g is a vertical cross-sectional view of a seventh example of a shielded gate MOSFET according to an embodiment of the present invention. The MOSFET shown in FIG5g comprises: a drain electrode 11, an n+-type semiconductor 21a in contact with the drain electrode 11, an n-type semiconductor 21b, a semiconductor region 21 (the semiconductor region 21 may be an n-type semiconductor 21b or a high-resistance semiconductor 41), an n+-type semiconductor 21c located on the semiconductor region 21, and a trench located in the n-type semiconductor 21b, a gate electrode 13 and a shielding source electrode 12c located in the trench and wrapped by a gate insulating film 51a, a Schottky source electrode 12b forming a Schottky barrier contact with the n-type semiconductor 21b, an ohmic source electrode 12a located thereon forming an ohmic contact with the n+-type semiconductor 21c, and a source electrode 12 located thereon; wherein the gate electrode 13 comprises a Schottky gate electrode 13c and an n-type gate electrode 13a, the n-type gate electrode may be phosphorus-doped n-type conductive polysilicon, and the Schottky gate electrode 13c is composed of a metal material.

[0135] The MOSFET shown in FIG5g is based on the MOSFET shown in FIG5a, with the structural design of the source electrode region adjusted so that the ohmic source electrode 12a is not in contact with the gate insulating film 51a. This structural design can also achieve the function of reducing off-state leakage.

[0136] For the shielded gate MOSFET shown in Figures 5a to 5g, regardless of whether the gate electrode 13 is a Schottky gate electrode 13c or a p-type gate electrode 13b, the gate electrode 13 and the Schottky source electrode 12b can jointly deplete the electron carriers in the semiconductor region 21 (the semiconductor region 21 can be an n-type semiconductor 21b or a high-resistance semiconductor 41) to achieve a better normally-off effect and smaller off-state leakage; in addition, the requirements for key dimensions in the process technology, such as the width of the semiconductor region 21, can be relaxed, the process window can be expanded, and the process yield can be improved.

[0137] For the shielded gate MOSFET shown in Figures 5a to 5g, when the work function of the metal material used for the Schottky source electrode 12b and the Schottky gate electrode 13c is higher, the width of the semiconductor region 21 is relatively wider while maintaining the normally-off function. For example, metal materials with high work function such as Pt, Ni, Au, Co, Cu, and Fe can be used.

[0138] FIG6 a is a vertical cross-sectional view of a first embodiment of a superjunction MOSFET according to an embodiment of the present invention. The superjunction MOSFET shown in FIG6 a comprises: a drain electrode 11, an n+-type semiconductor 21a, an n-type semiconductor 21b, a semiconductor region 21 (the semiconductor region 21 may be either an n-type semiconductor 21b or a high-resistance semiconductor 41), a deep trench in the n-type semiconductor 21b, p-type polysilicon 12d in the deep trench, a Schottky source electrode 12b, an ohmic source electrode 12a, and a source electrode 12; a gate insulating film 51a and a Schottky gate electrode 13c thereon; the Schottky gate electrode 13c being composed of a metal material.

[0139] FIG6 b is a vertical cross-sectional view of a second embodiment of a superjunction MOSFET according to an embodiment of the present invention. This embodiment differs from the superjunction MOSFET shown in FIG6 a in that the gate electrode 13 in this embodiment comprises a p-type conductive electrode material, i.e., the gate electrode 13 comprises a p-type gate electrode 13 b.

[0140] For the superjunction MOSFET shown in Figures 6a and 6b, regardless of whether a Schottky gate electrode 13c or a p-type gate electrode 13b is used, the gate electrode 13 and the Schottky source electrode 12b can jointly deplete the electron carriers in the semiconductor region 21 (the semiconductor region 21 can be an n-type semiconductor 21b or a high-resistance semiconductor 41) to achieve a better normally-off effect and smaller off-state leakage; in addition, the requirements for key dimensions in the process technology, such as the width of the semiconductor region 21, can be relaxed, the process window can be expanded, and the process yield can be improved.

[0141] FIG7 a is a vertical cross-sectional view of a first embodiment of a trench MOS diode according to an embodiment of the present invention. The trench MOS diode comprises a cathode electrode 61, an n-type semiconductor layer (including an n+-type semiconductor 21a and an n--type semiconductor 21b), a semiconductor region 21 (the semiconductor region 21 may be an n-type semiconductor or a high-resistance semiconductor), a trench in the n-type semiconductor 21b, a trench MOS gate 63 located in the trench and surrounded by a gate insulating film 51a, a Schottky anode 62b forming a Schottky barrier contact with the n-type semiconductor 21b, an ohmic anode 62a forming an ohmic contact with the semiconductor region 21, and an anode electrode 62 located thereon, with the trench MOS gate 63 electrically connected to the anode electrode 62. The trench MOS gate 63 of the n-type semiconductor 21b includes an n-type gate 63a and a Schottky gate 63c. The n-type gate 63a may be polycrystalline silicon with n-type conductivity. The Schottky gate 63c contacts the gate insulating film 51a and is composed of a metal material. In this embodiment, the n-type semiconductor layer has a first main surface 211 on one side and a second main surface 212 on the other side opposite thereto. The trench opens inward from the first main surface 211 of the n-type semiconductor layer.

[0142] In the trench MOS diode shown in FIG7a , when a positive voltage is applied between anode electrode 62 and cathode electrode 61, current flows between anode electrode 62 and cathode electrode 61, causing the diode to conduct forward. The current has two paths: the first path follows anode electrode 62, ohmic anode 62a, semiconductor region 21, n-type semiconductor 21b, n+-type semiconductor 21a, and cathode electrode 61; the second path follows anode electrode 62, Schottky anode 62b, n-type semiconductor 21b, n+-type semiconductor 21a, and cathode electrode 61. In the first current path, there is no contact barrier between ohmic anode 62a and semiconductor region 21; in the second current path, a Schottky barrier exists between Schottky anode 62b and n-type semiconductor 21b. When the diode conducts forward, the first current path presents less resistance and requires a lower threshold voltage than the second current path, so current flows preferentially along the first path. Compared with the traditional trench MOS Schottky diode, it is obvious that the trench MOS diode based on the present invention has lower turn-on voltage and conduction loss.

[0143] In the trench MOS diode shown in FIG7a , when a reverse voltage is applied between the anode electrode 62 and the cathode electrode 61, two types of electron carrier depletion effects occur: the first is the reverse-biased widening of the Schottky barrier formed by the Schottky anode 62b, the n-type semiconductor 21b, and the semiconductor region 21, which produces a longitudinal depletion effect on the electron carriers in the n-type semiconductor 21b and a lateral depletion effect on the electron carriers in the semiconductor region 21. The second is the lateral depletion effect of the trench MOS gate 63 on the electron carriers in the semiconductor region 21. Due to the combined effects of these two types of depletion effects, only a small leakage current flows between the cathode electrode 61 and the anode electrode 62, and the diode is reverse-biased.

[0144] FIG7b is a vertical cross-sectional view of a second embodiment of a trench MOS diode according to an embodiment of the present invention. The trench MOS diode in this embodiment differs from the trench MOS diode shown in FIG7a in that the trench MOS gate 63 in this embodiment comprises a p-type conductive electrode material, i.e., the trench MOS gate 63 comprises a p-type gate 63b. During forward conduction, two current paths exist, resulting in a lower turn-on voltage and conduction loss compared to conventional trench MOS Schottky diodes.

[0145] FIG8a is a vertical cross-sectional view of a first embodiment of an insulated gate bipolar transistor according to an embodiment of the present invention. The transistor comprises: a collector 11, a p+-type semiconductor 31a, an n+-type semiconductor 21a, an n-type semiconductor 21b, a semiconductor region 21 (the semiconductor region 21 may be either an n-type semiconductor 21b or a high-resistance semiconductor 41), a trench in the n-type semiconductor 21b, a gate electrode 13 in the trench and surrounded by a gate insulating film, a Schottky emitter 12b forming a Schottky barrier contact with the n-type semiconductor 21b, an ohmic emitter 12a forming an ohmic contact with the n-type semiconductor 21b, and an emitter 12 located thereon. The gate electrode 13 includes a Schottky gate electrode 13c and an n-type gate electrode 13a, and the Schottky gate electrode 13c is made of a metal material.

[0146] In the insulated gate bipolar transistor shown in FIG8a, a Schottky gate electrode 13c with a Schottky barrier between the gate electrode 13 and the semiconductor region 21 is introduced. The MIS (metal insulator semiconductor) junction formed by the Schottky gate electrode 13c, the gate insulating film 51a and the semiconductor region 21 will deplete the electron carriers in the semiconductor 21 located between the gate insulating film 51a and the Schottky emitter 12b. In addition, the Schottky junction formed by the Schottky emitter 12b and the semiconductor region 21 will also deplete the electron carriers located between the gate insulating film 51a and the Schottky emitter 12b. The electron carriers in the semiconductor region 21 between the Schottky source electrode 12b produce a depletion effect. When the width of the Schottky emitter 12b from the gate insulating film 51a is in the range of 3nm to 250nm, under the combined action of these two depletion effects, the electron carriers in the semiconductor region 21 between the gate insulating film 51a and the Schottky emitter 12b are completely depleted, thereby blocking the electron carrier conduction channel between the collector 11 and the emitter 12. Such a design through the combined action of the two depletion effects can reduce the off-state leakage of the device.

[0147] 8 b is a vertical cross-sectional view of a second example of an insulated gate bipolar transistor according to an embodiment of the present invention. The difference between the insulated gate bipolar transistor in this embodiment and the insulated gate bipolar transistor shown in FIG8a is that in this embodiment, the gate electrode 13 comprises a p-type conductive electrode material, that is, the electrode 13 includes a p-type gate electrode 13b, which can be boron-doped p-type conductive polycrystalline silicon. The p-type gate electrode 13b also depletes electron carriers in the semiconductor region 21. In addition, the Schottky junction formed by the Schottky emitter 12b and the semiconductor region 21 also depletes electron carriers in the semiconductor region 21 located between the gate insulating film 51a and the Schottky emitter 12b. When the width of the Schottky emitter 12b from the gate insulating film 51a ranges from 3nm to 250nm, the combined action of these two depletion effects completely depletes the carriers in the semiconductor region 21, thereby blocking the electron carrier conduction channel between the collector 11 and the emitter 12. This design, through the combined action of these two depletion effects, can reduce the off-state leakage of the device.

[0148] The MOSFETs shown in the various embodiments of the present invention are all n-channel MOSFETs based on the participation of electron carriers in conduction. The essence of the technical solution of the present invention is also applicable to p-channel MOSFETs based on the participation of hole carriers in conduction.

[0149] In the present invention, there is no specific limitation on the material of the semiconductor. The material of the semiconductor may be a single-element semiconductor such as germanium, silicon, etc.; the material of the semiconductor may be a compound semiconductor such as silicon carbide, gallium nitride, gallium oxide, tin oxide, etc.

[0150] It should be understood that the above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above-described embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A field effect transistor, comprising: a semiconductor layer of a first conductivity type; Electrodes, including a drain electrode, a source electrode and a gate electrode; a gate insulating film disposed between the gate electrode and the first conductive type semiconductor layer; Features: There is a Schottky barrier between the first portion of the source electrode and the first conductive type semiconductor layer, and the first portion of the source electrode is not in contact with the gate insulating film; the second portion of the source electrode forms an ohmic contact with the first conductive type semiconductor layer; The gate electrode at least includes a metal material having a Schottky barrier with the semiconductor layer of the first conductivity type, and the metal material is in contact with the gate insulating film; or the gate electrode at least includes an electrode material of the second conductivity type, and the electrode material of the second conductivity type is in contact with the gate insulating film, wherein the conductivity types of the second conductivity type and the first conductivity type are different.

2. The field effect transistor according to claim 1, characterized in that The first conductivity type is n-type, and the second conductivity type is p-type.

3. The field effect transistor according to claim 1, characterized in that The first portion of the source electrode contacts the first conductivity type semiconductor layer to form a Schottky contact.

4. The field effect transistor according to claim 1, characterized in that The width of the first portion of the source electrode from the gate insulating film is in the range of 3nm to 400nm.

5. The field effect transistor according to claim 1, characterized in that: The width of the first portion of the source electrode from the gate insulating film is in the range of 3nm to 200nm.

6. The field effect transistor according to claim 1, characterized in that The field effect transistor is a horizontal semiconductor element or a vertical semiconductor element.

7. A trench MOS diode, comprising: An n-type semiconductor layer having a first main surface on one side and a second main surface on the other side opposite thereto, wherein the n-type semiconductor layer is provided with a groove, and the groove opens inward from the first main surface of the n-type semiconductor layer; a cathode electrode formed on the second main surface of the n-type semiconductor layer; an anode electrode formed on the first main surface of the n-type semiconductor layer; A trench MOS gate, which is buried in the trench and wrapped by a gate insulating film, wherein the trench MOS gate and the n-type semiconductor layer are separated by the gate insulating film and the trench MOS gate is in contact with the anode electrode; Features: The first portion of the anode electrode forms a Schottky contact with the first main surface of the n-type semiconductor layer, and the second portion of the anode electrode forms an ohmic contact with the first main surface of the n-type semiconductor layer; The trench MOS gate at least includes a metal material having a Schottky barrier with the n-type semiconductor layer, and the metal material is in contact with the gate insulating film; or the trench MOS gate at least includes a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film; The width of the first portion of the anode electrode from the gate insulating film is in the range of 3nm to 400nm.

8. The trench MOS diode according to claim 7, characterized in that: The width of the first portion of the anode electrode from the gate insulating film is in the range of 3nm to 200nm.

9. An insulated gate bipolar transistor, comprising: p-type semiconductor layer; an n-type semiconductor layer stacked on the p-type semiconductor layer; An electrode including a collector, an emitter, and a gate electrode, wherein the collector is formed on a surface of the p-type semiconductor layer opposite to the n-type semiconductor layer; a gate insulating film, which is interposed between the gate electrode and the n-type semiconductor layer; Features: There is a Schottky barrier between the first part of the emitter and the n-type semiconductor layer, the first part of the emitter is not in contact with the gate insulating film, and the second part of the emitter forms an ohmic contact with the n-type semiconductor layer; The gate electrode at least includes a metal material having a Schottky barrier with the n-type semiconductor layer, and the metal material is in contact with the gate insulating film; or the gate electrode is made of a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film.

10. The insulated gate bipolar transistor according to claim 9, characterized in that: The first portion of the emitter contacts the n-type semiconductor layer to form a Schottky contact.

11. The insulated gate bipolar transistor according to claim 9, characterized in that: The width range of the first portion of the emission from the gate insulating film is between 3nm and 400nm.

12. The insulated gate bipolar transistor according to claim 9, characterized in that: The width range of the first portion of the emission from the gate insulating film is between 3nm and 200nm.

13. A field effect transistor comprising: A first semiconductor layer including an n-type semiconductor region; A second semiconductor layer including an n-type semiconductor region and a high-resistance semiconductor region; Electrodes, including a drain electrode, a source electrode and a gate electrode; a gate insulating film, which is interposed between the gate electrode and the semiconductor layer; Features: The drain electrode is formed on a surface of the first semiconductor layer opposite to the second semiconductor layer; The source electrode is formed on a surface of the second semiconductor layer opposite to the first semiconductor layer, a Schottky barrier exists between a first portion of the source electrode and the n-type semiconductor region of the second semiconductor layer, and the first portion of the source electrode is not in contact with the gate insulating film; and a second portion of the source electrode is in contact with the n-type semiconductor region of the second semiconductor layer to form an ohmic contact; The high-resistance semiconductor region of the second semiconductor layer is disposed in a region close to a surface layer of the second semiconductor layer and is formed between the gate insulating film and a first portion of the source electrode; The gate electrode at least includes a metal material having a Schottky barrier with the second semiconductor layer, and the metal material is in contact with the gate insulating film; or the gate electrode is made of a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film.

14. The field effect transistor according to claim 13, characterized in that: A first portion of the source electrode contacts the n-type semiconductor region of the second semiconductor layer to form a Schottky barrier.

Images