Commutation ratio determination method, power converter, electronic device and storage medium

Abstract

The present application provides a commutation ratio determination method, a power converter, an electronic device and a storage medium. The commutation ratio determination method is used for determining the commutation ratio of a three-level active neutral-point-clamped (ANPC) structure, and comprises: acquiring a thermal equilibrium mapping relationship, wherein the thermal equilibrium mapping relationship is used for indicating a mapping relationship among a power factor, a modulation index and a thermal equilibrium factor, and the thermal equilibrium factor is used for indicating the thermal equilibrium of an external half-bridge module in the three-level ANPC structure; acquiring a first power factor and a first modulation index; on the basis of the thermal equilibrium mapping relationship, determining a first thermal equilibrium factor mapped to the first power factor and the first modulation index; and on the basis of the first thermal equilibrium factor, determining the commutation ratio of the three-level ANPC structure, wherein the commutation ratio is used for indicating the number ratio of a short commutation path to a long commutation path in the working process of the three-level ANPC structure. The present solution can reduce the local hot spot temperature of a device in a three-level ANPC structure.

Description

Commutation ratio determination method, power converter, electronic device and storage medium Technical Field

[0001] The present application relates to the field of electrical technology, and in particular to a commutation ratio determination method, a power converter, an electronic device, and a storage medium. Background Art

[0002] Three-level active neutral-point-clamped (ANPC) converters are widely used in renewable energy conversion systems and medium-voltage industrial drives. Three-level ANPC converters include a three-level ANPC structure with multiple switch combinations and flexible commutation paths. The commutation paths in a three-level ANPC structure include short and long commutation paths. The short commutation path generates less stray inductance, while the long commutation path generates more stray inductance. Therefore, the short commutation path is preferred. However, the short commutation path generates more heat in the external half-bridge module of the three-level ANPC structure. Therefore, the long commutation path is needed to supplement the short commutation path to prevent damage to the transistors in the external half-bridge module due to overheating. Therefore, it is necessary to determine the ratio of the short and long commutation paths (the commutation ratio) to balance the losses and heat generation in the three-level ANPC structure.

[0003] Currently, the heating conditions of the three-level ANPC structure under different commutation ratios are detected through experiments, and the commutation ratio is determined based on the heating conditions.

[0004] However, due to the limitation of the number of tests, the determined commutation ratio cannot fully utilize the short commutation path and will lead to higher local hot spot temperatures of the devices in the three-level ANPC structure.

[0005] Summary of the Invention

[0006] In view of this, the commutation ratio determination method, power converter, electronic device and storage medium provided in the present application can improve the determined commutation ratio to make it more reasonable and reduce the local hot spot temperature of the device in the three-level ANPC structure.

[0007] According to a first aspect of an embodiment of the present application, a commutation ratio determination method is provided for determining the commutation ratio of a three-level active neutral point clamping structure. The method includes: obtaining a thermal balance mapping relationship, wherein the thermal balance mapping relationship is used to indicate a mapping relationship between a power factor, a modulation index, and a thermal balance factor, and the thermal balance factor is used to indicate the thermal balance of an external half-bridge module in the three-level active neutral point clamping structure; obtaining a first power factor and a first modulation index; determining a first thermal balance factor mapped to the first power factor and the first modulation index based on the thermal balance mapping relationship; and determining the commutation ratio of the three-level active neutral point clamping structure based on the first thermal balance factor, wherein the commutation ratio indicates the ratio of the number of short commutation paths to the number of long commutation paths during operation of the three-level active neutral point clamping structure.

[0008] According to a second aspect of an embodiment of the present application, a commutation ratio determination device is provided for determining the commutation ratio of a three-level active neutral point clamping structure. The device includes: a first acquisition unit, configured to acquire a thermal balance mapping relationship, wherein the thermal balance mapping relationship is used to indicate a mapping relationship between a power factor, a modulation index, and a thermal balance factor, and the thermal balance factor is used to indicate the thermal balance of an external half-bridge module in the three-level active neutral point clamping structure; a second acquisition unit, configured to acquire a first power factor and a first modulation index; a mapping unit, configured to determine, based on the thermal balance mapping relationship, a first thermal balance factor mapped to the first power factor and the first modulation index; and a processing unit, configured to determine, based on the first thermal balance factor, the commutation ratio of the three-level active neutral point clamping structure, wherein the commutation ratio indicates the ratio of the number of short commutation paths to the number of long commutation paths during operation of the three-level active neutral point clamping structure.

[0009] According to a third aspect of an embodiment of the present application, a power converter is provided, comprising: a control unit and a three-level active neutral point clamping structure; the three-level active neutral point clamping structure is electrically connected to a DC bus and an AC output terminal; the control unit is used to implement the commutation ratio determination method described in the first aspect above, and, based on the determined commutation ratio, controls the ratio of the number of short commutation paths to the number of long commutation paths during operation of the three-level active neutral point clamping structure.

[0010] According to the fourth aspect of the embodiments of the present application, an electronic device is provided, comprising: a processor, a memory, a communication interface and a bus, wherein the processor, the memory and the communication interface communicate with each other through the bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to perform operations corresponding to the commutation ratio determination method described in the first aspect above.

[0011] According to the fifth aspect of the embodiment of the present application, a computer-readable storage medium is provided, on which computer instructions are stored. When the computer instructions are executed by a processor, the processor executes the commutation ratio determination method as described in the first aspect above.

[0012] According to a sixth aspect of an embodiment of the present application, a computer program product is provided, which is tangibly stored on a computer-readable medium and includes computer-executable instructions, which, when executed, enable at least one processor to perform the commutation ratio determination method as described in the first aspect above.

[0013] As can be seen from the above technical solution, the thermal balance mapping relationship can indicate the mapping relationship between the power factor, modulation index, and thermal balance factor of the three-level ANPC structure. The thermal balance factor can indicate the thermal balance of the external half-bridge module in the three-level ANPC structure. After obtaining the first power factor and first modulation index during actual operation of the three-level ANPC structure, the first thermal balance factor corresponding to the first power factor and first modulation index can be determined based on the thermal balance mapping relationship. The commutation ratio of the three-level ANPC structure can then be determined based on the first thermal balance factor. Because overheating of the external half-bridge module can cause severe thermal imbalance in the external half-bridge module, and the thermal balance factor can reflect the thermal balance of the external half-bridge module, the commutation ratio can be determined based on the actual operating state of the three-level ANPC structure. Compared to the commutation ratio determined through a limited number of tests, this can more effectively utilize short commutation paths and reduce the local hotspot temperature of the components in the three-level ANPC structure, while ensuring that the external half-bridge module does not overheat. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG1 is a schematic diagram of a three-level ANPC structure according to an embodiment of the present application;

[0015] FIG2 is a schematic diagram of a short commutation path according to an embodiment of the present application;

[0016] FIG3 is a schematic diagram of a long commutation path according to an embodiment of the present application;

[0017] FIG4 is a schematic diagram of a short commutation path and a long commutation path according to an embodiment of the present application;

[0018] FIG5 is a flow chart of a method for determining a commutation ratio according to an embodiment of the present application;

[0019] FIG6 is a schematic diagram of a heat balance mapping relationship according to an embodiment of the present application;

[0020] FIG7 is a flow chart of a method for obtaining a thermal balance mapping relationship according to an embodiment of the present application;

[0021] FIG8 is a schematic diagram of a mapping function curve according to an embodiment of the present application;

[0022] FIG9 is a schematic diagram of a commutation ratio determination device according to an embodiment of the present application;

[0023] FIG10 is a schematic diagram of a power converter according to an embodiment of the present application;

[0024] FIG11 is a schematic diagram of an electronic device according to an embodiment of the present application.

[0025] Reference numerals list: 101: first external half-bridge module 102: internal half-bridge module 103: second external half-bridge module S1-S6: switches D1-D6: diodes P: DC bus positive pole N: DC bus negative pole O: DC bus midpoint V out : AC output terminal 500: Commutation ratio determination method 700: Thermal balance mapping relationship acquisition method 900: Commutation ratio determination device 1000: Power converter 1100: Electronic device m: Modulation index m′: Maximum thermal probability of switch W: Thermal balance factor PF: Power factor 1001: Control unit 1002: Three-level ANPC structure 1102: Processor 1104: Communication interface 1106: Memory 1108: Bus 1110: Program 501: Acquire thermal balance mapping relationship 502: Acquire first power factor and first modulation index 503: Determine first thermal balance factor mapped to first power factor and first modulation index based on thermal balance mapping relationship 504: Determine commutation ratio of three-level ANPC structure based on first thermal balance factor 701: Acquire multiple arrays including second power factors and second modulation indices 702: Obtain second thermal balance factors corresponding to the arrays based on the second power factors and second modulation indices included in the arrays 703: Generate thermal balance mapping relationship based on multiple arrays and the second thermal balance factors corresponding to the arrays DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field should fall within the scope of protection of the embodiments of the present application.

[0027] Since the embodiments of the present application are used to determine the commutation ratio of a three-level ANPC structure, which is the ratio of the number of short commutation paths to the number of long commutation paths used during operation of the three-level ANPC structure, the three-level ANPC structure and related contents such as the short commutation paths and the long commutation paths are first described.

[0028] FIG1 is a schematic diagram of a three-level ANPC structure according to an embodiment of the present invention. As shown in FIG1 , the three-level ANPC structure includes a first external half-bridge module 101 , a second external half-bridge module 103 , and an internal half-bridge module 102 .

[0029] The first external half-bridge module 101 includes a switch S1, a diode D1, a switch S5, and a diode D5. Diode D1 is a parasitic diode of switch S1, and diode D5 is a parasitic diode of switch S5. The collector of switch S1 is connected to the DC bus positive electrode P, the cathode of diode D1 is connected to the collector of switch S1, and the anode of diode D1 is connected to the emitter of switch S1. The collector of switch S5 is connected to the emitter of switch S1, the cathode of diode D5 is connected to the collector of switch S5, the anode of diode D5 is connected to the emitter of switch S5, and the emitter of switch S5 is connected to the DC bus midpoint (voltage midpoint) O.

[0030] The second external half-bridge module 103 includes a switch S4, a diode D4, a switch S6, and a diode D6. Diode D4 is a parasitic diode of switch S4, and diode D6 is a parasitic diode of switch S6. The emitter of switch S4 is connected to the negative terminal N of the DC bus. The anode of diode D4 is connected to the emitter of switch S4, and the cathode of diode D4 is connected to the collector of switch S4. The emitter of switch S6 is connected to the collector of switch S4, and the collector of switch S6 is connected to the midpoint O of the DC bus. The anode of diode D6 is connected to the emitter of switch S6, and the cathode of diode D6 is connected to the collector of switch S6.

[0031] The internal half-bridge module 102 includes a switch S2, a diode D2, a switch S3, and a diode D3. Diode D2 is a parasitic diode of switch S2, and diode D3 is a parasitic diode of switch S3. The collector of switch S2 is connected to the emitter of switch S1, the emitter of switch S2 is connected to the collector of switch S3, and the emitter of switch S3 is connected to the collector of switch S4. The anode of diode D2 is connected to the emitter of switch S2, and the cathode of diode D2 is connected to the collector of switch S2. The anode of diode D3 is connected to the emitter of switch S3, and the cathode of diode D3 is connected to the collector of switch S3. The emitter of switch S2 is connected to the AC output terminal V out connect.

[0032] The operation states of the three-level ANPC structure can include a positive state P, an upper zero state O U , lower zero state O L , upper and lower zero state O UL and negative state N. Switching between operating states includes and Among them, the operation state transition and For short commutation path, operating state transition and For long commutation paths, operating state transitions and It includes both short commutation paths and long commutation paths.

[0033] Figure 2 shows the short commutation path of the three-level ANPC structure, where the upper two figures in Figure 2 show the operation state transition to The two figures below Figure 2 show the short commutation path when the operating state is converted to The short commutation path.

[0034] Figure 3 shows the long commutation path of the three-level ANPC structure, where the upper two figures in Figure 3 show the operation state transition to The two lower figures in Figure 3 show the operation state transition to Long commutation path.

[0035] Figure 4 shows the short commutation path and the long commutation path of the three-level ANPC structure, wherein the upper two figures of Figure 4 show the operation state transition to The short commutation path and the long commutation path when the operation state is converted to The short commutation path and the long commutation path.

[0036] When a three-level ANPC structure operates with a short commutation path, heat is primarily generated by the external half-bridge module. Prolonged operation of the three-level ANPC structure with a short commutation path can damage the switches or diodes in the short commutation path due to overheating. The short commutation path shown in the upper left figure of Figure 2 primarily generates heat from switch S1 and diode D5. The short commutation path shown in the upper right figure of Figure 2 primarily generates heat from switch S5 and diode D1. The short commutation path shown in the lower left figure of Figure 2 primarily generates heat from switch S6 and diode D4. The short commutation path shown in the lower right figure of Figure 2 primarily generates heat from switch S4 and diode D6.

[0037] When the three-level ANPC structure operates with a long commutation path, heat is primarily generated by the internal half-bridge modules. The long commutation path shown in the upper left of Figure 3 primarily generates heat from switch S2 and diode D3. The long commutation path shown in the upper right of Figure 3 primarily generates heat from switch S3 and diode D2. The long commutation path shown in the lower left of Figure 3 primarily generates heat from switch S2 and diode D3. The long commutation path shown in the lower right of Figure 3 primarily generates heat from switch S3 and diode D2.

[0038] The following describes in detail the commutation ratio determination method and apparatus provided in embodiments of the present application, in conjunction with the three-level ANPC structure shown in FIG1 . It should be noted that, because the first external half-bridge module 101 and the second external half-bridge module 103 in the three-level ANPC structure have the same structure and heat generation characteristics, the following embodiments illustrate the commutation ratio determination process using the first external half-bridge module 101 as an example. It should be understood that the commutation ratio of the three-level ANPC structure can also be determined based on the second external half-bridge module 103.

[0039] Commutation ratio determination method

[0040] FIG5 is a flow chart of a commutation ratio determination method according to an embodiment of the present application. The commutation ratio determination method is used to determine the commutation ratio of a three-level ANPC structure. As shown in FIG5 , the commutation ratio determination method 500 includes:

[0041] Step 501: Obtain a thermal balance mapping relationship.

[0042] The thermal balance mapping relationship can indicate the mapping relationship between the power factor, modulation index, and thermal balance factor. That is, given the power factor and modulation index, the corresponding thermal balance factor can be determined using this thermal balance mapping relationship. The thermal balance factor can indicate the thermal balance of the external half-bridge modules in the three-level ANPC structure. For example, the thermal balance factor can indicate the thermal balance of the first external half-bridge module 101. That is, the thermal balance factor indicates the thermal distribution of the switch S1, diode D1, switch S5, and diode D5 in the first external half-bridge module 101.

[0043] Power factor and modulation index are operating parameters of the three-level ANPC structure. The power factor is determined by the load of the three-level ANPC structure. The load's power factor can be directly obtained or calculated based on the phase difference between voltage and current. In open-loop control mode, the modulation index is pre-set; in closed-loop control mode, it automatically adjusts.

[0044] The thermal balance mapping relationship can be expressed in different forms, such as a mapping table or a three-dimensional surface. Figure 6 shows a schematic diagram of a thermal balance mapping relationship. As shown in Figure 6, the thermal balance mapping relationship is a three-dimensional convex surface. The three coordinate axes of the three-dimensional convex surface are the power factor PF, the modulation index m, and the thermal balance factor W. The power factor PF ranges from [-1, 1], the modulation index m ranges from [0, 1], and the thermal balance factor W ranges from (0, 1).

[0045] Step 502: Obtain a first power factor and a first modulation index.

[0046] The first power factor is the power factor during the actual operation of the three-level ANPC structure, and the first modulation index is the modulation index during the actual operation of the three-level ANPC structure. The first power factor can be obtained from the parameters of the load of the three-level ANPC structure, or calculated based on the phase difference between the voltage and current of the load. If the three-level ANPC structure is open-loop control, the first modulation command can be predetermined. If the three-level ANPC structure is closed-loop control, the first modulation index can be dynamically obtained.

[0047] Step 503: Determine a first thermal balance factor mapped to the first power factor and the first modulation index according to the thermal balance mapping relationship.

[0048] Since the thermal balance mapping relationship can indicate the mapping relationship between the power factor, the modulation index, and the thermal balance factor, after obtaining the first power factor and the first modulation index, the first thermal balance factor mapped to the first power factor and the first modulation index can be determined according to the thermal balance mapping relationship. The first thermal balance factor can reflect the thermal balance of the first external half-bridge module 101 or the second external half-bridge module 103 during the operation of the three-level ANPC structure, that is, the first thermal balance factor can reflect whether the heat generation of the switch tube and the diode in the three-level ANPC structure is balanced.

[0049] In one example, after obtaining the first power factor and the first modulation index, according to the three-dimensional convex surface for indicating the thermal balance mapping relationship shown in Figure 6, a thermal balance factor corresponding to the first power factor and the first modulation index is determined from the three-dimensional convex surface as the first thermal balance factor.

[0050] Step 504: Determine the commutation ratio of the three-level ANPC structure according to the first thermal balance factor.

[0051] The commutation ratio of the three-level ANPC structure is used to indicate the ratio of the number of short commutation paths to the number of long commutation paths during the operation of the three-level ANPC structure. That is, the commutation ratio indicates the ratio of the number of short commutation paths used by the three-level ANPC structure to the number of long commutation paths used within a set control cycle.

[0052] Compared to long commutation paths, short commutation paths result in less stray inductance, resulting in smaller voltage spikes when the switches are turned off, making them less susceptible to damage. Therefore, short commutation paths are preferred in three-level ANPC operation. However, short commutation paths generate more heat in the external half-bridge modules. To prevent damage to the switches and diodes in these modules due to overheating, long commutation paths are used instead of short commutation paths. When the long commutation paths are in operation, the internal half-bridge modules in the three-level ANPC structure generate more heat, while the external half-bridge modules generate less heat, preventing damage to the switches and diodes in the external half-bridge modules due to overheating. However, the long commutation paths also result in greater stray inductance, increasing losses in the three-level ANPC structure and leading to higher turn-off voltage spikes. Therefore, determining an appropriate commutation ratio and alternating between short and long commutation paths during operation can reduce the local hotspot temperatures of the three-level ANPC components while preventing overheating in the short commutation paths.

[0053] In an embodiment of the present application, a thermal balance mapping relationship can indicate a mapping relationship between the power factor, modulation index, and thermal balance factor of a three-level ANPC structure. The thermal balance factor can indicate the thermal balance of an external half-bridge module in the three-level ANPC structure. After obtaining a first power factor and a first modulation index during actual operation of the three-level ANPC structure, a first thermal balance factor corresponding to the first power factor and the first modulation index can be determined based on the thermal balance mapping relationship. The commutation ratio of the three-level ANPC structure can then be determined based on the first thermal balance factor. Because overheating of the external half-bridge module can cause severe thermal imbalance in the external half-bridge module, and the thermal balance factor can reflect the thermal balance of the external half-bridge module, the commutation ratio can be determined based on the actual operating state of the three-level ANPC structure. Compared to a commutation ratio determined through a limited number of tests, this can utilize more short commutation paths while ensuring that the external half-bridge module does not overheat, thereby reducing the local hotspot temperature of the components in the three-level ANPC structure.

[0054] In one possible implementation, the thermal balance mapping relationship of the three-level ANPC structure can be determined by the correspondence between multiple sets of power factors, modulation indices, and thermal balance factors. FIG7 shows a flow chart of a method for obtaining a thermal balance mapping relationship. As shown in FIG7 , the thermal balance mapping relationship obtaining method 700 includes the following steps:

[0055] Step 701: Acquire multiple arrays including second power factors and second modulation indices.

[0056] At least one of the second power factor and the second modulation index in different arrays is different, that is, different arrays can include the same second power factor, but two arrays including the same second power factor cannot include the same second modulation index. Correspondingly, different arrays can include the same second modulation index, but two arrays including the same second modulation index cannot include the same second power factor.

[0057] The second power factor included in the array is a power factor that can be taken during the operation of the three-level ANPC structure, and the second modulation index included in the array is a modulation index that can be taken during the operation of the three-level ANPC structure.

[0058] Step 702: Obtain a second thermal balance factor corresponding to the array according to the second power factor and the second modulation index included in the array.

[0059] For each acquired array, a second thermal balance factor corresponding to the array can be determined based on the second power factor and second modulation index included in the array, thereby obtaining multiple second thermal balance factors corresponding to multiple arrays. The second thermal balance factors corresponding to the arrays can indicate the thermal balance of the external half-bridge modules in the three-level ANPC structure when the three-level ANPC structure operates with the second power factor and second modulation index included in the array.

[0060] When the three-level ANPC structure operates at different power factors and modulation indices, the heat generated by the switch tube and the diode in the external half-bridge module is different, which leads to different thermal balance of the external half-bridge module. Therefore, a corresponding second thermal balance factor can be determined according to the second power factor and the second modulation index.

[0061] Step 703: Generate a thermal balance mapping relationship according to the multiple arrays and the second thermal balance factors corresponding to the arrays.

[0062] The second thermal balance factor corresponding to the array indicates the thermal balance of the external half-bridge module in the three-level ANPC structure when the three-level ANPC structure operates with the second power factor and second modulation index included in the array. That is, the second thermal balance factor corresponding to the data has a mapping relationship with the second power factor and second modulation index included in the array, thereby determining the mapping relationship between multiple sets of second power factors, second modulation indices, and second thermal balance factors.

[0063] The multiple arrays and their corresponding second thermal balance factors can reflect the law of change of the second thermal balance factor with the second power factor and the second modulation index, thereby obtaining a thermal balance mapping relationship that can indicate the mapping relationship between the power factor, modulation index and thermal balance factor.

[0064] In an embodiment of the present application, after obtaining multiple arrays including second power factors and second modulation indices, the second thermal balance factor corresponding to each array is obtained, and then multiple groups of corresponding second power factors, second modulation indices and second thermal balance factors are obtained. Based on these multiple groups of corresponding second power factors, second modulation indices and second thermal balance factors, the correspondence between the power factors, modulation indices and thermal balance factors can be determined, and then the thermal balance mapping relationship can be obtained to ensure the accuracy of the obtained thermal balance mapping relationship.

[0065] In a possible implementation, when obtaining an array including a second power factor and a second modulation index, N second power factors and N second modulation indices may be obtained, and N second power factors and N second modulation indices may be obtained by combining the N second power factors and the N second modulation indices. 2 An array including second power factors and second modulation indices. The difference between the i+1th second power factor and the i-th second power factor among the N second power factors is equal to the difference between the i+2th second power factor and the i+1th second power factor, and the difference between the i+1th second modulation index and the i-th second modulation index among the N second modulation indices is equal to the difference between the i+2th modulation index and the i+1th second modulation index. Wherein, N is a positive integer greater than or equal to 3, and i is a positive integer greater than or equal to 1 and less than or equal to N-2.

[0066] For example, the power factor range is [-1, 1]. 21 second power factors are obtained. The difference between the i+1th second power factor and the ith second power factor is 0.1. Then the 21 second power factors are -1, -0.9, -0.8, -0.7, -0.6, -0.5, -0.4, -0.3, -0.2, -0.1, 0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, and 1, respectively. The modulation index m ranges from [0 to 1]. 21 second modulation indices are obtained, and the difference between the i+1th second modulation index and the ith second modulation index among the second modulation indices is 0.05. Then, the 21 second modulation indices are 0, 0.05, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, and 1. By combining these 21 second power factors and these 21 second modulation indices, 441 arrays including second power factors and second modulation indices can be obtained.

[0067] It should be noted that obtaining multiple arrays by combining 21 second power factors and 21 second modulation indices is only one embodiment of the present application. The embodiment of the present application does not limit the number of second power factors and second modulation indices. Arrays can be obtained by combining fewer or equal numbers of second power factors and second modulation indices, and the number of second power factors and second modulation data can be different.

[0068] In an embodiment of the present application, a plurality of second power factors with equal spacing are determined within the value range of the power factor, and a plurality of second modulation indices with equal spacing are determined within the value range of the modulation index. By combining the obtained plurality of second power factors and plurality of second modulation data, a plurality of arrays including second power factors and second modulation indices are obtained, thereby ensuring the uniformity of sampling of the second power factors and second modulation indices in the plurality of arrays. When determining the thermal balance mapping relationship based on these plurality of arrays, it is ensured that the determined thermal balance mapping relationship can accurately reflect the mapping relationship between the thermal balance factor and the power factor and the modulation index, that is, the accuracy of the thermal balance mapping relationship is ensured.

[0069] In one possible implementation, when obtaining the second thermal balance factor corresponding to the array based on the second power factor and second modulation index included in the array, the probability of the hottest switch corresponding to the array can be determined based on the second modulation index included in the array. Furthermore, the second thermal balance factor corresponding to the array can be determined based on the second power factor included in the array and the probability of the hottest switch corresponding to the switch. The probability of the hottest switch can indicate the probability of maximum thermal stress on the switch in the external half-bridge module.

[0070] The probability of a hottest switch indicates the probability of the switch in the external half-bridge module experiencing the greatest thermal stress. Specifically, the probability of the hottest switch indicates the probability of switch S1 or S5 experiencing the greatest thermal stress, or the probability of switch S4 or S6 experiencing the greatest thermal stress. Due to the different heating values ​​of the switches and diodes in the external half-bridge module, heat distribution within the module is uneven, leading to localized thermal stress. The thermal stress experienced by the switches and diodes is related to their heating values. When the switch generates the greatest heat, the switch experiences the greatest thermal stress, and when the diode generates the greatest heat, the diode experiences the greatest thermal stress.

[0071] As shown in FIG1 , when switch S1 in the first external half-bridge module 101 generates the maximum heat, switch S1 in the first external half-bridge module 101 experiences the maximum thermal stress. When switch S5 in the first external half-bridge module 101 generates the maximum heat, switch S5 in the first external half-bridge module 101 experiences the maximum thermal stress. When diode D1 in the first external half-bridge module 101 generates the maximum heat, diode D1 in the first external half-bridge module 101 experiences the maximum thermal stress. When diode D5 in the first external half-bridge module 101 generates the maximum heat, diode D5 in the first external half-bridge module 101 experiences the maximum thermal stress. The switch hottest probability indicates the probability that switch S1 or switch S5 experiences the maximum thermal stress.

[0072] The heat generated by the switch tube and diode in the external half-bridge module is related to the modulation index during the operation of the three-level ANPC structure. The heat generated by the switch tube and diode will affect the probability of the switch tube being subjected to maximum thermal stress. Therefore, the maximum heat probability of the switch tube can be determined based on the second modulation index.

[0073] There is a critical value of the modulation index. When the three-level ANPC structure operates at this critical value, the probability that the switch tube in the external half-bridge module is subjected to maximum thermal stress is equal to the probability that the diode is subjected to maximum thermal stress. When the modulation index is greater than the critical value, the probability that the switch tube is subjected to maximum thermal stress is greater than the probability that the diode is subjected to maximum thermal stress. When the modulation index is less than the critical value, the probability that the switch tube is subjected to maximum thermal stress is less than the probability that the diode is subjected to maximum thermal stress.

[0074] As shown in FIG. 1, the switching transistor S1 and the diode D1 form a first switching unit, and the switching transistor S5 and the diode D5 form a second switching unit. The probabilities of the first switching unit and the second switching unit suffering from the maximum thermal stress are affected by the power factor during the operation of the three-level ANPC structure. When the three-level ANPC structure operates at some power factors, the probability of the first switching unit suffering from the maximum thermal stress is greater than that of the second switching unit suffering from the maximum thermal stress. When the three-level ANPC structure operates at some other power factors, the probability of the first switching unit suffering from the maximum thermal stress is less than that of the second switching unit suffering from the maximum thermal stress.

[0075] In the embodiment of the present application, since the power factor affects the probabilities of the first switching unit and the second switching unit suffering from the maximum thermal stress, and the modulation index affects the probability of the switching transistor in the first switching unit or the second switching unit suffering from the maximum thermal stress, after determining the hottest probability of the switching transistor according to the second modulation index, the second thermal balance factor corresponding to the array can be determined according to the second power factor and the hottest probability of the switching transistor. Based on the second power factor and the second modulation index included in the array, the thermal stress distribution is performed at two levels, between different switching units and inside the switching unit, to determine the second thermal balance factor corresponding to the array, so as to ensure that the determined thermal balance factor can accurately reflect the thermal balance of the external half-bridge module.

[0076] In a possible implementation manner, a mapping function regarding the modulation index is preset. The independent variable of the mapping function is the modulation index, and the dependent variable is the hottest probability of the switching transistor. After inputting the second modulation index included in the array into the mapping function, the hottest probability of the switching transistor corresponding to the array can be obtained. The mapping function is a monotonically increasing function, and the domain of the mapping function is [0, 1], and the range is (0, 1).

[0077] The mapping function represents the probability of the switching transistor in the external half-bridge module suffering from the maximum thermal stress, that is, the dependent variable of the mapping function is the hottest probability of the switching transistor. Define the hottest probability of the switching transistor as m′, the modulation index as m, and the mapping function as F(x), then there is m′ = F(m), 0 ≤ m ≤ 1, 0 < m′ < 1. Define F(md) = 0.5, and the mapping function F(x) satisfies that when m < md, F(m) < 0.5, and when m > md, F(m) > 0.5.

[0078] The mapping function can be determined based on experiments. Let the three-level ANPC structure operate at a certain fixed power factor, and at the same time, adjust the modulation index during the operation of the three-level ANPC structure, and measure the thermal indices of the switching transistor and the diode during the operation of the three-level ANPC structure until the thermal indices of the corresponding switching transistor and diode are equal. At this time, the modulation index is the critical modulation index md, and then the mapping function F(x) can be designed based on the critical modulation index md.

[0079] As shown in FIG1 , during the design of the mapping function F(x), the critical modulation index md can be determined based on the switches and diodes in the first external half-bridge module 101, or based on the switches and diodes in the second external half-bridge module 103. Several feasible methods for determining the critical modulation index md are described below.

[0080] (1) Detect the thermal index of the switch tube S1 and the diode D5, adjust the modulation index during the operation of the three-level ANPC structure, make the thermal index of the switch tube S1 and the diode D5 equal, and determine the modulation index at this time as the critical modulation index md.

[0081] (2) Detect the thermal index of the switch tube S5 and the diode D1, adjust the modulation index during the operation of the three-level ANPC structure, make the thermal index of the switch tube S5 and the diode D1 equal, and determine the modulation index at this time as the critical modulation index md.

[0082] (3) Detect the thermal index of the switch tube S4 and the diode D6, adjust the modulation index during the operation of the three-level ANPC structure, make the thermal index of the switch tube S4 and the diode D6 equal, and determine the modulation index at this time as the critical modulation index md.

[0083] (4) Detect the thermal index of the switch tube S6 and the diode D4, adjust the modulation index during the operation of the three-level ANPC structure, make the thermal index of the switch tube S6 and the diode D4 equal, and determine the modulation index at this time as the critical modulation index md.

[0084] (5) Detect the thermal index of the switch tube S1, the diode D1, the switch tube S4, or the diode D4 as the first thermal index, and detect the thermal index of the switch tube S5, the diode D5, the switch tube S6, or the diode D6 as the second thermal index. Adjust the modulation index during the operation of the three-level ANPC structure so that the first thermal index is equal to the second thermal index. The modulation index at this time is determined as the critical modulation index md.

[0085] It should be noted that the thermal index of the switching tube and the diode can be the heat obtained by estimation, calculation or sensing, or the junction temperature obtained by estimation, calculation or sensing, or the ambient temperature obtained by estimation, calculation or sensing, etc., as long as the thermal index can reflect the heat generated or the thermal stress borne by the corresponding switching tube or diode. This application does not limit the specific content and acquisition method of the thermal stress.

[0086] In one example, the modulation index is adjusted under the condition of a power factor of 0.8 until the thermal index of switch S1 equals the thermal index of diode D5. At this point, the modulation index m is equal to 0.35. That is, when the modulation index m = md = 0.35, m′ = F(m) = 0.5. Figure 8 shows a schematic curve diagram of a mapping function. As shown in Figure 8, when m = 0.35, m′ = 0.5. Because the heat generated by the anti-parallel diode is generally less than that generated by the switch, the probability of switch S1 experiencing maximum thermal stress reaches 50% before the modulation index reaches 0.5.

[0087] It should be noted that the mapping function F(x) is a function of the modulation index and has nothing to do with the power factor. Therefore, for arrays with different power factors, the same mapping function F(x) can be used to determine the hottest probability of the switch tube corresponding to the array.

[0088] In an embodiment of the present application, a mapping function for the modulation index is pre-constructed, and the mapping function is constructed based on the heat generation conditions of the switch tube and the diode in the external half-bridge module under different modulation indices. After the second modulation index included in the array is input into the mapping function, the hottest probability of the switch tube corresponding to the array is calculated through the mapping function to ensure the accuracy of the determined hottest probability of the switch tube.

[0089] In one possible implementation, when determining the second thermal balance factor corresponding to an array, the first probability, second probability, third probability, and fourth probability can be calculated respectively based on the second power factor included in the array and the hottest probability of the switching tube corresponding to the array, and then the second balance factor corresponding to the array can be determined based on the first probability, second probability, third probability, and fourth probability.

[0090] The first probability can indicate the probability that the first switching tube in the external half-bridge module has the largest thermal stress, the second probability can indicate the probability that the second diode in the external half-bridge module has the largest thermal stress, the third probability can indicate the probability that the first diode in the external half-bridge module has the largest thermal stress, and the fourth probability can indicate the probability that the second switching tube in the external half-bridge module has the largest thermal stress. The first diode is a parasitic diode of the first switching tube, and the first diode is electrically connected to the positive or negative pole of the DC bus. The second diode is a parasitic diode of the second switching tube, and the second switching tube is electrically connected to the midpoint of the DC bus.

[0091] As shown in Figure 1, taking the external half-bridge module as the first external half-bridge module 101 as an example, the first probability can indicate the probability that the switch tube S1 has the largest thermal stress in the first external half-bridge module 101, the second probability can indicate the probability that the diode D5 has the largest thermal stress in the first external half-bridge module 101, the third probability can indicate the probability that the diode D1 has the largest thermal stress in the first external half-bridge module 101, and the fourth probability can indicate the probability that the switch tube S5 has the largest thermal stress in the first external half-bridge module 101.

[0092] In an embodiment of the present application, the power factor affects the probability of the first switch unit (including the first switch tube and the first diode) and the second switch unit (including the second switch tube and the second diode) to withstand the maximum thermal stress. The hottest probability of the switch tube can indicate the probability of the first switch tube or the second switch tube to withstand the maximum thermal stress. Therefore, according to the second power factor included in the array and the hottest probability of the switch tube corresponding to the array, the probability of the first switch tube, the second switch tube, the first diode and the second diode to withstand the maximum thermal stress can be determined respectively. Then, based on the probability of the first switch tube, the second switch tube, the first diode and the second diode to withstand the maximum thermal stress, the second thermal balance factor can be determined to ensure the accuracy of the determined second thermal balance factor.

[0093] In one possible implementation, the first probability P1 can be calculated using the formula P1 = (0.5 + 0.5 × PF) × m', the second probability P2 can be calculated using the formula P2 = (0.5 + 0.5 × PF) × (1 - m'), the third probability P3 can be calculated using the formula P3 = (0.5 - 0.5 × PF) × m', and the fourth probability P4 can be calculated using the formula P4 = (0.5 - 0.5 × PF) × (1 - m'). PF represents the second power factor, and m' represents the probability of the hottest switch. The second power factor PF ranges from [-1, 1], and the probability of the hottest switch m' ranges from (0, 1).

[0094] It can be seen from the calculation formulas of the first probability, the second probability, the third probability and the fourth probability that when the second power factor PF and the hottest probability m′ of the switching tube take any values, the sum of the first probability, the second probability, the third probability and the fourth probability is equal to 1.

[0095] In an embodiment of the present application, the first probability, the second probability, the third probability and the fourth probability are calculated respectively by the above four formulas to ensure that the calculated first probability can accurately reflect the probability that the first switching tube is subjected to the maximum thermal stress, the second probability can accurately reflect the probability that the second diode is subjected to the maximum thermal stress, the third probability can accurately reflect the probability that the first diode is subjected to the maximum thermal stress, and the fourth probability can accurately reflect the probability that the second switching tube is subjected to the maximum thermal stress. Then, the second thermal balance factor is calculated based on the first probability, the second probability, the third probability and the fourth probability to ensure that the calculated second thermal balance factor can accurately reflect the thermal balance of the external half-bridge module.

[0096] In one possible implementation, when calculating the second thermal balance factor based on the first probability, the second probability, the third probability and the fourth probability, the product of the first probability, the second probability, the third probability and the fourth probability can be calculated, and the product of the first probability, the second probability, the third probability and the fourth probability can be determined as the probability product, and then the second thermal balance factor corresponding to the array is determined based on the probability product.

[0097] In an example, the product of the first probability, the second probability, the third probability and the fourth probability can be used as the second thermal balance factor corresponding to the array, that is, the second thermal balance factor corresponding to the array W=P1·P2·P3·P4.

[0098] In another example, the product of the first probability, the second probability, the third probability and the fourth probability can be appropriately mathematically transformed to serve as the second thermal balance factor corresponding to the array, such as the second thermal balance factor corresponding to the array

[0099] In an embodiment of the present application, the first probability, the second probability, the third probability and the fourth probability respectively indicate the probabilities that the first switch tube, the second diode, the first diode and the second switch tube in the external half-bridge module are subjected to the maximum thermal stress, so the product of the first probability, the second probability, the third probability and the fourth probability can reflect the thermal distribution of the external half-bridge module as a whole, and then the product of the first probability, the second probability, the third probability and the fourth probability is used as the second thermal balance factor, or the product of the first probability, the second probability, the third probability and the fourth probability is subjected to appropriate mathematical transformation as the second thermal balance factor, to ensure that the second thermal balance factor can accurately reflect the thermal balance of the external half-bridge module.

[0100] In one possible implementation, when determining the commutation ratio of the three-level ANPC structure based on the first thermal balance factor, a commutation ratio corresponding to the first thermal balance factor can be determined based on a predetermined relationship between the thermal balance factor and the commutation ratio, and this commutation ratio can then be used as the commutation ratio during operation of the three-level ANPC structure. In this relationship, the thermal balance factor is positively correlated with the commutation ratio, and the thermal balance factor is positively correlated with the thermal balance of the external half-bridge module. Specifically, a larger thermal balance factor improves the thermal balance of the external half-bridge module and reduces the probability of overheating of the switches and diodes in the external half-bridge module. In this case, a larger commutation ratio can be used to control the operation of the three-level ANPC structure.

[0101] The correspondence between the thermal balance factor and the commutation ratio can be an array, a matrix, or a lookup table after a function indicating the correspondence between the thermal balance factor and the commutation ratio, which is not limited in this application. In one example, the commutation ratio is stored in an array form, and the alternative commutation ratios are [+∞, 4, 3.5, 3, 2.5, 2, 2.5, 1]. The corresponding commutation ratio is selected from the eight alternative commutation ratios based on the first thermal balance factor to control the operation of the three-level ANPC structure, where +∞ indicates that the three-level ANPC structure is controlled to operate with a purely short commutation path, rather than a long commutation path.

[0102] For example, as shown in Figure 6, when the first thermal balance factor is located at the top region of the three-dimensional convex surface, the commutation ratio of the three-level ANPC structure is determined to be +∞, and the three-level ANPC structure is controlled to operate with purely short commutation paths. When the first thermal balance factor is greater than 0.03 and less than 0.04, the commutation ratio of the three-level ANPC structure is determined to be 3, and the three-level ANPC structure is controlled to operate with a ratio of short commutation paths to long commutation paths of 3. When the first thermal balance factor is less than 0.01, the commutation ratio of the three-level ANPC structure is determined to be 1, and the three-level ANPC structure is controlled to operate with a ratio of commutation paths to long commutation paths of 1.

[0103] It should be understood that the commutation ratio can be the ratio of the number of short commutation paths used by the three-level ANPC structure to the number of long commutation paths used during a control period, or can be the proportion of time that the three-level ANPC structure uses the short commutation paths.

[0104] In an embodiment of the present application, the correspondence between the thermal balance factor and the commutation ratio is determined in advance. The correspondence can be an array, a matrix or a lookup table after a function indicating the correspondence between the thermal balance factor and the commutation ratio. Through the correspondence, the commutation ratio corresponding to the first thermal balance factor can be easily determined, thereby ensuring the efficiency of determining the commutation ratio.

[0105] Commutation ratio determining device

[0106] FIG9 is a schematic diagram of a commutation ratio determination device according to an embodiment of the present application. The device is used to determine the commutation ratio of a three-level ANPC structure. As shown in FIG9 , the commutation ratio determination device 900 includes:

[0107] A first acquiring unit 901 is configured to acquire a thermal balance mapping relationship, wherein the thermal balance mapping relationship is used to indicate a mapping relationship between a power factor, a modulation index, and a thermal balance factor, and the thermal balance factor is used to indicate thermal balance of an external half-bridge module in a three-level active neutral point clamping structure;

[0108] A second acquiring unit 902 is configured to acquire a first power factor and a first modulation index;

[0109] A mapping unit 903 is configured to determine a first thermal balance factor mapped to the first power factor and the first modulation index according to the thermal balance mapping relationship;

[0110] The processing unit 904 is configured to determine a commutation ratio of the three-level active neutral point clamped structure according to the first thermal balance factor, wherein the commutation ratio indicates a ratio of the number of short commutation paths to the number of long commutation paths during operation of the three-level active neutral point clamped structure.

[0111] In an embodiment of the present application, the thermal balance mapping relationship acquired by the first acquisition unit 901 may indicate a mapping relationship between the power factor, modulation index, and thermal balance factor of the three-level ANPC structure. The thermal balance factor may indicate the thermal balance of the external half-bridge module in the three-level ANPC structure. After the second acquisition unit 902 acquires the first power factor and first modulation index during actual operation of the three-level ANPC structure, the mapping unit 903 may determine a first thermal balance factor corresponding to the first power factor and first modulation index based on the thermal balance mapping relationship. Furthermore, the processing unit 904 may determine the commutation ratio of the three-level ANPC structure based on the first thermal balance factor. Because overheating of the external half-bridge module can cause severe thermal imbalance in the external half-bridge module, and the thermal balance factor can reflect the thermal balance of the external half-bridge module, the commutation ratio can be determined based on the actual operating state of the three-level ANPC structure. Compared to the commutation ratio determined through a limited number of tests, this can utilize more short commutation paths and reduce the local hot spot temperature of the components in the three-level ANPC structure while ensuring that the external half-bridge module does not overheat.

[0112] It should be noted that the interaction between the various parts in the above-mentioned commutation ratio determination device and the above-mentioned commutation ratio determination method embodiment are based on the same concept. The specific content and beneficial effects can be found in the description in the above-mentioned commutation ratio determination method embodiment, and will not be repeated here.

[0113] power converters

[0114] FIG10 is a schematic diagram of a power converter according to an embodiment of the present application. As shown in FIG10 , the power converter 1000 includes a control unit 1001 and a three-level ANPC structure 1002. The three-level ANPC structure 1002 is electrically connected to a DC bus and an AC output terminal. The control unit 1001 can execute the commutation ratio determination method described in any of the above embodiments and, based on the determined commutation ratio, control the ratio of the number of short commutation paths to the number of long commutation paths during operation of the three-level ANPC structure.

[0115] It should be noted that the power converter 1000 may include multiple three-level ANPC structures. For example, in a three-phase power application, the power converter 1000 includes three three-level ANPC structures. The three three-level ANPC structures are connected to the same DC bus. The three three-level ANPC structures are respectively connected to the three phases of the three-phase AC. The control unit 1001 controls the commutation ratios of the three three-level ANPC structures respectively. The commutation ratios of the three three-level ANPC structures can be the same or different, and this application does not limit this.

[0116] The three-level ANPC structure is shown in Figure 1, where the switches S1, S2, S3, S4, S5, and S6 can be insulated-gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs). The control unit 1001 can be a digital signal processor (DSP), a single-chip microcomputer, a control chip, etc.

[0117] It should be noted that the power converter 1000 in the embodiment of the present application is a specific application of the commutation ratio determination method in the aforementioned embodiment. The specific content and beneficial effects can be found in the description in the aforementioned commutation ratio determination method embodiment, which will not be repeated here.

[0118] electronic devices

[0119] FIG11 is a schematic diagram of an electronic device provided in an embodiment of the present application. The specific embodiments of the present application do not limit the specific implementation of the electronic device. Referring to FIG11 , the electronic device 1100 provided in an embodiment of the present application includes: a processor 1102, a communications interface 1104, a memory 1106, and a bus 1108. Among them:

[0120] The processor 1102 , the communication interface 1104 , and the memory 1106 communicate with each other via a bus 1108 .

[0121] The communication interface 1104 is used to communicate with other electronic devices or servers.

[0122] The processor 1102 is used to execute the program 1110, and specifically can execute the relevant steps in the above-mentioned embodiment of the commutation ratio determination method.

[0123] Specifically, the program 1110 may include program codes, which include computer operation instructions.

[0124] Processor 1102 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application. The one or more processors included in the smart device may be processors of the same type, such as one or more CPUs, or may be processors of different types, such as one or more CPUs and one or more ASICs.

[0125] The memory 1106 is used to store the program 1110. The memory 1106 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0126] The program 1110 can be specifically used to enable the processor 1102 to execute the commutation ratio determination method in any of the aforementioned embodiments.

[0127] The specific implementation of each step in program 1110 can be found in the corresponding descriptions of the corresponding steps and units in the above-mentioned embodiment of the method for determining the commutation ratio, and will not be repeated here. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding process descriptions in the above-mentioned method embodiment, and will not be repeated here.

[0128] In the electronic device of this embodiment, the thermal balance mapping relationship can indicate the mapping relationship between the power factor, modulation index, and thermal balance factor of the three-level ANPC structure. The thermal balance factor can indicate the thermal balance of the external half-bridge module in the three-level ANPC structure. After obtaining a first power factor and a first modulation index during actual operation of the three-level ANPC structure, a first thermal balance factor corresponding to the first power factor and the first modulation index can be determined based on the thermal balance mapping relationship. The commutation ratio of the three-level ANPC structure can then be determined based on the first thermal balance factor. Because overheating of the external half-bridge module can cause severe thermal imbalance in the external half-bridge module, and the thermal balance factor can reflect the thermal balance of the external half-bridge module, the commutation ratio can be determined based on the actual operating state of the three-level ANPC structure. Compared to the commutation ratio determined through a limited number of tests, this can utilize more short commutation paths while ensuring that the external half-bridge module does not overheat, thereby reducing the local hot spot temperature of the components in the three-level ANPC structure.

[0129] Computer-readable storage medium

[0130] The present application also provides a computer-readable storage medium storing instructions for causing a machine to execute the commutation ratio determination method described herein. Specifically, a system or device equipped with a storage medium can be provided, wherein the storage medium stores software program code that implements the functions of any of the above-described embodiments, and a computer (or CPU or MPU) of the system or device can read and execute the program code stored in the storage medium.

[0131] In this case, the program code read from the storage medium itself can realize the function of any one of the above embodiments, so the program code and the storage medium storing the program code constitute part of this application.

[0132] Examples of storage media for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, the program code can be downloaded from a server computer via a communication network.

[0133] In addition, it should be clear that the functions of any of the above embodiments can be achieved not only by executing the program code read by the computer, but also by enabling the operating system operating on the computer to complete part or all of the actual operations based on the instructions of the program code.

[0134] In addition, it can be understood that the program code read from the storage medium is written into a memory provided in an expansion board inserted into the computer or into a memory provided in an expansion module connected to the computer, and then based on the instructions of the program code, a CPU installed on the expansion board or expansion module is enabled to perform part or all of the actual operations, thereby realizing the functions of any of the above embodiments.

[0135] Computer program product

[0136] The present application also provides a computer program product tangibly stored on a computer-readable medium and comprising computer-executable instructions. When executed, the computer-executable instructions cause at least one processor to perform the commutation ratio determination method provided in the aforementioned embodiments. It should be understood that each solution in this embodiment has the corresponding technical effects of the aforementioned method embodiments, and will not be further elaborated here.

[0137] It should be noted that not all steps and modules in the above-mentioned processes and device structure diagrams are required, and certain steps or modules can be omitted according to actual needs. The execution order of each step is not fixed and can be adjusted as needed. The system structure described in the above-mentioned embodiments can be a physical structure or a logical structure, that is, some modules may be implemented by the same physical entity, or some modules may be implemented by multiple physical entities, or may be implemented by certain components in multiple independent devices.

[0138] Nouns and pronouns referring to persons in this patent application are not limited to a specific gender.

[0139] In the above embodiments, the hardware module can be implemented mechanically or electrically. For example, a hardware module can include a permanent dedicated circuit or logic (such as a dedicated processor, FPGA or ASIC) to complete the corresponding operation. The hardware module can also include programmable logic or circuits (such as a general-purpose processor or other programmable processors), which can be temporarily set by software to complete the corresponding operation. The specific implementation method (mechanical method, or dedicated permanent circuit, or temporarily set circuit) can be determined based on cost and time considerations.

[0140] The present application has been presented and described in detail above through the accompanying drawings and preferred embodiments. However, the present application is not limited to these disclosed embodiments. Based on the above multiple embodiments, those skilled in the art can know that the code review methods in the above different embodiments can be combined to obtain more embodiments of the present application, and these embodiments are also within the scope of protection of the present application.

Claims

1. A commutation ratio determination method (500) for determining a commutation ratio of a three-level active neutral point clamping structure, the method comprising: Acquire a thermal balance mapping relationship, wherein the thermal balance mapping relationship is used to indicate a mapping relationship between a power factor, a modulation index, and a thermal balance factor, and the thermal balance factor is used to indicate thermal balance of an external half-bridge module in the three-level active neutral point clamping structure; Obtaining a first power factor and a first modulation index; Determining a first thermal balance factor mapped to the first power factor and the first modulation index according to the thermal balance mapping relationship; A commutation ratio of the three-level active neutral point clamping structure is determined according to the first thermal balance factor, wherein the commutation ratio is used to indicate a ratio of the number of short commutation paths to the number of long commutation paths during operation of the three-level active neutral point clamping structure.

2. The method according to claim 1, wherein: The obtaining of the thermal balance mapping relationship comprises: Acquire a plurality of arrays including second power factors and second modulation indices, wherein at least one of the second power factors and the second modulation indices in different arrays is different; Obtaining a second thermal balance factor corresponding to the array according to a second power factor and a second modulation index included in the array; The thermal balance mapping relationship is generated according to the plurality of arrays and the second thermal balance factors corresponding to the arrays.

3. The method according to claim 2, wherein: The step of acquiring a plurality of arrays including a second power factor and a second modulation index comprises: Obtain N second power factors, wherein a difference between an i+1th second power factor and an i-th second power factor among the N second power factors is equal to a difference between an i+2th second power factor and an i+1th second power factor, where i is a positive integer greater than or equal to 1 and less than or equal to N-2, and N is a positive integer greater than or equal to 3; Obtaining N second modulation indexes, wherein a difference between an i+1th second modulation index and an i-th second modulation index among the N second modulation indexes is equal to a difference between an i+2th second modulation index and an i+1th second modulation index; The N second power factors and the N second modulation indexes are combined to obtain N 2 An array including a second power factor and a second modulation index.

4. The method according to claim 2, wherein: The step of obtaining a second thermal balance factor corresponding to the array according to the second power factor and the second modulation index included in the array comprises: Determine, according to the second modulation index included in the array, the hottest probability of the switch tube corresponding to the array, wherein the hottest probability of the switch tube is used to indicate the probability of maximum thermal stress of the switch tube in the external half-bridge module; A second thermal balance factor corresponding to the array is determined according to the second power factor included in the array and the hottest probability of the switch tube corresponding to the array.

5. The method according to claim 4, wherein: The step of determining the hottest probability of the switch tube corresponding to the array according to the second modulation index included in the array includes: The second modulation index included in the array is input into a preset mapping function to obtain the hottest probability of the switch tube corresponding to the array. The mapping function is a monotonically increasing function, and the value range of the mapping function is (0, 1).

6. The method according to claim 4, wherein: The determining, according to the second power factor included in the array and the hottest probability of the switch tube corresponding to the array, a second thermal balance factor corresponding to the array comprises: According to the second power factor included in the array and the hottest probability of the switch tube corresponding to the array, a first probability, a second probability, a third probability and a fourth probability are calculated respectively, wherein the first probability is used to indicate the probability that the thermal stress of the first switch tube in the external half-bridge module is the largest, the second probability is used to indicate the probability that the thermal stress of the second diode in the external half-bridge module is the largest, the third probability is used to indicate the probability that the thermal stress of the first diode in the external half-bridge module is the largest, and the fourth probability is used to indicate the probability that the thermal stress of the second switch tube in the external half-bridge module is the largest, the first diode is a parasitic diode of the first switch tube, and the first diode is electrically connected to the positive pole or the negative pole of the DC bus, and the second diode is a parasitic diode of the second switch tube, and the second switch tube is electrically connected to the midpoint of the DC bus; A second thermal balance factor corresponding to the array is determined according to the first probability, the second probability, the third probability and the fourth probability.

7. The method according to claim 6, wherein: The first probability, the second probability, the third probability and the fourth probability are calculated respectively according to the second power factor included in the array and the hottest probability of the switch tube corresponding to the array, including: The first probability is calculated by the following formula: P1=(0.5+0.5×PF)×m′ The second probability is calculated by the following formula: P2=(0.5+0.5×PF)×(1-m′) The third probability is calculated by the following formula: P3=(0.5-0.5×PF)×m′ The fourth probability is calculated by the following formula: P4 = (0.5-0.5×PF)×(1-m′) P1 is used to characterize the first probability, P2 is used to characterize the second probability, P3 is used to characterize the third probability, P4 is used to characterize the fourth probability, PF is used to characterize the second power factor, and m′ is used to characterize the hottest probability of the switch tube.

8. The method according to claim 6, wherein: The determining, according to the first probability, the second probability, the third probability and the fourth probability, a second thermal balance factor corresponding to the array includes: Calculating the product of the first probability, the second probability, the third probability and the fourth probability to obtain a probability product; A second thermal balance factor corresponding to the array is determined according to the probability product.

9. The method according to any one of claims 1 to 8, wherein: Determining the commutation ratio of the three-level active neutral point clamping structure according to the first thermal balance factor includes: According to the correspondence between the thermal balance factor and the commutation ratio, the commutation ratio corresponding to the first thermal balance factor is determined as the commutation ratio of the three-level active neutral point clamping structure, wherein the thermal balance factor is positively correlated with the commutation ratio in the correspondence, and the thermal balance factor is positively correlated with the thermal balance of the external half-bridge module.

10. A commutation ratio determination device (900), for determining a commutation ratio of a three-level active neutral point clamping structure, the device comprising: A first acquisition unit (901) is used to acquire a thermal balance mapping relationship, wherein the thermal balance mapping relationship is used to indicate a mapping relationship between a power factor, a modulation index and a thermal balance factor, and the thermal balance factor is used to indicate thermal balance of an external half-bridge module in the three-level active neutral point clamping structure; A second acquisition unit (902), configured to acquire a first power factor and a first modulation index; A mapping unit (903), configured to determine, according to the thermal balance mapping relationship, a first thermal balance factor mapped to the first power factor and the first modulation index; A processing unit (904) is used to determine a commutation ratio of the three-level active neutral point clamping structure according to the first thermal balance factor, wherein the commutation ratio is used to indicate a ratio of the number of short commutation paths to the number of long commutation paths during operation of the three-level active neutral point clamping structure.

11. A power converter (1000), comprising: A control unit (1001) and a three-level active midpoint clamping structure (1002); The three-level active midpoint clamping structure (1002) is electrically connected to the DC bus and the AC output terminal; The control unit (1001) is used to execute the commutation ratio determination method according to any one of claims 1 to 9, and control the ratio of the number of short commutation paths to the number of long commutation paths during the operation of the three-level active neutral point clamping structure according to the determined commutation ratio.

12. An electronic device (1100), comprising: A processor (1102), a communication interface (1104), a memory (1106) and a bus (1108), wherein the processor (1102), the communication interface (1104) and the memory (1106) communicate with each other via the bus (1108); The memory (1106) is used to store at least one executable instruction, and the executable instruction enables the processor (1102) to perform operations corresponding to the commutation ratio determination method as described in any one of claims 1-9.

13. A computer-readable storage medium having computer instructions stored thereon, wherein when the computer instructions are executed by a processor, the processor is caused to execute the method according to any one of claims 1 to 9.

14. A computer program product tangibly stored on a computer readable medium and comprising computer executable instructions which, when executed, cause at least one processor to perform the method according to any one of claims 1-9.

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