Multi pulse gate driving for power switches

Abstract

A method for operating a semiconductor switching device having a gate capacitance to switch the device from a starting steady state to an ending steady comprises: applying a first voltage pulse to a gate of the device when the device is in the starting steady state; and applying a second voltage pulse to the gate after applying the first gate driving pulse. The second voltage pulse is applied during a transition of the device between the starting steady state and the ending steady state.

Description

MULTI PULSE GATE DRIVING FOR POWER SWITCHES Cross-Reference to Related Applications

[0001] This application claims priority from US application No.63 / 546,027 filed 27 October 2023 and entitled MULTI PULSE GATE DRIVING FOR POWER SWITCHES which is hereby incorporated herein by reference for all purposes. For purposes of the United States of America, this application claims the benefit under 35 U.S.C. §119 of US application No.63 / 546,027 filed 27 October 2023 and entitled MULTI PULSE GATE DRIVING FOR POWER SWITCHES. Field

[0002] The present disclosure relates to semiconductor switching devices having a control terminal (e.g. a gate) with corresponding gage capacitance. Some embodiments provide systems and methods for driving a gate of a semiconductor transistor. Background

[0003] Gate driving circuits are an important component in switched-mode power converters. Gate driving circuits control the power semiconductor transistor switching transition slew-rates. Slew-rates refer to the maximum rate of change of the transistor output voltage with respect to time, i.e., how quickly a transistor can respond to changes in input signals. Slew-rates influence many performance metrics in hard- switched applications, including efficiency, electromagnetic compatibility (EMC), electromagnetic interference (EMI), etc.

[0004] Conventional gate driving circuits for semiconductor switching devices (e.g. transistors) having a gate capacitance typically utilize single pulse (step function) signals through a gate resistor (^^) to control turn-ON and turn-OFF slew-rates and transients of the power switch. One drawback of the conventional single pulse gate driving circuits is the limitation of slew-rate due to parasitic inductances (^^^^). If ^^is selected to be insufficiently large, the gate driving circuit will be underdamped, resulting in relatively large amounts of EMI, significant gate voltage oscillations and corresponding risk of false turn-ON events. Accordingly, in conventional single pulse circuits, there is a desire to choose ^^to be sufficiently large (to control the slew rate of the gate voltage and thereby reduce the amplitude of oscillations in gate voltage and lower the risk of false turn-ON events). However, if ^^is selected to be too large and the gate driving circuit is too overdamped, this can result in lower slew rates (lower switching times) and larger switching losses, thereby reducing operationalefficiency. The disadvantages of excessively overdamping are especially pronounced in high-frequency switching applications, where switching speed is correspondingly important.

[0005] FIG.1A is a schematic diagram of a circuit 10 for driving the gate of an enhancement mode metal oxide semiconductor field-effect transistor (MOSFET) 12 utilizing a conventional gate driving circuit incorporating gate resistor ^^. FIG.1B shows plots 20A to 20E of various circuit parameters as well as the magnitude of the switching losses over time when a conventional single pulse gate driving signal 20 is applied to circuit 10 for both turn-ON and turn-OFF operations in both underdamped (shown in dark black) and overdamped (shown in grey-scale) situations.

[0006] MOSFET 12 comprises a drain terminal 11, a source terminal 13, a gate terminal 15, and diode 17 (which may be the internal body diode 17 of MOSFET 12 and / or an external diode 17). Circuit 10 is illustrated with driving switches ^^and ^^representative of a half-bridge circuit (the rest of which is not expressly shown). The voltage measured across source terminal 13 and gate terminal 15 is denoted as ^^^and referred to herein as gate-source voltage. The voltage measured across drain terminal 11 and source terminal 13 is denoted as ^^^and referred to herein as drain- source voltage. A gate capacitance between source terminal 13 and gate terminal 15 is denoted as ^^^^. Capacitance ^^^^is typically determined by the physical and electrical properties of the MOSFET. A driving voltage ^^^is the output of a gate- control voltage source 14, which in the FIG.1A embodiment is half-bridge circuit(controlled by switches ^^ and ^^) and, in the illustrated embodiment, driving voltage^^^ is the voltage across ^^. Parasitic inductance ^^^^ is present between the gate-control voltage source 14 (the switched terminal 16 of the half bridge defined by ^^and ^^) and gate terminal 15. Inductance ^^^^is not a specific element of circuit 10, but is instead parasitically present in any conductor with relative magnetic permeability (^^) greater than zero (i.e. any conductor that creates a magnetic field when charge moves through the conductor). Sources of parasitic inductance ^^^^may include, without limitation, physical conductors, such as semiconductor traces, PCB traces, electrical wiring, bonds, busbars and connectors, etc. To dampen the above-discussed undesired oscillation in ^^^due to the parasitic inductance ^^^^, a gate resistor ^^is typically connected in series between the gate-control voltage source 14 (switched terminal 16) and gate terminal 15 in conventional gate-driving circuits. In operation, when the value of gate-source voltage ^^^exceeds thresholdvoltage ^^^(FIG.1B), a drain current ^^starts flowing between drain terminal 11 and source terminal 13.

[0007] In the FIG.1A embodiment, when driving voltage ^^^is applied in a single pulse step from some steady state voltage below the MOSFET threshold voltage ^^^(typically 0v) to some suitable step amplitude greater than ^^^, the voltage difference between driving voltage ^^^and gate-source voltage ^^^creates a current ^^that charges ^^^^over some time period until ^^^becomes greater than ^^^(a characteristic of MOSFET 12) and turns MOSFET 12 ON so that current ^^flows through MOSFET 12 from drain to source. The application of driving voltage ^^^may also be referred to as a gate driving signal herein. When driving voltage ^^^steps back down below ^^^(typically, to 0v), gate capacitance ^^^^discharges over some time period, reducing ^^^to a value below ^^^to turn MOSFET 12 OFF and, in the steady state OFF condition, current ^^drops to zero.

[0008] Referring to FIG.1B, values of circuit parameters including driving voltage ^^^(shown in plot 20A), gate-source voltage ^^^(shown in plot 20B), drain current ^^(shown in plot 20C), drain-source voltage ^^^(shown in plot 20D), and switching losses ^^^(shown in plot 20E) are shown over time for a turn-ON operation (an upward step of driving voltage ^^^) and a turn-OFF operation (a downward step of driving voltage ^^^) when circuit 10 is underdamped (dark black lines) corresponding to relatively low values of gate resistance ^^and when circuit 10 is overdamped (grey scale lines) corresponding to relatively large values of gate resistance ^^.

[0009] As shown in plots 20A-E of FIG.1B, MOSFET 12 is initially in an OFF-state, when driving voltage ^^^is stepped up (i.e. a single pulse step from some steady state voltage below the MOSFET threshold voltage ^^^(typically 0v) to some suitable step amplitude greater than ^^^) in a turn-ON operation. The application of driving voltage ^^^causes a corresponding increase in the value of gate-source voltage ^^^as discussed above. As the value of gate-source voltage ^^^exceeds the threshold voltage ^^^, current ^^starts to flow through MOSFET 12 as a conductive channel is formed between drain terminal 11 and source terminal 13. Current ^^increases until it reaches some terminal steady state ON value and, once ^^reaches its terminal steady state ON value, drain-source voltage ^^^decreases toward its terminal steady state value. Meanwhile, the value of drain-source voltage ^^^decreases to a relatively small value.

[0010] MOSFET 12 is initially in an ON (conducting) state when driving voltage ^^^isstepped down (i.e. a single pulse step from some suitable step amplitude above ^^^to an amplitude lower than ^^^(typically 0v)) in a turn-OFF operation, MOSFET 12 is initially in an ON (conducting) state. Applying driving voltage ^^^less than ^^^causes a corresponding decrease in the value of gate-source voltage ^^^, as gate capacitance ^^^^discharges. As gate-source voltage ^^^decreases, drain-source voltage ^^^increases and current ^^decreases until gate-source voltage ^^^falls below ^^^and current ^^stops flowing through MOSFET 12. In the steady state OFF state, ^^^eventually settles to some value below ^^^, ^^is zero and ^^^settles at some circuit-dependent voltage level.

[0011] Plots 20B-20E of FIG.1B illustrate two conditions: the underdamped condition (shown in dark black lines) which corresponds to relatively large gate resistance ^^; and the overdamped condition (shown in grey lines) which corresponds to relatively small gate resistance ^^. It can be observed from plot 20B, that there is significant oscillation in ^^^and corresponding voltage stress across MOSFET 12 in the underdamped condition. Plots 20B-20E show that this oscillation (if sufficiently large) can result in false turn-ON events during a turn-OFF operation. Such a false turn-ON event is shown at portion 21B of the ^^^plot 20B, where the oscillation in ^^^is of sufficient amplitude that the value of ^^^falls below and then climbs back above ^^^during a turn-OFF operation and MOSFET 12 becomes undesirably conductive (see portion 21C of ^^curve 20C and portion 21D of drain-source voltage ^^^curve 20D). False turn-ONs may lead to excessive and undesirable power loss (as shown at portion 21D) of switching power ^^^curve 20D, overheating, and even short circuits, destructive failures of the semiconductor and / or component damage.

[0012] To avoid false turn-ON events and the associated problems, it is typically desirable to choose gate resistance ^^to have a reasonable value greater than zero, but when gate resistance is large enough to create the overdamped condition, there are corresponding increases in transient times and switching power resulting in reduced efficiency. The relatively slow transients associated with overdamped condition are shown in regions 23B of the ^^^plot 20B, where ^^^takes a relatively long time to climb to its steady state level (in the turn-ON operation) and a relatively long time to fall back to zero (in the turn-OFF operation). Because of the slow rate of change of gate-source voltage ^^^in the overdamped condition, it takes longer (∆^) to transition between the ON and OFF states (see the transients of current ^^as shown at 23C and voltage ^^^as shown at 23D). These longer transients, in turn, areassociated with undesirable switching power ^^^losses as shown at 21E.

[0013] There is a general desire to provide simple-to-implement gate driving methods for semiconductor switching devices having control terminal capacitance (e.g. semiconductor transistors having gate capacitance) and circuits incorporating such methods which ameliorate one or more of the drawbacks of conventional gate driving methods, such as, by way of non-limiting example, those described above. Summary

[0014] One aspect of the invention provides a method for operating a semiconductor switching device having a gate capacitance to switch the device from a starting steady state to an ending steady state that is different from the starting steady state. The method comprises: applying a first gate-driving voltage pulse to a gate of the device when the device is in the starting steady state, the first voltage pulse having a first effective amplitude a first pulse duration ^^; and applying a second gate-driving voltage pulse to the gate after applying the first gate driving pulse, the second gate- driving voltage pulse having a second effective amplitude and a second pulse duration. The second voltage pulse is applied during a transition of the device between the starting steady state and the ending steady state.

[0015] The first effective amplitude may cross from a starting state value that is below a threshold voltage ^^^associated with the device to a first pulse value that is above the threshold voltage ^^^. The second gate-driving voltage pulse has a second effective amplitude that may cross from an intermediate value that is below the threshold voltage ^^^to a second pulse value that is above the threshold voltage ^^^.

[0016] The first effective amplitude may cross from a starting state value that is above a threshold voltage ^^^associated with the device to a first pulse value that is below the threshold voltage ^^^. The second gate-driving voltage pulse has a second effective amplitude that may cross from an intermediate value that is above the threshold voltage ^^^to a second pulse value that is below the threshold voltage ^^^.

[0017] The intermediate value may be about equal to the starting state value.

[0018] The first pulse duration ^^may be less than a time that it takes for the device to reach the ending steady state. The second gate-driving pulse has a duration that may be sufficiently long for the device to reach the ending steady state during the second gate-driving pulse.

[0019] The method may comprise maintaining the gate-driving voltage at an intermediate value for a period of time ^^after a conclusion of the first gate-drivingpulse and before applying the second gate-driving voltage pulse.

[0020] The first effective amplitude may be the same as the second effective amplitude.

[0021] The method may be applied to a turn-ON operation, where the device is non- conducting (e.g. between drain and source) in the starting steady state, the device is conducting (e.g. between drain and source) in the ending steady state, the starting state value and the intermediate value are less than the threshold voltage ^^^and thefirst pulse value and the second pulse value are greater than the threshold voltage^^^.

[0022] The method may be applied to a turn-OFF operation, where the device is conducting (e.g. between drain and source) in the starting steady state, the device is non-conducting (e.g. between drain and source) in the ending steady state, thestarting state value and the intermediate value are greater than the threshold voltage^^^ and the first pulse value and the second pulse value are less than the thresholdvoltage ^^^.

[0023] The method may comprise applying one or more additional gate-driving voltage pulses to the gate after applying the first gate driving pulse and prior to applying the second gate driving pulse. The one or more additional gate-driving pulses have the same pulse parameters (e.g. amplitude and duration) as the first pulse or different pulse parameters (e.g. amplitude and duration) from the first pulse. Temporal pulse-spacing between the first pulse, the one or more additional pulses and the second pulse may be the same or may be different.

[0024] Applying the first and second gate-driving pulses may comprise controlling a gate-control voltage source.

[0025] Controlling the gate-control voltage source may comprise controlling a half- bridge circuit having its switched terminal electrically connected to the gate.

[0026] The electrical connection between the switched terminal and the gate may be made by an electrically conductive connection wherein any resistance between the switched terminal and the gate is the inherent internal resistance of the electrically conductive connection, including, possibly, any internal driver and / or MOSFET connections of the half-bridge circuit. Any inductance between the switched terminal and the gate may be the inherent internal inductance ^^^^of the electrically conductive connection, including, possibly, any internal driver and / or MOSFET connections of the half-bridge circuit.

[0027] Applying the first pulse may comprise controlling the half-bridge circuit to provide a pulse-width modulated (PWM) signal at the switched terminal and wherein the first effective amplitude is based on one or more of the parameters (e.g. pulse amplitude, frequency and / or duty cycle) of the PWM signal. The method may comprise controlling the half-bridge circuit to vary one or more of the parameters (e.g. pulse amplitude, frequency and / or duty cycle) of the PWM signal during the first pulse duration ^^.

[0028] Applying the second pulse may comprise controlling the half-bridge to clamp the voltage at the switched terminal to the second effective amplitude when a gate current ^^is at or near zero.

[0029] Controlling the gate-control voltage source may comprise controlling a full- bridge circuit.

[0030] The full-bridge circuit may have one of its switched terminals electrically connected to the gate. The electrical connection between the one of the switched terminals and the gate may be made by an electrically conductive connection wherein any resistance between the one of the switched terminals and the gate is the inherent internal resistance of the electrically conductive connection, including, possibly, any internal driver and / or MOSFET connections of the full-bridge circuit. Any inductance between the one of the switched terminals and the gate may be the inherent internal inductance ^^^^of the electrically conductive connection, including, possibly, any internal driver and / or MOSFET connections of the full-bridge circuit.

[0031] The full-bridge circuit may comprise an inductor ^^connected between the one of the switched terminals and a second one of the switched terminals of the full- bridge.

[0032] Applying the first gate-driving pulse may comprise: controlling the full-bridge to charge the inductor ^^prior to applying the first pulse; and controlling the full-bridge to cause the inductor ^^to act as a current source when the first pulse is applied. Applying the second pulse may comprise controlling the full-bridge to clamp the voltage at the one of the switched terminals to the second effective amplitude when a gate current ^^is at or near zero.

[0033] Applying the first pulse may comprise controlling the full-bridge circuit to provide a pulse-width modulated (PWM) signal at the second one of the switched terminals and wherein the first effective amplitude is based on one or more of the parameters (e.g. pulse amplitude, frequency and / or duty cycle) of the PWM signal.The method may comprise controlling the full-bridge circuit to vary one or more of the parameters (e.g. pulse amplitude, frequency and / or duty cycle) of the PWM signal during the first pulse duration ^^. Applying the second pulse may comprise controlling the full-bridge to clamp the voltage at the one of the switched terminals to the second effective amplitude when a gate current ^^is at or near zero.

[0034] The method may comprise repeatedly applying the method to switch the device from the starting state to the ending state and to switch the device from the ending state back to the starting state.

[0035] The repeated application of the method may be used in one of: a switch-mode power supply; a digital communication circuit; a discrete amplifier; a signal conditioning crcuit; a LED drive; and a digital clock.

[0036] The method may comprise: sensing a value of at least one of a voltage at a node of the device and a current through a node of the device; and adjusting one or more parameters of at least one of the first gate-driving pulse and the second gate- driving pulse based at least in part on the sensed value. The node of the device may be one of a gate, a source or a drain of a transistor.

[0037] The method may comprise: sensing a temperature correlated with a temperature of the device; and adjusting one or more parameters of at least one of the first gate-driving pulse and the second gate-driving pulse based at least in part on the sensed value.

[0038] Adjusting the one or more parameters of at least one of the first gate-driving pulse and the second gate-driving pulse based at least in part on the sensed value may be performed by a controller. The controller may be configured to implement a control algorithm based at least in part on a desired value for the sensed value.

[0039] The one or more parameters of the at least one of the first gate-driving pulse and the second gate-driving pulse may comprise: the first pulse duration ^^; the first effective amplitude; a period of time ^^after a conclusion of the first gate-driving pulse and before applying the second gate-driving voltage pulse during which the gate- driving voltage is maintained at the intermediate value; and / or the second effective amplitude.

[0040] Applying the first gate-driving pulse may comprise applying a first series of pulse-width modulated (PWM) voltage pulses to the gate, the first series of pulse- width modulated voltage pulses having first PWM parameters (e.g. a first PWM frequency, a first PWM duty cycle and / or a first PWM amplitude) which achieve thefirst effective amplitude. The one or more parameters of the at least one of the first gate-driving pulse and the second gate-driving pulse may comprise at least one of the first PWM parameters.

[0041] Applying the second gate-driving pulse may comprise applying a second series of pulse-width modulated (PWM) voltage pulses to the gate, the second series of pulse-width modulated voltage pulses having second PWM parameters (e.g. a second PWM frequency, a second PWM duty cycle and / or a second PWM amplitude) which achieve the second effective amplitude. The one or more parameters of the at least one of the first gate-driving pulse and the second gate-driving pulse may comprise at least one of the second PWM parameters.

[0042] Another aspect of the invention provides a circuit for operating a semiconductor switching device having a gate capacitance to switch the device from a starting steady state to an ending steady state that is different from the starting steady state. The circuit comprises: a gate-control voltage source connected to a gate of the transistor by an electrically conductive (e.g. metal) connection between an output of the gate-control voltage source and the gate; and a controller connected to the gate-control voltage source, the controller configured to: cause the gate-control voltage source to apply a first gate-driving voltage pulse to a gate of the device when the device is in the starting steady state, the first voltage pulse having a first effective amplitude a first pulse duration ^^; and cause the gate-control voltage source to apply a second gate-driving voltage pulse to the gate after applying the first gate driving pulse, the second gate-driving voltage pulse having a second effective amplitude and a second pulse duration. The second voltage pulse is applied during a transition of the device between the starting steady state and the ending steady state.

[0043] The gate-control voltage source may comprise a half-bridge circuit comprising a pair of switches and a switched terminal therebetween, the switched terminal electrically connected to the gate by the electrically conductive connection.

[0044] Any resistance between the switched terminal and the gate may be the inherent internal resistance of the electrically conductive connection, including, possibly, any internal driver and / or MOSFET connections of the half-bridge circuit. Any inductance between the switched terminal and the gate may be the inherent internal inductance ^^^^of the electrically conductive connection, including, possibly, any internal driver and / or MOSFET connections of the half-bridge circuit.

[0045] The controller may be configured to cause the gate-control voltage source toapply the first pulse by controlling the switches of the half-bridge circuit to provide a pulse-width modulated (PWM) signal at the switched terminal and wherein the first effective amplitude is based on one or more of the parameters (e.g. pulse amplitude, frequency and / or duty cycle) of the PWM signal. The controller may be configured to control the switches of the half-bridge circuit to vary one or more of the parameters (e.g. pulse amplitude, frequency and / or duty cycle) of the PWM signal during the first pulse duration ^^.

[0046] The controller may be configured to cause the gate-control voltage source to apply the second pulse by controlling the switches of the half-bridge circuit to clamp the voltage at the switched terminal to the second effective amplitude when a gate current ^^is at or near zero.

[0047] The gate-control voltage source may comprise a full-bridge circuit comprising a pair of branches, each branch comprising a pair of switches and a switched terminal therebetween. One of the switched terminals of the full-bridge circuit may be electrically connected to the gate. The electrical connection between the one of the switched terminals and the gate may be made by an electrically conductive connection wherein any resistance between the one of the switched terminals and the gate may be the inherent internal resistance of the electrically conductive connection, including, possibly, any internal driver and / or MOSFET connections of the full-bridge circuit. Any inductance between the one of the switched terminals and the gate may be the inherent internal inductance ^^^^of the electrically conductive connection, including, possibly, any internal driver and / or MOSFET connections of the full-bridge circuit.

[0048] The full-bridge circuit may comprise an inductor ^^connected between the switched terminals of the full-bridge.

[0049] The controller may be configured to cause the gate-control voltage source toapply the first pulse by controlling the switches of the full-bridge to charge the inductor^^ prior to applying the first pulse; and controlling the switches of the full-bridge tocause the inductor ^^to act as a current source when the first pulse is applied. The controller may be configured to cause the gate-control voltage source to apply the second pulse by controlling the switches of the full-bridge to clamp the voltage at theone of the switched terminals to the second effective amplitude when a gate current^^ is at or near zero.

[0050] The controller may be configured to cause the gate-control voltage source toapply the first pulse by controlling the switches of the full-bridge circuit to provide a pulse-width modulated (PWM) signal at the second one of the switched terminals and wherein the first effective amplitude is based on one or more of the parameters (e.g. pulse amplitude, frequency and / or duty cycle) of the PWM signal. The controller may be configured to control the switches of the full-bridge circuit to vary one or more of the parameters (e.g. pulse amplitude, frequency and / or duty cycle) of the PWM signal during the first pulse duration ^^. The controller may be configured to cause the gate- control voltage source to apply the second pulse by controlling the switches of the full-bridge to clamp the voltage at the one of the switched terminals to the second effective amplitude when a gate current ^^is at or near zero.

[0051] The first effective amplitude may cross from a starting state value that is below a threshold voltage ^^^associated with the device to a first pulse value that is above the threshold voltage ^^^. The second gate-driving voltage pulse has a second effective amplitude that may cross from an intermediate value that is below the threshold voltage ^^^to a second pulse value that is above the threshold voltage ^^^.

[0052] The first effective amplitude may cross from a starting state value that is above a threshold voltage ^^^associated with the device to a first pulse value that is below the threshold voltage ^^^. The second gate-driving voltage pulse has a second effective amplitude that may cross from an intermediate value that is above the threshold voltage ^^^to a second pulse value that is below the threshold voltage ^^^.

[0053] The intermediate value may be about equal to the starting state value.

[0054] The controller may configured to control the first pulse duration ^^to be less than a time that it takes for the device to reach the ending steady state. The controller may be configured to control the second gate-driving pulse have a duration that is sufficiently long for the device to reach the ending steady state during the second gate-driving pulse.

[0055] The controller may be configured to maintain the gate-driving voltage at an intermediate value for a period of time ^^after a conclusion of the first gate-driving pulse and before causing the gate-control voltage source to apply the second gate- driving voltage pulse.

[0056] The first effective amplitude may be the same as the second effective amplitude.

[0057] The controller may be configured to implement a turn-ON operation, where the device is non-conducting (e.g. between drain and source) in the starting steady state,the device is conducting (e.g. between drain and source) in the ending steady state,the starting state value and the intermediate value are less than the threshold voltage^^^ and the first pulse value and the second pulse value are greater than thethreshold voltage ^^^.

[0058] The controller may be configured to implement a turn-OFF operation, where the device is conducting (e.g. between drain and source) in the starting steady state, the device is non-conducting (e.g. between drain and source) in the ending steady state, the starting state value and the intermediate value are greater than the threshold voltage ^^^and the first pulse value and the second pulse value are less than the threshold voltage ^^^.

[0059] The controller may be configured to apply one or more additional gate-driving voltage pulses to the gate after applying the first gate driving pulse and prior to applying the second gate driving pulse. The one or more additional gate-driving pulses have the same pulse parameters (e.g. amplitude and duration) as the first pulse or different pulse parameters (e.g. amplitude and duration) from the first pulse.

[0060] Temporal pulse-spacing between the first pulse, the one or more additional pulses and the second pulse may be the same or different.

[0061] The controller may be configured to repeatedly switch the device from the starting state to the ending state and to switch the device from the ending state back to the starting state.

[0062] The circuit may be used in one of: a switch-mode power supply; a digital communication circuit; a discrete amplifier; a signal conditioning crcuit; a LED drive; and a digital clock.

[0063] The circuit may comprise a sensor connected to sense a value of at least one of a voltage at a node of the device and a current through a node of the device. The controller may be configured to adjust one or more parameters of at least one of the first gate-driving pulse and the second gate-driving pulse based at least in part on the sensed value. The node of the device may be one of a gate, a source or a drain of a transistor.

[0064] The circuit may comprise a sensor connected to sense a temperature correlated with a temperature of the device. The controller may be configured to adjust one or more parameters of at least one of the first gate-driving pulse and the second gate-driving pulse based at least in part on the sensed value.

[0065] The controller may be configured to implement a control algorithm based atleast in part on a desired value for the sensed value.

[0066] The one or more parameters of the at least one of the first gate-driving pulse and the second gate-driving pulse may comprise: the first pulse duration ^^; the first effective amplitude; a period of time ^^after a conclusion of the first gate-driving pulse and before applying the second gate-driving voltage pulse during which the gate- driving voltage is maintained at the intermediate value; and / or the second effective amplitude.

[0067] The controller may be configured to apply the first gate-driving pulse by applying a first series of pulse-width modulated (PWM) voltage pulses to the gate, the first series of pulse-width modulated voltage pulses having first PWM parameters (e.g. a first PWM frequency, a first PWM duty cycle and / or a first PWM amplitude) which achieve the first effective amplitude. The one or more parameters of the at least one of the first gate-driving pulse and the second gate-driving pulse may comprise at least one of the first PWM parameters.

[0068] The controller may be configured to apply the second gate-driving pulse by applying a second series of pulse-width modulated (PWM) voltage pulses to the gate, the second series of pulse-width modulated voltage pulses having second PWM parameters (e.g. a second PWM frequency, a second PWM duty cycle and / or a second PWM amplitude) which achieve the second effective amplitude. The one or more parameters of the at least one of the first gate-driving pulse and the second gate-driving pulse may comprise at least one of the second PWM parameters.

[0069] Other aspects of the invention provide apparatus having any new and inventive feature, combination of features, or sub-combination of features as described herein.

[0070] Other aspect of the invention provide methods having any new and inventive steps, acts, combination of steps and / or acts or sub-combination of steps and / or acts as described herein.

[0071] It is emphasized that the invention relates to all combinations of the above features, even if these are recited in different claims.

[0072] Further aspects and example embodiments are illustrated in the accompanying drawings and / or described in the following description. Brief Description of the Drawings

[0073] The accompanying drawings illustrate non-limiting example embodiments of the invention.

[0074] FIG.1A is a schematic circuit diagram for driving an enhancement mode metal oxide semiconductor field-effect transistor (MOSFET) utilizing a conventional gate driving circuit incorporating a gate resistance ^^.

[0075] FIG.1B shows plots of various circuit parameters as well as the magnitude of the switching losses over time when a conventional single pulse (step function) gate- driving signal ^^^is applied to the FIG.1A circuit for both turn-ON and turn-OFF operations in both underdamped and overdamped situations.

[0076] FIG.2A is a schematic circuit diagram of an enhancement mode metal oxide semiconductor field-effect transistor (MOSFET) suitable for use with a multi-pulse gate-driving methodology according to a particular embodiment of the invention.

[0077] FIG.2B shows plots of various circuit parameters as well as the magnitude of the switching losses over time when a multi-pulse gate-driving signal ^^^is applied to the FIG.2A circuit for both turn-ON and turn-OFF operations.

[0078] FIG.3 is a flowchart of a method for driving the gate of a semiconductor transistor having a gate capacitance according to an example embodiment.

[0079] FIG.4A is a schematic circuit diagram of an enhancement mode metal oxide semiconductor field-effect transistor (MOSFET) and a corresponding gate-driving circuit suitable for use with the multi-pulse gate-driving methodology of FIGS 2A and 3 according to a particular embodiment of the invention. FIG.4B shows a plurality of operational modes of the FIG.4A gate-driving circuit 300. FIG.4C shows a simplified equivalent gate-driving circuit corresponding to the FIG.4A gate-driving circuit.

[0080] FIG.5 shows a plurality of plots of various circuit parameters of the FIG.4A gate-driving circuit during a turn-ON operation according to a particular embodiment.

[0081] FIG.6A shows a normalized state plane plot during time period ^^shown in FIG.5. FIG.6B shows a normalized state plane plot 500B during time period ^^shown in FIG.5.

[0082] FIG.7 shows a plurality of plots of various circuit parameters of the FIG.4A gate-driving circuit during a turn-OFF operation according to a particular embodiment.

[0083] FIG.8A shows a normalized state plane plot during time period ^^shown in FIG.7. FIG.8B shows a normalized state plane plot 500B during time period ^^shown in FIG.7.

[0084] FIG.9 is a schematic illustration of a method for determining the parameters ^^and ^^according to particular embodiment including an optional fine turning adjustment method using an additional incremental time-adjustment parameter ^.

[0085] FIGS.10A, 10B, 10C (collectively, FIG.10) illustrate a comparison of the traditional approach (using single step function gate-drive signal ^^^and a gate resistance ^^) for the underdamped condition (FIG.10A) and the overdamped condition (FIG.10B) applied to the FIG.1A circuit and the mutli-pulse approach shown in FIGS.5, 7 applied to the circuit of FIG.4A.

[0086] FIG.11A is a schematic circuit diagram of full H-bridge (also known as a full- bridge or full H-bridge) configuration which can be used to provide a multi-pulse gate- driving methodology according to a particular embodiment of the invention which can operate in a number of operating modes. FIG.11B is a schematic illustration of a number of circuit parameters of the FIG.11A full-bridge circuit when operating in an operating mode A which is equivalent to the half-bridge configuration described elsewhere herein. FIG.11C is a schematic illustration of a number of circuit parameters of the FIG.11A full-bridge circuit when operating in an operating mode B. FIG.11D is a schematic illustration of a number of circuit parameters of the FIG.11A full-bridge circuit when operating in an operating mode C. FIG.11E is a schematic illustration of a number of circuit parameters of the FIG.11A full-bridge circuit in an example implementation wherein a variation of PWM duty cycle is used during the first pulse of a turn-ON operation.

[0087] FIG.12 is a schematic depiction of a closed loop system which involves measurement of one or more variables and feeding back this information to a controller which can be configured to implement a suitable control mechanism to adapt the multi-pulse parameters of the ^^^gate-driving pulses according to a particular embodiment.

[0088] FIGS.13A, 13B and 13C (collectively FIG.13) respectively depict a window comparator circuit implementing feedback according to a particular embodiment, waveforms for various parameters when the transferred charge is too low and waveforms for various parameters when the transferred charge is too high.

[0089] FIG.14 is a flow chart illustrating a methodology 930 that may be used to implement the ^^feedback illustrated in the FIG.13A circuit according to a particular embodiment. Detailed Description

[0090] Throughout the following description, specific details are set forth in order to provide a more thorough understanding of the invention. However, the invention maybe practiced without these particulars. In other instances, well known elements have not been shown or described in detail to avoid unnecessarily obscuring the invention. Accordingly, the specification and drawings are to be regarded in an illustrative, rather than a restrictive sense.

[0091] Various aspects of the invention provide gate driving circuits and associated control terminal (e.g. gate) driving methodologies involving the application of multi- pulse gate driving signals ^^^to control the switching operation a semiconductor switching device (e.g. a semiconductor) transistor. In some embodiments, these multi-pulse gate-driving signals are used to provide relatively fast transients (and corresponding switching power efficiency) when compared to the overdamped condition resulting from the gate resistance ^^used in prior art techniques while reducing the amplitude of oscillation (and the corresponding risk of false turn-ON events) when compared to the underdamped condition resulting from the gate resistance ^^used in prior art techniques.

[0092] Some aspects of the invention provide a method for operating a semiconductor switching device having a gate capacitance to switch the device from a starting steady state to an ending steady state. The method comprises: applying a first gate-driving voltage pulse to a gate of the device when the device is in the starting steady state, the first voltage pulse having a first effective amplitude a first pulse duration; and applying a second gate-driving voltage pulse to the gate after applying the first gate driving pulse, the second gate-driving voltage pulse having a second effective amplitude and a second pulse duration. The second voltage pulse may be applied during a transition of the device between the starting steady state and the ending steady state.

[0093] FIG.2A is a schematic diagram of a circuit 110 for driving the gate of an enhancement mode MOSFET 12 suitable for use with a multi-pulse gate-driving methodology according to a particular embodiment of the invention. MOSFET 12 of and gate-control voltage source 14 circuit 110 may be the same as MOSFET 12 and gate-control voltage source 14 described above in connection with FIG.1A. Circuit 110 differs from circuit 10 primarily in that circuit 110 dispenses with gate resistor ^^between the switched half-bridge terminal 16 and gate 15 and, in a different approach, uses a multi-pulse gate driving signal ^^^described in more detail below. In some embodiments, switched half-bridge terminal 16 is connected to directly to gate node 15 by an electrically conductive (e.g. metal) connection – e.g. anyresistance between half-bridge terminal 16 and gate node 15 is the inherent internal resistance of the electrically conductive connection (including, possibly, any internal driver and / or MOSFET connections (e.g. of gate-control voltage source 14 or the half- bridge circuit)) and inductance ^^^^is the inherent or parasitic inductance of this conductive connection (including, possibly, any internal driver and / or MOSFET connections (e.g. of gate-driving voltage source 14 or the half-bridge)).

[0094] FIG.2B shows plots of various circuit parameters as well as the magnitude of the switching losses over time when a multi-pulse gate-driving signal ^^^is applied to the FIG.2A circuit 110 for both turn-ON and turn-OFF operations. In particular, in the illustrated embodiment, plot 200A shows a multi-pulse gate-driving signal ^^^comprising a plurality (e.g. two in the case of the illustrated embodiment of FIGS.2A, 2B but optionally more than two) pulses for the turn-ON operation and a plurality (e.g. two in the case of the illustrated embodiment of FIGS.2A, 2B but optionally more than two) pulses for a turn-OFF operation. Plot 200A’ shows expanded detail of the plot 200A multi-pulse gate-driving signal ^^^according to the particular multi-pulse profile of the illustrated embodiment.

[0095] Plot 200A’ illustrates a number of parameters ^^, ^^"", ^^, ^^which may be used to characterize the particular plot 200A multi-pulse gate-driving signal ^^^. In the particular case of the FIG.2B embodiment, a turn-ON operation comprises a pair of pulses 210, 212 of the gate-driving signal ^^^, where each pulse 210, 212 has an amplitude ranging from ^^""to ^^, where ^^""is less than ^^^(e.g.0v) and ^^is greater than ^^^. First turn-ON pulse 210 comprises a rising edge 214 from ^^""to ^^and a duration of ^^followed by a falling edge 216 where gate-driving signal ^^^stepsback down from ^^ to ^^"". After a period ^^, where gate-driving signal ^^^ stays at^^"", second turn-ON pulse 212 has a rising edge 218 from ^^""to ^^and stays at^^ for any suitable period for which it is desired that MOSFET 12 be in a conductingstate.

[0096] Similarly, in the particular case of the FIG.2B embodiment, a turn-OFF operation comprises a pair of pulses 220, 222 of the gate-driving signal ^^^, where each pulse 220, 222 has an amplitude ranging from ^^to ^^"", where ^^""is less than ^^^(e.g.0v) and ^^is greater than ^^^. First turn-OFF pulse 220 comprises a falling edge 224 from ^^to ^^""and a duration of ^^followed by a rising edge 226 where gate-driving signal ^^^steps back up from ^^""to ^^. After a period ^^, wheregate-driving signal ^^^stays at ^^, second turn-ON pulse 212 has a falling edge 228 from ^^to ^^""and stays at ^^""for any suitable period for which it is desired that MOSFET 12 be in a non-conducting state. In some embodiments, the multi-pulse parameters ^^, ^^"", ^^, ^^are the same for both the turn-ON operation and the turn- OFF operation, but this is not necessary. In some embodiments, one or more of these parameters is different as between the turn-ON operation and the turn-OFF operation.

[0097] As can be seen from plots 200B-200E in FIG.2B, the multi-pulse gate-driving signal ^^^shown in plot 200A (when compared to the prior art single-pulse (step function) gate driving signal shown in FIGS.1A, 1B) achieves reduced voltage stress and reduced oscillations in ^^^, while operating at high slew rates (fast transients) of current ^^and drain-source voltage ^^^with consequent low switching power ^^^losses. Also, because of the relatively low oscillation in ^^^(when compared to the prior art single-pulse (step function) gate driving signal shown in FIGS.1A, 1B), there is relatively little risk of false turn-ON during the turn-OFF operation in contrast to the underdamped scenario shown in FIG.1B.

[0098] FIG.3 is a flowchart of a method 100 for driving the control terminal of a semiconductor switching device (e.g. the gate of a semiconductor transistor) having a gate capacitance according to an example embodiment. The semiconductor switch controlled in accordance with method 100 may, for example, be MOSFFET 12 shown in FIGS.2A, 2B although this is not necessary. Method 100 may be used to drive the control terminals (referred to herein as “gates” for brevity) of other semiconductor switching devices. By way of non-limiting example, such devices may include thyristors, transistors, such as gate turn-off Thyristors (GTO), MOS-controlled thyristors (MCT) and integrated gate-commutated thyristors (IGCT), bipolar junction transistors (BJT) with anti-parallel diodes, insulated-gate bipolar transistors (IGBT), field-effect transistors (FETs) like enhancement-mode and / or depletion-mode metal- oxide-semiconductor (MOS-FET), Gallium Nitride (GaN-FET), Silicon Carbide metal- oxide-semiconductor (SiC MOSFET), V-groove metal-oxide semiconductor (VMOS), junction-gate field-effect transistors (JFET) or high electron-mobility transistors (HEMT), based on IV-IV or III-V semiconductor materials like silicon (Si), siliconcarbide (SiC), silicon-germanium (SiGe), gallium-nitride (GaN), gallium-arsenid (GaAs), gallium-oxide (GaO).

[0099] For the sake of brevity and without loss of generality, the following description utilizes a silicon-MOSFET as an example of a semiconductor switching device andrefers to the control terminal of the switching device as the gate of the device for brevity. However, the methods and circuits described herein are applicable to other controllable semiconductor switching devices with gate capacitance.

[0100] The semiconductor device (e.g. transistor 12) controlled in method 100 may be characterized as being in one of three states for any switching operation: a starting state 103, a transition state 105 (occasionally referred to as “transition” herein), and an ending state 107. Starting state 103 may be a steady state. Starting state 103 may be a steady state ON state (e.g. where the transistor being controlled is conducting in a steady state) or a steady state OFF state (e.g. where the transistor is being controlled is non-conducting in a steady state). Ending state 107 may also be a steady state. Ending state 107 may be a steady state ON state or a steady state OFF state. For example, in a turn-ON operation, starting state 103 is in a steady state OFF state (e.g. the transistor being controlled is non-conducting) and ending state 107 is in a steady state ON state (e.g. the transistor being controlled is conducting). Conversely, in a turn-OFF operation, starting state 103 is in a steady state ON state (e.g. the transistor being controlled is conducting) and ending state 107 is in a steady state OFF state (e.g. the transistor being controlled is non-conducting). Transition state 105 may be defined to be the state of the semiconductor transistor between starting state 103 and ending state 107. The switching of the transistor between starting steady state 103 and ending steady state 107 may be referred to as commutation.

[0101] By way of non-limiting example, a semiconductor transistor in an “ON steady state” (sometimes referred to herein as an ON state for brevity), in the context of this disclosure, may mean meeting one or more of the following conditions for a period of time that is at least as long as the period of the resonant tank defined by the parasitic inductance of the gate terminal and the gate capacitance (e.g. by ^^^^and ^^^^): • a value of gate-source voltage ^^^of the semiconductor transistor has converged to within ± 5% or ± 10% or ± 15% of a desired gate-source voltage^^^ ON value ^^^_^ , where the ON value ^^^_^ is a configurable operationalparameter which is greater than ^^^and may be specific to any given circuit and / or transistor; • a value of gate current ^^into the gate of the transistor has converged to near zero (e.g. within ± 5% or ± 10% or ± 15% of the leakage gate current of transistor 12); and• a value of the current ^^through the transistor has converged to within ± 5% or ± 10% or ± 15% of a desired operational value of drain current ^^_^, where the desired operational value of drain current ^^_^is a configurable operational parameter which may be specific to any given circuit and / or transistor.

[0102] By way of non-limiting example, a semiconductor transistor in an “OFF steady state” (sometimes referred to herein as an OFF state for brevity), in the context of this disclosure, may mean meeting one or more of the following conditions for a period of time that is at least as long as the period of the resonant tank defined by the parasitic inductance of the gate terminal and the gate capacitance (e.g. by ^^^^and ^^^^): • a value of gate-source voltage ^^^of the semiconductor transistor has converged to within ± 5% or ± 10% or ± 15% of a desired gate-source voltage^^^ OFF value ^^^_^"", where the OFF value ^^^_^"" is a configurableoperational parameter which is less than ^^^and may be specific to any given circuit and / or transistor; • a value of gate current ^^has converged to near zero (e.g. within ± 5% or ± 10% or ± 15% of the leakage gate current of transistor 12) ; and • a value of the current ^^through the transistor has converged to approximately zero (e.g. within ± 5% or ± 10% or ± 15% of the drain-to-source leakage current of transistor 12).

[0103] Method 100 begins with the transistor 12 in a starting state 103. Method 100 comprises performing step 102 of providing a first gate-driving voltage pulse (e.g. first pulse 210 of a turn-ON operation or first pulse 220 of a turn-OFF operation) having a first effective amplitude. The first gate-driving voltage pulse may be provided when the transistor is in a starting state 103. The first effective amplitude of the first voltage pulse may comprise any suitable amplitude and, in some embodiments, may be sufficient to cause ^^^to cross the threshold voltage ^^^of MOSFET 12. In a non- limiting example embodiment of a turn-ON operation, the first effective amplitude of the first gate-driving voltage pulse may be from ^^""to ^^(see rising edge 214 of first turn-ON pulse 210 of plot 200A’ of FIG.2B), where ^^""is less than ^^^(e.g.0v) and ^^is greater than ^^^. In a non-limiting example embodiment of a turn-OFF operation, the first gate-driving voltage pulse may be a negative voltage pulse with an effective amplitude from ^^to ^^""(see falling edge 224 of first turn-OFF pulse 220 of plot 200A’ of FIG.2B), where, in some embodiments, ^^""is less than ^^^(e.g.0v)and ^^is greater than ^^^. The gate-driving signal ^^^may be described as being a gate-discharging signal during a turn-OFF operation. The first gate-driving voltage pulse may have a duration (e.g. ^^in the FIG.2B embodiment) after which the gate- driving signal returns to some intermediate value which may be the value that it had in starting state 103. For example, in the non-limiting example embodiment of a turn-ON operation shown in FIG.2B, first turn-ON pulse 210 may return from ^^to ^^""(see falling edge 216 of first turn-ON pulse 210 of plot 200A’ of FIG.2B) – i.e. ^^""is the intermediate value between pulses. In the non-limiting example embodiment of a turn- OFF operation shown in FIG.2B, first turn-OFF pulse 220 may return from ^^""to ^^(see rising edge 226 of first turn-OFF pulse 220 of plot 200A’ of FIG.2B) – i.e. ^^is the intermediate value between pulses.

[0104] The first gate-driving voltage pulse may have a duration (e.g. ^^in the FIG.2B embodiment) that is less than the time required for the transistor (e.g. MOSFET 12) to transition from starting state 103 to ending state 107, so that the transistor is in transition state 105 at the end of the first pulse when the gate-driving signal returns to the intermediate value (e.g. the value that it had in starting state 103). As discussed elsewhere herein, the durations of the first gate driving pulses 210, 220 in the exemplary FIG.2B turn-ON operation and in the exemplary FIG.2B turn-OFF operation are shown as being equal (e.g. ^^in the FIG.2B embodiment), but this is not necessary and the durations of the first gate-driving pulses can be different as between turn-ON and turn-OFF operations. As explained in more detail below, in some embodiments, the first voltage pulse comprises a pulse width modulated (PWM) signal and the first “effective” amplitude of the first gate-driving pulse is based on (e.g. a product of) a duty cycle and amplitude of the PWM signal.

[0105] Returning to FIG.3, method 100 then proceeds with step 104 of providing a second gate-driving voltage pulse (e.g. second pulse 212 of a turn-ON operation or second pulse 222 of a turn-OFF operation in the illustrated embodiment of FIG.2B) having a second effective amplitude. The second gate-driving voltage pulse is applied (i.e. starts) during transition 105 of the semiconductor transistor between starting state 103 and ending state 107. In the illustrated embodiment, there is a delay (e.g. ^^in the FIG.2B embodiment) between the end of the first gate-driving voltage pulse and the start of the second gate-driving voltage pulse. During this delay, the gate- driving voltage may have an intermediate value. The intermediate value may be on the same side of ^^^as the value in starting state 103. For example, if the gate-driving voltage was below ^^^at starting state 103, then the intermediate value of the gate-driving voltage may return below ^^^or, if the gate-driving voltage was above ^^^at starting state 103, then the intermediate value of the gate-driving voltage may return to a value above ^^^. In the illustrated FIG.2B embodiment, the intermediate value of the gate-driving voltage between the first and second pulses (e.g. during the time ^^in the FIG.2B embodiment) is the same value that it had in starting state 103. For example, in the non-limiting example embodiment of a turn-ON operation shown in FIG.2B, during the delay between falling edge 216 of first turn-ON pulse 210 and rising edge 218 of second turn-ON pulse 212, the gate drive signal may have the value ^^"". In the example non-limiting example embodiment of a turn-OFF operation shown in FIG.2B, during the delay between rising edge 226 of first turn-OFF pulse 220 and falling edge 228 of second turn-OFF pulse 222, the gate drive signal may have the value ^^. The temporal spacing between the end of the first pulse and the start of the second pulse (e.g. ^^in the FIG.2B embodiment) may be less than the time required for the transistor to transition from transition state 105 back to starting state 103, so that the second pulse is applied (i.e. starts) when the transistor is still in transition state 105. As discussed elsewhere herein, the durations of the delays between the first and second gate driving pulses 210, 212 in the exemplary FIG.2B turn-ON operation and between the first and second gate driving pulses 220, 222 in the exemplary FIG.2B turn-OFF operation are shown as being equal (e.g. ^^in the FIG.2B embodiment), but this is not necessary and the durations of the delays between first and second gate-driving pulses can be different as between turn-ON and turn-OFF operations.

[0106] The second effective amplitude of the second voltage pulse may comprise any suitable amplitude and, in some embodiments, may be sufficient to cause ^^^to cross the threshold voltage ^^^of MOSFET 12. In a non-limiting example embodiment of a turn-ON operation, the second effective amplitude of the second gate-driving voltage pulse may be from ^^""to ^^(see rising edge 218 of second turn-ON pulse 212 ofplot 200A’ of FIG. 2B), where ^^"" is less than ^^^ (e.g. 0v) and ^^ is greater than^^^. In a non-limiting example embodiment of a turn-OFF operation, the second gate-driving voltage pulse may be a negative voltage pulse with a second effective amplitude from ^^to ^^""(see falling edge 228 of second turn-OFF pulse 222 of plot 200A’ of FIG.2B), where ^^""is less than ^^^(e.g.0v) and ^^is greater than ^^^. The gate-driving signal ^^^may be described as being a gate-discharging signalduring a turn-OFF operation.

[0107] The second gate-driving voltage pulse may have a duration that is greater than the time required for the transistor (e.g. MOSFET 12) to transition from transition state 105 to ending state 107, so that the transistor reaches ending state 107 during the second pulse. As explained in more detail below, in some embodiments, the second voltage pulse comprises a pulse width modulated (PWM) signal and the second “effective” amplitude is based on (e.g. a product of) a duty cycle and amplitude of the PWM signal.

[0108] In the example embodiment of FIG.2B, during the turn-ON operation which involves first pulse 210 and second pulse 212, it can be observed that starting state 103 of MOSFET 12 is steady state OFF (non-conducting) state prior to the application of first pulse 210, that second pulse 212 starts when MOSFET 12 is in a transition state 105 and that ending state 107 of MOSFET 12 is a steady state ON (conducting) state which is reached during the second voltage pulse 212. During the turn-OFF operation which involves first pulse 220 and second pulse 222, it can be observed that starting state 103 of MOSFET 12 is a steady state ON (conducting) state prior to the application of first pulse 220, that second pulse 222 starts when MOSFET 12 is in a transition state 105 and that ending state 107 of MOSFET 12 is a steady state OFF (non-conducting) which is reached during the second voltage pulse 212.

[0109] In some embodiments, additional gate-driving pulses may be applied when the transistor is in transition state 105 (e.g. between the first voltage pulse which is applied when the transistor is in starting state 103 and the second voltage pulse which is applied when the transistor is in transition state 105 but lasts until the transistor is in the ending state 107 as described above). Such additional gate-driving pulses may have the same or different pulse parameters (e.g. pulse amplitude, effective pulse amplitude, pulse voltage levels, pulse duration, temporal pulse separation, pulse frequency, pulse duty cycle, charge time and / or the like) than each other and / or than the first and second pulses of the FIG.2B embodiment. Any of these gate-driving pulse parameters may be tunable or actively controlled or controllable. Examples, of tuning and controlling gate-driving pulse parameters are described below.

[0110] In the embodiments described herein the gate-driving voltage source is connected directly to the gate of the device being controlled. In some embodiments, it may be desirable to provide one or more additional components (e.g. inductors,resistors and / or the like) in series between the gate-driving voltage source and the gate to provide design flexibility. In some embodiments, it may be desirable to provide one or more additional components (e.g. capacitors, diodes and / or the like) in parallel between the gate and the source to provide design flexibility. Example Embodiments

[0111] FIG.4A is a schematic circuit diagram of an enhancement mode metal oxide semiconductor field-effect transistor (MOSFET) 12 and a corresponding gate-driving circuit 300 suitable for use with the multi-pulse gate-driving methodology of FIGS 2A and 3 according to a particular embodiment of the invention. MOSFET 12 of the FIG. 4A embodiment may be substantially similar to MOSFET 12 described elsewhere herein and comprises a drain terminal 11, a source terminal 13, a gate terminal 15 and an internal body diode 17. Gate-driving circuit 300 is supplied by a gate-control voltage source 14 which may be substantially similar to gate-control voltage source 14 described herein and, in the case of the illustrated embodiment, comprise a half- bridge topology comprising switches ^^and ^^. FIG.4A and circuit 300 are similar to FIG.2A and circuit 110, except and circuit 300 explicitly show the gate-to-source capacitance ^^^, the gate-to-drain capacitance ^^^and the drain-to-source capacitance ^^^which are associated with the physical and electrical properties of MOSFET 12; and, in circuit 300, the parasitic inductance ^^^^associated with the gate drive is replaced with and inductance ^^to indicate that this inductance ^^may comprise a combination of parasitic inductance and added inductance such that to some degree the inductance ^^is actually a controllable parameter of the FIG.4A circuit 300. FIG.4B shows a plurality of six operational modes or states (identified by Roman numerals I, II, III, IV, V and VI) of the FIG.4A gate-driving circuit 300. FIG.4C shows a simplified equivalent gate-driving circuit 300E of gate-driving circuit 300 of FIG.4A.

[0112] Each of the plurality of modes I-VI of the FIG.4B gate-driving circuit 300 can be represented with FIG.4C equivalent circuit 300E with gate-driving voltage ^^^andequivalent capacitance ^$ for each state described by:%&, '', '(, (';(**, ', ''', (;', '';(1) '(;(, (';where: ^5is the total gate charge of MOSFET 12 (typically a known parameter of MOSFET 12) and ^66is the driver supply voltage (described as ^78in the context ofFIG. 2B). For equivalent circuit 300E:9: ; 9<= , 9>? (2)which can be extended through differential equations for ^@and ^^^to: :<A / <AB;C*D / <AB , 9>? (3)To obtain generality andplane, the time (^), voltages (^E), currents (^E), and charges (FE) may be normalized according to: BGH,BG 94 ; 9GH,G9 ; / GH, / G; LGH,LG(4) where theis a placeholder for a corresponding variable. For example, ^^^is the normalized gate-source voltage. The base quantities of the circuit 300E resonant circuit (also referred to as a resonant tank) are described by: :: * R < C4< +T+where U is thespeed of the resonant tank. The normalizing voltage, currentcharge may be: 9HIJK, (**; / HIJK9HIJKG , R ; LHIJK, 9HIJK*+ (6)&+With this / <H,ALHAB; 9<=H,LH(7)equation (3) may beALHYBH) L 9; HYBH) >?H* (8)Solving the generalequations for ^^^ via (7) as9<=HYBH) , .R&+ Z[\YT+BH) ; 2 ]^ZYT+BH) ; 9>?H (9)and for ^2 / <HYBH) , . ]^ZYT+BH) _ Z[\YT+BH) (10)with ` , ^^ Y0), b , ^^^ Y0) _ ^^^ , where ^^^ Y0) is the initial voltage for ^^^ and^^ (9) and (10) to eliminatevariable results in a circular state plane described by / O ; Y9 H _ 9 H)O , / OHY&) ; Y9 O<H <= >? < <=HY&) _ 9>?H) (11)Thetime domain by equations (9) and (10) and in state space by equation (11).

[0113] FIG.5 shows a plurality of plots 400A to 400G of various circuit parameters of gate-driving circuit 300 during the application of a multi-pulse turn-ON operation according to a particular embodiment. FIG.6A shows a state plane plot 500A normalized to a current ^8c(according to capacitance ^^) during time period ^^as defined in equation (12) and shown in FIG.5. FIG.6B shows a state plane plot 500B normalized to a current ^8d(according to capacitance ^^) during time period ^^as defined in equation (12) and shown in FIG.5. FIG.7 shows a plurality of plots 600A to 600G of various circuit parameters of gate-driving circuit 300 during the application of a multi-pulse turn-OFF operation according to a particular embodiment. FIG.8A shows a state plane plot 700A normalized to a current ^8cduring time period ^^as defined in equation (12) and shown in FIG.7. FIG.8B shows a state plane plot 700B normalized to a current ^8dduring time period ^^as defined in equation (12) and shown in FIG.7.

[0114] The following section of this disclosure describes the timing of the multi-pulse driving sequence 400C (FIG.5) of the turn-ON operation with the aid of the waveforms shown in FIG.5. In the particular case of the illustrated embodiment, the parameters ^^, ^^are selected to be the same in the turn-ON operation driving sequence 400C and in the turn-OFF operation 600C (FIG.7), although this symmetry of the turn-ON and turn-OFF operations is generally not necessary. With this symmetry and having regard to FIGS.5 and 7, the parameters ^^, ^^may be described according to:B. , B&eO ; BOef ; Bfeg , Bhei ; Biej ; BjekB2 , Bgel , BkeCC(12)The turn-ON operation is described in detail herein with the understanding that the symmetrical (in the case of the illustrated embodiment) turn-OFF operation is analogous.

[0115] Interval ^Ve^

[0116] Prior to this interval, ^^^ , 0 is applied to keep MOSFET 12 OFF. The interval^Ve^ begins at ^V with ^^^ Y0)=0 and ^^ Y0)=0 and represents state I as identified inequation (1) interval ends at ^^where ^ meets the so-called Miller^^voltage ^mwhich is described by / (n, (Bo; >p(13)Kat B&eO ,q]^ZYC _ (nH)T(14).where X^is the angular speed of the resonant tank with ^E, ^^, ^^^is the threshold voltage and rsis the transconductance of MOSFET 12.

[0117] Interval ^^et

[0118] This interval corresponds to state III as identified in equation (1) and FIG.4B at begins at ^^with ^^^Y0) , ^muand ^^Y0) , ^^Y^^). The initial current in this interval is given by, / HIJK. Z[\YT.B&eO) (15)where ^^^scis theThis interval ends at ^twhen the gate-drain charge (^^^) of ^^^is delivered by ^^via Bf3<>, D / <AB , / <YBO)BOef; &. lBOef∆ / Of(16) where∆ / Of w BOef(>? _ (n:(17)<Consequently, equation (16) can be rewritten, with equation (17) and thex, Yyz{e|})@~ , as

[0119] Interval ^te^

[0120] This interval corresponds to state V described in equation (1) and FIG.4B andstarts at ^twith ^^^Y0), ^muand ^^Y0), ^^Y^t). The initial current in this interval is / <HYBf), / <∆ / OfHYBO); (20)This interval ends at ^^,intersects with the OFF-trajectory (shown in grey-scale in FIG.6B). The OFF-trajectory can be described via equation (11) as / O O<H ; 9<=H , C (21)whereas the ON-trajectory can be described by equation (11) as / O ; O O O<H Y9<=H _ 9>?H) , / <HYBf) ; Y(nH _ 9>?H) (22)Theand (22) to(, C _ & OGH . lJ (23)where J , ^ / O<HYBf); Y(nH_ 9>?H)O(24) With ^ determined,difference of the voltage vectors ^^^Y^t) and ^^^Y^^) (see FIG.6B) through C_ (^g _ ^f q]^ZY nJH C _ () _ q]^ZY GJH )(25)where X is

[0121] Interval ^^e^

[0122] This interval corresponds to state VI described in equation (1) and FIG.4B and starts at ^^with ^^^Y0) , ^Euand ^^Y0) , ^^Y^^). The initial current in this interval isdetermined by / <HYBg , / <HYBf ; / HIJK2 Z[\YBfegT2) (26)This interval endsfor this is determined by Bgel ,q]^ZY(GH)(27)At the end of this interval, ^ON, which concludes the multi-pulse gate-drive sequence which (when compared toprior art techniques which use a gate resistance ^^) provides swift commutation times, while maintaining low voltage stress and reduced oscillations in the gate circuitry for the turn-ON operation. As described above, the turn-OFF operation is analogous to the turn-ON operation and , consequently, the detailed description of the turn-OFF operation is omitted for breviy.

[0123] The above-derived equations may be used to determine the parameters ^^ and^^ for the turn-ON drive sequence 400C (FIG. 5) and the turn-OFF drive sequence600C (FIG.7) according to the particular case of the illustrated embodiment. For practicality, these equations (e.g. equations (14), (19) and (25) and equation (27)) can be simplified to provide the following approximations: ^O(nH _ (OnHandB2 w34^Z Y(nEquations (28), (29) together with equation (13) can be used to determineapproximate values for the parameters ^^ and ^^ based on quantities / parameters (e.g.^^^^, ^^^, ^5, ^^^, rs) that are typically present in the datasheet of a MOSFET powerswitching transistor (e.g. MOSFET 12) together with quantities / parameters (e.g. the operating drain current ^^, ^^, ^^^) of the circuit in which MOSFET 12 is being used. Equations (28) and (29) represent approximations as described above. In some embodiments, different approximations or even equations (14), (19) and (25) and equation (27) may be used to determine multi-pulse parameters ^^and ^^.

[0124] FIG.9 is a schematic illustration of a method 800 for determining the parameters ^^and ^^according to particular embodiment, where block 802 involves determining the parameter ^mbased on datasheet parameters ^^^, rsand circuit parameter ^^and block 804 involve calculating ^^and ^^based on the block 802value for ^m, the datasheet parameters ^^^^, ^^^, ^5 and the circuit parameters ^^ ,^^^. In some embodiments, block 802 may involve the use of equation (13) describedabove and block 804 may involve the use of simplified equations (28) and (29) described above.

[0125] Fig.9 also shows an optional fine turning adjustment method 810 using anadditional incremental time-adjustment parameter ^. The time-adjustment parameter^ may be determined on the basis of the quantities ^^^ and ^^ at ^^^ during the turn-OFF operation (see FIG.7). In particular, if the quantity ∆^^^Y^^^) > 0 (as determined at block 812) then parameter ^^can be incremented by time-adjustment ^ at block 816; if the quantity ∆^^^Y^^^) < 0 (as determined at block 814) then parameter ^^can be decreased by time-adjustment ^ at block 818; if the quantity ^^Y^^^)> 0 (as determined at block 820) then parameter ^^can be decreased by time-adjustment ^ at block 824 and / or ^^Y^^^)< 0 (as determined at block 822) then parameter ^^can be increased by time-adjustment ^ at block 826. In some embodiments, the value of time-adjustment parameter ^ may be different for adjusting ^^in blocks 816, 818 than for adjusting ^^in blocks 824, 826.

[0126] FIGS.10A, 10B, 10C (collectively, FIG.10) illustrate a comparison of the traditional approach (using single step function gate-drive signal ^^^and a gate resistance ^^) for the underdamped condition with ^^, 0Ω and ^^, ^^^^, 100M^ (FIG.10A), the overdamped condition with ^^, 50Ω and ^^, ^^^^, 100M^ (FIG. 10B) applied to the FIG.1A circuit 10 and the mutli-pulse approach shown in plots400C, 600C of FIGS. 5, 7 applied to the circuit of FIG. 4A 300 with ^^ , 0Ω and ^^ ,100M^. FIG. 10A shows that the traditional underdamped response results in swiftcommutation times but suffers from excessive voltage stress and large oscillations, which lead to multiple false turn-ON failures in the turn-OFF operation as seen in the plots of ^^^and ^^. FIG.10B shows that the traditional overdamped response results in slow transients with reduced voltage stress and oscillations, mitigating false turn- ON failures. However, this overdamped approach suffers from significantly reduced slew-rates with the consequential penalty in efficiency (switching power loss). In contrast to the traditional approach, the proposed multi-pulse gate-drive signal shown in FIG.10C achieves swift commutation times while maintaining low voltage stress and oscillations, which effectively mitigates false turn-ON failures.

[0127] In various experiments, the inventors have been able to demonstrate 5X and 18X reduction in oscillation amplitude, while delivering the same peak output current (1.2A) with respect to the conventional approach for ^^^and ^^respectively, which permits the multi-pulse approach described herein to operate the transistor withrelatively fast slew rates while mitigating false turn-ON failures. Further, using the commonly used double pulse test, the inventors have demonstrated switching loss reductions of up to 22% at ^^^, 400^ using the multi-pulse gate driving technique described herein relative to the traditional (single step) gate driving technique incorporate a gate resistance ^^.

[0128] FIG.11A is a schematic circuit diagram of full full-bridge circuit 900 which can be used to provide a multi-pulse gate-driving methodology according to a particular embodiment of the invention. Full-bridge circuit 900 comprises a pair of branches 902A, 902B4 connected between the terminals of voltage source ^^^. First branch 902A comprises switches ^^, ^^and a first full-bridge switched terminal 904A therebetween; second branch 902A comprises switches ^t, ^^and a second full- bridge switched terminal 904B therebetween. Inductor ^^is connected between full- bridge switched terminals 904A, 904B. In the illustrated embodiment, full-bridge switched terminal 904B is connected to directly to gate node 15 by an electrically conductive (e.g. metal) connection – e.g. any resistance between half-bridge terminal 16 and gate node 15 is the inherent internal resistance of the electrically conductive connection (including, possibly, any internal driver and / or MOSFET connections (e.g. of the full-bridge)) and inductance ^^^^is the inherent or parasitic inductance of this conductive connection (including, possibly, any internal driver and / or MOSFET connections (e.g. of the full-bridge)). Full-bridge circuit 900 can operate in a number of operating modes. The FET being controlled is omitted from FIG.11A, but its gate node 15 and source node 13 are shown as well as the gate current ^^and gate- source voltage ^^^. FIG.11B is a schematic illustration of a number of circuit parameters of the FIG.11A full-bridge circuit 900 when operating in an operating mode A which is equivalent to the half-bridge configuration described elsewhereherein, wherein switches ^t and ^^ of circuit 900 are analogous to switches ^^ and^^ of circuits 110 (FIG. 2A) and 300 (FIG. 4A) when switches ^^ and ^^ of circuit 900are kept OFF (non-conducting). In a turn-ON operation: the transistor starts in an OFF (non-conducting) steady state; at ^V, ^^is opened (switched to a non-conducting state) and ^tis closed (switched to a conducting state), causing ^^^to appear at full- bridge switched terminal 904B (a first gate-driving pulse); at ^^, ^^is closed and ^tis opened, causing full-bridge switched terminal 904B to fall to an intermediate value below ^^^of the transistor; and at ^^, ^^is opened again and ^tis closed, causing ^^^to appear at full-bridge switched terminal 904B again (a second gate-driving pulse). Aturn-OFF operation is analogous and will be understood by those skilled in the art on the basis of the description provided herein.

[0129] FIG.11C is a schematic illustration of a number of circuit parameters of the FIG.11A full-bridge circuit 900 when operating in an operating mode B wherein gate inductor ^^is precharged and then connected in series with ^^^^and the gate 15 of the transistor being controlled to charge or discharge the gate capacitance ^^^^(not shown) of the transistor being controlled. The amplitude of the current ^@^through inductor ^^may be selected such that the target voltage of ^^^(^^^_^) is reached when the gate current ^^is near-zero. After the commutation of the FET being controlled, ^tand ^^are operated in a way to clamp ^^^to the target voltage ^^^_^. In a turn-ON operation, the transistor being controlled starts in an OFF (non-conducting) steady state. At ^V, ^^ and ^^ are in conducting states, creating current^@^ and charging inductor ^^ while full-bridge switched terminal 904B remains at a lowvoltage and current ^^remains at zero because ^^is conducting and bypassing gate 15. At ^^, ^^and ^^are switched to non-conducting states and ^^is switched to a conducting state and inductor ^^turns into a current source providing gate current ^^, charging the gate capacitance ^^^^of the transistor being controlled and providing a first gate-driving voltage pulse at full-bridge switched terminal 904B. As the gatecapacitance ^^^^ charges and ^^^ increases, the currents ^^ and ^@^ decrease; at ^^,^^ is switched to non-conducting states and ^t is switched to a conducting state,thereby providing a second gate-driving voltage pulse at full-bridge switched terminal 904B and clamping ^^^to the target voltage ^^^_^. A turn-OFF operation is analogous and will be understood by those skilled in the art on the basis of the description provided herein. With this full-bridge operational mode, the commutation speed of the FET being controlled can be significantly increased, while maintaining near-zero oscillations in the gate circuitry.

[0130] FIG.11D is a schematic illustration of a number of circuit parameters of theFIG. 11A full-bridge circuit 900 when operating in an operating mode C, which utilizes^^ and ^^ to provide a pulse-width modulated (PWM) gate-driving voltage signalwhich controls the currents ^^and ^@^during the commutation. The PWM frequency of the gate-driving signal may be selected such that the PWM period is significantly shorter than the typical commutation time (switching time) of the transistor being controlled. For example, in some embodiments, the PWM period may be less than 1 / 3 of the period of the resonant tank defined by the parasitic inductance of the gateterminal and the gate capacitance (e.g. by ^^^^and ^^^^), less than 1 / 5 of this resonant tank period, or less than 1 / 10 of this resonant tank period. Because the PWM period is fast in comparison to the commutation time, the PWM signal gate driving signal applied during commutation may be considered to be a first voltage pulse having an “effective” amplitude dictated by a product of the PWM amplitude and duty cycle. The PWM parameters (which may include frequency, amplitude and duty cycle) may selected a such that ^^is near-zero when ^^^is at the target voltage ^^^_^at the conclusion of the commutation process. After the commutation of the transistor being controlled, ^tand ^^are operated in a way provide a second gate-drivingvoltage pulse at full-bridge terminal 904B and clamping ^^^to the target voltage^^^_^ .

[0131] In a turn-ON operation, the transistor being controlled starts in an OFF (non- conducting) steady state. Starting at ^V, ^^and ^^are alternatingly turned on and off, while ^tand ^^remain non-conducting, creating a first gate driving voltage pulse, which in turn causes ^^, ^@^and ^^^to increase. As ^^^increases, the effective voltage at full-bridge node 904B increases (relative to the effective voltage at full- bridge node 904A) and currents ^^, ^@^start to decrease again. At ^^, ^^and ^^are switched to non-conducting states and ^tis switched to a conducting state while ^^is maintained in a non-conducting state, thereby providing a second gate-driving voltage pulse at full-bridge terminal 904B and clamping ^^^to the target voltage ^^^_^in a manner analogous to that at ^^of the embodiment shown in FIG.11C. A turn-OFF operation is analogous and will be understood by those skilled in the art on the basis of the description provided herein. With this full-bridge operational mode, the commutation of the FET being controlled can be controlled with enhanced precision, which allows for improvements in slew-rate control and consequent benefits with respect to electromagnetic compatibility (EMC) and electromagnetic interference (EMI).

[0132] In another embodiment (not explicitly shown), ^^and ^^of full-bridge circuit 900 could be effectively left non-conducting and ^tand ^^could be controlled to provide a first voltage pulse having a first effective amplitude to full-bridge terminal904B using a PWM signal during commutation and then could be operated such that^t is switched to a conducting state while ^^ is maintained in a non-conducting state,thereby providing a second gate-driving voltage pulse at full-bridge terminal 904B and clamping ^^^to the target voltage ^^^_^in a manner analogous to that discussed inrelation to FIGS.11C and 11D. Like the embodiment of FIG.11D, the PWM frequency of the gate-driving signal during commutation in this embodiment may be selected such that the PWM period is significantly shorter than the typical commutation time (switching time) of the transistor being controlled. For example, in some embodiments, the PWM period may be less than 1 / 3 of the period of the resonant tank defined by the parasitic inductance of the gate terminal and the gate capacitance (e.g. by ^^^^and ^^^^), less than 1 / 5 of this resonant tank period, or less than 1 / 10 of this resonant tank period. Because the PWM period is fast in comparison to the commutation time, the “effective” amplitude of the first gate-driving pulse may be dictated by a product of the PWM amplitude and duty cycle. The PWM parameters (which may include frequency, amplitude and duty cycle) may selected a such that ^^is near-zero when ^^^is at the target voltage ^^^_^at the conclusion of the commutation process. A turn-OFF operation is analogous and will be understood by those skilled in the art on the basis of the description provided herein. Those skilled in the art will appreciate that because this non-illustrated embodiment leaves ^^and ^^of full-bridge circuit 900 non-conducting and applies the multi-pulse gate-driving signal using ^tand ^^, this embodiment could also be implemented using the half- bridge circuits with the pair of switches shown in FIG.2A and FIG.4A.

[0133] In some embodiments, the pulse-width modulation (PWM) parameters (e.g. frequency, amplitude and / or duty cycle) could be varied during a pulse (e.g. during the first pulse). An example implementation wherein a variation of PWM duty cycle is used during the first pulse of a turn-ON operation is shown in FIG.11E). In the FIG. 11E example, the duty cycle (implemented by full-bridge switches ^^and ^^has three different duty cycles (D1, D2 and D3) during the first pulse. The second pulse of the FIG.11E example is shown as being the same as that of the FIG.11D embodiment. It will be appreciated that the three difference duty cycles of the FIG. 11E example result in three different “effective” amplitudes of the first pulse. A similar variation of PWM parameters could be implemented in the first pulse of a turn-OFF operation. Variation of PWM parameters could also be used in the switches ^tand ^^of full-bridge circuit 900 (e.g. with ^^and ^^non-conducting), which is effectively the same as varying the PWM parameters in this manner in the half-bridge circuits with the pair of switches shown in FIG.2A and FIG.4A.

[0134] PWM is described above for use during the first pulse to provide an effective amplitude during the first pulse and the second pulse is described as clamping thevoltage (of the relevant node). In some embodiments, PWM may additionally or alternatively be used in the second pulse to provide the second pulse with an effective amplitude.

[0135] The description to this point describes open loop selection of various parameters of the multi-pulse gate-driving signal ^^^based on specified (e.g. by a datasheet) or measured parameters of other components. There may be a desire in practice, to tune the parameters of the multi-pulse gate-driving signal ^^^using a closed loop control solution which may help to mitigate drift or other variation of the parameters of other components which may be caused, for example, by aging, temperature changes and changes in the operating points of various components.

[0136] FIG.12 is a schematic depiction of a closed loop system 910 which involves measurement of one or more of ^^, ^^^, ^^, ^^^, ^^^and / or temperature or other parameters (not expressly shown in FIG.12) and feeding back this information to a controller (shown as a microcontroller MCU in the illustrated example embodiment) which can be configured to implement a suitable control mechanism to adapt the multi-pulse parameters (e.g. pulse amplitude, pulse voltage levels, pulse duration, temporal pulse separation, pulse frequency, pulse duty cycle, charge time and / or the like (e.g. ^^, ^^described above)) of the ^^^pulses according to a particular embodiment. Such a control mechanism may comprise any suitable control mechanism such as a linear (e.g. PID) controller and / or a non-linear controller and may use pre-defined and / or dynamic look-up tables (LUTs). The measured feedback may be continuous, discrete or binary. The controller and / or measurement function may be implemented as an analog circuit, as a digital scheme or a combination of analog and digital. In the case of a digital controller, the implementation can be performed through a microcontroller unit (MCU) as is the case in the illustrated FIG. 12 embodiment, which may comprise either the central MCU of some system of which the FET under control is a part or a dedicated MCU which is solely responsible for the proposed multi-pulse gate-driving scheme. Since power conversion applications typically use an MCU for operation, an implementation in a central MCU may be favorable, although not necessary. It may be desirable for the MCU to be physically or electrically close to the driver for performance and / or signal integrity. These MCUs can be implemented as digital signal processors (DSPs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs) and / or the like and any combination thereof.

[0137] FIGS.13A, 13B and 13C (collectively FIG.13) respectively depict a window comparator circuit 910 implementing ^^feedback according to a particular embodiment, waveforms for various parameters when the transferred charge is too low and waveforms for various parameters when the transferred charge is too high. FIG.13A illustrates the current sensing resistor ^^^ ^^, which produces the sensing voltage ^^^ ^^and two comparators (CMPA and CMPB) that operate with two corresponding reference voltages RefA and RefB. With these comparators (CMPA and CMPB), the zero-crossing (ZC) of ^^can be detected (ZC=CMPA XOR CMPB) where XOR is the exclusive OR operator, which in turn may be utilized to determine the end of the proposed modulation as well as the fine-tuning.

[0138] FIG.13B depicts the operation of the feedback when the transferred charge is too low. It can be seen from FIG.13B that, at the turn-ON ZC, the current ^^will have an oscillation starting with positive amplitude to account for the lack of charge in ^^^^necessary to complete the commutation. This results in an additional ZC, where the current ^^transitions from positive to negative direction. This direction is then later utilized to adjust the timing parameter ^^by an incremental time-adjustment parameter ^. Similarly, it can be seen at the turn-OFF ZC that the current ^^will experience an oscillation starting with negative amplitude to account to account for the lack of charge in ^^^^to complete the commutation. This results in an additional ZC, where the current ^^transitions from negative to positive direction. This direction is then later utilized to adjust the timing parameter ^^by an incremental time- adjustment parameter ^. FIG.13C depicts the operation of the feedback when the transferred charge is too large. This operation is analogous to that shown in FIG.13B and is omitted for brevity.

[0139] FIG.14 is a flow chart illustrating a methodology that may be used to implement control of the multi-pulse parameters ^^, ^^using the ^^feedback provided by the window comparator illustrated in the FIG.13A circuit 920 according to a particular embodiment. In principle, after a ZC-event, the states of the comparators (CMPA and CMPB) are observed and depending on the sequence of comparator changes, the timing parameters ^^and / or ^^are adjusted accordingly. The update of the timing parameters may be performed cycle-by-cycle and thus should track any changes in operating point swiftly.

[0140] This disclosure describes the use of standard and off the shelve components for its implementation. Although, this showcases the ease of adaptability of the multi-pulse gate-driving concept, there may be options of further harnessing the multi-pulse gate-driving concept with custom integrated circuits (ICs) and / or custom designed switches, which may further enhance the characteristics of particular embodiments. For example, potential candidates for driver ICs may comprise drivers based on gallium nitride (GaN), as they provide very fast turn on and off times. Further, the above-described closed loop control may be implemented within an custom IC that includes the measurement of the needed parameters and control logic. This option may or may not include isolation of driving features. This IC may be included within a power switch or a power switch may be implemented on an IC.

[0141] Further, some power switches come with an internal gate resistor for controllability. With the proposed multi-pulse gate-driving scheme, power switches may want to remove this internal gate resistance for performance improvement. Furthermore, additional gate circuitry for performance and reliability enhancements may be incorporated into particular embodiments. For instance, clamping circuits may be implemented to improve the reliability of the circuit protecting overvoltages. Moreover, additional capacitance may be added to the switch for enhanced controllability and added margins towards safe operation of the power switch. Also, multiple inductors may be implemented to allow for different transitions of the on and off transients. These inductors may also be used to alter the on or off trajectory of the transient as they may or may not be enabled in the circuit through control switches.

[0142] In the multi-pulse strategies described above, the gate-driving strategy involve two ON pulses for a turn–ON operation and two OFF pulses for a turn-OFF operation. In other embodiments, multiple (more than two) ON pulses may be used for a turn- ON operation and / or multiple (more than two) OFF pulses may be used for a turn- OFF operation. Both the two pulse embodiments and the train of (more than two) pulses can be implemented using open loop (predefined) or close loop (adaptive) parameters. With these strategies, conversion efficiency and electromagnetic interference (EMI) may be controlled through software, which allows for tremendous advantages in the power electronics community. This may lead to reduction of EMI and voltage stress without compromising efficiency or vice versa. Moreover, the driving can be adapted on the operating condition leading to enhanced controllability of power conversion applications.

[0143] Where a component (e.g. a software module, processor, assembly, device, circuit, etc.) is referred to herein, unless otherwise indicated, reference to thatcomponent (including a reference to a “means”) should be interpreted as including as equivalents of that component any component which performs the function of the described component (i.e., that is functionally equivalent), including components which are not structurally equivalent to the disclosed structure which performs the function in the illustrated exemplary embodiments of the invention.

[0144] Embodiments of the invention may be implemented using specifically designed hardware, configurable hardware, programmable data processors configured by the provision of software (which may optionally comprise “firmware”) capable of executing on the data processors, special purpose computers or data processors that are specifically programmed, configured, or constructed to perform one or more steps in a method as explained in detail herein and / or combinations of two or more of these. Examples of specifically designed hardware are: logic circuits, application-specific integrated circuits (“ASICs”), large scale integrated circuits (“LSIs”), very large scale integrated circuits (“VLSIs”), and the like. Examples of configurable hardware are: one or more programmable logic devices such as programmable array logic (“PALs”), programmable logic arrays (“PLAs”), and field programmable gate arrays (“FPGAs”). Examples of programmable data processors are: microprocessors, digital signal processors (“DSPs”), embedded processors, graphics processors, math co- processors, general purpose computers, server computers, cloud computers, mainframe computers, computer workstations, and the like. For example, one or more data processors in a control circuit for a device may implement methods as described herein by executing software instructions in a program memory accessible to the processors.

[0145] Processing may be centralized or distributed. Where processing is distributed, information including software and / or data may be kept centrally or distributed. Such information may be exchanged between different functional units by way of a communications network, such as a Local Area Network (LAN), Wide Area Network (WAN), or the Internet, wired or wireless data links, electromagnetic signals, or other data communication channel.

[0146] The invention may also be provided in the form of a program product. The program product may comprise any non-transitory medium which carries a set of computer-readable instructions which, when executed by a data processor, cause the data processor to execute a method of the invention. Program products according to the invention may be in any of a wide variety of forms. The program product maycomprise, for example, non-transitory media such as magnetic data storage media including floppy diskettes, hard disk drives, optical data storage media including CD ROMs, DVDs, electronic data storage media including ROMs, flash RAM, EPROMs, hardwired or preprogrammed chips (e.g., EEPROM semiconductor chips), nanotechnology memory, or the like. The computer-readable signals on the program product may optionally be compressed or encrypted.

[0147] In some embodiments, the invention may be implemented in software. For greater clarity, “software” includes any instructions executed on a processor, and may include (but is not limited to) firmware, resident software, microcode, code for configuring a configurable logic circuit, applications, apps, and the like. Both processing hardware and software may be centralized or distributed (or a combination thereof), in whole or in part, as known to those skilled in the art. For example, software and other modules may be accessible via local memory, via a network, via a browser or other application in a distributed computing context, or via other means suitable for the purposes described above.

[0148] Software and other modules may reside on servers, workstations, personal computers, tablet computers, and other devices suitable for the purposes described herein. Interpretation of Terms

[0149] Unless the context clearly requires otherwise, throughout the description and the claims: • “comprise”, “comprising”, and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to”; • “connected”, “coupled”, or any variant thereof, means any connection or coupling, either direct or indirect, between two or more elements; the coupling or connection between the elements can be physical, logical, or a combination thereof; • “herein”, “above”, “below”, and words of similar import, when used to describe this specification, shall refer to this specification as a whole, and not to any particular portions of this specification; • “or”, in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list;• the singular forms “a”, “an”, and “the” also include the meaning of any appropriate plural forms. These terms (“a”, “an”, and “the”) mean one or more unless stated otherwise; • “and / or” is used to indicate one or both stated cases may occur, for example A and / or Β includes both (A and Β) and (A or Β); • “approximately” when applied to a numerical value means the numerical value ± 10%; • where a feature is described as being “optional” or “optionally” present or described as being present “in some embodiments” it is intended that the present disclosure encompasses embodiments where that feature is present and other embodiments where that feature is not necessarily present and other embodiments where that feature is excluded. Further, where any combination of features is described in this application this statement is intended to serve as antecedent basis for the use of exclusive terminology such as "solely," "only" and the like in relation to the combination of features as well as the use of "negative" limitation(s)” to exclude the presence of other features; and • “first” and “second” are used for descriptive purposes and cannot be understood as indicating or implying relative importance or indicating the number of indicated technical features.

[0150] Words that indicate directions such as “vertical”, “transverse”, “horizontal”, “upward”, “downward”, “forward”, “backward”, “inward”, “outward”, “left”, “right”, “front”, “back”, “top”, “bottom”, “below”, “above”, “under”, and the like, used in this description and any accompanying claims (where present), depend on the specific orientation of the apparatus described and illustrated. The subject matter described herein may assume various alternative orientations. Accordingly, these directional terms are not strictly defined and should not be interpreted narrowly.

[0151] Where a range for a value is stated, the stated range includes all sub-ranges of the range. It is intended that the statement of a range supports the value being at an endpoint of the range as well as at any intervening value to the tenth of the unit of the lower limit of the range, as well as any subrange or sets of sub ranges of the range unless the context clearly dictates otherwise or any portion(s) of the stated range is specifically excluded. Where the stated range includes one or both endpoints of the range, ranges excluding either or both of those included endpoints are alsoincluded in the invention.

[0152] Certain numerical values described herein are preceded by "about". In this context, "about" provides literal support for the exact numerical value that it precedes, the exact numerical value ±5%, as well as all other numerical values that are near to or approximately equal to that numerical value. Unless otherwise indicated a particular numerical value is included in “about” a specifically recited numerical value where the particular numerical value provides the substantial equivalent of the specifically recited numerical value in the context in which the specifically recited numerical value is presented. For example, a statement that something has the numerical value of “about 10” is to be interpreted as: the set of statements: • in some embodiments the numerical value is 10; • in some embodiments the numerical value is in the range of 9.5 to 10.5; and if from the context the person of ordinary skill in the art would understand that values within a certain range are substantially equivalent to 10 because the values with the range would be understood to provide substantially the same result as the value 10 then “about 10” also includes: • in some embodiments the numerical value is in the range of C to D where C and D are respectively lower and upper endpoints of the range that encompasses all of those values that provide a substantial equivalent to the value 10

[0153] Specific examples of systems, methods and apparatus have been described herein for purposes of illustration. These are only examples. The technology provided herein can be applied to systems other than the example systems described above. Many alterations, modifications, additions, omissions, and permutations are possible within the practice of this invention. This invention includes variations on described embodiments that would be apparent to the skilled addressee, including variations obtained by: replacing features, elements and / or acts with equivalent features, elements and / or acts; mixing and matching of features, elements and / or acts from different embodiments; combining features, elements and / or acts from embodiments as described herein with features, elements and / or acts of other technology; and / or omitting combining features, elements and / or acts from described embodiments.

[0154] As will be apparent to those of skill in the art upon reading this disclosure, each of the individual embodiments described and illustrated herein has discrete components and features which may be readily separated from or combined with thefeatures of any other described embodiment(s) without departing from the scope of the present invention.

[0155] Any aspects described above in reference to apparatus may also apply to methods and vice versa.

[0156] Any recited method can be carried out in the order of events recited or in any other order which is logically possible. For example, while processes or blocks are presented in a given order, alternative examples may pdalyerform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified to provide alternative or subcombinations. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, simultaneously or at different times.

[0157] Various features are described herein as being present in “some embodiments”. Such features are not mandatory and may not be present in all embodiments. Embodiments of the invention may include zero, any one or any combination of two or more of such features. All possible combinations of such features are contemplated by this disclosure even where such features are shown in different drawings and / or described in different sections or paragraphs. This is limited only to the extent that certain ones of such features are incompatible with other ones of such features in the sense that it would be impossible for a person of ordinary skill in the art to construct a practical embodiment that combines such incompatible features. Consequently, the description that “some embodiments” possess feature A and “some embodiments” possess feature B should be interpreted as an express indication that the inventors also contemplate embodiments which combine features A and B (unless the description states otherwise or features A and B are fundamentally incompatible).This is the case even if features A and B are illustrated in different drawings and / or mentioned in different paragraphs, sections or sentences.

[0158] It is therefore intended that the following appended claims and claims hereafter introduced are interpreted to include all such modifications, permutations, additions, omissions, and sub-combinations as may reasonably be inferred. The scope of the claims should not be limited by the preferred embodiments set forth in the examples, but should be given the broadest interpretation consistent with the description as a whole.

Claims

WHAT IS CLAIMED IS:

1. A method for operating a semiconductor switching device having a gate capacitance to switch the device from a starting steady state to an ending steady state that is different from the starting steady state, the method comprising: applying a first gate-driving voltage pulse to a gate of the device when the device is in the starting steady state, the first voltage pulse having a first effective amplitude a first pulse duration ^^; applying a second gate-driving voltage pulse to the gate after applying the first gate driving pulse, the second gate-driving voltage pulse having a second effective amplitude and a second pulse duration; wherein the second voltage pulse is applied during a transition of the device between the starting steady state and the ending steady state.

2. The method of claim 1 or any other claim herein wherein the first effective amplitude crosses from a starting state value that is below a threshold voltage^^^ associated with the device to a first pulse value that is above the thresholdvoltage ^^^.

3. The method of any of claims 1 to 2 or any other claim herein wherein the second gate-driving voltage pulse has a second effective amplitude that crosses from an intermediate value that is below the threshold voltage ^^^to a second pulse value that is above the threshold voltage ^^^.

4. The method of claim 1 or any other claim herein wherein the first effective amplitude is from a starting state value that is above a threshold voltage ^^^associated with the device to a first pulse value that is below the threshold voltage ^^^.

5. The method of any of claims 1 and 4 or any other claim herein wherein the second gate-driving voltage pulse has a second effective amplitude that crosses from an intermediate value that is above the threshold voltage ^^^to a second pulse value that is below the threshold voltage ^^^.

6. The method of any one of claims 3 and 5 or any other claim herein wherein the intermediate value is about equal to the starting state value.

7. The method of any one of claims 1 to 6 or any other claim herein wherein the first pulse duration ^^is less than a time that it takes for the device to reach the ending steady state.

8. The method of any one of claims 1 to 7 or any other claim herein wherein the second gate-driving pulse has a duration that is sufficiently long for the device to reach the ending steady state during the second gate-driving pulse.

9. The method of any one of claims 1 to 8 or any other claim herein comprising maintaining the gate-driving voltage at an intermediate value for a period of time ^^after a conclusion of the first gate-driving pulse and before applying the second gate-driving voltage pulse.

10. The method of claim 9 or any other claim herein wherein the second gate- driving voltage pulse has a second effective amplitude that crosses from the intermediate value that is below the threshold voltage ^^^to a second pulse value that is above the threshold voltage ^^^.

11. The method of claim 9 or any other claim herein wherein the second gate- driving voltage pulse has a second effective amplitude that crosses from the intermediate value that is above the threshold voltage ^^^to a second pulse value that is below the threshold voltage ^^^.

12. The method of any one of claims 9 to 11 or any other claim herein wherein the intermediate value is the same at the starting state value.

13. The method of any one of claims 1 to 12 or any other claim herein wherein the first effective amplitude is the same as the second effective amplitude.

14. The method of any one of claims 1 to 13 or any other claim herein, wherein themethod is applied to a turn-ON operation, the device is non-conducting (e.g. between drain and source) in the starting steady state, the device is conducting (e.g. between drain and source) in the ending steady state, the starting state value and the intermediate value are less than the threshold voltage ^^^and the first pulse value and the second pulse value are greater than the threshold voltage ^^^.

15. The method of any one of claims 1 to 13 or any other claim herein, wherein the method is applied to a turn-OFF operation, the device is conducting (e.g. between drain and source) in the starting steady state, the device is non- conducting (e.g. between drain and source) in the ending steady state, the starting state value and the intermediate value are greater than the threshold voltage ^^^and the first pulse value and the second pulse value are less than the threshold voltage ^^^.

16. The method of any one of claims 1 to 15 or any other claim herein comprising applying one or more additional gate-driving voltage pulses to the gate after applying the first gate driving pulse and prior to applying the second gate driving pulse.

17. The method of claim 16 or any other claim herein wherein the one or more additional gate-driving pulses have the same pulse parameters (e.g. amplitude and duration) as the first pulse.

18. The method of claim 16 or any other claim herein wherein at least one of the one or more additional gate-driving pulses has different pulse parameters (e.g. amplitude and duration) as the first pulse.

19. The method of any one of claims 16 to 18 wherein temporal pulse-spacing between the first pulse, the one or more additional pulses and the second pulse is the same.

20. The method of any one of claims 16 to 18 wherein temporal pulse-spacing between at least a first temporally adjacent pair of the first pulse, the one ormore additional pulses and the second pulse is different than at least a second temporally adjacent pair of the first pulse, the one or more additional pulses and the second pulse.

21. The method of any one of claims 1 to 20 or any other claim herein wherein applying the first and second gate-driving pulses comprises controlling a gate- control voltage source.

22. The method of claim 21 or any other claim herein wherein controlling the gate- control voltage source comprises controlling a half-bridge circuit having its switched terminal electrically connected to the gate.

23. The method of claim 22 or any other claim herein wherein the electrical connection between the switched terminal and the gate is made by an electrically conductive connection wherein any resistance between the switched terminal and the gate is the inherent internal resistance of the electrically conductive connection, including, possibly, any internal driver and / or MOSFET connections of the half-bridge circuit.

24. The method of any one of claims 22 to 23 or any other claim herein wherein any inductance between the switched terminal and the gate is the inherent internal inductance ^^^^of the electrically conductive connection, including, possibly, any internal driver and / or MOSFET connections of the half-bridge circuit.

25. The method of any one of claims 22 to 24 or any other claim herein wherein applying the first pulse comprises controlling the half-bridge circuit to provide a pulse-width modulated (PWM) signal at the switched terminal and wherein the first effective amplitude is based on one or more of the parameters (e.g. pulse amplitude, frequency and / or duty cycle) of the PWM signal.

26. The method of claim 25 or any other claim herein comprising controlling the half-bridge circuit to vary one or more of the parameters (e.g. pulse amplitude, frequency and / or duty cycle) of the PWM signal during the first pulse duration^^.

27. The method of any one of claims 25 to 26 or any other claim herein wherein applying the second pulse comprises controlling the half-bridge to clamp the voltage at the switched terminal to the second effective amplitude when a gate current ^^is at or near zero.

28. The method of claim 21 or any other claim herein wherein controlling the gate- control voltage source comprises controlling a full-bridge circuit.

29. The method of claim 28 or any other claim herein wherein the full-bridge circuit has one of its switched terminals electrically connected to the gate.

30. The method of claim 29 or any other claim herein wherein the electrical connection between the one of the switched terminals and the gate is made by an electrically conductive connection wherein any resistance between the one of the switched terminals and the gate is the inherent internal resistance of the electrically conductive connection, including, possibly, any internal driver and / or MOSFET connections of the full-bridge circuit.

31. The method of any one of claims 29 to 30 or any other claim herein wherein any inductance between the one of the switched terminals and the gate is the inherent internal inductance ^^^^of the electrically conductive connection, including, possibly, any internal driver and / or MOSFET connections of the full- bridge circuit.

32. The method of any one of claims 29 to 31 or any other claim herein wherein the full-bridge circuit comprises an inductor ^^connected between the one of the switched terminals and a second one of the switched terminals of the full- bridge.

33. The method of claim 32 or any other claim herein wherein applying the first gate-driving pulse comprises: controlling the full-bridge to charge the inductor^^ prior to applying the first pulse; and controlling the full-bridge to cause theinductor ^^to act as a current source when the first pulse is applied.

34. The method of claim 33 or any other claim herein wherein applying the second pulse comprises controlling the full-bridge to clamp the voltage at the one of the switched terminals to the second effective amplitude when a gate current^^ is at or near zero.

35. The method of claim 32 or any other claim herein wherein applying the first pulse comprises controlling the full-bridge circuit to provide a pulse-width modulated (PWM) signal at the second one of the switched terminals and wherein the first effective amplitude is based on one or more of the parameters (e.g. pulse amplitude, frequency and / or duty cycle) of the PWM signal.

36. The method of claim 35 or any other claim herein comprising controlling the full-bridge circuit to vary one or more of the parameters (e.g. pulse amplitude, frequency and / or duty cycle) of the PWM signal during the first pulse duration^^.

37. The method of any one of claims 35 to 36 or any other claim herein wherein applying the second pulse comprises controlling the full-bridge to clamp the voltage at the one of the switched terminals to the second effective amplitude when a gate current ^^is at or near zero.

38. The method of any one of claims 1 to 37 or any other claim herein comprising repeatedly applying the method to switch the device from the starting state to the ending state and to switch the device from the ending state back to the starting state.

39. The method of claim 38 or any other claim herein wherein the repeated application of the method is used in one of: a switch-mode power supply; a digital communication circuit; a discrete amplifier; a signal conditioning crcuit; a LED drive; and a digital clock.

40. The method of any one of claims 38 to 39 or any other claim hereincomprising: sensing a value of at least one of a voltage at a node of the device and a current through a node of the device; and adjusting one or more parameters of at least one of the first gate-driving pulse and the second gate-driving pulse based at least in part on the sensed value.

41. The method of claim 40 or any other claim herein wherein the node of the device is one of a gate, a source or a drain of a transistor.

42. The method of any one of claims 38 to 39 or any other claim herein comprising: sensing a temperature correlated with a temperature of the device; and adjusting one or more parameters of at least one of the first gate-driving pulse and the second gate-driving pulse based at least in part on the sensed value.

43. The method of any one of claims 40 to 42 or any other claim herein wherein adjusting the one or more parameters of at least one of the first gate-driving pulse and the second gate-driving pulse based at least in part on the sensed value is performed by a controller.

44. The method of claim 43 or any other claim herein wherein the controller configured to implement a control algorithm based at least in part on a desired value for the sensed value.

45. The method of any one of claims 40 to 44 or any other claim herein wherein the one or more parameters of the at least one of the first gate-driving pulse and the second gate-driving pulse comprises the first pulse duration ^^.

46. The method of any one of claims 40 to 45 or any other claim herein wherein the one or more parameters of the at least one of the first gate-driving pulse and the second gate-driving pulse comprises the first effective amplitude.

47. The method of any one of claims 40 to 46 or any other claim herein wherein the one or more parameters of the at least one of the gate-driving first pulse and the second gate-driving pulse comprises a period of time ^^after a conclusion of the first gate-driving pulse and before applying the second gate- driving voltage pulse during which the gate-driving voltage is maintained at the intermediate value.

48. The method of any one of claims 40 to 47 or any other claim herein wherein the one or more parameters of the at least one of the first gate-driving pulse and the second gate-driving pulse comprises the second effective amplitude.

49. The method of any one of claims 40 to 48 or any other claim herein wherein applying the first gate-driving pulse comprises applying a first series of pulse- width modulated (PWM) voltage pulses to the gate, the first series of pulse- width modulated voltage pulses having first PWM parameters (e.g. a first PWM frequency, a first PWM duty cycle and / or a first PWM amplitude) which achieve the first effective amplitude and wherein the one or more parameters of the at least one of the first gate-driving pulse and the second gate-driving pulse comprises at least one of the first PWM parameters.

50. The method of any one of claims 40 to 49 or any other claim herein wherein applying the second gate-driving pulse comprises applying a second series of pulse-width modulated (PWM) voltage pulses to the gate, the second series of pulse-width modulated voltage pulses having second PWM parameters (e.g. a second PWM frequency, a second PWM duty cycle and / or a second PWM amplitude) which achieve the second effective amplitude and wherein the one or more parameters of the at least one of the first gate-driving pulse and the second gate-driving pulse comprises at least one of the second PWM parameters.

51. A circuit for operating a semiconductor switching device having a gate capacitance to switch the device from a starting steady state to an ending steady state that is different from the starting steady state, the circuit comprising:a gate-control voltage source connected to a gate of the transistor by an electrically conductive (e.g. metal) connection between an output of the gate-control voltage source and the gate; a controller connected to the gate-control voltage source, the controller configured to: cause the gate-control voltage source to apply a first gate- driving voltage pulse to a gate of the device when the device is in the starting steady state, the first voltage pulse having a first effective amplitude a first pulse duration ^^; cause the gate-control voltage source to apply a second gate- driving voltage pulse to the gate after applying the first gate driving pulse, the second gate-driving voltage pulse having a second effective amplitude and a second pulse duration; wherein the second voltage pulse is applied during a transition of the device between the starting steady state and the ending steady state.

52. The circuit of claim 51 or any other claim herein wherein the gate-control voltage source comprises a half-bridge circuit comprising a pair of switches and a switched terminal therebetween, the switched terminal electrically connected to the gate by the electrically conductive connection.

53. The circuit of claim 52 or any other claim herein wherein any resistance between the switched terminal and the gate is the inherent internal resistance of the electrically conductive connection, including, possibly, any internal driver and / or MOSFET connections of the half-bridge circuit.

54. The circuit of any one of claims 52 to 53 or any other claim herein wherein any inductance between the switched terminal and the gate is the inherent internal inductance ^^^^of the electrically conductive connection, including, possibly, any internal driver and / or MOSFET connections of the half-bridge circuit.

55. The circuit of any one of claims 52 to 54 or any other claim herein wherein the controller is configured to cause the gate-control voltage source to apply the first pulse by controlling the switches of the half-bridge circuit to provide apulse-width modulated (PWM) signal at the switched terminal and wherein the first effective amplitude is based on one or more of the parameters (e.g. pulse amplitude, frequency and / or duty cycle) of the PWM signal.

56. The circuit of claim 55 or any other claim herein wherein the controller is configured to control the switches of the half-bridge circuit to vary one or more of the parameters (e.g. pulse amplitude, frequency and / or duty cycle) of the PWM signal during the first pulse duration ^^.

57. The circuit of any one of claims 55 to 56 or any other claim herein wherein the controller is configured to cause the gate-control voltage source to apply the second pulse by controlling the switches of the half-bridge circuit to clamp the voltage at the switched terminal to the second effective amplitude when a gate current ^^is at or near zero.

58. The circuit of claim 51 or any other claim herein wherein the gate-control voltage source comprises a full-bridge circuit comprising a pair of branches, each branch comprising a pair of switches and a switched terminal therebetween.

59. The circuit of claim 58 or any other claim herein wherein one of the switched terminals of the full-bridge circuit is electrically connected to the gate.

60. The circuit of claim 59 or any other claim herein wherein the electrical connection between the one of the switched terminals and the gate is made by an electrically conductive connection wherein any resistance between the one of the switched terminals and the gate is the inherent internal resistance of the electrically conductive connection, including, possibly, any internal driver and / or MOSFET connections of the full-bridge circuit.

61. The circuit of any one of claims 59 to 60 or any other claim herein wherein any inductance between the one of the switched terminals and the gate is the inherent internal inductance ^^^^of the electrically conductive connection, including, possibly, any internal driver and / or MOSFET connections of the full-bridge circuit.

62. The circuit of any one of claims 59 to 61 or any other claim herein wherein the full-bridge circuit comprises an inductor ^^connected between the switched terminals of the full-bridge.

63. The circuit of claim 62 or any other claim herein wherein the controller is configured to cause the gate-control voltage source to apply the first pulse by controlling the switches of the full-bridge to charge the inductor ^^prior to applying the first pulse; and controlling the switches of the full-bridge to cause the inductor ^^to act as a current source when the first pulse is applied.

64. The circuit of claim 63 or any other claim herein wherein the controller is configured to cause the gate-control voltage source to apply the second pulse by controlling the switches of the full-bridge to clamp the voltage at the one of the switched terminals to the second effective amplitude when a gate current^^ is at or near zero.

65. The circuit of claim 62 or any other claim herein wherein the controller is configured to cause the gate-control voltage source to apply the first pulse by controlling the switches of the full-bridge circuit to provide a pulse-width modulated (PWM) signal at the second one of the switched terminals and wherein the first effective amplitude is based on one or more of the parameters (e.g. pulse amplitude, frequency and / or duty cycle) of the PWM signal.

66. The circuit of claim 65 or any other claim herein wherein the controller is configured to control the switches of the full-bridge circuit to vary one or more of the parameters (e.g. pulse amplitude, frequency and / or duty cycle) of the PWM signal during the first pulse duration ^^.

67. The circuit of any one of claims 65 to 66 or any other claim herein wherein the controller is configured to cause the gate-control voltage source to apply the second pulse by controlling the switches of the full-bridge to clamp the voltage at the one of the switched terminals to the second effective amplitude when agate current ^^is at or near zero.

68. The circuit of any one of claims 51 to 67 or any other claim herein wherein the first effective amplitude crosses from a starting state value that is below a threshold voltage ^^^associated with the device to a first pulse value that is above the threshold voltage ^^^.

69. The circuit of 51 to 68 wherein the second gate-driving voltage pulse has a second effective amplitude that crosses from an intermediate value that is below the threshold voltage ^^^to a second pulse value that is above the threshold voltage ^^^.

70. The circuit of any one of claims 51 to 67 or any other claim herein wherein the first effective amplitude crosses from a starting state value that is above a threshold voltage ^^^associated with the device to a first pulse value that is below the threshold voltage ^^^.

71. The circuit of any one of claims 51 to 67 and 70 or any other claim herein wherein the second gate-driving voltage pulse has a second effective amplitude that crosses from an intermediate value that is above the threshold voltage ^^^to a second pulse value that is below the threshold voltage ^^^.

72. The circuit of any one of claims 69 and 71 or any other claim herein wherein the intermediate value is about equal to the starting state value.

73. The circuit of any one of claims 51 to 72 or any other claim herein wherein the controller is configured to control the first pulse duration ^^to be less than a time that it takes for the device to reach the ending steady state.

74. The circuit of any one of claims 51 to 73 or any other claim herein wherein the controller is configured to control the second gate-driving pulse have a duration that is sufficiently long for the device to reach the ending steady state during the second gate-driving pulse.

75. The circuit of any one of claims 51 to 74 or any other claim herein wherein the controller is configured to maintain the gate-driving voltage at an intermediate value for a period of time ^^after a conclusion of the first gate-driving pulse and before causing the gate-control voltage source to apply the second gate- driving voltage pulse.

76. The circuit of claim 75 or any other claim herein wherein the second gate- driving voltage pulse has a second effective amplitude that crosses from the intermediate value that is below the threshold voltage ^^^to a second pulse value that is above the threshold voltage ^^^.

77. The circuit of claim 75 or any other claim herein wherein the second gate- driving voltage pulse has a second effective amplitude that crosses from the intermediate value that is above the threshold voltage ^^^to a second pulse value that is below the threshold voltage ^^^.

78. The circuit of any one of claims 75 to 77 or any other claim herein wherein the intermediate value is the same at the starting state value.

79. The circuit of any one of claims 51 to 78 or any other claim herein wherein the first effective amplitude is the same as the second effective amplitude.

80. The circuit of any one of claims 51 to 79 or any other claim herein, wherein the controller is configured to implement a turn-ON operation, the device is non- conducting (e.g. between drain and source) in the starting steady state, the device is conducting (e.g. between drain and source) in the ending steady state, the starting state value and the intermediate value are less than the threshold voltage ^^^and the first pulse value and the second pulse value are greater than the threshold voltage ^^^.

81. The circuit of any one of claims 51 to 79 or any other claim herein, wherein the controller is configured to implement a turn-OFF operation, the device is conducting (e.g. between drain and source) in the starting steady state, the device is non-conducting (e.g. between drain and source) in the ending steadystate, the starting state value and the intermediate value are greater than the threshold voltage ^^^and the first pulse value and the second pulse value are less than the threshold voltage ^^^.

82. The circuit of any one of claims 51 to 81 or any other claim herein wherein the controller is configured to apply one or more additional gate-driving voltage pulses to the gate after applying the first gate driving pulse and prior to applying the second gate driving pulse.

83. The circuit of claim 82 or any other claim herein wherein the one or more additional gate-driving pulses have the same pulse parameters (e.g. amplitude and duration) as the first pulse.

84. The circuit of claim 82 or any other claim herein wherein at least one of the one or more additional gate-driving pulses has different pulse parameters (e.g. amplitude and duration) as the first pulse.

85. The circuit of any one of claims 82 to 84 wherein temporal pulse-spacing between the first pulse, the one or more additional pulses and the second pulse is the same.

86. The circuit of any one of claims 82 to 84 wherein temporal pulse-spacing between at least a first temporally adjacent pair of the first pulse, the one or more additional pulses and the second pulse is different than at least a second temporally adjacent pair of the first pulse, the one or more additional pulses and the second pulse.

87. The circuit of any one of claims 51 to 86 or any other claim herein wherein the controller is configured to repeatedly switch the device from the starting state to the ending state and to switch the device from the ending state back to the starting state.

88. The circuit of claim 87 or any other claim herein used in one of: a switch-mode power supply; a digital communication circuit; a discrete amplifier; a signalconditioning circuit; a LED drive; and a digital clock.

89. The circuit of any one of claims 87 to 88 or any other claim herein comprising: a sensor connected to sense a value of at least one of a voltage at a node of the device and a current through a node of the device; wherein the controller is configured to adjust one or more parameters of at least one of the first gate-driving pulse and the second gate-driving pulse based at least in part on the sensed value.

90. The circuit of claim 89 or any other claim herein wherein the node of the device is one of a gate, a source or a drain of a transistor.

91. The circuit of any one of claims 87 to 88 or any other claim herein comprising: a sensor connected to sense a temperature correlated with a temperature of the device; and wherein the controller is configured to adjust one or more parameters of at least one of the first gate-driving pulse and the second gate-driving pulse based at least in part on the sensed value.

92. The circuit of any one of claims 89 to 91 or any other claim herein wherein the controller configured to implement a control algorithm based at least in part on a desired value for the sensed value.

93. The circuit of any one of claims 89 to 92 or any other claim herein wherein the one or more parameters of the at least one of the first gate-driving pulse and the second gate-driving pulse comprises the first pulse duration ^^.

94. The circuit of any one of claims 89 to 93 or any other claim herein wherein the one or more parameters of the at least one of the first gate-driving pulse and the second gate-driving pulse comprises the first effective amplitude.

95. The circuit of any one of claims 89 to 94 or any other claim herein wherein the one or more parameters of the at least one of the gate-driving first pulse and the second gate-driving pulse comprises a period of time ^^after a conclusionof the first gate-driving pulse and before applying the second gate-driving voltage pulse during which the gate-driving voltage is maintained at the intermediate value.

96. The circuit of any one of claims 89 to 95 or any other claim herein wherein the one or more parameters of the at least one of the first gate-driving pulse and the second gate-driving pulse comprises the second effective amplitude.

97. The circuit of any one of claims 89 to 96 or any other claim herein wherein the controller is configured to apply the first gate-driving pulse by applying a first series of pulse-width modulated (PWM) voltage pulses to the gate, the first series of pulse-width modulated voltage pulses having first PWM parameters (e.g. a first PWM frequency, a first PWM duty cycle and / or a first PWM amplitude) which achieve the first effective amplitude and wherein the one or more parameters of the at least one of the first gate-driving pulse and the second gate-driving pulse comprises at least one of the first PWM parameters.

98. The circuit of any one of claims 89 to 97 or any other claim herein wherein the controller is configured to apply the second gate-driving pulse by applying a second series of pulse-width modulated (PWM) voltage pulses to the gate, the second series of pulse-width modulated voltage pulses having second PWM parameters (e.g. a second PWM frequency, a second PWM duty cycle and / or a second PWM amplitude) which achieve the second effective amplitude and wherein the one or more parameters of the at least one of the first gate-driving pulse and the second gate-driving pulse comprises at least one of the second PWM parameters.

99. Apparatus having any new and inventive feature, combination of features, or sub-combination of features as described herein.

100. Methods having any new and inventive steps, acts, combination of steps and / or acts or sub-combination of steps and / or acts as described herein.

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