Voltage RAMP generator for analog-to-digital conversion in a solid-state imaging device

Abstract

A voltage ramp generator for a solid-state imaging device includes an accumulator resistor. Unit cells switch between an on-state and an off-state in response to cell-specific select signals, wherein in the on- state each unit cell supplies an integer multiple of a unit current through the accumulator resistor, and wherein the unit current depends on an initial voltage. A first detection cell supplies a first detector current depending on the initial voltage. An error signal circuit outputs an active error signal when in a conversion period the first detector current falls below the unit current by more than a lower threshold current or exceeds the unit current by more than an upper threshold current.

Description

[0001] VOLTAGE RAMP GENERATOR FOR ANALOG-TO-DIGITAL CONVERSION IN A SOLID-STATE

[0002] IMAGING DEVICE

[0003] The present disclosure relates to a voltage ramp generator for analog -to-digital conversion of pixel voltages in solid-state imaging devices. In particular, the present disclosure refers to a digital-to-analog converter circuit for a voltage ramp generator.

[0004] BACKGROUND

[0005] Active image sensors in solid-state imaging devices include photoelectric conversion elements that generate a photocurrent with a current rating that is proportional to the received radiation intensity. A pixel circuit converts the small photocurrent into a pixel voltage with a comparatively large voltage amplitude. A downstream analog-to-digital converter converts the pixel voltage from the pixel circuit into a digital pixel value. For this purpose, the analog-to-digital converter compares the pixel voltage with a falling voltage ramp signal and counts regular clock pulses until the voltage level of the voltage ramp signal falls below the voltage level of the pixel voltage. The number of counted clock pulses results in the digital pixel value. The digital pixel values obtained from all pixel circuits of the image sensor for the same exposure describe a digital image. Computer vision methods utilize automatic feature recognition and extraction methods to obtain relevant information from the digital image or a digital image sequence in order to control higher- level processes in the fields of surveillance, information gathering, and automated process control.

[0006] SUMMARY

[0007] Computer vision methods can fail when the image information obtained from an image sensor is incorrect. A system employing computer vision can be less capable of identifying erroneous information in the received images than a human. Therefore, there is an ongoing need for solid-state imaging devices with high reliability and / or with the ability to output a measure for the reliability of the output image information. The present disclosure has been made in view of the above circumstances, and it is therefore desirable to provide a solid-state imaging device that outputs information on the reliability and / or quality of the output image information.

[0008] The present disclosure mitigates such and other shortcomings of the prior art. For this purpose, a voltage ramp generator according to the present disclosure includes an accumulator resistor, unit cells, a first detection cell, and an error signal circuit. The unit cells switch between an on-state and an off-state in response to cell-specific select signals, wherein in the on-state each unit cell supplies an integer multiple of a unit current through the accumulator resistor. The unit current depends on an initial voltage. The first detection cell supplies a first detector current depending on the initial voltage. The error signal circuit outputs an active error signal in a conversion period when the first detector current falls below the unit current by more than a lower threshold current or exceeds the unit current by more than an upper threshold current. Typically, the voltage ramp generator for the analog-to-digital converter of a solid-state imaging device with active image sensor does not actively drive the initial voltage during a conversion phase. Instead, a driver circuit supplies the initial voltage to a hold capacitor outside the conversion phase and a switch decouples the hold capacitor and the initial voltage from the output of the driver circuit for the conversion phase to isolate the initial voltage from noise and to reduce the influence of noise on the voltage ramp signal. When the initial voltage is decoupled from the output of the driver circuit, the initial voltage depends on the charge sampled on the hold capacitor. This charge may leak. The leakage current reduces or increases the initial voltage. A reduced initial voltage results in lower currents through the accumulator resistor and an in an unintentional intrinsic decrease of the amplitude of the voltage ramp signal tapped across the accumulator resistor. An increased initial voltage results in higher currents through the accumulator resistor and an in an unintentional intrinsic increase of the amplitude of the voltage ramp signal tapped across the accumulator resistor. The first detection cell detects when a leakage current exceeds a predefined threshold value. As the detection is based on the evaluation of current differences, the error detection is robust against noise. As the first detection cell can replicate the unit cell, the additional effort required for error detection is low. The detection cell enables early detection of a leakage current fault of the digital-to-analog converter that can be reported to a higher-level self-monitoring component of the solid-state imaging device.

[0009] BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

[0011] FIG. l is a schematic block diagram illustrating an imaging apparatus as an example for an electronic device including a solid-state imaging device with voltage ramp generator error detection in accordance with the embodiments.

[0012] FIG. 2 is a simplified block diagram illustrating a configuration example of a solid-state imaging device that includes an image sensor assembly with a voltage ramp generator for analog-to-digital conversion and voltage ramp generator failure detection in accordance with an embodiment.

[0013] FIG. 3 is a simplified block diagram of a voltage ramp generator with unit cells and two detection cells for voltage ramp generator failure detection in accordance with another embodiment.

[0014] FIG. 4 is a simplified circuit diagram indicating possible leakage paths in a voltage ramp generator for discussing effects of the embodiments.

[0015] FIG. 5 is a timing diagram illustrating voltage ramp signals VRMP for the leakage-free case and for the leakage case for illustrating effects of the leakage paths shown in FIG. 4. FIG. 6 is a circuit diagram of a voltage ramp generator with an error detection part for voltage ramp generator failure detection in accordance with another embodiment.

[0016] FIG. 7 is a circuit diagram of an error signal circuit for generating an error signal in accordance with another embodiment.

[0017] FIG. 8 is a diagram showing an example of a laminated structure of a solid-state imaging device according to an embodiment of the present disclosure.

[0018] FIG. 9 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

[0019] FIG. 10 is a diagram of assistance in explaining an example of installation positions of an outside-vehicle information detecting section and an imaging section of the vehicle control system of FIG. 9.

[0020] DETAILED DESCRIPTION

[0021] Embodiments for implementing techniques of the present disclosure (also referred to as “embodiments” in the following) will be described below in detail using the drawings. The techniques of the present disclosure are not limited to the described embodiments, and various features in the embodiments are illustrative only. The same elements or elements with the same functions are denoted by the same reference signs. Duplicate descriptions are omitted.

[0022] Connected electronic elements may be electrically connected through a direct, permanent low-resistive connection, e.g., through a conductive line. The terms “electrically connected” and “signal -connected” may also include a connection through other electronic elements provided and suitable for permanent and / or temporary signal transmission and / or transmission of energy. Electronic elements can be electrically connected or signal-connected via resistors, capacitors, electronic switches such as FETs (field effect transistors), or transistor circuits such as transmission gates. Directly electrically connected electronic elements are connected through a low-resistive wiring, an ohmic contact and / or a unipolar semiconductor junction.

[0023] The load path of a transistor is the controlled current path through a transistor. A voltage applied to the gate of a field effect transistor (FET) controls the current flow through the load path (controlled path) between source and drain of the FET by field effect.

[0024] A digital signal alternates between at least one active level and at least one inactive level. A digital signal having an active level is active. A digital signal having an inactive level is inactive. For each signal separately, the active level can be a digital high level and the inactive level a digital low level, or the active level can be the digital low level and the inactive level the digital high level. Though in the following a technology for voltage ramp generator failure detection in solid-state imaging devices is described in the context of certain types of row-wise pixel readouts, the technology may also be used for other types of pixel circuits and for pixel-wise pixel readout.

[0025] In FIG. 1, an imaging apparatus 1 includes an optical system 91, a solid-state imaging device 90, a storage unit 92, and a control unit 93. The optical system 91 includes one or more lenses and various mechanisms such as an autofocus mechanism and a diaphragm mechanism, and guides light from an object to a light receiving surface of the solid-state imaging device 90.

[0026] The solid-state imaging device 90 includes an image sensor assembly having a plurality of active pixel circuits for intensity readout. Each pixel circuit converts incident radiation into electric signals by photoelectric conversion, and outputs pixel voltages with a voltage level monotonically increasing with increasing intensity of the incident radiation. The solid-state imaging device 90 converts the pixel voltages into digital pixel values and further includes a signal processing unit that performs predetermined signal processing on the digital pixel values to obtain image data.

[0027] The storage unit 92 stores the image data, e.g., frames output from the solid-state imaging device 90 in a storage medium. The storage medium may include a volatile storage medium and / or non-volatile storage medium. The non-volatile storage medium may be or include a flash memory or a hard disk drive. The nonvolatile storage medium may be or include a dynamic random -access memory (DRAM).

[0028] The control unit 93 controls the solid-state imaging device 90 such that the solid-state imaging device 90 performs an imaging operation. The imaging operation includes obtaining images from a scene and outputting image data including information about the images.

[0029] FIG. 2 illustrates a configuration example of a solid-state imaging device 90 in accordance with embodiments of the present technology. The solid-state imaging device 90 includes a signal processing unit 80 and an image sensor assembly 70. The image sensor assembly 70 includes a row decoder / driver 30, a pixel array 10, a group signal processing unit 20 that includes a plurality of group signal processing circuits 200, a digital readout unit 40, and a sensor controller 50.

[0030] The pixel array unit 10 includes a plurality of identical pixel circuits 100. The pixel circuits 100 may be any active pixel sensors (APS) for intensity readout with one or two photoelectric conversion elements and three, four or more pixel transistors. The pixel circuits 100 convert incident radiation into a pixel internal voltage that is a monotonic function of the intensity of incident radiation detected by the pixel circuit 100 in an exposure period. When a pixel circuit 100 is selected in a row readout period, the selected pixel circuit 100 outputs a pixel voltage controlled by the pixel internal voltage to a voltage signal line 1 .

[0031] The pixel circuits 100 may be arranged matrix-like in columns and rows. A subset of pixel circuits 100 assigned to the same column form a pixel column. A subset of pixel circuits 100 assigned to the same row form a pixel row. The row decoder / driver 30 controls the pixel circuits 100 by generating pixel control signals for operating and selecting groups of pixel circuits 100. The pixel control signals control reset states, exposure time, internal temporal storage of the illumination information, and the readout of the pixel circuits 100. The row decoder / driver 30 outputs the control signals for operating the pixel transistors of the pixel circuits 100 on pixel control lines 13 according to driver timing signals supplied from the sensor controller 50.

[0032] The row decoder / driver 30 controls all pixel circuits 100 of a selected group of pixel circuits 100 synchronously. The selected group of pixel circuits 100 may include some pixel circuits 100 of one pixel row, all pixel circuits 100 of one pixel row, or some or all pixel circuits 100 of more than one pixel row. The following part of the description refers to “pixel rows” as examples for “groups of pixel circuits” for simplicity.

[0033] The pixel circuits 100 of a pixel output group sequentially pass information about the pixel internal voltage that depends on an illumination intensity detected by the pixel circuits 100 in an exposure period to at least one voltage signal line (vertical signal line) 19. Each pixel output group may include some pixel circuits 100 of one pixel column, all pixel circuits 100 of one pixel column, or some or all pixel circuits 100 of more than one pixel column. The following part of the description refers to “pixel columns” as examples for “pixel output groups” for simplicity.

[0034] Each pixel circuit 100 includes an amplifier transistor 102 in a source follower configuration with an element of the group signal processing unit 20. A load path of the amplifier transistor 102 is electrically connected between a positive pixel supply potential VDDH and the voltage signal line 19. Each voltage signal line 19 sequentially conveys the pixel voltages from the pixel circuits 100 of one of the pixel columns to the group signal processing unit 20.

[0035] The column signal processing unit 20 includes a column signal processing circuit 200 for each voltage signal line 19, at least one voltage ramp generator 300 and at least one counter circuit 26. The column signal processing circuit 200 converts the pixel voltage into digital pixel values, may preprocess the digital pixel values and outputs the digital pixel values or the preprocessed digital pixel values to the digital readout unit 40. Each column signal processing circuit 200 includes a constant current source 210, a comparator circuit 220, and a digital counting circuit 230.

[0036] The constant current source 210 complements the amplifier transistor 102 of the selected pixel circuit 100 to a source follower that outputs the pixel voltage of a selected pixel circuit 100 to a first input of the comparator circuit 220 in a row readout period. The constant current source 210 sinks a constant current.

[0037] The column signal processing unit 20 may include one voltage ramp generator 300 for each column signal processing circuit 200. In the illustrated example, one single global voltage ramp generator 300 supplies the same voltage ramp signal VRMP to all column signal processing circuits 200. The voltage ramp generator 300 outputs the voltage ramp signal VRMP in response to an active ramp enable signal REN. The voltage ramp signal VRMP falls from a high voltage level to a low voltage level continuously or in small steps. The voltage ramp signal VRMP is applied to the second inputs of the comparator circuits 220 in the row readout periods. The comparator circuit 220 outputs an active comparator output signal when the voltage level of the voltage ramp signal VRMP falls below the voltage level of the pixel voltage applied to the first input of the comparator circuit 220.

[0038] The voltage ramp generator 300 outputs an active error signal ERR when an error condition is fulfilled, wherein the error condition indicates that a deviation of the voltage ramp signal VRMP from a target ramp signal form is outside a tolerance window. The error signal ERR can be transmitted to the sensor controller 50 and / or to a signal interface of the image sensor assembly 70.

[0039] The column signal processing unit 20 may include one counter circuit 26 or each column signal processing circuit 200. In the illustrated example, one global counter circuit supplies the same count signals to all column signal processing circuits 200.

[0040] The counter circuit 26 outputs a digital count value of a digital counter on a digital bus to data inputs of the digital counting circuits 230 in response to an active count enable signal CEN. The active count enable signal CEN and the active ramp enable signal REN have a predetermined temporal relationship to each other and to the beginning of the row readout period. The digital counting circuit 230 latches the current count value applied to the data inputs with a transition from an inactive comparator output signal to the active comparator output signal. The latched count value represents the digital pixel value of the pixel voltage obtained from the pixel circuit 100 in the row readout period. The digital readout unit 40 may store digital values obtained in data phases and preset phases for correlated double sampling (CDS) and / or digital double sampling (DDS).

[0041] The digital readout unit 40 receives and temporarily stores the digital pixel values from the column signal processing unit 20.

[0042] The sensor controller 50 generates the driver timing signal and outputs the driver timing signals to the row decoder / driver 30. The sensor controller 50 generates the ramp enable signal REN and the count enable signal CEN for controlling the voltage ramp generator 300 and the counter circuit 26 and may generate a readout control signal that controls the readout of the digital values from the readout digital readout unit 40 to the signal processing unit 80 and / or to a digital interface.

[0043] FIG. 3 shows the voltage ramp generator 300 of FIG. 2 in more detail.

[0044] The voltage ramp generator 300 includes an accumulator resistor 340. Unit cells 330 are configured to switch between an on-state and an off-state in response to cell-specific select signals si, s2, ... . In the on- state, each unit cell 330 supplies an integer multiple n of a unit current Io through the accumulator resistor 340. The unit current Io depends on an initial voltage Vo. The voltage ramp generator 300 further includes at least a first detection cell 361 supplying a first detector current IDI depending on the initial voltage Vo. An error signal circuit 370 is configured to output an active error signal ERR when in a conversion period the first detector current IDI falls below the unit current Io by more than a lower threshold current or exceeds the unit current Io by more than a higher threshold current.

[0045] Each unit cell 330 may supply the same integer multiple n of the unit current Io. For example, the integer multiple n for all unit cells 330 may be equal 1. Alternatively, the integer multiple n for the unit cells 330 increases according to 2n. The voltage ramp generator 300 may further include an idle unit cell supplying the unit current Io to the accumulator resistor 340, wherein the idle unit cell does not include a switch and is permanently in the on-state.

[0046] The cell-specific select signals si, s2, ... can be controlled to digitally count down by one from a high digital count value to a low digital count value, so that the total current through the accumulator resistor 340 is reduced by the unit current Io with each count value in a conversion period.

[0047] The conversion period includes first phases and second phases. In the first phases, the initial voltage Vo is precharged and kept at a high initial voltage, with all unit cells 330 in the on-state. In the second phases, the cell-specific select signals si, s2, .... count down and the voltage across the accumulator resistor 340 decreases monotonously in small steps.

[0048] The accumulator resistor 340 adds up the currents through all switched-on unit cells 330. The voltage ramp signal VRMP is tapped across the accumulator resistor 340. An instantaneous voltage level of the voltage ramp signal VRMP depends not only on the digital number applied via the cell-specific select signals si, s2, ... but also on the initial voltage Vo. Under certain conditions, the initial voltage Vo can drift. A drift of the initial voltage Vo distorts the shape of the voltage ramp signal VRMP. When the voltage ramp signal VRMP deviates from a target shape, the output signal of the comparator circuit 220 of FIG. 2 becomes erroneous. By receiving the error signal ERR output from the error signal circuit 370, a higher-level processing instance can be informed at an early stage that the present digital pixel values are unreliable.

[0049] The voltage ramp generator may include a hold capacitor 325 configured to be charged to the initial voltage Vo in a sampling period outside the conversion period.

[0050] The hold capacitor 325 may be electrically connected between a conductor track 326 for the initial voltage Vo and a power supply potential. For example, a first electrode (fixed electrode) of the hold capacitor 325 is electrically connected with a positive supply potential VDD and a second electrode (controlled electrode) is electrically connected with the conductor track 326 for the initial voltage Vo.

[0051] The voltage ramp generator 300 may further include a sampling switch 320 configured to connect a controllable electrode of the hold capacitor 325 with a voltage source 310 in the sampling period and disconnect the controllable electrode and the unit cells 330 from the voltage source 310 in the conversion period. The sampling switch 320 may include a field effect transistor or a circuit including field effect transistors, e.g., a transmission gate. In the illustrated embodiment, the sampling switch 320 is a p channel field effect transistor (pFET) with a load path electrically connected between an output of a voltage source 310 and the hold capacitor 325. An active sample / hold signal SHSW supplied to the gate of the pFET switches on the sampling switch 325 for a sampling period and switches off the sampling switch 325 for the conversion period. The sample / hold signal SHSW may be controlled by the sensor controller 50 of FIG. 2.

[0052] The voltage ramp generator 300 may include one single detection cell 361 in cases when it is known that one leakage current direction dominates the other.

[0053] The illustrated voltage ramp generator 300 includes a second detection cell 362 configured to supply a second detector current ID2 depending on the initial voltage Vo, wherein the error signal circuit 370 is configured to generate an active first fault signal when the first detector current IDI falls below the unit current Io by more than an lower threshold current and an active second fault signal when the second detector current ID2 exceeds the unit current Io by more than an upper threshold current.

[0054] In combination with two detection circuits 361, 362, the error signal circuit 370 can output an active error signal ERR regardless of the direction of the leakage current. No deep knowledge about a dominating leakage current direction is required.

[0055] In the illustrated embodiment, the error signal circuit 370 is configured to output the active error signal ERR when the first fault signal or the second fault signal is active.

[0056] Each unit cell 330 includes a unit field effect transistor 331 and a unit switch 333 electrically connected in series between a positive supply potential VDD and the accumulator resistor 340, wherein the unit field effect transistors 331 have a same channel length.

[0057] The unit field effect transistors 331 may be pFETs receiving the initial voltage Vo at the gates. The unit field effect transistors 331 may be processed side-by-side so that significant transistor dimensions including the channel lengths in the unit field effect transistors are to a high degree identical. The unit field effect transistors 331 may have the same channel widths or integer multiples of a unit channel width. The unit switches 331 may be FETs receiving the cell-specific select signals si, s2, ... at the gates.

[0058] In the illustrated embodiment, each detection cell 361, 362 includes a unit field effect transistor 331 connected in series with a cell specific detector load 365 between the positive supply potential VDD and a reference potential VSS, wherein the unit field effect transistors 331 of the unit cells 330 and the detection cells 360 have the same size.

[0059] For example, the unit field effect transistors 331 of the detection cells 360 and the unit cells 330 may have a same channel width per unit current and a same channel length. FIG. 4 shows possible leakage current paths Ii, I2, I2, I4 for the charge stored on the controllable electrode of the hold capacitor 325. The controllable electrode is charged in the sampling period and holds the sampled charge in the conversion period, which is the hold period of the sampling switch 320. A first potential leakage path Ii is between the body and source connection of the sampling switch 325. A second leakage path I2is between the electrodes of the hold capacitor 325. A third leakage path I3is through the pn junction of a protection diode 328 provided between the positive supply potential VDD and a conductor track 326 connecting the controlled electrode of the hold capacitor 325 with the unit cells 330 and the detection cells 361, 362. A fourth leakage path I4 is gate tunneling in the unit field effect transistors 331.

[0060] FIG. 5 shows an ideal voltage ramp signal 391 in a conversion period tc of the analog -to-digital converter including the comparator circuit 220 and the digital counting circuit 230 of FIG. 2. The conversion period tc corresponds to the hold period of the sampling switch 320. In the conversion period tc, the sample / hold signal SHSW is inactive and turns off the sampling switch 320 in FIG. 3. The select signals si, s2, ... are controlled so that the voltage amplitude of the voltage ramp signal VRMP is constant at a high level VH from to to ti, linearly falls starting from ti, is constant at a high level VH from t2to t2, and linearly falls starting from t2. At ti and tv the digital counter circuit 230 of FIG. 2 starts to count. The comparator circuit 220 of FIG. 2 compares the pixel voltage with the voltage ramp signal VRMP and stops the digital counter circuit 230 of FIG. 2 when the voltage ramp signal VRMP falls below the pixel voltage for the preset phase VP at tp and below the pixel voltage for the data phase VD at to.

[0061] FIG. 5 also shows a faulty voltage ramp signal 392 for the case of a significant leakage current from the controlled electrode of the hold capacitor 325. The voltage amplitude of the faulty voltage ramp signal 392 decreases between to and ti and between t2and f. From ti to t2, and from t3to t4, the voltage amplitude of the faulty voltage ramp signal 392 decreases faster and falls below the pixel voltage for the preset phase Vp at tpewhich is earlier than tp and below the pixel voltage for the data phase VD at tee which is earlier than tD. For the fault voltage ramp signal 392 the digital counting circuit 230 stops at a lower count value than for the ideal voltage ramp signal 391.

[0062] Accordingly, for the case of a significant leakage current onto the controlled electrode of the hold capacitor 325, the amplitude of the corresponding faulty voltage ramp signal rises between to and ti and between t2and t2. From ti to t2and from ts to t4, the voltage amplitude of the faulty voltage ramp signal decreases at a lower rate than the ideal voltage ramp signal 391. The digital counting circuit 230 stops at a higher count value than for the ideal voltage ramp signal 391.

[0063] In the voltage ramp generator illustrated in FIG. 6, the detector load 365 of the first detection cell 361 includes a first load field effect transistor 366, and the detector load 365 of the second first detection cell 362 includes a second load field effect transistor 367, wherein the first and second load field effect transistor 366, 367 have different size. The first and second threshold currents may be adjusted by the channel widths of the first and second load field effect transistors 366, 367 and / or the gate bias applied to the gates of the first and second load field effect transistors 366, 367.

[0064] To adjust the first and second threshold currents, the first and second detection cells 361, 362 are designed such that in the ideal case without leakage current the first detection current IDI and the second detection current ID2 are equal to the unit current Io. The different load detection currents IO+ITH, IO-ITH are adjusted via channel widths and / or the gate bias of the first and second load field effect transistors 366, 367. In the illustrated embodiment, the first and second load field effect transistors 366, 367 receive the same gate bias voltage Vbias at the gates. The threshold currents ITH may be programmable in a range of about O.25*Io.

[0065] The first fault signal becomes active when the first detector current IDI in the first detection cell 361 exceeds a first load detection current IO+ITH, and the second fault signal becomes active when the second detector current ID2 in the second detection cell 362 falls below a second load detection current IO-ITH.

[0066] FIG. 7 shows an error signal circuit 370 that includes a first comparator circuit 371 configured to output the first fault signal when a voltage generated by the current in the first detection cell 361 exceeds a first comparator threshold voltage, and a second comparator circuit 372 configured to output the second fault signal, when a voltage generated by the current in the first detection cell 361 falls below a second comparator threshold voltage.

[0067] The first comparator circuit 371 may include a non-inverting Schmitt trigger. The second comparator circuit 372 may include an inverting Schmitt trigger.

[0068] The error signal circuit 370 may output the first and second fault signals independently from each other in order to inform the high-level processing instance in more detail about the current leakage mechanism.

[0069] In the illustrated embodiment, the error signal circuit 370 further includes a gate circuit 375 configured to output an active error signal ERR when at least one of the first and second fault signals is active.

[0070] The voltage ramp generator 300 further includes a voltage source 310 including a unit field effect transistor 331 and a load 311 electrically connected in series between the positive supply potential VDD and the reference potential VSS, wherein gate and drain of the unit field effect transistor 331 are short-circuited and connected to the sampling switch 320 at a side opposite the hold capacitor 325.

[0071] The voltage source 310 is effective as the control branch of a current mirror circuit in the sampling periods.

[0072] A counter circuit 390 is configured to output the select signals si, s2, ... according to a digital counting scheme. An image sensor assembly 70 as illustrated in FIG. 2 includes a pixel circuit 100 configured to output a pixel voltage, wherein the pixel voltage is a function of received radiation intensity. An analog-to-digital converter is configured to convert the pixel voltage into a digital pixel value by comparing the pixel voltage with a voltage ramp signal VRMP generated by a voltage ramp generator 300 as illustrated in FIG. 3 or FIG. 6. The voltage ramp generator 300 includes an accumulator resistor 340 and unit cells 330 configured to switch between an on-state and an off-state in response to cell-specific select signals, wherein in the on- state each unit cell 330 supplies an integer multiple of a unit current Io through the accumulator resistor 340, and wherein the unit current Io depends on an initial voltage Vo. The voltage ramp generator 300 further includes at least a first detection cell 361 configured to supply a first detector current depending on the initial voltage; and an error signal circuit 370 configured to output an active error signal ERR when in a conversion period the first detector current IDI falls below the unit current Io by more than a lower threshold current or exceeds the unit current Io by more than an upper threshold current.

[0073] FIG. 8 is a diagram illustrating an example in which the image sensor assembly 70 of FIG. 2 is formed by a stacked CMOS image sensor (CIS) having a two-layer structure with a first chip 910 (radiation receiving chip) and a second chip 920 (processing chip). The radiation receiving chip includes at least the photoelectric conversion elements. For example, the radiation receiving chip may include only the photoelectric conversion elements, only the conversion portions of the pixel circuits, or the conversion portions and at least some elements of the PWM portions of the pixel circuits. The image sensor assembly is formed as one sensor by bonding the radiation receiving chip and the processing chip while electrically bringing contact pads on the radiation receiving chip in contact with corresponding contact pads on the processing chip.

[0074] FIG. 9 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a system to which the technology according to an embodiment of the present disclosure can be applied.

[0075] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in FIG. 9, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and a vehiclemounted network interface 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0076] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like. The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

[0077] The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. The outside-vehicle information detecting unit 12030 can be connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 imaging an image of the outside of the vehicle and receives the imaged image. Based on the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

[0078] The imaging section 12031 maybe or may include an image sensor assembly according to the embodiments of the present disclosure. The light received by the imaging section 12031 may contain visible light and / or invisible light such as infrared rays or the like.

[0079] The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle and may be or may include an image sensor assembly according to the embodiments of the present disclosure. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that includes the solid-stage imaging device and that is focused on the driver. Based on detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver or may determine whether the driver is dozing.

[0080] The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in- vehicle information detecting unit 12040 and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like. In addition, the microcomputer 12051 can perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0081] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle which information is obtained by the outsidevehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0082] The sound / image output section 12052 transmits an output signal of at least one of a sound or an image to an output device capable of visually or audible notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of FIG. 9, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display or a head-up display.

[0083] FIG. 10 is a diagram depicting an example of the installation position of the imaging section 12031, wherein the imaging section 12031 may include imaging sections 12101, 12102, 12103, 12104, and 12105.

[0084] The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, side-view mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the side view mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0085] Incidentally, FIG. 10 depicts an example of photographing ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the side view mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird's-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example. At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, imaging element having pixels for phase difference detection or may include a ToF module including an image sensor according to the embodiments of the present disclosure.

[0086] For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100 on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km / hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

[0087] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

[0088] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images ofthe imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0089] The example of the vehicle control system to which the technology according to an embodiment of the present disclosure is applicable has been described above. By applying an image sensor according to the embodiments of the present disclosure, an early error detection can be implemented, and reliability of the system can be enhanced.

[0090] Additionally, embodiments of the present technology are not limited to the above-described embodiments, but various changes can be made within the scope of the present technology without departing from the gist of the present technology.

[0091] The image sensor according to the present disclosure may be any device used for analyzing and / or processing radiation such as visible light, infrared light, ultraviolet light, and X-rays. For example, an image sensor according to the embodiments may be any electronic device in the field of traffic, the field of home appliances, the field of medical and healthcare, the field of security, the field of beauty, the field of sports, the field of agriculture, the field of image reproduction or the like.

[0092] Specifically, in the field of image reproduction, the image sensor according to the embodiments may be a device for capturing an image to be provided for appreciation, such as a digital camera, a smart phone, or a mobile phone device having a camera function. In the field of traffic, for example, a solid-state imaging device including an image sensor according to the embodiments may be integrated in an in-vehicle sensor that captures the front, rear, peripheries, an interior of the vehicle, etc. for safe driving such as automatic stop, recognition of a state of a driver, or the like, in a monitoring camera that monitors traveling vehicles and roads, or in a distance measuring sensor that measures a distance between vehicles or the like.

[0093] In the field of home appliances, the image sensor according to the embodiments may be integrated in any type of sensor that can be used in devices provided for home appliances such as TV receivers, refrigerators, and air conditioners to capture gestures of users and perform device operations according to the gestures. Accordingly, the image sensor according to the embodiments may be integrated in home appliances such as TV receivers, refrigerators, and air conditioners and / or in devices controlling the home appliances. Furthermore, in the field of medical and healthcare, the image sensor according to the embodiments may be integrated in any type of sensor, e.g., a solid-state image device, provided for use in medical and healthcare, such as an endoscope or a device that performs angiography by receiving infrared light.

[0094] In the field of security, the image sensor according to the embodiments can be integrated in a device provided for use in security, such as a monitoring camera for crime prevention or a camera for person authentication use. Furthermore, in the field of beauty, an image sensor according to the embodiments can be used in a device provided for use in beauty, such as a skin measuring instrument that captures skin or a microscope that captures a probe. In the field of sports, an image sensor according to the embodiments can be integrated in a device provided for use in sports, such as an action camera or a wearable camera for sport use or the like. Furthermore, in the field of agriculture, the image sensor can be used in a device provided for use in agriculture, such as a camera for monitoring the condition of fields and crops.

[0095] The present technology can also be configured as described below:

[0096] [1] A voltage ramp generator (300) for a solid-state imaging device, comprising: an accumulator resistor (340); unit cells (330) configured to switch between an on-state and an off-state in response to cell-specific select signals, wherein in the on-state each unit cell (330) supplies an integer multiple of a unit current through the accumulator resistor (340), and wherein the unit current depends on an initial voltage; a first detection cell (361) configured to supply a first detector current depending on the initial voltage; an error signal circuit (370) configured to output an active error signal when in a conversion period the first detector current falls below the unit current by more than a lower threshold current or exceeds the unit current by more than an upper threshold current.

[0097] [2] The voltage ramp generator according to [1], further including: a hold capacitor (325) configured to be charged to the initial voltage in a sampling period outside the conversion period.

[0098] [3] The voltage ramp generator according to [2], further comprising: a sampling switch (320) configured to connect a controllable electrode of the hold capacitor (325) with a voltage source (310) in the sampling period and disconnect the controllable electrode and the unit cells (330) from the voltage source (310) in the conversion period.

[0099] [4] The voltage ramp generator according to any of [1] to [3], further comprising: a second detection cell (362) configured to supply a second detector current depending on the initial voltage, wherein the error signal circuit (370) is configured to generate an active first fault signal when the first detector current falls below the unit current by more than a lower threshold current and an active second fault signal when the second detector current exceeds the unit current by more than an upper threshold current.

[0100] [5] The voltage ramp generator according to [4], wherein the error signal circuit (370) is configured to output the active error signal when the first fault signal or the second fault signal is active.

[0101] [6] The voltage ramp generator according to any of [1] to [5], wherein each unit cell (330) comprises a unit field effect transistor (331) and a unit switch (333) electrically connected in series between a positive supply potential and the accumulator resistor (340), and wherein the unit field effect transistors (331) have a same channel length.

[0102] [7] The voltage ramp generator according to [6], wherein each detection cell (361, 362) comprises a unit field effect transistor (331) connected in series with a cell specific detector load (365) between the positive supply potential and a reference potential, and wherein the unit field effect transistors (331) of the unit cells (330) and the detection cells (360) have the same size. [8] The voltage ramp generator according to [7], wherein the detector load (365) of the first detection cell (361) comprises a first load field effect transistor (366), the detector load (365) of the second first detection cell (362) comprises a second load field effect transistor (367), the first and second load field effect transistor (366, 367) have different size.

[0103] [9] The voltage ramp generator according to [8], wherein the first fault signal becomes active when the first detector current ID1 in the first detection cell (361) exceeds a first load detection current I0+1TH, and the second fault signal becomes active when the second detector current ID2 in the second detection cell (362) falls below a second load detection current I0-ITH.

[0104]

[0010] The voltage ramp generator according to any of [7] to [9], wherein the error signal circuit (370) comprises a first comparator circuit (371) configured to output the first fault signal when a voltage generated by the current in the first detection cell (361) exceeds a first comparator threshold voltage, and a second comparator circuit (372) configured to output the second fault signal when a voltage generated by the current in the second detection cell (362) falls below a second comparator threshold voltage.

[0105]

[0011] The voltage ramp generator according to

[0010] , wherein the error signal circuit (370) comprises a gate circuit (375) configured to output an active error signal when at least one of the first and second fault signals is active.

[0106]

[0012] The voltage ramp generator according to any of [6] to

[0011] , further comprising: a voltage source (310) comprising a unit field effect transistor (331) and a load (311) electrically connected in series between the positive supply potential and the reference potential, wherein gate and drain of the unit field effect transistor are short-circuited and connected to the sampling switch (320) at a side opposite the hold capacitor 325.

[0107]

[0013] The voltage ramp generator according to any of [1] to

[0012] , further comprising: a counter circuit (390) configured to output the select signals si, s2, ... according to a digital counting scheme.

[0108]

[0014] An image sensor assembly (70), includes a pixel circuit (100) configured to output a pixel voltage, wherein the pixel voltage is a function of received radiation intensity; and an analog-to-digital converter configured to convert the pixel voltage into a digital pixel value by comparing the pixel voltage with a voltage ramp signal generated by a voltage ramp generator (300), the voltage ramp generator (300) comprising: an accumulator resistor (340), unit cells (330) configured to switch between an on-state and an off-state in response to cell-specific select signals, wherein in the on-state each unit cell (330) supplies an integer multiple of a unit current through the accumulator resistor (340), and wherein the unit current depends on an initial voltage, a first detection cell (361) configured to supply a first detector current depending on the initial voltage, and an error signal circuit (370) configured to output an active error signal when in a conversion period the first detector current falls below the unit current by more than a lower threshold current or exceeds the unit current by more than an upper threshold current.

Claims

CLAIMS1. A voltage ramp generator for a solid-state imaging device, comprising: an accumulator resistor; unit cells configured to switch between an on-state and an off-state in response to cell-specific select signals, wherein in the on-state each unit cell supplies an integer multiple of a unit current through the accumulator resistor, and wherein the unit current depends on an initial voltage; a first detection cell configured to supply a first detector current depending on the initial voltage; an error signal circuit configured to output an active error signal when in a conversion period the first detector current falls below the unit current by more than a lower threshold current or exceeds the unit current by more than an upper threshold current.

2. The voltage ramp generator according to claim 1, further comprising: a hold capacitor configured to be charged to the initial voltage in a sampling period outside the conversion period.

3. The voltage ramp generator according to claim 2, further comprising: a sampling switch configured to connect a controllable electrode of the hold capacitor with a voltage source in the sampling period and disconnect the controllable electrode and the unit cells from the voltage source in the conversion period.

4. The voltage ramp generator according to claim 1, further comprising: a second detection cell configured to supply a second detector current depending on the initial voltage, wherein the error signal circuit is configured to generate an active first fault signal when the first detector current falls below the unit current by more than a lower threshold current and an active second fault signal when the second detector current exceeds the unit current by more than an upper threshold current.

5. The voltage ramp generator according to claim 4, wherein the error signal circuit is configured to output the active error signal when the first fault signal or the second fault signal is active.

6. The voltage ramp generator according to claim 1, wherein each unit cell comprises a unit field effect transistor and a unit switch electrically connected in series between a positive supply potential and the accumulator resistor, and wherein the unit field effect transistors have a same channel length.

7. The voltage ramp generator according to claim 6, wherein each detection cell comprises a unit field effect transistor connected in series with a cell specific detector load between the positive supply potential and a reference potential, andwherein the unit field effect transistors of the unit cells and the detection cells have the same size.

8. The voltage ramp generator according to claim 7, wherein the detector load of the first detection cell comprises a first load field effect transistor, the detector load of the second first detection cell comprises a second load field effect transistor, the first and second load field effect transistor have different size.

9. The voltage ramp generator according to claim 8, wherein the first fault signal becomes active when the first detector current in the first detection cell exceeds a first load detection current, and the second fault signal becomes active when the second detector current in the second detection cell falls below a second load detection current.

10. The voltage ramp generator according to claim 7, wherein the error signal circuit comprises a first comparator circuit configured to output the first fault signal when a voltage generated by the current in the first detection cell exceeds a first comparator threshold voltage, and a second comparator circuit configured to output the second fault signal when a voltage generated by the current in the second detection cell falls below a second comparator threshold voltage.

11. The voltage ramp generator according to claim 10, wherein the error signal circuit comprises a gate circuit configured to output an active error signal when at least one of the first and second fault signals is active.

12. The voltage ramp generator according to claim 6, further comprising: a voltage source comprising a unit field effect transistor and a load electrically connected in series between the positive supply potential and the reference potential, wherein gate and drain of the unit field effect transistor are short-circuited and connected to the sampling switch at a side opposite the hold capacitor.

13. The voltage ramp generator according to claim 1, further comprising: a counter circuit configured to output the select signals according to a digital counting scheme.

14. An image sensor assembly, comprising: a pixel circuit configured to output a pixel voltage, wherein the pixel voltage is a function of received radiation intensity; and an analog-to-digital converter configured to convert the pixel voltage into a digital pixel value by comparing the pixel voltage with a voltage ramp signal generated by a voltage ramp generator, the voltage ramp generator comprising: an accumulator resistor,unit cells configured to switch between an on-state and an off-state in response to cell-specific select signals, wherein in the on-state each unit cell supplies an integer multiple of a unit current through the accumulator resistor, and wherein the unit current depends on an initial voltage, a first detection cell configured to supply a first detector current depending on the initial voltage, and an error signal circuit configured to output an active error signal when in a conversion period the first detector current falls below the unit current by more than a lower threshold current or exceeds the unit current by more than an upper threshold current.

Images