Duobinary signal reception device and method

Abstract

The present invention relates to a duobinary signal reception device and method in which: a variable gain amplifier (VGA) amplifies a duobinary signal; a duobinary-to-non return to zero (NRZ) converter restores an NRZ signal on the basis of a differential signal of the amplified duobinary signal and a predetermined reference voltage signal; a digital regulator voltage (DRV) circuit outputs the restored NRZ signal; and the duobinary-to-NRZ converter comprises an exclusive OR (XOR) gate to which the differential signal of the amplified duobinary signal is input, and a comparator to which an output of the XOR gate and the reference voltage signal are input.

Description

Duobinary signal receiving device and method

[0001] The present invention relates to a duobinary signal receiving device and method.

[0002] As technological advancements increase the required data rates, channel bandwidth remains limited. If the data rate exceeds the channel bandwidth, inter-symbol interference (ISI) and noise can distort the signal, increasing bit errors. To address this, multi-level signaling (MLS) can be used instead of the traditional binary Non Return to Zero (NRZ) method.

[0003] Duobinary is a type of multilevel signaling method with three levels: low, middle, and high. The receiver, which receives the multilevel signal, typically uses an analog-to-digital converter (ADC) to convert the signal into NRZ. The ADC receives a data signal and a reference voltage signal, compares their magnitudes, and outputs a digital output. The reference voltage signal must be located between each level. Therefore, the reference voltage margin for duobinary signals is 1 / 2 VDD.

[0004] Meanwhile, for a PAM-4 (Pulse Amplitude Modulation-4) signal with 4 levels, the reference voltage margin is 1 / 3 VDD, and thus, the duobinary signal has a larger voltage margin than the PAM-4 signal, which is advantageous in setting the reference voltage and enables the ADC to perform accurate NRZ conversion.

[0005] Meanwhile, the duobinary signal y[n] is synthesized using the formula y[n] = x[n] + x[n-1], and the signal synthesized in this way at the transmitter must be received at the receiver and restored to the original signal x[n].

[0006] However, since the restoration formula at this time is x[n] = y[n] - x[n-1], if x[n] is restored incorrectly once, x[n-1] also becomes incorrect data, so there is a problem that an error propagates once it occurs.

[0007] Therefore, research is needed on how to prevent the spread of these errors.

[0008] [Prior Art Literature]

[0009] [Patent Document]

[0010] Korean Patent Publication No. 10-2022-0070941

[0011] The present invention has been devised to solve the above problems, and an object of the present invention is to provide a duobinary signal receiving device and method.

[0012] According to one embodiment of the present invention for achieving the above object, a duobinary signal receiving device comprises: a VGA for amplifying a duobinary signal; a duobinary-to-NRZ converter for restoring an NRZ signal based on a differential signal of the amplified duobinary signal and a predetermined reference voltage signal; and a DRV circuit for outputting the restored NRZ signal; wherein the duobinary-to-NRZ converter is characterized by comprising an XOR gate into which the differential signal of the amplified duobinary signal is input and a comparator into which the output of the XOR gate and the reference voltage signal are input.

[0013] In order to achieve the above object, a duobinary signal receiving method in a duobinary signal receiving device according to one embodiment of the present invention comprises: a step of amplifying a duobinary signal by a VGA; a step of restoring an NRZ signal by a duobinary-to-NRZ converter based on a differential signal of the amplified duobinary signal and a predetermined reference voltage signal; a step of outputting the restored NRZ signal by a DRV circuit; wherein the duobinary-to-NRZ converter is characterized in that it comprises an XOR gate into which a differential signal of the amplified duobinary signal is input, and a comparator into which an output of the XOR gate and the reference voltage signal are input.

[0014] According to one aspect of the present invention described above, by providing a duobinary signal reception device and method utilizing a decoder, the decoder of the duobinary reception device proposed in the present invention has an expanded reference voltage margin compared to existing structures. Furthermore, this increased reference voltage margin makes the comparator constituting the decoder less sensitive to noise or external interference, thereby enabling better signal discrimination, and this improvement can enhance the stability and reliability of a data transmission system.

[0015] FIG. 1 is a diagram showing the structure of a duobinary signal receiving device according to an embodiment of the present invention;

[0016] Figure 2 is a timing diagram illustrating the operation of the VGA of Figure 1 to amplify a duobinary signal.

[0017] Fig. 3 is a drawing showing the internal structure of the duobinary-NRZ converter of Fig. 1.

[0018] FIG. 4 is a timing diagram illustrating an operation of the duobinary-NRZ converter of FIG. 3 to restore the differential signal of a duobinary signal to an NRZ signal.

[0019] And, FIG. 5 is a flowchart showing the duobinary signal receiving operation of the duobinary signal receiving device according to an embodiment of the present invention.

[0020] The following detailed description of the present invention refers to the accompanying drawings, which illustrate specific embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. It should be understood that the various embodiments of the present invention, while different from each other, are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention. Furthermore, it should be understood that the positions or arrangements of individual components within each disclosed embodiment may be modified without departing from the spirit and scope of the present invention. Accordingly, the following detailed description is not intended to be limiting, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly described. Like reference numerals in the drawings designate the same or similar functionality throughout the several aspects.

[0021] The components according to the present invention are defined by functional distinctions rather than physical distinctions, and can be defined by the functions each component performs. Each component may be implemented as hardware or program code and processing units that perform each function, and the functions of two or more components may be implemented by including them in a single component. Therefore, the names given to the components in the following embodiments are not intended to physically distinguish each component, but rather to suggest the representative functions performed by each component, and it should be noted that the technical spirit of the present invention is not limited by the names of the components.

[0022] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

[0023] FIG. 1 is a drawing showing the structure of a duobinary signal receiving device according to an embodiment of the present invention, and FIG. 2 is a drawing showing a timing diagram for explaining the operation of the VGA of FIG. 1 to amplify a duobinary signal.

[0024] The illustrated duobinary signal receiving device (100) includes a variable gain amplifier (VGA) (110), a duobinary-to-NRZ converter (120), a digital regulator voltage (DRV) (130) circuit, and a clock circuit (140).

[0025] The VGA (110) amplifies a duobinary signal. That is, the VGA (110) amplifies a duobinary signal having a small swing width in the vertical direction as shown in Fig. 2. Amplifying the duobinary signal to have a large swing width in this way means increasing the variation range of the duobinary signal, and the VGA (110) can minimize noise or distortion of the duobinary signal and maintain the accuracy of the signal through this operation.

[0026] The duobinary-NRZ converter (120) restores an NRZ (Non Return to Zero) signal based on the differential signal of the duobinary signal amplified through the VGA (110) and a predetermined reference voltage signal. Here, the differential signal means two signals with opposite phases.

[0027] The NRZ signal restored through the duobinary-NRZ converter (120) is output through the DRV circuit (130). Here, the DRV (130) circuit is an output driver used to stably output the restored NRZ signal outside the chip.

[0028] The clock circuit (140) is a circuit that supplies a 4-phase (0 degrees, 90 degrees, 180 degrees, 270 degrees) quarter-rate clock to the duobinary-NRZ converter (120), and is composed of a QCC (Quadrature Clock Corrector) (141), a CML2CMOS (Current-Mode-Logic to Complementary Metal-Oxide-Semiconductor) (142), and an IQ divider (143).

[0029] Looking at the detailed operation of the clock circuit (140), when a 10.5 GHz differential clock is received from an external source, it is divided into a 4-phase quarter-rate clock through an IQ divider (143), and the quarter-rate clock is converted into a digital clock signal through a CML2CMOS (142). The quarter-rate clock converted into a digital clock signal in this way is corrected through a QCC (141) so that each phase has an exact 90 degree difference from each other, and finally, the corrected 5.25 GHz quarter-rate clock is supplied to the duobinary-NRZ converter (120).

[0030] Meanwhile, the process of restoring a duobinary signal to an NRZ signal in a duobinary-NRZ converter (120) is called decoding, and the decoding method is as shown in Table 1 below: if the duobinary signal y[n] is 0 (low) or 2 (high), the NRZ signal x[n] is converted to 0, and if the duobinary signal y[n] is 1 (middle), the NRZ signal x[n] is converted to 1.

[0031] [Table 1]

[0032]

[0033] Hereinafter, the duobinary-NRZ converter (120) will be described in more detail with reference to FIGS. 3 and 4.

[0034] FIG. 3 is a drawing showing the internal structure of the duobinary-NRZ converter of FIG. 1, and FIG. 4 is a drawing showing a timing diagram for explaining the operation of the duobinary-NRZ converter of FIG. 3 to restore the differential signal of a duobinary signal to an NRZ signal.

[0035] The illustrated duobinary-NRZ converter (120) is composed of an exclusive OR (XOR) gate (121) into which a differential signal of a duobinary signal is input, and a comparator (122) into which the output of the XOR gate (121) and a reference voltage signal are input, and the comparator (122) is connected to an inverter (123) that converts the output signal into an opposite signal.

[0036] When the differential signal of the amplified duobinary signal from the VGA (110) is input to the XOR gate (121), it performs an XOR operation on the differential signal of the amplified duobinary signal and outputs the XOR operation result. At this time, inductive peaking is applied to the XOR gate (121) that receives 21 Gbits / sec of data. Inductive peaking refers to correcting the frequency characteristic using an inductor, and can improve the frequency response of the circuit to a high-frequency signal. In addition, since the differential signal of the duobinary signal is input to the XOR gate (121), it has a characteristic of being strong against noise.

[0037] The operation of the above XOR gate (121) will be described in more detail through the timing diagram of Fig. 4. For example, when the duobinary signal is '1', the differential signal ( ) is '1', so the output of the XOR gate (121) is '0'. Also, if the duobinary signal is '0', the differential signal ( ) is '2', so the output of the XOR gate (121) becomes '1'. Also, if the duobinary signal is '2', the differential signal ( ) is '0', so the output of the XOR gate (121) becomes '1'.

[0038] The comparator (122) outputs the XOR operation result, which is the output of the XOR gate (121), and a predetermined reference voltage signal (V TH ) is input, the XOR operation result and the reference voltage signal are compared to output the comparison result, and at this time, the output of the comparator (122) is converted into an opposite signal through the inverter (123) and output.

[0039] That is, the XOR operation result of the XOR gate (121), which is an analog signal, is converted into a digital signal by passing through the comparator (122) together with the reference voltage signal. At this time, the output of the comparator (122) is the opposite of the output result according to Table 1 described above, that is, the NRZ signal, so it must be converted into the opposite signal using an inverter (123).

[0040] As described through FIGS. 3 and 4, the duobinary-NRZ converter proposed in the present invention uses only one comparator, so it requires only one reference voltage signal, and has the advantage of having a relaxed reference voltage margin compared to the existing duobinary-NRZ converter structure.

[0041] FIG. 5 is a flowchart showing a duobinary signal receiving operation of a duobinary signal receiving device according to an embodiment of the present invention.

[0042] The VGA of the duobinary signal receiving device amplifies the duobinary signal (S401), and the duobinary-NRZ converter restores the NRZ signal based on the differential signal of the duobinary signal amplified in S401 and a predetermined reference voltage signal (S403).

[0043] Afterwards, the DRV circuit outputs the restored NRZ signal from S403 (S405).

[0044] The duobinary signal receiving method of the present invention as described above may be implemented in the form of program commands that can be executed by various computer components and recorded on a computer-readable recording medium. The computer-readable recording medium may include program commands, data files, data structures, etc., either singly or in combination.

[0045] The program commands recorded on the above computer-readable recording medium may be specially designed and configured for the present invention or may be known and available to those skilled in the art of computer software.

[0046] Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical recording media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, and flash memory.

[0047] Examples of program instructions include not only machine language codes, such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like. The hardware device may be configured to operate as one or more software modules to perform processing according to the present invention, and vice versa.

[0048] Although various embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and various modifications can be made by a person having ordinary skill in the art to which the present invention pertains without departing from the gist of the present invention as claimed in the claims, and such modifications should not be understood individually from the technical idea or prospect of the present invention.

[0049] [Explanation of symbols]

[0050] 100: Duobinary signal receiving device

[0051] 110: VGA

[0052] 120: Duobinary-NRZ converter

[0053] 121: XOR gate

[0054] 122: Comparator

[0055] 123: Reversal

[0056] 130: DRV circuit

[0057] 140: Clock circuit

[0058] 141: QCC

[0059] 142: CML2CMOS

[0060] 143: IQ Divider

Claims

1. Variable Gain Amplifier (VGA) that amplifies the duobinary signal; A duobinary-NRZ converter that restores an NRZ (Non Return to Zero) signal based on the differential signal of the amplified duobinary signal and a predetermined reference voltage signal; and It includes a DRV (Digital Regulator Voltage) circuit that outputs the restored NRZ signal; A duobinary signal receiving device characterized in that the above duobinary-NRZ converter comprises an exclusive OR (XOR) gate into which a differential signal of the amplified duobinary signal is input, and a comparator into which the output of the XOR gate and the reference voltage signal are input.

2. In paragraph 1, The above XOR gate is a duobinary signal receiving device that performs an XOR operation on the differential signal of the amplified duobinary signal and outputs the XOR operation result.

3. In paragraph 2, The above comparator is a duobinary signal receiving device that compares the XOR operation result with the reference voltage signal and outputs the comparison result.

4. In paragraph 3, A duobinary signal receiving device characterized in that the output of the above comparator is converted into an opposite signal and output through an inverter connected to the above comparator.

5. In paragraph 1, It further includes a clock circuit, The above clock circuit is a duobinary signal receiving device that converts a differential clock received from an external source into a 4-phase quarter-rate clock and supplies it to a decoder.

6. A method for receiving a duobinary signal in a duobinary signal receiving device, A step in which a variable gain amplifier (VGA) amplifies a duobinary signal; A step of a duobinary-NRZ converter restoring an NRZ (Non Return to Zero) signal based on a differential signal of the amplified duobinary signal and a predetermined reference voltage signal; and A step of the DRV (Digital Regulator Voltage) circuit outputting the restored NRZ signal; A duobinary signal receiving method, characterized in that the above duobinary-NRZ converter comprises an exclusive OR (XOR) gate into which a differential signal of the amplified duobinary signal is input, and a comparator into which the output of the XOR gate and the reference voltage signal are input.

7. In paragraph 6, A duobinary signal receiving method in which the above XOR gate performs an XOR operation on the differential signal of the amplified duobinary signal and outputs the XOR operation result.

8. In paragraph 7, A duobinary signal receiving method in which the above comparator compares the XOR operation result with the reference voltage signal and outputs the comparison result.

9. In paragraph 8, A duobinary signal receiving method characterized in that the output of the above comparator is converted into an opposite signal and output through an inverter connected to the above comparator.

10. In paragraph 6, The above duobinary signal receiving device, It further includes a clock circuit, The above clock circuit is a duobinary signal receiving method that converts a differential clock received from an external source into a 4-phase quarter-rate clock and supplies it to a decoder.

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