A method of patterning materials

Abstract

The present invention provides a method for producing a patterned film disposed on a support. The method comprises the steps of providing a layered structure comprising a sacrificial protection layer disposed on the film, and a photoresist layer disposed on the sacrificial protection layer. The sacrificial protection layer selected to be free (or substantially free) of residues upon removal without damaging film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment. The photoresist layer is then patterned to produce masked and un-masked areas of the layered structure, and in the unmasked areas the sacrificial protection layer and the film are removed to reveal the support, and in the masked areas the sacrificial protection layer is exposed to the solvent such that the sacrificial protection layer is released from the underlying film, thereby resulting in the patterned film disposed on the support. Also disclosed is the use of a layered structure for producing a patterned film disposed on a support, and a method for making the layered structure. The present invention enables the suppression or elimination of fabrication-induced photoresist (PR) residues on the contacts and / or at the interfaces of material layers, which finds particular utility in the fabrication of two-dimensional (2D) electronic devices such as field-effect transistors (2D-FETs).

Description

A METHOD OF PATTERNING MATERIALSRELATED APPLICATION

[0001] The present application claims priority to Australian Provisional Patent Application No. 2024901896, filed 21 June 2024, the content of which is incorporated herein by reference in its entirety.FIELD OF THE INVENTION

[0002] The present invention relates to the field of micro / nano-manufacturing, and in particular to microelectronic manufacturing processes. In particular, the present invention enables the suppression or elimination of fabrication-induced photoresist residues on the contact and / or at the interfaces of material layers, which finds particular utility in the fabrication of two- dimensional (2D) electronic devices such as 2D field-effect transistors (2D-FETs). However, it will be appreciated that the invention is not limited to this particular field of use.BACKGROUND OF THE INVENTION

[0003] The following discussion of the prior art is provided to place the invention in an appropriate technical context and enable the advantages of it to be more fully understood. It should be appreciated, however, that any discussion of the prior art throughout the specification should not be considered as an express or implied admission that such prior art is widely known or forms part of the common general knowledge in the field.

[0004] Two-dimensional layered materials, such as graphene or two-dimensional transition metal dichalcogenides (TMDs), have recently captured enormous attention in the field of nanoelectronics, optoelectronics and spintronics since the discovery that graphene or monolayer semiconducting TMDs have preferred physical and electrical properties, such that the two- dimensional (2D) layered materials have good developmental and applied potential. However, contaminates, especially photoresist residues, are easily adsorbed onto the surface of the 2D layered material during device fabrication processes. Accordingly, after the photoresist on the 2D layered material is patterned, the photoresist residues may still remain on the exposed 2D layered material. Specifically, parts of the photoresist can be damaged during the patterning process, rendering them insoluble in the organic solvent. These residues can be detrimental to the overall performance of fabricated devices. For example, during the following step of depositing a metal layer or a dielectric layer on the exposed 2D layered semiconductor to form a contact for connecting to an external circuit or a gate dielectric to electrically insulate the gate from thechannel, the photoresist residues will exist between the patterned 2D layered semiconductor and the metal electrode layer or the dielectric layer.

[0005] However, the photoresist residues or the other contaminates existing at the interface between the metal electrode layer and the 2D layered semiconductor will seriously affect the quality of the electrical contact between the metal layer and the 2D layered semiconductor or the or gate control between the dielectric layer and the 2D layered semiconductor. That is, it is harder for the electrons to tunnel from the 2D layered semiconductor to the metal electrode layer or for the electrons to be controlled by the gate voltage due to the photoresist residues or contaminates. Furthermore, the resulting poor electrical contact may also result in higher power consumption of the electronic device.

[0006] In particular, residues at the channel / dielectric interfaces and dielectric / gate electrode interfaces can seriously affect the capability of gate modulation, resulting in quenched device performance, such as reduced ON / OFF ratio and deteriorated subthreshold swing.

[0007] Since the 2D layered material has an ultrathin thickness of a monoatomic layer, or a few atomic layers, the 2D layered material is more sensitive to the surface contaminates, and a higher surface cleanliness of the 2D layered material is required compared to three-dimensional materials. Additionally, the surface cleanliness of the 2D layered material has become a critical factor affecting the overall electrical performance of the 2D electronic device.

[0008] Previously, these photoresist-induced residues (“PR residues”) have been subject to a sequence of cleaning procedures, such as ultrasonic treatment, treatment with acid, or plasma. However, removing such PR residues from 2D materials is extremely difficult. Due to their atomically thin structure, high susceptibility to oxidation, and relatively weak adhesion to substrates, 2D materials are extremely sensitive to aggressive cleaning processes. One current solution to tackle these challenges employs the use of soft plasma or ultraviolet (UV) / ozone to clean such residues. However, it has been observed that these methods induce damage to the atomically thick materials. Another method that has been investigated is contact mode atomic force microscopy (AFM). However, this is inapplicable for mass production. A further option is to utilize thermal annealing in forming gas or high vacuum, however this method cannot effectively remove the residues while protecting the 2D materials from degradation. Some researches have suggested the use of polydimethylglutarimide-based resists for reducing such residues, but use of these resists requires additional N-methyl-pyrrolidinone cleaning, which is too aggressive for 2D materials and can result in “peeling off”.

[0009] It is an object of the present invention to overcome or ameliorate one or more the disadvantages of the prior art, or at least to provide a useful alternative.

[0010] It is an object of at least one preferred embodiment of the present invention to provide an efficient method to suppress or even eliminate fabrication-induced PR residues in the production of 2D electronics. In particular, it is an object of at least one preferred embodiment of the present invention to provide a method which avoids fabrication-induced PR residues on the contact, channel and dielectric areas to produce an “ultraclean” surface / interface of 2D electronic devices.

[0011] It is an object of at least one preferred embodiment of the present invention to provide efficient and scalable methods which suppress or eliminate unwanted PR residues on the 2D layered material used to make 2D-FETs. It is an object of another preferred embodiment of the present invention to provide methods that reduce or eliminate PR residues, thereby reducing device-to-device variation to thereby enhance the performance of 2D-FETs and equivalent or similar devices. It is an object of yet a further preferred embodiment of the present invention to provide methods that reduce or eliminate PR residues that are suitable for mass production, and are compatible with current main-steam mass production facilitates, and whereby no additional facilities and / or new materials are required compared to existing facilities / materials.SUMMARY OF THE INVENTION

[0012] The semiconductor industry has experienced unprecedented development in recent times, while gaining importance in nearly all aspects of life. However, the conventional silicon industry is nearly approaching a ceiling because of its limited potential for power and dimensional miniaturization. 2D semiconductors have notable advantages over conventional bulk semiconductors. Most notably, their greater resistance to short-channel effects makes them particularly promising for the development of highly performing transistors, which are crucial components of all electronic devices. Simultaneously, 2D semiconductors and other 2D materials are thermodynamically stable as single atomic layers, and have a thickness of about half a nanometer. Ideally, the surfaces of these 2D layers are inert and free of dangling bonds and other defects, which allow for the formation of nearly defect-free interfaces in 2D electronic devices.

[0013] The present inventors have now developed surprisingly efficient and scalable methods which eliminate unwanted PR residues on the 2D layered material used to make 2D-FETs and equivalent or similar devices, which would ordinarily be present during main-stream manufacturing / fabrication processes. The present invention enables improved interfaces of metal-semiconductor, semiconductor-insulator, and insulator-metal contacts in 2D-FETs, thereby significantly enhancing their performance. The present invention reduces or eliminates residues, and residue-imposed effects, such as doping, device-to-device variation and quenched gate modulation, all of which combine to enhance the performance of 2D FETs and equivalent or similar devices. Additionally, the invention disclosed herein is suitable for mass production, andis compatible with current main-steam mass production facilities. Furthermore, no additional facilities or new materials are required in the present invention. Accordingly, the novel methods disclosed herein are suitable for the large-scale production of 2D electronic devices.

[0014] It is envisaged that the present invention can be utilized for individual components within FETs or electronic devices requiring photoresist materials for lithography processing. Essentially, the invention could be deployed for, for example: (a) enhancing the surface / interface condition between the source / drain electrodes and the channel, (b) improving the surface / interface conditions between the gate dielectric and the channel and / or (c) improving the surface / interface conditions between the gate electrode and the gate dielectric.

[0015] In particular, the present invention provides a sacrificial protection layer which is “sandwiched” or disposed between the (underlying) film waiting for pattern and the (overlying) photoresist layer. The sacrificial protection layer is selected or configured to be free (or substantially free) of residues upon removal without damaging film layer, at least partially soluble or swellable in a solvent (such as water), and preferably clear to photolithographic alignment. In one embodiment, the sacrificial protection layer may be a single layer having these properties, or alternatively, the sacrificial protection layer may be a plurality of layers that each have properties which, when combined, mean that the sacrificial protection layer overall is free (or substantially free) of residues upon removal without damaging film layer, at least partially soluble or swellable in a solvent (such as DI water), and preferably clear to photolithographic alignment. The surprising utility of the sacrificial protection layer will become apparent in light of the current / conventional method of 2D FET fabrication. In this regard, the left-hand side of Figure 1 shows the conventional method in which in Step 1 a film (2D layered material) is disposed on a support and coated with a photoresist (“PR coating”). In Step 2, a standard lithography process is undertaken to pattern the PR coating. In Step 3, a plasma etching or wet etching process is undertaken using the patterned PR coating as a masking film, to thereby provide masked and un-masked areas. It will be appreciated that the PR coating is in direct contact with the film. In Step 4, a solvent rinse process is undertaken to remove the residual PR coating, which results in some unwanted PR residue remaining on the underlying film (i.e., “Step 5”), which causes deleterious effects as discussed above.

[0016] T urning now to the right-hand side of Figure 1 , the use of the novel sacrificial protection layer as described herein is exemplified. Under the heading “additional steps”, a coating of a polymer (buffer) layer is provided on the film, followed by a coating of an inorganic (carrier) layer on the polymer layer. An alternative to this bi-layer approach is to use a single layer, which is discussed further below. Steps 1 and 2 are then undertaken in a similar way to the conventional method, to produce a layered structure comprising the PR coating disposed on the sacrificial protection layer, which is disposed on the film. Steps 3 and 4 are then undertaken in a similar wayto the conventional method, to thereby provide a patterned film on the support with no unwanted PR residue remaining on the film. This is because the PR coating is never in contact with the film, which is only made possible due to the use of the sacrificial protection layer that is selected to be free (or substantially free) of residues upon removal without damaging film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment.

[0017] In the conventional method, the lithography process and plasma bombardment cause the PR coating to become very rigid, and as a consequence it resists dissolving in the solvents, causing unwanted PR residues to be left behind on the film. In the method of the invention, the use of a carrier layer (which is preferably clear to photolithographic alignment) protects the underlying polymeric buffer layer from deposited with PR residues, meaning that it captures the PR residues and thus prevents the PR residues left on the film layer. Preferably the carrier layer is not dissolvable or swellable in the solvent, or substantially resists dissolving in the solvent, or swelling in the solvent. Exposure to the solvent causes the buffer layer to dissolve and all the layers above the film to lift off (or peel away from) the film at the same time. Because only the buffer layer, which is free (or substantially free) of residues upon removal without damaging film layer, contacts the film layer, the film is free (or substantially free) of residues after all the layers above are released from the film.

[0018] In another embodiment of the invention where the sacrificial protection layer is single layer and is a soluble inorganic material (preferably water soluble, or etchant which does not affect the underlying film), the inorganic material is at least partially soluble or swellable in water or the etchant.

[0019] In summary, the inventors describe herein a novel “lift-off” method to avoid the presence of PR residues on the film that would ordinarily be present with the conventional method. The provision of the sacrificial protection layer prevents the source of the PR residues from coming into contact with the patterned film during device fabrication, and mitigates the aforementioned technical challenges that involve damage to the film or ineffective residue cleaning processing.

[0020] According to a first aspect, the present invention provides a method for producing a patterned film disposed on a support, the method comprising the steps of: providing a layered structure comprising a sacrificial protection layer disposed on the film, and a photoresist layer disposed on the sacrificial protection layer, the sacrificial protection layer selected to be free (or substantially free) of residues upon removal without damaging the film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment;patterning the photoresist layer to produce masked and un-masked areas of the layered structure; in the unmasked areas, removing the sacrificial protection layer and the film to reveal the support; and in the masked areas, exposing the sacrificial protection layer to the solvent such that the sacrificial protection layer releases from the underlying film, thereby resulting in the patterned film disposed on the support.

[0021] According to a second aspect, the present invention provides a layered structure for producing a patterned film disposed on a support, the layered structure comprising a sacrificial protection layer disposed on the film, and a photoresist layer disposed on the sacrificial protection layer, the sacrificial protection layer selected to be free (or substantially free) of residues upon removal without damaging the film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment;

[0022] According to a third aspect, the present invention provides use of a layered structure for producing a patterned film disposed on a support, the layered structure comprising a sacrificial protection layer disposed on the film, and a photoresist layer disposed on the sacrificial protection layer, the sacrificial protection layer selected to be free (or substantially free) of residues upon removal without damaging the film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment;

[0023] According to a fourth aspect, the present invention provides a method for making a layered structure for producing a patterned film disposed on a support, the method comprising the steps of: providing the film disposed or deposited on the support, providing a sacrificial protection layer disposed or deposited on the film, wherein the sacrificial protection layer is selected to be free (or substantially free) of residues upon removal without damaging the film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment; and providing a photoresist layer disposed on the sacrificial protection layer, thereby providing the layered structure.

[0024] In one specific form of the invention, there is provided a method of eliminating or avoiding photoresist residues on a film layer. A sacrificial protection layer separates the photoresist layer and the film layer.

[0025] In some embodiments, the sacrificial protection layer is a single layer. In this embodiment, the single layer may be a water-soluble inorganic material.

[0026] In some embodiments, the sacrificial protection layer may consist of at least two heterostructure layers, comprising a polymer (buffer) layer and an inorganic (carrier) layer. The polymer (buffer) layer is coated on the film layer and the inorganic (carrier) layer is coated or deposited on the polymer (buffer) layer. The polymer (buffer) layer is preferably made of polymers that free (or substantially free) of residues upon removal without damaging the film layer, such as polymethyl methacrylate (PMMA). The inorganic (carrier) layer may be oxide, carbide, nitride, metal or alloy. Preferably the inorganic (carrier) layer is SiC>2. The photoresist layer is coated on the inorganic (carrier) layer. This “stack” of layers is then subject to the steps of: lithography to pattern the PR coating, an etching process to un-mask the stack of layers to reveal the support in those un-masked areas, and then exposure of the masked areas to solvent to release the sacrificial protection layer from the film to reveal the underlying film layer.

[0027] The support layer

[0028] In some embodiments, the support is formed from a relatively rigid material, which may be selected from the group consisting of semiconductors, metals, and insulators, such as oxides, fluorides, nitrides, arsenides, carbides, diamond, glass, and their combination. However, it will be appreciated by the skilled addressee that other types of rigid support materials would be suitable.

[0029] Examples of rigid supports include:• Semiconductors: such as Si, Ge, InP, ZnO, CdTe, PbTe, AIN, InGaP, Copper Indium Gallium Selenide (CIGS)• Metals (including semi-metals): such as Au, Ag, Cu, Pt, Ti, Bi, graphite• Oxides: such as SiO2, AI2O3, SrTiOs, BaTiOs, BiFeOs, TiO2, SrRuOs, LaAIOs, Ga2Os• Fluorides: such as CaF2, MgF2• Nitrides: such as SisN^ GaN• Arsenides: such as GaAs• Carbides: such as SiCDiamond: such as c-diamondGlass: such as borosilicate glass and soda-lime glass

[0030] In some embodiments, the support is a more flexible material, such as a polymer. Preferred polymers may be chosen from: polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethylene (PE), polycarbonate (PC), polypropylene (PP), polyether ether ketone (PEEK), polyarylate (PAR), polyethylene terephthalate glycol-modified (PETG), polydimethylsiloxane (PDMS), and their combination. However, it will be appreciated by the skilled addressee that other types of polymer materials would be suitable.

[0031] A further example of a flexible support is a metal foil such as Cu or Al. A further example of a flexible support is ultrathin glass. A further example of a flexible support is mica.

[0032] The thickness of the support is not particularly limited. For example, the thickness of the support may be about 1 , 50, 100, 150, 200, 250, 300, 350, 400, 450, 500, 550, 600, 650, 700, 750, 800, 850, 900, 950, or 1000 nm. The thickness of the support may be about 1 , 50, 100, 150, 200, 250, 300, 350, 400, 450, 500, 550, 600, 650, 700, 750, 800, 850, 900, 950, or 1000 micrometers. The thickness of the support may be about 1 , 2, 3, 4, 5, 6, 7, 8, 9, 10 or more mm.

[0033] The support may include silicon, germanium, silicon germanium or other suitable semiconductor material, such as diamond, silicon carbide or gallium arsenic. The support may further include additional features and / or material layers, such as various isolation features formed in the substrate. The substrate may include various p-type doped regions and / or n-type doped regions configured and coupled to form various devices and functional features. All doping features may be achieved using a suitable process, such as ion implantation in various steps and techniques. The substrate may include other features, such as a shallow trench isolation (STI).

[0034] The support may further include various material layers, such as metal-gate-stack material layers. A high-K dielectric material layer may be formed on the substrate. The high-K dielectric material layer is formed by a suitable process such as an atomic layer deposition (ALD). Other methods to form the high-K dielectric material layer include metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), UV-Ozone Oxidation and molecular beam epitaxy (MBE). In one embodiment, the high-K dielectric material includes AhOx, HfOx. Alternatively, the high-K dielectric material layer includes metal nitrides, metal silicates, complex oxides, or other metal oxides.

[0035] The film layer

[0036] In preferred embodiments of the present invention the film comprises a semiconductor material, and in other embodiments the film is not a semiconductor material. Preferred materials of the film are selected from the group consisting of: graphene, transition metal dichalcogenides[e.g., molybdenum disulfide (M0S2), tungsten diselenide (WSe2), tungsten disulfide (WS2)], boron nitride, black phosphorus, and combinations thereof. In one embodiment, the film comprises a semiconductor material, which can be used as a channel material.

[0037] Examples of channel materials include: graphene, transition metal dichalcogenides (TMDs) - e.g., molybdenum disulfide (M0S2), tungsten diselenide (WSe2), tungsten disulfide (WS2), etc.; transition metal carbides and nitrides (MXenes), black phosphorus (phosphorene), boron nitride, arsenene, antimonene, silicene, germanene, phosphorene, borophene, stanene, tellurene, indium selenide (InSe), gallium selenide (GaSe), tin selenide (SnSe), indium sulfide (InS), gallium sulfide (GaS), tin sulfide (SnS), indium telluride (InTe), gallium telluride (GaTe), tin telluride (SnTe), oxides - e.g.,Bi2O2Se, Ga2Os, etc.; and ultra-thin materials like diamond, SiC, GaN, GaAs, and more.

[0038] In some preferred embodiments, the film comprises 2D layered materials, which can be graphene or metal-based chalcogenide film or others. The metal-based chalcogenide film can be a transition metal dichalcogenide (TMD) film. The term "chalcogenides" include dichalcogenides, trichalcogenides, and does not preclude chalcogenides having more than one chalcogen atom. Moreover, the dichalcogenide has a composition generally represented by a formula, MX2, where M is a metal, and X is a chalcogen such as sulfur, selenium, tellurium, and the combination thereof, and the chalcogens are not limited to the examples provided herein. For example, the 2D layered semiconductor can be transition metal dichalcogenides (TMDs), I ll-VI compound semiconductors, or ll-VI compound semiconductors. The transition metal dichalcogenides can be M0S2, MoSe2, MoTe2, HfS2, HfSe2, HfTe2, WS2, WSe2, WTe2, NbS2, NbSe2, NbTe2, ReS2, ReSe2, ReTe2, and so on. The HI-VI compound semiconductors may be GaS, GaSe, GaTe, or ln2Se3. The IV-VI compound semiconductors may be GeSe.

[0039] In some preferred embodiments of the present invention, the film is a 2D layered semiconductor, which is preferably a transition metal dichalcogenide film, such as M0S2 and WSe2.

[0040] In one embodiment, the film is homogenous. However, in other embodiments the film comprises two or more sublayers (e.g. 2, 3, 4, 5, or more), that may be a heterostructure, meaning it can consist of a stack of two or more different material layers. One example of a heterostructure is LaAIOs / SrTiOs, which can generate an electron transport layer at their interfaces, making it promising for use in electronics. Another example is MoS2 / WSe2, which forms a p-n junction. A further example is h-BN / WSe2 / h-BN, which forms a quantum well. Some examples of heterostructures can be seen in Figure 6.

[0041] It will be appreciated that the film, which is eventually patterned, is disposed on the support.

[0042] Preferably the thickness of the film is from about 0.3 nm to about 10 .m, for example from about 0.5 nm to about 10 .m, for example from about 0.3 nm to about 5 .m, for example from about 0.3 nm to about 3 .m, for example from about 0.3 nm to about 1 .m, for example from about 0.3 nm to about 500 nm, for example from about 0.3 nm to about 100 nm, for example from about 0.3 nm to about 50 nm. The film thickness may be atomically thin, for example 0.35 to 0.75 nanometres (3.5 x 10"10m to 7.5 x 10"10m), or may be 1 , 2, 3, 4, 5, 6, 7, 8, 9, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 2000, 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000 nm, or more thick.

[0043] The sacrificial protection layer

[0044] As described above, the present invention provides a layered structure comprising a sacrificial protection layer disposed on the film (which is disposed on the support), and a photoresist layer disposed on the sacrificial protection layer. The sacrificial protection layer is selected or configured to be free (or substantially free) of residues upon removal without damaging film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment. In one embodiment, the sacrificial protection layer may be a single layer having these properties. In an alternative embodiment, the sacrificial protection layer may be a plurality of layers that each have properties which, when combined, mean that the sacrificial protection layer overall is to be free (or substantially free) of residues upon removal without damaging film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment.

[0045] In some preferred embodiments, the sacrificial protection layer is a single layer. In this embodiment, the single layer may be a water-soluble inorganic material. Some examples of preferred inorganic materials are: SrsAhOe, S^AhO?, CasAhOe, MgsAhOe, BasAhOe, NaAIC>2, KAIO2, salts [NaCI, K, Cl, CaCI2, MgCI2, NH4CI, NaNO3, KNO3, Ca(NO3)2, Na2SO4, K2SO4, Na2SO4, K2SC , (NH4)2SO4], carbonates and bicarbonates [Na2CO3, K2CO3, (NH4)2CO3, NaHCO3, KHCO3], phosphates [Na3PO4, K2PO4, (NH4)3PO4, Acetates [CH3COONa, CH3COOK], Other suitable inorganic materials will be known to the skilled addressee. Preferred inorganic materials are those which are water-soluble, although in other embodiments other inorganic materials that have solubility in solvents other than water may also be suitable. For example, other suitable solvents may be alcohol / water mixtures, or acids. In the case where the sacrificial protection layer is SrsAhOe, which is a water-soluble inorganic material, since it is water-soluble, the removal of SrsAhOe does not need additional etchant and thus would not damage the underlying film. Thus,a buffer layer is not necessarily needed to lift the inorganic layer off the film, as SrsAhOe can be easily removed.

[0046] As mentioned above, in alternative embodiments the sacrificial protection layer may be a plurality of layers which, when combined, provide mean that the sacrificial protection layer overall is free (or substantially free) of residues upon removal without damaging film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment. In this embodiment, the sacrificial protection layer comprises a buffer layer which is in contact with the film, and a carrier layer which is in contact with the buffer layer and the (overlying) photoresist layer (i.e., is disposed therebetween). In this embodiment, the buffer layer is the sacrificial protection layer overall is free (or substantially free) of residues upon removal without damaging film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment. The carrier layer is preferably clear to photolithographic alignment.

[0047] Preferably the buffer layer is formed from at least one polymeric material. Preferred polymeric materials will be known to the skilled addressee, but for example may be selected from: PMMA, cellulose acetate (CA), polystyrene (PS), polyethylene (PE), polypropylene (PP), polyvinyl chloride (PVC), polycarbonate (PC), acrylonitrile butadiene styrene (ABS), and polytetrafluoroethylene (PTFE). The preferred polymer material is selected such that it is at least partially soluble or swellable in a predetermined solvent such that it can relatively easily lift off carrier layer and without leaving residue on the film layer and damage the film layer.

[0048] Preferably the carrier layer is formed from at least one inorganic material, which may be selected from the group consisting of an oxide, a carbide, a nitride, a metal or an alloy. Examples may be SiC>2, AhOx, ITO, SrTiOs, TiO2, SiC, Sisl^ , GaN, Ag, Al, Au, Co, Cr, Cu, Fe, Ge, Ir, Nb, Ni, Pd, Pt, Si, Sn, Ti, NbTi, AuGe, PdAu, and NiFe. Other suitable oxides, carbides, nitrides, metals or alloys will be known to the skilled addressee.

[0049] It will be appreciated that the carrier and / or the buffer layer may each be formed from more than one layer, or may be composite layers.

[0050] The carrier layer or the buffer layer or the sacrificial protection layer (carrier layer + buffer layer) may have a thickness which is atomically thin, for example 0.35 to 0.75 nanometres (0.35 x 10’10m to 7.5 x 10’10m), or may be 1 , 2, 3, 4, 5, 6, 7, 8, 9, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 2000, 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000 nm, or more thick.

[0051] Solvents for the sacrificial protection layer

[0052] As discussed above, where the sacrificial protection layer is a single layer, the composition of that single layer is formulated or selected to be at least partially soluble or swellable in a solvent. In this case, the solvent may be water, or other fluids that would dissolve or swell the single layer and yet not damage the underlying film, or leave residue on the underlying film.

[0053] As discussed above, where the sacrificial protection layer is a plurality of layers (e.g., a buffer layer and a carrier layer), the buffer layer is formulated or selected to be at least partially soluble or swellable in a solvent. Preferably the solvent is an organic solvent, or a mixture of two or more organic solvents, selected from the group consisting of: ketone solvents, alcohols and dimethylsulfoxide (DMSO). One preferred solvent is a mixture of acetone and isopropyl alcohol (I PA). It will be appreciated that the solvent, or solvent system, is chosen to be suitable for the buffer such that the polymeric buffer is soluble or swellable in that solvent, such that the buffer layer “lifts off’ the overlying film and leaves no residue on the underlying film layer, and does not damage the underlying film layer.

[0054] The photopatternable material / photoresist layer

[0055] The photoresist (PR) layer is formed from a photopatternable material which is selected from the group consisting of: a photoresist comprising the main polymer resin, a photoactive compound (PAC) or a photoresist comprising the main a polymer resin, a photoinitiator, and a cross-linking agent, or other photopatternable materials that are well known in the art may be used in the present invention.

[0056] In some embodiments the photoresist layer is produced by coating or printing a photoresist solution on the sacrificial protection layer, exposing the photoresist layer, and developing the photoresist layer, resulting in the patterned photoresist layer to thereby produce the masked and un-masked areas of the layered structure. An exemplary photolithography process may include processing steps of photoresist coating, soft baking, mask aligning, exposing, post-exposure baking, developing photoresist and hard baking. The lithography process may implement ultraviolet lithography, deep ultraviolet lithography, extreme ultraviolet lithography (EUV), and others.

[0057] It will be appreciated by a skilled person that there are at least two types of photoresists, positive and negative. Positive photoresists become more soluble when exposed to light, allowing the exposed areas to be washed away. Negative photoresists becomes less soluble when exposed to light, causing the exposed areas to remain while the unexposed areas are washed away. Commercial positive photoresists include AZ® 1500 Serie and AZ® ECI 3000Serie. Commercial negative photoresists include AZ® nLOF 2000 Serie. Other commercially available photoresists will be known to the skilled addressee.

[0058] The thickness of the photoresist layer is from about 20 nm to about 20 .m, or more thick, for example from about 20 nm to about 10 .m, for example from about 100 nm to about 3 |_im, for example from about 100 nm to about 20 .m, for example from about 500 nm to about 20 .m, for example from about 1 .m to about 10 .m.

[0059] Etching processes

[0060] Etching processes that are well known in the art may be used in the present invention.

[0061] In the unmasked areas, the sacrificial protection layer may be removed to reveal the film by an etching process, such as a process selected from the group consisting of: wet etching process and / or a dry etching process.

[0062] In the case of plasma etching, the process may be undertaken with a gas selected from the group consisting of: O2, N2, H2, CI2, He, Ar, SFe, CH4, CHF3, NF3, C2F6, CH3CI, BC , and more.

[0063] In the case of wet etching, the process may be undertaken with an etchant selected according to the material. Examples may be gold etchant (KI / I2 solution)], hydrofluoric (HF) acid solution, FeC solution and ammonium persulfate [(NH4)2S20s]. Other suitable etchants will be known to the skilled addressee.

[0064] As discussed above, removal / etching is any process that removes material. Examples include etch processes (either wet or dry), and solvent lift off, and the like. A dry etch process such as reactive ion etching (RIE) uses chemically reactive plasma to remove a material, such as a masked pattern of semiconductor material, by exposing the material to a bombardment of ions that dislodge portions of the material from the exposed surface. The details of removal / etching process will be appreciated by the skilled addressee.

[0065] Layer deposition processes

[0066] The layers described herein (e.g., the film disposed on the support, the photoresist layer disposed on the sacrificial protection layer, etc) may be disposed on an underlying layer by processes that are well known in the art.

[0067] By way of example only, the film may be disposed on the support by a thin film growth technique, or thin film transfer technique, or the combination of both.

[0068] By way of further example only, the sacrificial protection layer or the part of sacrificial protection layer may be disposed on the film by physical vapor deposition methods including electron beam evaporation, RF magnetron sputtering, DC magnetron sputtering, thermal evaporation, molecular beam epitaxy and chemical vapor deposition methods including atomic layer deposition, molecular organic chemical vapor deposition, and other methodologies including transferring a layer of freestanding inorganic carrier membrane on the buffer layer.

[0069] By way of further example only, the buffer layer may be disposed on the film by coating or printing.

[0070] By way of further example only, the carrier layer may be disposed on the buffer layer by physical vapor deposition methods including electron beam evaporation, RF magnetron sputtering, DC magnetron sputtering, thermal evaporation, molecular beam epitaxy and chemical vapor deposition methods including atomic layer deposition, molecular organic chemical vapor deposition, and other methodologies including transferring a layer of freestanding inorganic carrier membrane on the buffer layer.

[0071] By way of further example only, the photoresist may be disposed on the sacrificial protection layer by spin-coating a photoresist solution on the sacrificial protection layer. The coated sample may be gently heated to evaporate the solvent and solidify the photoresist layer (i.e. , “soft bake”). The sample may then be exposed to ultraviolet light (or EUV, DUV), depending on the photoresist type. The light alters the solubility of the exposed areas, i.e., an exposure step. Optionally, it may be possible to undertake a “hard bake” for negative photoresists, for further hardening the photoresist. The sample is immersed in a developer solution that selectively dissolves the exposed (positive) or unexposed (negative) areas of the photoresist, followed by rinse to remove residual developer and dried, i.e. a development step. Optionally it may be possible to expose the sample to a higher temperature bake to further harden the remaining photoresist and improve its adhesion and etch resistance, i.e. an optional final baking step. Finally, the patterned photoresist serves as a mask for subsequent etching (removal of exposed material) or deposition (adding new material) processes to create the desired structures.

[0072] Uses of the patterned films as disclosed herein

[0073] In one preferred embodiment, the patterned film disposed on the support is a part of a field-effect transistor (FET), such as a 2D-FET. Other embodiments will be known to the skilled addressee.

[0074] The present disclosure is not limited to applications in which the semiconductor structure includes a FET, and may be extended to other micro / nano-electronic devices having semiconductors, metals and insulators that need to be patterned as designed. For example, thesemiconductor structure may include a dynamic random access memory (DRAM) cell, a single electron transistor (SET), and / or other microelectronic devices (collectively referred to herein as micro / nano-electronic devices). Of course, aspects of the present disclosure are also applicable and / or readily adaptable to other type of transistors, such as gate-all-around transistors, and other type of micro / nano-electronic devices employed in many different applications, including optoelectronics, spintronics and others.DEFINITIONS

[0075] In describing and claiming the present invention, the following terminology will be used in accordance with the definitions set out below. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments of the invention only and is not intended to be limiting.

[0076] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one having ordinary skill in the art to which the invention pertains.

[0077] Unless the context clearly requires otherwise, throughout the description and the claims, the terms “comprise”, “'comprising”, and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to”. For example, a composition, mixture, process or method that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process or method.

[0078] The transitional phrase "consisting of’ excludes any element, step, or ingredient not specified. If in the claim, such would close the claim to the inclusion of materials other than those recited except for impurities ordinarily associated therewith. When the phrase "consisting of' appears in a clause of the body of a claim, rather than immediately following the preamble, it limits only the element set forth in that clause; other elements are not excluded from the claim as a whole.

[0079] The transitional phrase "consisting essentially of' is used to define a composition, process or method that includes materials, steps, features, components, or elements, in addition to those literally disclosed, provided that these additional materials, steps, features, components, or elements do not materially affect the basic and novel characteristic(s) of the claimed invention. The term "consisting essentially of' occupies a middle ground between "comprising" and "consisting of".

[0080] Where the applicant has defined an invention or a portion thereof with an open-ended term such as "comprising", it should be readily understood that (unless otherwise stated) the description should be interpreted to also describe such an invention using the terms "consisting essentially of" or "consisting of." In other words, with respect to the terms “comprising”, “consisting of”, and “consisting essentially of’, where one of these three terms is used herein, the presently disclosed and claimed subject matter may include the use of either of the other two terms. Thus, in some embodiments not otherwise explicitly recited, any instance of “comprising” may be replaced by “consisting of” or, alternatively, by “consisting essentially of”.

[0081] While reference may be made in this disclosure to the invention comprising a combination of a plurality of elements, it is also understood that this invention is regarded to comprise combinations which omit or exclude one or more of such elements, even if this omission or exclusion of an element or elements is not expressly stated herein, unless it is expressly stated herein that an element is essential to the applicant' s combination and cannot be omitted. It is further understood that the related prior art may include elements from which this invention may be distinguished by negative claim limitations, even without any express statement of such negative limitations herein. It is to be understood, between the positive statements of applicant's invention expressly stated herein, and the prior art and knowledge of the prior art by those of ordinary skill which is incorporated herein even if not expressly reproduced here for reasons of economy, that any and all such negative claim limitations supported by the prior art are also considered to be within the scope of this disclosure and its associated claims, even absent any express statement herein about any particular negative claim limitations.

[0082] As used herein, with reference to numbers in a range of numerals, the terms "about," "approximately" and "substantially" are understood to refer to the range of -10% to +10% of the referenced number, preferably -5% to +5% of the referenced number, more preferably -1 % to + 1 % of the referenced number, most preferably -0 .1 % to +0 .1 % of the referenced number. Moreover, with reference to numerical ranges, these terms should be construed as providing support for a claim directed to any number or subset of numbers in that range. For example, a disclosure of from 1 to 10 should be construed as supporting a range of from 1 to 8, from 3 to 7, from 1 to 9, from 3.6 to 4.6, from 3.5 to 9.9, from 8 to 10, and so forth.

[0083] The terms “preferred” and “preferably” refer to embodiments of the invention that may afford certain benefits, under certain circumstances. However, other embodiments may also be preferred, under the same or other circumstances. Furthermore, the recitation of one or more preferred embodiments does not imply that other embodiments are not useful, and is not intended to exclude other embodiments from the scope of the invention.

[0084] The complete disclosures of the patents, patent documents and publications cited herein are incorporated by reference in their entirety as if each were individually incorporated.

[0085] Unless expressly stated to the contrary, "or" refers to an inclusive or and not to an exclusive or. For example, a condition A or B is satisfied by any one of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present).

[0086] The term "and / or" used in the context of "X and / or Y" should be interpreted as "X," or "Y," or "X and Y." Similarly, "at least one of X or Y" should be interpreted as "X," or "Y," or "both X and Y."

[0087] The indefinite articles "a" and "an" preceding an element or component of the invention are intended to be non-restrictive regarding the number of instances (i.e., occurrences) of the element or component. Therefore "a" or "an" should be read to include one or at least one, and the singular word form of the element or component also includes the plural unless the number is obviously meant to be singular.

[0088] As used herein, wt.% refers to the weight of a particular component relative to total weight of the referenced composition.

[0089] It will be understood that use of the term “between” herein when referring to a range of numerical values encompasses the numerical values at each endpoint of the range. For example, a temperature of between 80 °C and 150 °C is inclusive of a temperature of 80 °C and a temperature of 150 °C.

[0090] Various features of the embodiments of the invention disclosed herein are, for brevity, described in the context of a single embodiment, but may also be provided separately or in any suitable sub-combination. All combinations of the embodiments are specifically embraced by the illustrative embodiments disclosed herein just as if each and every combination was individually and explicitly disclosed. In addition, all sub-combinations listed in the embodiments describing such variables are also specifically embraced by the present compositions and are disclosed herein just as if each and every such sub-combination was individually and explicitly disclosed herein.

[0091] In the foregoing paragraphs, where various ratios of components have been disclosed. It will be appreciated that these ratios of components can be combined in any disclosed combination. For example, the ratio of A:B (which may be between about 100:1 and 1 :100 or any range therein), may be combined with the ratio of C:D (which may be between about 50:1 and1 :50 or any range therein), and may be combined with the ratio of E:F (which may be between about 10:1 and about 1 :10 or any range therein).

[0092] The term “photopattern” refers to exposure of areas of a surface to UV (or DUV and EUV) light. A mask (either a physical mask or a digital mask) is used to partially block the UV (or DUV and EUV) light and thereby selectively expose areas of the surface to the UV (or DUV and EUV) light. Photopatternable refers to a photoresist which undergoes a chemical change on exposure to UV (or DUV and EUV) light.

[0093] Negative photoresist (N-PR) is photocurable and becomes insoluble in developer after exposure to UV (or DUV and EUV). Positive photoresist (P-PR) becomes soluble in developer after exposure to UV (or DUV and EUV).

[0094] Wet etching (Dry etching) is a process wherein a chemical or etchant (gases or plasma) is used to remove parts of material in the etching process.

[0095] A dielectric material is an electrically insulating material that can store electric energy by polarization when subjected to an electric field.

[0096] A channel material is a material for conveying electrical or electromagnetic signals.

[0097] An electrode material is a conducting material.

[0098] The sacrificial protection layer is selected or configured to be free (or substantially free) of residues upon removal without damaging the film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment. The term “free of residues” is also understood herein to mean that the number of residues may be reduced, or substantially reduced, compared to the conventional technique, and in a preferred embodiment the film is completely free from the residues. The term “clear to photolithographic alignment” is also understood herein to mean that the likelihood of failure in the process of mask alignment (either physical mask alignment or digital mask alignment) may not be increased, or substantially increased, compared to the conventional technique.

[0099] It will be understood that relative terms such as "above", "below", "top", "bottom", "above" and "below" when used herein may be used to describe various elements relative to each other. These relative terms are intended to encompass different orientations of the elements in addition to the orientation depicted in the figures.BRIEF DESCRIPTION OF THE DRAWINGS[000100] The aspects described above, as well as other apparent aspects, advantages, and objectives of the present invention are apparent from the detailed description below in combination with the drawing, in which:[000101] Figure 1 is a graphical step-by-step representation of the method of the prior art (“conventional method”) and present invention, on the left-hand side and right-hand side of the figure, respectively. It will be appreciated that the 2D “channel” (i.e. , film) is formed on a support (termed a “substrate” in the figure). The term “RLO” describes that the photoresist is being “lift off’ the film.[000102] Figure 2 shows the comparison of M0S2 channels etched by (a-c) the conventional etching method and (d-f) the present invention, (a, d) The optical portrait of pattered M0S2 channels. Scale bar: 50 pm. The green dashed boxes highlight the areas of patterned M0S2 channels with (a) and without (d) PR residue coverage, (b, e) The SEM image. The upper panel of (b) shows unwanted / undesired PR residues on the patterned M0S2 channel with a scale bar of 2 pm, while the lower panel shows a small area (2.4 pm by 1.6 pm) of PR residues on metal film layer. SEM image of (e) shows the patterned M0S2 channel and contacts without any unwanted / undesired photoresist residue. The scale bar is 2 pm. (c, f) The AFM topographies. The scale bar on images: 2 pm. The insets show the measured thickness profiles along the green lines.[000103] Figure 3 shows electrical performance comparison of top-gate M0S2 FETs fabricated by the conventional method and the present invention, (a) Transfer characteristics of M0S2 FETs. (b) The measured capacitance equivalent thickness (GET) of 35-nm AI2O3 top gate dielectric on M0S2 channels.[000104] Figures 4A and B show the spectroscopy analysis of M0S2 channels after patterned by conventional methods and the present invention. Data collected from as-grown M0S2 is employed as a reference. Both P-PR and N-PR are tested in the conventional method. Figure 4A (a): FTIR analysis of M0S2 after channel patterning. The spectra show the range where the difference is present. Figure 4A (b) and Figures 4B (a-b): Spectra of M0S2 channels defined by different methods showing residue-induced effects. Figure 4A (b): Raman spectroscopy. Figure 4B (a): PL map of peak position. Scale bars on images: 3 pm. Figure 4B (b): XPS spectra of Mo 3d (left panel) and S 2p (right panel).[000105] Figure 5 shows an example of applying the present invention. The photoresist layer: P-PR. The carrier layer: 20 nm gold. The buffer layer: 100 nm PMMA. The film is approx. ~0.7nm M0S2 measured under AFM, which suggests that it is a monolayer, consisting of one layer of molybdenum atoms sandwiched between two layers of sulfur atoms.[000106] Figure 6 shows some examples of a film comprising heterostructures.DETAILED DESCRIPTION[000107] The skilled addressee will understand that the invention comprises the embodiments and features disclosed herein as well as all combinations and / or permutations of the disclosed embodiments and features.Methods of making a layered material[000108] In one example, the support can be cut from a three-dimensional (3D) bulk crystal.[000109] In one example, the film is provided on the support by a thin film growth technique, or thin film transfer technique, or the combination of both. Examples of thin film growth techniques for providing the film on the support include chemical vapour deposition (CVD), such as cold- or hot-wall CVD, atomic layer deposition (ALD), metal organic CVD on (MOCVD), thermal CVD, plasma-enhanced CVD (PECVD), photo-enhanced CVD (photo-CVD), low-pressure CVD (LPCVD), high-pressure CVD (HPCVD), laser-assisted CVD (LCVD), atmospheric pressure CVD, and physical vapour deposition (PVD), such as pulsed laser deposition (PLD), molecular-beam epitaxy (MBE), oxide molecular-beam epitaxy (OMBE), RF or DC magnetron sputtering deposition, thermal evaporation, electron beam evaporation, arc vapour deposition, ion plating, and reactive PVD.[000110] T echniques of thin film transfer are conventional in the art. These techniques have the potential to be used in very large-scale integration (VLSI) technology at either the front or back end of line-through monolithic or heterogeneous integration. Examples of combinations of thin film growth techniques and thin film transfer techniques for providing the film layer on the support include transferring a thin film onto the support followed by growing additional materials on the transferred thin film to form the film layer, or, growing a thin film onto the support followed by transferring additional materials on the as-grown thin film to form the film layer.[000111] In one embodiment, the buffer layer can be provided by coating or printing. Examples of methods for providing the buffer layer include coating such as spin coating. Other coating techniques are also feasible, such as dip coating or thin film printing including slot die coating, roller printing, and screen printing and inject printing. These are techniques which are conventional in the art and with which the skilled person is familiar.[000112] Examples of methods for providing a carrier layer (e.g. an inorganic carrier layer) include electron beam evaporation and other PVD techniques. Electron beam evaporation is a technique which is conventional in the art and with which the skilled person is familiar.[000113] In one embodiment, the photoresist layer is provided by coating. In another embodiment, the photoresist layer is provided by printing. Examples of methods for providing the photoresist layer include spin-coating or thin-film printing including slot die coating, roller printing, and screen printing and inject printing. Spin-coating or thin-film printing including slot die coating, roller printing, screen printing and inject printing, is a technique which is conventional in the art and with which the skilled person is familiar.EXAMPLES[000114] The present invention will now be described with reference to the following examples which should be considered in all respects as illustrative and non-restrictive.[000115] EXAMPLE 1[000116] An example according to the invention is as follows:[000117] Example: thin film materials[000118] Example: inorganic carrier layer[000119] Example: All organic materials (including buffer layers and photoresists):[000120] Example of parameters used in lithography.[000121] Dry etching method. Examples of dry etching methods include plasma etching using gases, such as O2, Ar, SFe, etc., wherein the used parameters (such as flow rate, working pressure, power and duration) are decided by the materials, material thickness, and chamber conditions.[000122] Example of parameters used in dry etching and wet etching:[000123] Sacrificial protection layers: dissolution using solvents, such as Acetone, Isopropyl Alcohol (I PA). Rinse for 3 mins to 60 mins.[000124] EXAMPLE 2[000125] An example according to prepare the sacrificial protection layer where the sacrificial protection layer is single layer.[000126] To demonstrate the methods of the invention and the significant advantages and improvements which result, the inventors have employed the techniques disclosed herein to pattern monolayer M0S2 into a rectangular shape for use as a FET channel. Figure 2 (a-c) show the M0S2 channel etched by the conventional method described in Figure 1. In Figure 2 (a), the grey shadow as boxed are PR residues located above the patterned M0S2. The scanning electron microscope (SEM) image shown in Figure 2 (b) clearly shows the topography of these PR residues. The thin-film-like residues are deformed with folds and wrinkles, suggesting that they experienced re-deposition to channel areas after photoresist decomposition. The enlarged SEM image shown in Figure 2 (b) lower panel shows the continuous distribution of the PR residues in nanometer scales on gold electrodes, where the darker portrait of the residues in the image suggests its non-conductive nature. In practice, such detrimental residues encapsulate M0S2 channels from dielectrics and electrical contacts, and thus degrade the channel-dielectric interfaces and channel-electrical contacts in electronic devices. Moreover, Figure 2 (c) shows the AFM scan over the PR residues and the M0S2 channel. Excluding the folded and wrinkled PRresidues at the edge, the thicknesses of PR residues on the patterned M0S2 are estimated to be ~8 nm, as shown in the inset of Figure 2 (c). This is much thicker than the atomic thin monolayer 2D channels, and thus can significantly alter the electrical performance of the ultra-thin device. For comparison, Figure 2 (d-f) show the monolayer M0S2 patterned by the method proposed in the present invention. In contrast to Figure 2 (a-b), the optical micrograph in Figure 2 (d) and the SEM image shown in Figure 2 (e) indicate that the patterned M0S2 are free of PR residues and are presented with sharp and clean edges exposed by etching. Figure 2 (f) shows the AFM profile of the M0S2 channel patterned using the method proposed in the present invention, as well as two electrical contacts deposited on the M0S2 channel. The measured channel thickness is -0.81 nm (as shown in the inset), which is accordant with the previously reported thickness of the as- prepared monolayer M0S2, verifying the residue-free surface of the patterned M0S2.[000127] By integrating the patterned M0S2 channel into the FET, it is demonstrated herein that suppression of PR residues can enhance the device performance. In this regard, Figure 3 characterizes and compares the performance of top-gate FETs fabricated by the conventional method and the present invention, where 35 nm AI2O3 is used as the top-gate dielectric. Figure 3 (a) shows the transfer characteristics of the two FETs, showing that the top-gate FETs fabricated by the conventional method exhibit smaller on-state currents, moderate SS, and limited ON / OFF ratios. In contrast, the present invention contributes to a FET with an ON / OFF ratio of more than 106and increases the ON current by at least 2 orders. This enhancement can be attributed to the suppression of the PR residues at the interface of patterned M0S2 channel and top dielectrics, thus enhancing the electrostatic control. To quantify the PR-residue-induced degradation of electrostatic control, the inventors extracted the capacitance equivalent thickness (GET) of the two sets of FETs, which are integrated with the same gate oxides but fabricated with different patterned techniques (i.e., the conventional method and the method proposed in the present invention). To extract the effective permittivity (Eetr), the inventors used the gate electrodes and patterned M0S2 channel as top and bottom electrodes to measure the capacitance-voltage (CV) curves, and extract eefr with oxide thickness (t) and effective areas. GET can be calculated by using the equation of 3.9t / £eff and the results are shown in Figure 3 (b) as a function of voltage sweep frequency. The FETs fabricated by the method proposed in the present invention show a GET of -16 (blue dots), while conventional-method-patterned FETs (red dots) show a higher value of -20.5 at 10 kHz. Using the GET extracted from the FET fabricated by the conventional method as a reference, it is revealed that the present invention significantly enhances the gate modulation capability of the FET.[000128] Beyond the straightforward influence on interfaces, evidence from spectroscopy demonstrates that these PR residues may alter properties of the patterned material as well. Figure 4A (a) compares the FTIR spectra of the M0S2 patterned by the method proposed in the presentinvention and the conventional method. It is noteworthy that the peaks that are shared by all spectra, such as peaks around 630 cm-1, can be attributed to the MoS2 / sapphire stacks (the sapphire here functions as the support). The difference in IR fingerprints appears in the range from 675 cm-1to 775 cm-1. The conventional-method-patterned M0S2, no matter patterned by P- PR or N-PR, shows higher intensity than the M0S2 patterned by the method proposed in the present invention as well as the reference M0S2 (the as-grown M0S2 without any treatment). The FTIR results indicate the existence of PR residues in conventional-method-patterned M0S2. Figure 4A (b) shows the Raman spectra of the reference M0S2, the M0S2 patterned by the method proposed in the present invention, as well as the conventional-method-patterned M0S2 (P-PR and N-PR), from left to right, respectively. All spectra are normalized by Aigpeaks. The comparison of these spectra reveals a remarkably decreased Aig / E12g intensity ratio from left to right, demonstrating an increase of n-doping in M0S2. This data indicates that PR residues induced by the conventional methods can induce additional electron doping to M0S2. PL maps of the peak position shown in Figure 4B (a) further confirm the electron doping by significant peak redshifts from left to right as the consequence of increased trions being generated (quasi-particles consist of two electrons and one hole).[000129] Similarly, Figure 4B (b) shows the X-ray photoelectron spectroscopy (XPS) spectra of the reference M0S2, the M0S2 patterned by the method proposed in present invention, as well as the conventional-method-patterned M0S2, from the top to the bottom. The binding energies of Mo 3d and S 2p electrons remain inert after etching with the method proposed in the present invention while they are upshifted in the M0S2 patterned by the conventional methods, suggesting the shifting of Fermi level towards the conduction band of M0S2, i.e. , the n-doping to M0S2. Combining the Raman, PL, and XPS spectra, it can be concluded that the conventionally used method considerably induces PR residues and significantly influences the M0S2 properties, while the M0S2 patterned by the method proposed in present invention can be prevented from doping after the pattern processes, presenting properties similar to the as-grown M0S2. Based on the experimental results from the topography, spectroscopy, and device performance measurement, apparently, using the present invention to update the conventional method can effectively suppress PR residues on M0S2 channels, preventing the M0S2 channel from apparent doping and enhancing the gate electrostatic control capability in terms of FET operation. This experimental data demonstrates the significant advantages of the present invention.[000130] The sacrificial protection layer used in the aforementioned M0S2 pattern process consists of a buffer layer (PMMA) and a carrier layer (SiC>2). Figure 5 demonstrates that as an alternative, gold can replace SiC>2 functioning as the carrier layer, allowing the etchant of the carrier layer to be a mild gold etchant instead of HF solution. The optical image shown in Figure5(c) illustrates the successful patterning of the M0S2 channel, and thus further demonstrates the diversity of choices on the carrier layer (and / or the sacrificial protection layer).[000131] EMBODIMENTS OF THE INVENTION[000132] Other embodiments of the invention as described herein are defined in the following paragraphs:1. A method for producing a patterned film disposed on a support, the method comprising the steps of: providing a layered structure comprising a sacrificial protection layer disposed on the film, and a photoresist layer disposed on the sacrificial protection layer, the sacrificial protection layer selected to be free (or substantially free) of residues upon removal without damaging film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment, patterning the photoresist layer to produce masked and un-masked areas of the layered structure; in the unmasked areas, removing the sacrificial protection layer and the film to reveal the support; and in the masked areas, exposing the sacrificial protection layer to the solvent (such as water) such that the sacrificial protection layer releases from the underlying film, thereby resulting in the patterned film disposed the support.2. A layered structure for producing a patterned film disposed on a support, the layered structure comprising a sacrificial protection layer disposed on the film, and a photoresist layer disposed on the sacrificial protection layer, the sacrificial protection layer selected to be free (or substantially free) of residues upon removal without damaging film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment.3. Use of a layered structure for producing a patterned film disposed on a support, the layered structure comprising a sacrificial protection layer disposed on the film, and a photoresist layer disposed on the sacrificial protection layer, the sacrificial protection layer selected to be free (or substantially free) of residues upon removal without damaging film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment.4. A method for making a layered structure for producing a patterned film disposed on a support, the method comprising the steps of: providing the film disposed on the support, providing a sacrificial protection layer disposed on the film, wherein the sacrificial protection layer is selected to be free (or substantially free) of residues upon removal without damaging film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment, and providing a photoresist layer disposed on the sacrificial protection layer, thereby providing the layered structure.5. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the support is a rigid support, optionally selected from the group consisting of semiconductors, metals, and insulators, such as oxides, fluorides, nitrides, arsenides, carbides, diamond, glass, and their combination.6. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the support is a flexible support (e.g. polymer), optionally selected from the group consisting of polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethylene (PE), polycarbonate (PC), polypropylene (PP), polyether ether ketone (PEEK), polyarylate (PAR), polyethylene terephthalate glycol-modified (PETG), polydimethylsiloxane (PDMS), and their combination.7. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the film comprises a film material including atomically thin or thick film as well as quantum dot that is selected from the group consisting of semiconductors, metals, insulators, or their combination, such as: graphene, transition metal dichalcogenides [e.g., molybdenum disulfide (M0S2), tungsten diselenide (WSe2), tungsten disulfide (WS2)], transition metal carbides and nitrides (MXenes), black phosphorus (phosphorene), boron nitride, arsenide, antimonide, silicene, germanene, phosphorene, borophene, stanene, telluride, indium selenide (InSe), gallium selenide (GaSe), tin selenide (SnSe), indium sulfide (InS), gallium sulfide (GaS), tin sulfide (SnS), indium telluride (InTe), gallium telluride (GaTe), tin telluride (SnTe), oxides (e.g., Bi2O2Se, Ga2Os, etc.), and ultra-thin materials like diamond, SiC, GaN, GaAs, and more.8. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the film is a 2D layered semiconductor which is preferably a transition metal dichalcogenide film.9. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the film is homogenous.10. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the film comprises two or more sublayers, or an inplane mixture of different materials.11. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the sacrificial protection layer is a single layer and is selected from the group consisting of: water-soluble inorganic materials, such as Sr3AhO6, S^AhO?, CasAhOe, MgsAhOe, BasAhOe, NaAIO2, KAIO2, salts [NaCI, K, Cl, CaCI2, MgCI2, NH4CI, NaNO3, KNO3, Ca(NO3)2, Na2SO4, K2SO4, Na2SO4, K2SO4, (NH4)2SO4], carbonates and bicarbonates [Na2CO3, K2CO3, (NH4)2CO3, NaHCO3, KHCO3], phosphates [Na3PO4, K2PO4, (NH4)3PO4, Acetates [CH3COONa, CH3COOK],12. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the sacrificial protection layer comprises a buffer layer which is in contact with the film, and a carrier layer which is in contact with the buffer layer and the photoresist layer.13. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the buffer layer is formed from at least one polymeric material.14. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the polymeric material is selected from the group consisting of: PMMA, cellulose acetate (CA), polystyrene (PS), polyethylene (PE) polypropylene (PP), polyvinyl chloride (PVC), polycarbonate (PC), acrylonitrile butadiene styrene (ABS), polytetrafluoroethylene (PTFE)), or their mixture and more.15. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the carrier layer is preferably formed from at least one inorganic material.16. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the inorganic material is selected from the group consisting of an oxide, a carbide, a nitride, a metal, an alloy, and their combination.17. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein an oxide, or a carbide, or a nitride, or a metal or an alloy is selected from the group consisting of SiC>2, AhOx, ITO, SrTiOs, TiO2, SiC, Sisl^ , GaN, Ag, Al, Au, Co, Cr, Cu, Fe, Ge, Ir, Nb, Ni, Pd, Pt, Si, Sn, Ti, NbTi, AuGe, PdAu, NiFe, or their combination and more.18. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs comprising exposing the sacrificial protection layer to a solvent selected from the group consisting of: water, or acidic solutions or alkaline solutions.19. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs comprising exposing the sacrificial protection layer to an organic solvent, or a mixture of two or more organic solvents, selected from the group consisting of: ketone solvents, alcohols and dimethylsulfoxide (DMSO), preferably a mixture of acetone and isopropyl alcohol (I PA).20. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the photoresist layer is formed from a photopatternable material which is selected from the group consisting of: a photoresist comprising the main polymer resin, a photoactive compound (PAC), or a photoresist comprising the main a polymer resin, a photoinitiator, and a cross-linking agent, or other photopatternable materials that are well known in the art may be used in the present invention.21 . A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the patterned photoresist layer is produced by coating a photoresist solution on the sacrificial protection layer, exposing the photoresist layer, and developing the photoresist layer, resulting in the patterned photoresist layer to thereby produce the masked and un-masked areas of the layered structure.22. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the patterned film disposed the support is a part of a field-effect transistor (FET).23. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein in the unmasked areas, the sacrificial protection layer is removed to reveal the film by etching, such as a process selected from the group consisting of: wet etching process and / or a dry etching process.24. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein in the unmasked areas, the film is removed to reveal the support by etching, such as a process selected from the group consisting of: wet etching process and / or a dry etching process.25. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein dry etching is undertaken with a plasma gas selected from the group consisting of: O2, N2, H2, CI2, He, Ar, SFe, CH4, CHF3, NF3, C2F6, CH3CI, BC or other gases well known in the art may also be utilized within the scope of the present invention.26. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein wet etching is undertaken with an etchant selected from the group consisting of: gold etchant (Kl / 12 solution)], hydrofluoric (HF) acid solution, buffered oxide etch (BOE), phosphoric acid (H3PO4), sulfuric acid (H2SO4), nitric acid (HNO3), potassium hydroxide (KOH), chromium etchants, FeC solution, ammonium persulfate [(NH4)2S20s], and others well known to those skilled in the art and depending on the materials to be etched.27. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the film is disposed on the support by a thin film growth technique, or thin film transfer technique, or the combination of both.28. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the sacrificial protection layer is single layer disposed on the film by physical vapor deposition (PVD) methods including pulsed laser deposition (PLD), molecular-beam epitaxy (MBE), oxide molecular-beam epitaxy (OMBE), RF or DC magnetron sputtering deposition, thermal evaporation, electron beam evaporation, arc vapour deposition, ion plating, and reactive PVD, and chemical vapor deposition (CVD) methods including cold- or hot-wall CVD, atomic layer deposition (ALD), metal organic chemical vapour deposition (MOCVD), thermal CVD, plasma- enhanced CVD (PECVD), photo-enhanced CVD (photo-CVD), low-pressure CVD (LPCVD), high-pressure CVD (HPCVD), laser-assisted CVD (LCVD), atmosphericpressure CVD, and other methodologies including transferring a layer of freestanding inorganic sacrificial protection layer membrane on the buffer layer .29. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the sacrificial protection layer is multilayer and one of layers is the buffer layer disposed on the film by coating or printing.30. A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the sacrificial protection layer is multilayer and one of layers is carrier layer disposed on the buffer layer by physical vapor deposition (PVD) methods including pulsed laser deposition (PLD), molecular-beam epitaxy (MBE), oxide molecular-beam epitaxy (OMBE), RF or DC magnetron sputtering deposition, thermal evaporation, electron beam evaporation, arc vapour deposition, ion plating, and reactive PVD, and chemical vapor deposition (CVD) methods including cold- or hot-wall CVD, atomic layer deposition (ALD), metal organic chemical vapour deposition (MOCVD), thermal CVD, plasma-enhanced CVD (PECVD), photo-enhanced CVD (photo-CVD), low-pressure CVD (LPCVD), high-pressure CVD (HPCVD), laser-assisted CVD (LCVD), atmospheric pressure CVD, and other methodologies including transferring a layer of freestanding inorganic carrier membrane on the buffer layer.31 . A method, a layered structure, or use of a layered structure according to any one of the previous paragraphs wherein the photoresist is disposed on the sacrificial protection layer by spin-coating a photoresist solution on the sacrificial protection layer.[000133] Although the invention has been described with reference to specific examples, it will be appreciated by those skilled in the art that the invention may be embodied in many other forms, and in particular features of any one of the various described examples may be provided in any combination in any of the other described examples. Various modifications and alterations to this invention will become apparent to those skilled in the art without departing from the scope and spirit of this invention. It should be understood that this invention is not intended to be unduly limited by the illustrative embodiments and examples set forth herein and that such examples and embodiments are presented by way of example only with the scope of the invention intended to be limited only by the claims set forth herein as follows.

Claims

CLAIMS1. A method for producing a patterned film disposed on a support, the method comprising the steps of: providing a layered structure comprising a sacrificial protection layer disposed on the film, and a photoresist layer disposed on the sacrificial protection layer, the sacrificial protection layer selected to be free (or substantially free) of residues upon removal without damaging film layer, and at least partially soluble or swellable in a solvent (such as water), and preferably clear to photolithographic alignment, patterning the photoresist layer to produce masked and un-masked areas of the layered structure; in the unmasked areas, removing the sacrificial protection layer and the film to reveal the support; and in the masked areas, exposing the sacrificial protection layer to the solvent such that the sacrificial protection layer releases from the underlying film, thereby resulting in the patterned film disposed on the support.

2. The method according to claim 1 wherein the support is a rigid support, optionally selected from the group consisting of semiconductors, metals, insulators, or their combination, such as oxides, fluorides, nitrides, arsenides, carbides, diamond, and glass.

3. The method according to claim 1 wherein the support is a flexible support, optionally selected from the group consisting of inorganic, organic materials, or their combination, such as graphite, mica, polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethylene (PE), polycarbonate (PC), polypropylene (PP), polyether ether ketone (PEEK), polyarylate (PAR), polyethylene terephthalate glycol-modified (PETG), polydimethylsiloxane (PDMS).

4. The method according to any one of the preceding claims wherein the film comprises a thin film material that is selected from the group consisting of semiconductors, metals, insulators, or their combination, such as graphene / graphite, transition metal dichalcogenides [e.g., molybdenum disulfide (M0S2), tungsten diselenide (WSe2), tungsten disulfide (WS2)], transition metal carbides and nitrides (MXenes), black phosphorus (phosphorene), boron nitride, arsenide, antimonide, silicene, germanene, phosphorene, borophene, stanene, telluride, indium selenide (InSe), gallium selenide (GaSe), tin selenide (SnSe), indium sulfide (InS), gallium sulfide (GaS),tin sulfide (SnS), indium telluride (InTe), gallium telluride (GaTe), tin telluride (SnTe), oxides (e.g., Bi2C>2Se, Ga2C>3, etc.), and other ultra-thin materials like diamond, SiC, GaN, GaAs, and more.

5. The method according to any one of claims 1 to 4 wherein the film is a 2D layered semiconductor, which is preferably a transition metal dichalcogenide film, such as M0S2 and WSe2.

6. The method according to any one of claims 1 to 5 wherein the film is homogenous.

7. The method according to any one of claims 1 to 5 wherein the film comprises two or more sublayers, or an in-plane mixture of different materials.

8. The method according to any one of claims 1 to 7 wherein the sacrificial protection layer is a solvent-soluble single layer and is selected from the group consisting of: water-soluble inorganic materials, such as SrsAhOe, S^AhO?, CasA^Oe, MgsAhOe, BasAhOe, NaAIO2, KAIO2, salts [NaCI, K, Cl, CaCI2, MgCI2, NH4CI, NaNO3, KNO3, Ca(NO3)2, Na2SO4, K2SO4, Na2SO4, K2SO4, (NH4)2SO4], carbonates and bicarbonates [Na2CO3, K2CO3, (NH4)2CO3, NaHCOs, KHCO3], phosphates [Na3PO4, K2PO4, (NH4)3PO4, and acetates [CH3COONa, CH3COOK].

9. The method according to any one of claims 1 to 7 wherein the sacrificial protection layer comprises a buffer layer which is in contact with the film, and a carrier layer which is in contact with the buffer layer and the photoresist layer.

10. The method according to claim 9 wherein the buffer layer is formed from at least one polymeric material.

11. The method according to claim 10 wherein the polymeric material is selected from the group consisting of: PMMA, cellulose acetate (CA), polystyrene (PS), polyethylene (PE) polypropylene (PP), polyvinyl chloride (PVC), polycarbonate (PC), Acrylonitrile Butadiene Styrene (ABS), polytetrafluoroethylene (PTFE)), or their mixture.

12. The method according to any one of claims 9 to 11 wherein the carrier layer is formed from at least one inorganic material.

13. The method according to claim 12 wherein the inorganic material is selected from the group consisting of an oxide, a carbide, a nitride, a metal or an alloy.

14. The method according to claim 13 wherein an oxide, or a carbide, or a nitride, or a metal or an alloy is selected from the group consisting of SiO2, AhOx, ITO, SrTiO3, TiO2, SiC, Si3N4, GaN, Ag, Al, Au, Co, Cr, Cu, Fe, Ge, Ir, Nb, Ni, Pd, Pt, Si, Sn, Ti, NbTi, AuGe, PdAu, NiFe or their combination.

15. The method according to claim 8 wherein the step of exposing the sacrificial protection layer to a solvent includes a solvent selected from the group consisting of: water, acidic solutions and alkaline solution.

16. The method according to claim 9 wherein the step of exposing the sacrificial protection layer to an organic solvent, or a mixture of two or more solvents, includes an organic solvent selected from the group consisting of: ketone solvents, alcohols, and dimethylsulfoxide (DMSO), preferably a mixture of acetone and isopropyl alcohol (I PA).

17. The method according to any one of claims 1 to 16 wherein the photoresist layer is formed from a photopatternable material which is selected from the group consisting of: a photoresist comprising the main polymer resin, a photoactive compound (PAC), or a photoresist comprising the main a polymer resin, a photoinitiator, and a cross-linking agent, or other photopatternable material.

18. The method according to claim 17 wherein the patterned photoresist layer is produced by coating a photoresist solution on the sacrificial protection layer, exposing the photoresist layer, and developing the photoresist layer, resulting in the patterned photoresist layer to thereby produce the masked and un-masked areas of the layered structure.

19. The method according to any one of claims 1 to 18 wherein the patterned film disposed the support is a part of a device used in circuits, such as a field-effect transistor (FET), or a device used for energy conversion, such as a photodetector.

20. The method according to any one of claims 1 to 19 wherein in the unmasked areas, the sacrificial protection layer is removed to reveal the film by etching, such as a process selected from the group consisting of: wet etching process and / or a dry etching process.

21. The method according to any one of claims 1 to 20 wherein in the unmasked areas, the film is removed to reveal the support by etching, such as a process selected from the group consisting of: wet etching process and / or a dry etching process.

22. The method according to any one of claims 20 to 21 wherein the dry etching is undertaken by plasma etching with a gas selected from the group consisting of: O2, N2, H2, CI2, He, Ar, SFe, CH4, CHF3, NF3, C2F6, CH3CI, BCI3.

23. The method according to any one of claims 20 to 21 wherein wet etching is undertaken with an etchant selected from the group consisting of: gold etchant (KI / I2 solution)], HF solution, FeCI3solution, ammonium persulfate.

24. A layered structure for producing a patterned film disposed on a support, the layered structure comprising a sacrificial protection layer disposed on the film, and a photoresist layer disposed on the sacrificial protection layer, the sacrificial protection layer selected to be free (or substantially free) of residues upon removal without damaging film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment.

25. Use of a layered structure for producing a patterned film disposed on a support, the layered structure comprising a sacrificial protection layer disposed on the film, and a photoresist layer disposed on the sacrificial protection layer, the sacrificial protection layer selected to be free (or substantially free) of residues upon removal without damaging film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment.

26. A method for making a layered structure for producing a patterned film disposed on a support, the method comprising the steps of: providing the film disposed on the support, providing a sacrificial protection layer disposed on the film, wherein the sacrificial protection layer is selected to be free (or substantially free) of residues upon removal without damaging film layer, at least partially soluble or swellable in a solvent, and preferably clear to photolithographic alignment, and providing a photoresist layer disposed on the sacrificial protection layer, thereby providing the layered structure.

27. The method according to claim 26 wherein the film is disposed on the support by a thin film growth technique, or thin film transfer technique, or the combination of both.

28. The method according to any one of claims 26 to 27 wherein the sacrificial protection layer on the film is a single inorganic layer disposed by physical vapor deposition methods including electron beam evaporation, RF magnetron sputtering, DC magnetron sputtering, thermal evaporation, molecular beam epitaxy, and chemical vapor deposition methods including atomic layer deposition, molecular organic chemical vapor deposition and others.

29. The method according to any one of claims 26 to 27 wherein the sacrificial protection layer is multilayer and one of layers is the buffer layer disposed on the film by coating or printing.

30. The method according to any one of claims 26 to 27 wherein the sacrificial protection layer is multilayer and one of layers is carrier layer disposed on the buffer layer by physical vapor deposition methods including electron beam evaporation, RF magnetron sputtering, DC magnetron sputtering, thermal evaporation, molecular beam epitaxy, and chemical vapordeposition methods including atomic layer deposition, molecular organic chemical vapor deposition and other methodologies including transferring a layer of freestanding inorganic carrier membrane on the buffer layer.

31. The method according to any one of claims 26 to 30 wherein the photoresist layer is formed from a photopatternable material which is selected from the group consisting of: a photoresist comprising the main polymer resin, a photoactive compound (PAC), or a photoresist comprising the main a polymer resin, a photoinitiator, and a cross-linking agent, or other photopatternable materials.

32. The method according to claim 31 wherein the photoresist is disposed on the sacrificial protection layer by coating or printing a photoresist solution on the sacrificial protection layer.

Images