Sine wave generator

Abstract

The present invention provides a sine wave generating device, comprising: a first frequency divider, which inputs a clock signal, performs frequency division in different proportions and outputs a plurality of frequency division signals; a multiplexer, which inputs the plurality of frequency division signals and selects one of the target frequency division signals for output according to a first control word; a second frequency divider, which inputs the target frequency division signal and generates an address clock signal using a second control word as a frequency division coefficient; a memory, which stores a quantized amplitude value of a sine wave; and an address counter, which inputs the address clock signal and generates an address signal under the control of the address clock signal, and generates a sine wave by indexing the quantized amplitude value of the sine wave from the memory.

Description

Technical Field

[0001] The invention mainly relates to a digital frequency synthesizer, and in particular to a sine wave generating device. Background Art

[0002] Direct digital synthesizers (DDS) are used to generate sine waves and their derivatives for automatic test equipment, software defined radio, medical imaging, and other applications.

[0003] Figure 1 The schematic diagram of an existing DDS sine wave generator is shown in Figure 1. Figure 1 As shown, the quantized amplitude value of a sine wave, for example, for one cycle is stored in a lookup table (LUT), which is indexed using the high-order output of the counter. Figure 1 In the example, assume that the length of the counter L is 29 bits, and the upper 8 bits of the counter are used as the address of the lookup table. Parameter E can control whether the lowest E bit of the counter is used, and parameter M can control the cumulative step value of the counter. In this way, the effective length of the counter Le = LE. The frequency of the final generated sine wave is:

[0004]

[0005] Where Fs is the system clock frequency.

[0006] However, in the existing DDS sine wave generating device, E is at the exponential position and M is at the numerator position. The frequency step generated by the change of these two parameters is relatively large, and the frequency accuracy needs to be improved. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide a sine wave generating device which can provide higher frequency accuracy.

[0008] To solve the above technical problems, the present invention provides a sine wave generating device, comprising: a first frequency divider, which inputs a clock signal, divides the frequency at different ratios and outputs a plurality of divided frequency signals; a multiplexer, which inputs the plurality of divided frequency signals and selects one of the target divided frequency signals to output according to a first control word; a second frequency divider, which inputs the target divided frequency signal and generates an address clock signal using a second control word as a frequency division coefficient; a memory, which stores a quantized amplitude value of a sine wave; and an address counter, which inputs the address clock signal and generates an address signal under the control of the address clock signal, and generates a sine wave by indexing the quantized amplitude value of the sine wave from the memory.

[0009] In one embodiment of the present invention, the second frequency divider is a PWM clock generator.

[0010] In one embodiment of the present invention, the second frequency divider includes a counter and a comparator, the counter inputs the target frequency division signal, one input end of the comparator is connected to the output end of the counter, the other input end of the comparator is connected to the second control word, and the output end of the comparator is connected to the reset end of the counter.

[0011] In one embodiment of the present invention, the memory stores the quantized amplitude value of a half period of the sine wave.

[0012] In one embodiment of the present invention, the memory stores the quantized amplitude value of a quarter period of the sine wave.

[0013] In one embodiment of the present invention, the quantized amplitude value of the sine wave is stored in a lookup table.

[0014] Compared with the prior art, in the sine wave generating device of the present invention, since the first control word E and the second control word M are both in the denominator position in the frequency expression of the sine wave, the frequency change step caused by their changes is smaller, so that the frequency accuracy of the sine wave generating device is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The schematic diagram of a sine wave generating device of an existing DDS is shown in FIG.

[0016] Figure 2 4 is a circuit diagram of a sine wave generating device according to an embodiment of the present invention.

[0017] Figure 3 4 is a circuit diagram of a PWM clock generator according to an embodiment of the present invention.

[0018] Figure 4 is a graph of a sine wave in a lookup table according to an embodiment of the present invention.

[0019] Figure 5 is a graph of sine and cosine waves generated according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0021] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0022] Figure 2 FIG. 1 is a circuit diagram of a sine wave generating device according to an embodiment of the present invention. Figure 2As shown, a sine wave generating device 20 of the present embodiment includes a first frequency divider 21, a multiplexer 22, a second frequency divider 23, a memory 24 and an address counter 25. The first frequency divider 21 inputs a clock signal Main_clk, whose frequency is Fs, and outputs a plurality of frequency-divided signals after frequency division in different proportions. The clock signal Main_clk is, for example, a system clock signal. The number of frequency-divided signals that the first frequency divider 21 can divide varies. The multiplexer 22 inputs a plurality of frequency-divided signals, and selects one of the target frequency-divided signals T_clk for output according to the first control word E. The upper limit of the first control word E of the multiplexer 22 is the number of frequency-divided signals that the first frequency divider 21 can divide. For example, if the number of frequency-divided signals that the first frequency divider 21 can divide is 32, then the first control word E is less than 32, and takes 0-31. The first control word E can be input to the multiplexer 22 through a multi-bit signal. Taking the first control word as 0-31 as an example, the signal width is 5 bits.

[0023] The second frequency divider 23 inputs the target frequency division signal T_clk, and generates the address clock signal addr_clk using the second control word M as the frequency division coefficient. That is, the frequency of addr_clk is 1 / M of the target frequency division signal T_clk. The second control word M is a positive integer.

[0024] The memory 24 stores the quantized amplitude value of the sine wave. The address counter 25 receives the address clock signal addr_clk and generates the address signal addr under the control of the address clock signal addr_clk, indexing the quantized amplitude value of the sine wave from the memory 24 to generate the sine wave sine.

[0025] Assume the frequency of the sine wave is F, then

[0026]

[0027] Here, N is the bit width of the address signal addr of the address counter 25, which is a constant. E is the first control word, and M is the second control word, which is a variable. Thus, by changing the first control word E and the second control word M, sine waves of different frequencies can be obtained. Moreover, since the first control word E and the second control word M are both in the denominator position, the frequency change step caused by their change is smaller, so that the frequency accuracy of the sine wave generating device 20 is higher.

[0028] In the embodiment of the present invention, the second frequency divider 23 may have different known implementations. In one embodiment, the second frequency divider 23 may be a PWM clock generator. Figure 3 FIG. 1 is a circuit diagram of a PWM clock generator according to an embodiment of the present invention. Figure 3As shown, the second frequency divider 23 may include a counter 31 and a comparator 32, the counter 31 inputs the target frequency division signal T_clk, one input end of the comparator 32 is connected to the output end of the counter 31, the other input end of the comparator 32 is connected to the second control word M, and the output end of the comparator 32 is connected to the reset end of the counter 31. Under the timing control of the target frequency division signal T_clk, the counter 31 counts the target frequency division signal T_clk, and the count value is compared with the second control word M at the comparator 32. If the count value is less than the second control word M, the comparator 32 outputs a first level (such as a low level), and if the count value is equal to the second control word M, the comparator 32 flips and outputs a second level (such as a high level), thereby generating a pulse of the address clock signal addr_clk. At the same time, the comparator 32 outputs to the reset end of the counter 31, so that the counter 31 is reset to 0. Thus, the output of the counter 31 is similar to a triangular wave signal in the time domain, and the counter 31 outputs a pulse of the address clock signal addr_clk each time it is "saturated" (the count value is equal to the second control word M), and the frequency of addr_clk is 1 / M of the target divided signal T_clk.

[0029] In the memory 24, the quantized amplitude value of the sine wave is stored in a lookup table. Conventionally, the lookup table can store the quantized amplitude value of a sine wave. For example Figure 4 is a graph of a sine wave in a lookup table according to an embodiment of the present invention, and the graph is exactly one cycle. In this case, the index value of the lookup table is 0-255, 256 values. Preferably, the lookup table can store the quantized amplitude value of a half cycle or even a quarter cycle of a sine wave. Figure 4 For example, the lookup table may only include the quantized amplitude values ​​(Q1 and Q2 parts) of the sine wave with index values ​​0-127, or only include the quantized amplitude values ​​(Q1 part) of the sine wave with index values ​​0-63. In this case where a complete sine wave cycle is not included, the address signal addr is translated and the quantized amplitude values ​​of a half cycle or a quarter cycle are repeatedly used to read out the complete sine wave cycle.

[0030] In addition to the sine wave, a cosine wave can also be generated by controlling the bias of the read address. Figure 5 is a graph of sine and cosine waves generated according to an embodiment of the present invention.

[0031] The sine wave generating device of the above embodiment of the present invention achieves higher frequency resolution by setting the control word compared with the existing sine wave generating device. The embodiment of the present invention is easy to implement in hardware and occupies less hardware resources.

[0032] Although the present invention has been described with reference to the current specific embodiments, a person skilled in the art should recognize that the above embodiments are only used to illustrate the present invention, and various equivalent changes or substitutions may be made without departing from the spirit of the present invention. Therefore, any changes or modifications to the above embodiments within the spirit of the present invention will fall within the scope of the claims of this application.

Claims

1. A sine wave generating device, comprising: The first frequency divider inputs a clock signal, divides the clock signal at different ratios, and outputs a plurality of divided frequency signals; a multiplexer, inputting the multiple frequency-divided signals and selecting one of the target frequency-divided signals for output according to a first control word; A second frequency divider, inputting the target frequency division signal and using the second control word as a frequency division coefficient to generate an address clock signal; A memory for storing the quantized amplitude value of the sine wave; as well as An address counter inputs the address clock signal and generates an address signal under the control of the address clock signal, indexing the quantized amplitude value of the sine wave from the memory to generate a sine wave; The frequency F of the sine wave is expressed by the following formula: Fs represents the frequency of the input clock signal; E represents the first control word, and the upper limit of the first control word E is the number of divided signals that the first divider can divide; M represents the second control word, and the second control word M is a positive integer; N represents the bit width of the address signal of the address counter, and N is a constant.

2. The sine wave generating device according to claim 1, characterized in that: The second frequency divider is a PWM clock generator.

3. The sine wave generating device according to claim 2, characterized in that: The second frequency divider includes a counter and a comparator. The counter inputs the target frequency division signal, one input end of the comparator is connected to the output end of the counter, the other input end of the comparator is connected to the second control word, and the output end of the comparator is connected to the reset end of the counter.

4. The sine wave generating device according to claim 1, characterized in that: The memory stores the quantized amplitude value of a half period of the sine wave.

5. The sine wave generating device according to claim 1, characterized in that: The memory stores the quantized amplitude value of 1 / 4 period of the sine wave.

6. The sine wave generating device according to claim 1, characterized in that: The quantized amplitude value of the sine wave is stored in a lookup table.

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