DC dual power supply starting and switching current limiting circuit

Abstract

The present invention relates to a DC dual power supply starting and switching current limiting circuit. Two DC power supplies are connected to a starting / switching current limiting unit through their respective contactors. The starting / switching unit is composed of an IGBT Q1 and a peak voltage absorption circuit. The absorption circuit absorbs the voltage spike generated by the parasitic inductance on the DC power transmission line to protect the IGBT Q1 from overvoltage damage. The present invention can suppress the impact current during the switching process of the two DC power supplies, while taking into account the working conditions when the inverter power supply is started, suppressing the starting impact current, and eliminating the need for an additional soft start circuit. The present invention has a simple control strategy, can realize the closing and disconnection of the contactor without current, is reliable in operation, and has good application prospects.

Description

Technical Field

[0001] The invention relates to a power electronic technology, in particular to a DC dual power supply starting and switching current limiting circuit suitable for an inverter power supply. Background Art

[0002] The inverter converts DC power into AC power to supply power to the load of the small power grid. To ensure reliability, two DC power supplies are often used for DC input, one for main use and one for backup. When the main power supply is powered off, it automatically switches to the backup power supply. The conversion of the two power supplies does not affect the normal operation of the inverter. When the input power supply and the inverter power supply are required to be electrically isolated in the power-off state, a contactor is usually used as a switching switch, and the contactor action time is usually long. In order to prevent the inverter power bus capacitor from losing power significantly during this period of no power supply, the bus capacitor is required to have a large enough capacity. When the input DC power supply switches from low voltage to high voltage, the bus capacitor will be recharged, generating a large impact current, which is prone to tripping. Summary of the invention

[0003] The present invention aims at solving the problems existing in the commonly used DC conversion switch and proposes a DC dual power supply starting and switching current limiting circuit to suppress the impact current in the switching process of two DC power supplies.

[0004] The technical solution of the present invention is: a DC dual power supply starting and switching current limiting circuit, two DC input power supplies I and II supply power to the inverter, the output of the DC power supply I is connected to the contactor I, and the output of the DC power supply II is connected to the contactor II.

[0005] The outputs of contactor I and contactor II are connected in parallel to the same point and then connected to the starting and switching current limiting unit, and the outputs of the starting and switching current limiting unit are connected to the DC bus capacitor of the inverter power supply;

[0006] The output voltage signals of DC power supply I and DC power supply II, and the contact feedback signals of contactor I and contactor II are collected and sent to the control algorithm circuit. The control algorithm circuit generates a contactor control signal and sends it to the current limiting implementation circuit and the contactor control circuit. The starting and switching current limiting unit includes a parallel IGBT Q1 and a voltage spike absorption circuit. The inverter power input current signal is sent to the current limiting implementation circuit as a feedback value. The current limiting implementation circuit generates an IGBT Q1 control signal to the starting and switching current limiting unit. By controlling the switching action of the IGBT and the contactor, the impact current generated during starting and power switching is coordinated and suppressed.

[0007] The voltage spike absorption circuit is composed of a first capacitor C1, a second capacitor C2, a first resistor R1, and a first diode D1; the first capacitor C1 is connected in parallel to the collector and emitter of the IGBT Q1; one end of the first resistor R1 is connected to the collector of the IGBT Q1, and the other end is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to the emitter of the IGBT Q1; the first diode D1 is connected in parallel to the first resistor R1, and the anode of D1 is connected to the collector of the IGBT Q1.

[0008] The current limiting implementation circuit comprises a comparator N1, a D trigger N2, a second resistor R2, a third resistor R3, a second diode D2, a third diode D3 and an IGBT driving circuit;

[0009] The input current feedback value is sent to the positive end of the comparator N1, the current limiting reference value is sent to the negative end of the comparator, and the output end of the comparator N1 is pulled up to the power supply Vcc through the third resistor R3; the anode of the third diode D3 is connected to the output end of the comparator N1, and the cathode of D3 is connected to the set end S of the D flip-flop N2; the anode of the second diode D2 is connected to the D flip-flop enable and lock signal generated by the control algorithm circuit, and the cathode of D2 is connected to the cathode of the third diode D3; one end of the second resistor R2 is connected to the set end S of the D flip-flop N2, and the other end is grounded; the clock end CK of the D flip-flop N2 is connected to a square wave signal of a fixed frequency, the reset end R is grounded, the data input end D is grounded, and the inverting output end Qn is sent to the IGBT drive circuit.

[0010] The beneficial effects of the present invention are as follows: the DC dual power supply starting and switching current limiting circuit of the present invention can suppress the impact current during the switching process of the two DC power supplies, while taking into account the working conditions when the inverter power supply is started, suppressing the starting impact current, and eliminating the need for an additional soft start circuit. The control strategy of the present invention is simple, and the contactor can be closed and disconnected without current, and the operation is reliable, and has good application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of the structure of the DC dual power supply starting and switching current limiting circuit of the present invention;

[0012] Figure 2 It is a schematic diagram of the control of the DC dual power supply starting and switching current limiting circuit of the present invention;

[0013] Figure 3 This is a schematic diagram of a current limiting circuit for the present invention;

[0014] Figure 4 This is a waveform diagram of the DC dual power supply starting current limiting circuit of the present invention;

[0015] Figure 5 This is a waveform diagram of the DC dual power supply switching current limiting circuit of the present invention. DETAILED DESCRIPTION

[0016] like Figure 1 and Figure 2 The structure and control schematic diagram of the DC dual power supply starting and switching current limiting circuit shown in the figure, the circuit includes two DC input power supplies I and II, the two power supplies supply power to the inverter, the output of the DC power supply I is connected to the contactor I, the output of the DC power supply II is connected to the contactor II, the outputs of the contactors I and II are connected in parallel to the same point and then connected to the starting and switching current limiting unit 101, and the output of the starting and switching current limiting unit 101 is connected to the DC bus capacitor of the inverter power supply. The output voltage signals of the DC power supply I and the DC power supply II, and the contact feedback signals of the contactors I and II are collected and sent to the control algorithm circuit, the control algorithm circuit generates a contactor control signal and sends it to the current limiting implementation circuit and the contactor control circuit, the inverter power input current signal is sent to the current limiting implementation circuit, the current limiting implementation circuit generates an IGBT control signal to the starting and switching current limiting unit 101, and finally by controlling the switching action of the IGBT and the contactor, the impact current generated during starting and power switching is coordinated and suppressed.

[0017] In the DC dual power supply starting and switching current limiting circuit, the parasitic inductance on the output cables of the DC power supply I and the DC power supply II cannot be ignored, and are equivalent to the first inductance L1 and the second inductance L2 respectively.

[0018] The starting and switching current limiting unit 101 includes an IGBT Q1 and a voltage spike absorption circuit 102 connected in parallel. The voltage spike absorption circuit 102 is composed of a first capacitor C1, a second capacitor C2, a first resistor R1, and a first diode D1. The first capacitor C1 is connected in parallel to the collector and emitter of the IGBT Q1; one end of the first resistor R1 is connected to the collector of the IGBT Q1, and the other end is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to the emitter of the IGBT Q1; the first diode D1 is connected in parallel to the first resistor R1, and the anode of D1 is connected to the collector of the IGBT Q1.

[0019] like Figure 3The current limiting circuit 103 is shown as a schematic diagram, and the current limiting circuit 103 includes a comparator N1, a D flip-flop N2, a second resistor R2, a third resistor R3, a second diode D2, a third diode D3 and an IGBT driving circuit. The input current feedback value is sent to the positive end of the comparator N1, the current limiting reference value is sent to the negative end of the comparator, and the output end of the comparator N1 is pulled up to the power supply Vcc through the third resistor R3; the anode of the third diode D3 is connected to the output end of the comparator N1, and the cathode of D3 is connected to the set end S of the D flip-flop N2; the anode of the second diode D2 is connected to the D flip-flop enable and lockout signal generated by the control algorithm circuit, and the cathode of D2 is connected to the cathode of the third diode D3; one end of the second resistor R2 is connected to the set end S of the D flip-flop N2, and the other end is grounded; the clock end CK of the D flip-flop N2 is connected to a square wave signal of a fixed frequency, the reset end R is grounded, the data input end D is grounded, and the inverting output end Qn is sent to the IGBT driving circuit.

[0020] The present invention adopts the starting and current limiting switching unit 101 to suppress the impact current, and the implementation method is: IGBT Q1 works in a fixed frequency switching state, when the impact current reaches the set value, IGBT Q1 is turned off to reduce the input current, and IGBT Q1 is turned on again when the next cycle arrives.

[0021] Taking into account the parasitic inductance effect of the DC power transmission line, the starting and current limiting switching unit 101 further includes a peak voltage absorption circuit 102, and the first capacitor C1 is connected in parallel to both ends of the IGBT Q1 to absorb switching noise; after the IGBT Q1 is turned off, the first inductor L1 or the second inductor L2 is freewheeling through the first diode D1 and charges the second capacitor C2. The second capacitor C2 enables the voltage of the IGBT Q1 to rise slowly when it is turned off, protecting the IGBT Q1 from overvoltage damage. When the IGBT Q1 is turned on in the next cycle, the energy stored in the second capacitor C2 is consumed by the first resistor R1.

[0022] The control algorithm circuit outputs the D flip-flop enable and lockout signals, which are connected to the set terminal S of the D flip-flop N2 through the second diode D2. The lockout signal is high level and the enable signal is low level. When shutting down or performing fault protection, the control algorithm circuit gives a high level lockout signal, the second diode D2 is turned on, and the set terminal S of the D flip-flop N2 is pulled up to a high level. From the working principle of the D flip-flop, it can be seen that Qn outputs a low level signal to turn off the IGBT. When starting or switching, the control algorithm circuit gives a low-level enable signal. The working state of the D flip-flop is determined by the output state of the comparator N1. The working process within a switching cycle is as follows: the sampled input current feedback value is sent to the positive input terminal of the comparator N1, and the set current limit reference value is sent to the negative input terminal of the comparator N1. The output terminal of the comparator N1 is connected to the set terminal S of the D flip-flop N2 through the third diode D3. When the current feedback value is greater than the current limit setting value, the comparator N1 outputs a high level, the third diode D3 is turned on, and the set terminal S of the D flip-flop N2 is pulled up to a high level. According to the working principle of the D flip-flop, Qn outputs a low-level signal to turn off the IGBT Q1. After the IGBT Q1 is turned off, the input current begins to decrease. When the current feedback value is less than the current limit setting value, the comparator N1 outputs a low level, the third diode D3 is turned off, and the set terminal S of the D flip-flop N2 is pulled down to a low level. When the next high level of the clock terminal CK of the D flip-flop N2 arrives, Qn is flipped from a low-level signal to a high-level signal, and the IGBT Q1 is turned on again. After several switching cycles, the inverter power bus capacitor is fully charged, the input current feedback value is always less than the current limiting reference value, Qn is always a high level signal, and IGBT Q1 always remains in the on state.

[0023] Assuming that the voltage value of DC power supply II is greater than the voltage value of DC power supply I, DC power supply I is started and switched to DC power supply II. The entire starting and switching process can be described as follows:

[0024] After the control algorithm circuit detects that the state of the DC power supply I is normal, it gives a closing instruction to the contactor I to close it, and at the same time enables the D flip-flop N2, the IGBT Q1 is turned on, and the inverter power bus capacitor starts to charge, generating an impact current. When it is detected that the current is greater than the current limiting reference value, the IGBT Q1 is turned off, and the input current drops below the current limiting reference value. The voltage spike induced by the first inductor L1 is suppressed by the spike voltage absorption circuit 102. When the next high level of the clock terminal CK of the D flip-flop N2 arrives, the IGBT is turned on again. After several cycles, the inverter power bus capacitor is charged, the input current feedback value is always less than the current limiting reference value, Qn is always a high level signal, and the IGBT Q1 always remains in the on state.

[0025] After the control algorithm circuit detects that the state of DC power supply I is abnormal and the state of DC power supply II is normal, the D trigger N2 is first blocked to turn off the IGBT Q1, and then the disconnection instruction of contactor I is given to make contactor I disconnect with zero current. After the control algorithm circuit receives the feedback signal of contactor I contact disconnection, the closing instruction of contactor II is given. When contactor II is closed, the control algorithm circuit enables the D trigger N2, and the IGBT Q1 is turned on. Since the voltage value of DC power supply II is greater than the voltage value of DC power supply I, the inverter power bus capacitor begins to charge and generates a surge current. When it is detected that the current is greater than the current limiting reference value, the IGBT Q1 is turned off, and the input current drops below the current limiting reference value. The voltage spike induced by the second inductor L2 is suppressed by the spike voltage absorption circuit 102. When the next high level of the clock terminal CK of the D trigger N2 arrives, the IGBT is turned on again. After several cycles, the inverter power bus capacitor is fully charged, the input current feedback value is always less than the current limiting reference value, Qn is always a high level signal, and the IGBT Q1 always remains in the on state.

[0026] Figure 4 and Figure 5 The current limiting waveforms during starting and switching are shown respectively, and the impact current can be effectively suppressed.

Claims

1. A DC dual power supply starting and switching current limiting circuit, two DC input power supplies I and II supply power to the inverter, the output of DC power supply I is connected to contactor I, and the output of DC power supply II is connected to contactor II, characterized in that: The outputs of contactor I and contactor II are connected in parallel to the same point and then connected to the starting and switching current limiting unit, and the outputs of the starting and switching current limiting unit are connected to the DC bus capacitor of the inverter power supply; The output voltage signals of DC power supply I and DC power supply II and the contact feedback signals of contactor I and contactor II are collected and sent to the control algorithm circuit. The control algorithm circuit generates a contactor control signal and sends it to the current limiting implementation circuit and the contactor control circuit. The starting and switching current limiting unit includes a parallel IGBT Q1 and a voltage spike absorption circuit. The inverter power input current signal is sent to the current limiting implementation circuit as a feedback value. The current limiting implementation circuit generates an IGBT Q1 control signal to the starting and switching current limiting unit. The starting and current limiting switching unit suppresses the impact current. The implementation method is: IGBT Q1 works in a fixed frequency switching state. When the impact current reaches a set value, IGBT Q1 is turned off to reduce the input current, and IGBT Q1 is turned on again when the next cycle arrives.

2. The DC dual power supply starting and switching current limiting circuit according to claim 1, characterized in that: The voltage spike absorption circuit is composed of a first capacitor C1, a second capacitor C2, a first resistor R1, and a first diode D1; the first capacitor C1 is connected in parallel to the collector and emitter of the IGBT Q1; one end of the first resistor R1 is connected to the collector of the IGBT Q1, and the other end is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to the emitter of the IGBT Q1; the first diode D1 is connected in parallel to the first resistor R1, and the anode of D1 is connected to the collector of the IGBT Q1.

3. The DC dual power supply starting and switching current limiting circuit according to claim 1 or 2, characterized in that: The current limiting implementation circuit comprises a comparator N1, a D trigger N2, a second resistor R2, a third resistor R3, a second diode D2, a third diode D3 and an IGBT driving circuit; The input current feedback value is sent to the positive end of the comparator N1, the current limiting reference value is sent to the negative end of the comparator, and the output end of the comparator N1 is pulled up to the power supply Vcc through the third resistor R3; the anode of the third diode D3 is connected to the output end of the comparator N1, and the cathode of D3 is connected to the set end S of the D flip-flop N2; the anode of the second diode D2 is connected to the D flip-flop enable and lock signal generated by the control algorithm circuit, and the cathode of D2 is connected to the cathode of the third diode D3; one end of the second resistor R2 is connected to the set end S of the D flip-flop N2, and the other end is grounded; the clock end CK of the D flip-flop N2 is connected to a square wave signal of a fixed frequency, the reset end R is grounded, the data input end D is grounded, and the inverting output end Qn is sent to the IGBT drive circuit.

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