Method for manufacturing a semiconductor element including a high-resistance substrate

Abstract

The present application relates to a method of manufacturing a semiconductor component comprising a high resistivity substrate. The method of manufacturing a semiconductor component comprises a rapid thermal processing step exposing a substrate comprising a base having a resistivity greater than 1000 Ohm-cm to a peak temperature capable of degrading the resistivity of the base. According to the present application, a corrective thermal processing is performed after the step of rapid thermal processing, said corrective thermal processing exposing the substrate to a corrective temperature between 800°C and 1250°C and having a cooling rate less than 5°C / s when the corrective temperature is between 1250°C and 1150°C, less than 20°C / s when the corrective temperature is between 1150°C and 1100°C and less than 50°C / s when the corrective temperature is between 1100°C and 800°C.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device comprising a high-resistivity substrate. Background Technology

[0002] Integrated devices are typically fabricated on a wafer-like substrate, which serves primarily as the base for the fabrication of integrated devices. However, the increasing integration and expected performance of these devices have led to a growing correlation between device performance and the characteristics of the substrate on which the device is formed. This is especially true for radio frequency (RF) devices, which handle signals at frequencies between approximately 3 kHz and 300 GHz and are particularly used in the telecommunications field (telephones, Wi-Fi, Bluetooth, etc.).

[0003] As an example of device / substrate interaction, the electromagnetic field generated by a high-frequency signal propagating in the device penetrates deep into the substrate and interacts with any charge carriers that may be present in the substrate depth. The result is the wasted energy of the signal due to insertion loss, and potential interference between components due to "crosstalk".

[0004] Radio frequency devices such as antenna switches and tuners, as well as power amplifiers, can be manufactured on substrates specifically designed to allow these phenomena and enhance their performance.

[0005] High-resistivity silicon-on-insulator (HR SOI) substrates are also known, such as Figure 1a As shown, it includes a silicon substrate 2 with a resistivity greater than 1 kiloohm-cm, an insulating layer 4 on the substrate 2, and a silicon surface layer 5 disposed on the insulating layer. Figure 1b As shown, substrate 1 may also include a charge trapping layer 3 disposed between substrate 2 and insulating layer 4. The trapping layer 3 may include undoped polysilicon. The fabrication of this type of substrate is described, for example, in documents FR2860341, FR2933233, FR2953640, US2015115480, US7268060, or US6544656.

[0006] The applicant has observed that the application of rapid thermal processing to such SOI substrates can lead to damage to the radio frequency characteristics of the substrate. Currently, these rapid thermal processes are particularly useful for surface treatment of substrates during substrate manufacturing. They are also necessary steps in typical manufacturing methods for CMOS devices, such as for activating dopants.

[0007] therefore, Figure 2 The resistivity loss observed on a high-resistivity SOI substrate after rapid thermal processing is shown. Figure 2In the graph, the horizontal axis represents the measurement depth (in micrometers) in substrate 2. This distance is taken from the interface with the insulating layer (this SOI substrate has no trapping layer). The vertical axis represents the resistivity (in ohm-cm) obtained by SRP (spread resistance measurement) type measurement.

[0008] To perform this measurement, a substrate is prepared by polishing a bevel with an appropriate angle from a planar surface into the desired depth. Then, the ends of two electrodes are applied to the beveled portion of the substrate, and a defined voltage is applied between the two electrodes, whose ends are spaced a fixed distance apart and form a segment parallel to the edge of the bevel. The resistance between the two electrodes is measured, and then the resistivity of the substrate at the measurement depth is subtracted from this measurement. By performing this measurement at different distances relative to the edge of the bevel (corresponding to different depths in the substrate), a resistivity distribution curve can be plotted, representing the resistivity according to the depth in the substrate.

[0009] exist Figure 2 In the graph, the first curve "a" corresponds to the expected resistivity of the SOI substrate before rapid thermal processing. This substrate is specially manufactured to have p-type residual conductivity.

[0010] Figure 2 The second curve "b" in the graph corresponds to the SRP measurement performed on the SOI substrate after it has undergone rapid thermal processing (exposing the substrate to a temperature of approximately 1200°C for a few seconds before rapidly reducing the temperature at a rate greater than 200°C / second).

[0011] It was observed that the resistivity of the SOI substrate was significantly impaired by this treatment, exhibiting a resistivity of less than 1000 ohm-cm at depths exceeding 200 micrometers from its surface. Furthermore, after rapid thermal processing, the charges present in substrate 2 were predominantly n-type.

[0012] After the SOI substrate 1 has undergone rapid thermal processing, the resistivity of the substrate 2 at its depth is not high enough and not stable enough to guarantee operation according to the specifications required for the RF devices formed in the substrate.

[0013] The subject of this invention

[0014] One object of the present invention is to provide a method for manufacturing semiconductor devices that includes a rapid thermal processing step, without or limiting the resistivity changes that occur in prior art methods. Summary of the Invention

[0015] To achieve this objective, the present invention provides, in its broadest sense, a method for manufacturing a semiconductor device, the method comprising a rapid thermal treatment step that exposes a substrate comprising a substrate having a resistivity greater than 1000 ohm·cm to a peak temperature capable of degrading the resistivity of the substrate.

[0016] According to the present invention, the method is characterized in that a curing heat treatment is performed after the rapid heat treatment step, the curing heat treatment exposing the substrate to a curing temperature between 800°C and 1250°C, and having the following cooling rate:

[0017] - When the correction temperature is between 1250℃ and 1150℃, the speed is less than 5℃ / second.

[0018] - When the correction temperature is between 1150℃ and 1100℃, less than 20℃ / second, and

[0019] - When the correction temperature is between 1100℃ and 800℃, the speed is less than 50℃ / second.

[0020] During the corrective heat treatment, the concentration of holes in the substrate approaches thermodynamic equilibrium. Controlled cooling of the corrective heat treatment allows this near-equilibrium state to be maintained and the hole concentration to be reduced. Therefore, excessive freezing or precipitation of these holes at the end of the corrective heat treatment (e.g., in the form of easily charge-carrying complexes, which would excessively alter the resistivity of the substrate) is avoided.

[0021] Other advantageous and non-limiting features according to the invention (either alone or in any technically feasible combination):

[0022] Peak temperatures range from 1050℃ to 1250℃;

[0023] • In the rapid thermal annealing layout, rapid heat treatment and straightening heat treatment are implemented in situ;

[0024] • Achieve corrective heat treatment in a different layout than that used for rapid heat treatment;

[0025] • Achieve corrective heat treatment in a vertical furnace;

[0026] • Maintain the correction temperature below 1050°C for at least 20 seconds;

[0027] • The correction temperature is maintained at:

[0028] At or below 1000°C for at least 1 minute, or

[0029] ο Below or equal to 950°C for at least 5 minutes, or

[0030] ο Below or equal to 900°C for at least 30 minutes, or

[0031] Temperatures below or equal to 800°C for at least 3 hours;

[0032] • The straightening heat treatment is carried out in a neutral, reducing, or oxidizing atmosphere;

[0033] The substrate also includes an insulating layer on the substrate and a surface layer on the insulating layer;

[0034] The substrate also includes a charge trapping layer between the substrate and the insulating layer;

[0035] • The charge trapping layer is a polycrystalline silicon layer;

[0036] • A protective layer is formed on the substrate prior to the corrective heat treatment;

[0037] The substrate is made of silicon;

[0038] Semiconductor components are radio frequency (RF) devices;

[0039] Semiconductor components are silicon wafers on an insulator with a diameter of 200 or 300 mm. Attached Figure Description

[0040] The invention will be better understood from the following description of a non-limiting embodiment of the invention with reference to the accompanying drawings, wherein:

[0041] - Figure 1a and Figure 1b This illustrates a high-resistivity SOI substrate from the prior art;

[0042] - Figure 2 This is a graph showing the resistivity loss observed on a high-resistivity SOI substrate after undergoing rapid thermal processing.

[0043] - Figure 3 The sequence of steps in the method for manufacturing a semiconductor device according to the present invention is shown.

[0044] - Figure 4 This represents a known construction of a rapid thermal annealing layout;

[0045] - Figure 5 The temperature distribution of rapid heat treatment was reproduced;

[0046] - Figure 6 An example of a corrective heat treatment according to an embodiment of the present invention is shown;

[0047] - Figure 7 An example of a corrective heat treatment according to another embodiment of the invention is shown. Detailed Implementation

[0048] To simplify the following description, in the prior art or in different embodiments illustrating the method, the same reference numerals are used for the same elements or elements that provide the same function.

[0049] Figure 3 The sequence of steps constituting a manufacturing method for a semiconductor element according to the present invention is shown.

[0050] "Semiconductor element" refers to a semiconductor device or substrate, particularly a semiconductor device or substrate used in the RF field. Therefore, this invention can be applied to the manufacture of one or more of these elements.

[0051] During the first step, a substrate 1 with a high-resistivity substrate 2 (i.e., resistivity greater than 1000 ohm-cm) is provided. Preferably, the substrate 2 has this high resistivity quality over its entire thickness. This characteristic can be measured using the SRP technique described in the introduction of this application.

[0052] Preferably, the substrate 2 is at least partially made of silicon, which is obtained, for example, by a technique of the Czochralski (Cz) method. Thus, the substrate 2 can correspond to a P-type silicon substrate having a small amount of interstitial oxygen (referred to as "low Oi") between 6 ppm and 10 ppm. Prior to precipitation, the substrate 2 can also be a silicon substrate having a large amount of interstitial oxygen (referred to as "high Oi") greater than 26 ppm.

[0053] Preferably, the substrate 1 is a silicon-on-insulator (SOI) substrate having a silicon surface layer 5, an insulating layer 4 (e.g., silicon oxide) and a silicon substrate 2. The substrate may also have a charge trapping layer 3 located between the insulating layer 4 and the substrate 2.

[0054] As taught in the prior art and in the preamble, substrate 1 can be manufactured in many ways. Preferably, it is manufactured by applying Smart Cut. TM The technology is used to manufacture the substrate 1, in which an oxidized silicon layer intended to form a silicon surface layer 5 and an insulating layer 4 is transferred to a substrate 2, which optionally has a trapping layer 3. Typically, a finishing sequence is performed on the substrate 1 after this transfer step to impart the desired properties to the substrate 1 (particularly with respect to its surface state).

[0055] Typically, substrate 1 can exist in the form of a circular wafer with a diameter of 200mm, 300mm or even 450mm.

[0056] The surface layer 5 can have a thickness between 10 nm and 10 micrometers. The insulating layer 4 can be formed of silicon dioxide and has a thickness between 10 nm and 50 micrometers.

[0057] Generally, the trapping layer 3 can be composed of an amorphous semiconductor layer with structural defects such as dislocations, grain boundaries, amorphous regions, interstices, inclusions, and pores. These structural defects form traps for charges that may move in the material, such as in regions of incomplete or suspended chemical bonds. This prevents conduction in the trapping layer, thus resulting in high resistivity.

[0058] Advantageously, and for ease of implementation, the trapping layer 3 is formed of a polycrystalline silicon layer. Its thickness can be between 1 and 3 micrometers. However, other thicknesses, smaller or larger than this range, are also very possible.

[0059] The properties and attributes of the surface layer 5, the insulating layer 4, and the trapping layer 3 are not of particular importance in the semantics of this invention and can be selected or specified as needed and in the application environment.

[0060] In subsequent steps of the method according to the invention, still regarding Figure 2 The substrate 1, including the substrate 2, is exposed to a peak temperature. The peak temperature is the highest temperature to which the substrate 1 is exposed during a rapid thermal processing step. This step can be part of the final processing flow of the substrate 1 during its manufacturing process. It can also correspond to a semiconductor device manufacturing step, such as the step of activating dopants.

[0061] "Rapid thermal processing" refers to a step in which substrate 1 is exposed to a processing atmosphere at a plateau temperature for a maximum of 2 minutes. The plateau temperature is typically between 1125 and 1250 degrees Celsius and corresponds to the peak temperature to which substrate 1 is exposed. The rise and fall phases to reach the plateau temperature occur with a strong thermal gradient greater than 60°C / s, which limits the total duration of the processing.

[0062] The duration of the processing platform can be very short, depending on the chosen rapid heat treatment layout, ranging from a few microseconds in a flash annealing layout to 15 to 45 seconds in a rapid annealing furnace.

[0063] The treatment atmosphere depends on the purpose of the treatment. For example, it can be a neutral, reducing, or oxidizing atmosphere.

[0064] To apply this rapid heat treatment, it is known, for example (e.g.) Figure 4(Illustrated schematically) A rapid thermal annealing layout including a quartz chamber 6 to receive the substrate to be processed. The processing is performed by means of heating lamps 7 positioned below and above the substrate. During processing, the substrate remains horizontal within the chamber on a base formed by three points 8. The atmosphere of the chamber can be controlled by introducing a selected gas, which is then exhausted through a controlled exhaust opening 9.

[0065] This layout enables rapid heat treatment by supplying power to lamp 7, heating the substrate to a predetermined temperature, for example, between 1150°C and 1250°C, via radiation. Although it takes 10 to 20 seconds to reach the plateau temperature, the substrate temperature rises very rapidly, at approximately 60°C / second or higher. In this layout, heat treatment at this plateau temperature can last for 30 seconds to 2 minutes. At the end of this time, the power supply to lamp 7 is cut off, and the substrate temperature drops rapidly, again at approximately 60°C / second. Typically, 20 to 30 seconds are required to cool the substrate and allow it to be removed from the chamber. The typical temperature distribution obtained in this layout is reproduced in, for example... Figure 5 It should be noted that the pyrometer equipped in chamber 6, capable of temperature measurement, is only valid for temperature values ​​greater than approximately 600°C or 700°C. This explains... Figure 5 The cutoff shape of the curve graph.

[0066] Rapid heat treatment can also be applied using laser annealing or flash annealing layouts.

[0067] At the end of this rapid thermal processing, as mentioned in the introduction of this application, the resistivity of substrate 1 may deteriorate. Therefore, there is no guarantee that the semiconductor devices formed in / on substrate 1 will operate according to the required specifications.

[0068] It is not intended to associate the present invention with any physical explanation for these observations and possible phenomena, but it appears that substrate 2 is particularly sensitive to rapid thermal treatment.

[0069] The applicant's analysis tends to show that a large concentration of cavities forms in the substrate when the peak temperature is between 1050°C and 1250°C. During cooling, especially when the temperature drops below 1050°C, these cavities readily combine with interstitial oxygen in the substrate, thereby (particularly when the cavity concentration exceeds the thermodynamic equilibrium concentration) forming stable hole / oxygen complexes in the bulk of substrate 2. These complexes are known by the terms "hole-oxygen complex" or "VO complex".

[0070] Under thermodynamic equilibrium, the concentration of holes increases with temperature. For example, at 1200℃, this concentration can reach 3 × 10⁻⁶.12 cm -3 Up to 5×10 12 cm -3 The concentration of these holes is high. During the rapid cooling of substrate 1, and without any specific precautions, these holes freeze in substrate 2 by combining with interstitial oxygen. This general mechanism has been reported in the technical literature of the art. However, in a particularly original manner, the applicant has determined that these compounds are not electrically neutral, but are capable of carrying negative charges. Based on the analysis conducted in the context of this invention, the charge carried by the hole / oxygen compound at the end of the rapid thermal treatment results in the change in resistivity discussed in the introduction of this application. It should also be understood that the generation of a high concentration of negative charge causes the conductivity of the substrate to change from P-type to N-type conductivity.

[0071] This invention proposes an improved method for manufacturing semiconductor devices based on these novel results.

[0072] Therefore, and again refer to Figure 2 The present invention proposes to perform a corrective heat treatment on the substrate 1 after a rapid heat treatment step, thereby restoring or at least partially preventing the loss of resistivity.

[0073] According to the present invention, the correction heat treatment exposes the substrate 1 to a correction temperature between 800°C and 1250°C, and has the following cooling rate:

[0074] - When the correction temperature is between 1250℃ and 1150℃, the speed is less than 5℃ / second.

[0075] - When the correction temperature is between 1150℃ and 1100℃, less than 20℃ / second, and

[0076] - When the correction temperature is between 1100℃ and 800℃, the speed is less than 50℃ / second.

[0077] Within a temperature range of 800°C to 1250°C, the oxygen / hole complex can be dissociated, thereby destabilizing it. Furthermore, by controlling the cooling of substrate 1 (and thus substrate 2), the hole concentration is gradually reduced to its thermodynamic equilibrium concentration (which decreases with temperature). Therefore, freezing of these holes in excess concentration as hole / oxygen complexes is avoided.

[0078] The corrective heat treatment atmosphere can consist of a neutral gas (such as argon), a reducing gas (such as hydrogen), or even a mixture of both. The corrective heat treatment atmosphere can also be oxygen.

[0079] According to the first embodiment, the straightening heat treatment can be performed in a different layout than that used for rapid heat treatment.

[0080] This implementation is particularly recommended when it is not possible to change the conditions of the rapid thermal treatment to prevent or limit the concentration of excessive hole / oxygen complexes. This is especially true when the rapid thermal treatment is intended to activate dopants pre-introduced into the surface layer 5 of the substrate 1. In such cases, it is known that it is important to limit the thermal treatment to only the necessary thermal treatment to avoid the diffusion of these dopants, which does not always allow for cooling control of such rapid thermal treatment within recommended ranges.

[0081] To correct the change in substrate resistivity that would occur under these conditions, a corrective heat treatment with a corrective temperature of 1050°C or lower can be applied to substrate 1 in a conventional vertical oven for at least 20 seconds. This heat treatment is followed by cooling at a rate of less than 50°C / second to maintain compatibility with the general conditions for heat treatments capable of correcting substrates as described above.

[0082] By using a threshold temperature not exceeding 1050°C, the generation of new holes in substrate 2 is avoided, as is the formation of new, stable hole / oxygen complexes that could easily damage the resistivity of substrate 2. As an example, the correction temperature of the correction heat treatment can be maintained at less than or equal to 1000°C for at least 1 minute, or less than or equal to 950°C for at least 5 minutes, or less than or equal to 900°C for at least 30 minutes, or less than or equal to 800°C for at least 3 hours, to at least partially restore the resistivity of substrate 2. Between 1050°C and 800°C, whichever temperature is chosen, it is maintained for a sufficient time to reduce the hole concentration by bringing it close to its thermodynamic equilibrium concentration.

[0083] In the process of Figure 2 The curves a and b show measurements taken on an SOI substrate similar to the substrate in question, and on this substrate, temperature distribution has been performed. Figure 5 The temperature distribution shown is quite rapid, followed by a heat treatment at 900°C lasting for over 1 hour. Prior to this heat treatment was the oxidation of the surface layer of the SOI substrate. At the end of this corrective heat treatment, SRP measurements were performed, where... Figure 2 The resistivity curve marked with the letter 'c' in the figure is the result. Note that the resistivity of the substrate is relatively constant, and its magnitude is close to the original resistivity represented by curve 'a'. This finding demonstrates the effect and effectiveness of the proposed corrective annealing.

[0084] According to a second embodiment of the invention (which is particularly advantageous), rapid heat treatment and corrective heat treatment (e.g., in a rapid heat annealing configuration) are performed in situ.

[0085] According to a first variation of this embodiment, the straightening heat treatment is integrated into the rapid heat treatment. By controlling the electrical energy supplied to the lamps 7 in the chamber 6 of the rapid heat annealing layout at the end of the temperature plateau (corresponding to the peak temperature), the straightening heat treatment can be established by controlling the temperature to decrease at the following thermal gradients: less than 5 °C / s when the straightening temperature is between 1250 °C and 1150 °C, less than 20 °C / s when the straightening temperature is between 1150 °C and 1100 °C, and less than 50 °C / s when the straightening temperature is between 1100 °C and 800 °C.

[0086] Therefore, compared with the rapid heat treatment of the prior art, this slower cooling can be easily achieved by adjusting the power supplied to lamp 7 during this cooling stage. Figure 6 A rapid heat treatment integrating a corrective heat treatment after a temperature plateau is shown according to the present invention.

[0087] According to another variation, the corrective heat treatment is applied to substrate 1 separately from the rapid heat treatment and in a rapid thermal annealing layout. For example, the corrective heat treatment can be applied to substrate 1 at the end of the rapid heat treatment and once the processing temperature returns to a temperature close to room temperature.

[0088] This variant allows for rapid heat treatment, for example, in a first atmosphere (e.g., a neutral or reducing atmosphere), followed by corrective heat treatment in a second atmosphere (e.g., an oxidizing atmosphere) that is different from the first atmosphere.

[0089] According to another variation, a corrective heat treatment is applied to substrate 1 in a rapid annealing layout after rapid heat treatment, but not directly after the temperature plateau. Figure 7 An example of this implementation is shown. In this example, rapid cooling (i.e., at least 60°C / second) followed by a drop to 1000°C after a 1200°C plateau does not contribute to the corrective heat treatment. Figure 7 In one example, the corrective heat treatment involved heat treatment at 1000°C for 60 seconds, followed by cooling to room temperature at a rate of less than 50°C / second.

[0090] Regardless of the implementation scheme of the corrective heat treatment, the resistivity of substrate 2 changes very little (if it does) at the end of the treatment. In any case, the possible change in substrate resistivity after the corrective heat treatment is less than the change in resistivity that would be observed without such a corrective heat treatment.

[0091] Of course, the present invention is not limited to the described embodiments, and variations thereof may be implemented without departing from the scope of the invention as defined by the claims.

[0092] Therefore, to protect the surface of substrate 1 from the effects of the processing atmosphere, the corrective heat treatment can be performed after or include the oxidation stage. The oxide layer formed can then be removed at the end of the corrective heat treatment step by simple chemical etching. The oxidized surface limits the formation of holes during rapid heat treatment through a recombination effect.

[0093] This invention is not limited in any way to applying corrective heat treatment to SOI-type substrates. It can be applied to any type of substrate, including high-resistivity silicon substrates. The substrate can be constructed from a substrate formed from a large, massive wafer of high-resistivity silicon. The substrate can also include additional layers formed on or within the substrate. Fully or partially implemented semiconductor devices can be disposed thereon. When it relates to SOI-type substrates, the insulating layer and surface layer can be continuous or patterned or trenched.

[0094] According to the invention, it may be advantageous to provide a substrate with a very small amount of interstitial oxygen, thereby limiting the formation of hole / oxygen complexes and further reducing the change in substrate resistivity. Advantageously, the interstitial oxygen concentration in substrate 2 can be between 5 (in earlier uses) ppma and 15 ppma (according to standard ASTM 1979), which yields an acceptable trade-off between the mechanical strength of the substrate (interstitial oxygen contributes to mechanical strength) and the residual change in the resistivity of substrate 2.

[0095] Alternatively, (when feasible) the duration of rapid heat treatment can be limited, particularly within the temperature range between 1050°C and 1250°C, to limit the generation of cavitation, which is the cause of the reported phenomenon.

Claims

1. A method for manufacturing a semiconductor device, the method comprising a rapid thermal treatment step, the rapid thermal treatment step exposing a substrate (1) to a peak temperature, the substrate (1) comprising a substrate (2) with a resistivity greater than 1000 ohm·cm, an insulating layer (4) on the substrate (2) and a surface layer (5) on the insulating layer (4), the peak temperature being capable of degrading the resistivity of the substrate (2), the method being characterized in that a corrective thermal treatment is performed after the rapid thermal treatment step, the corrective thermal treatment exposing the substrate to a corrective temperature between 800°C and 1250°C and having the following cooling rate: - When the correction temperature is between 1250℃ and 1150℃, the cooling rate is less than 5℃ / second. - When the correction temperature is between 1150℃ and 1100℃, the cooling rate is less than 20℃ / second, and - When the correction temperature is between 1100℃ and 800℃, the cooling rate is less than 50℃ / second. in, The correction temperature is maintained at: - At or below 1000°C for at least 1 minute, or - At a temperature of 950°C or lower for at least 5 minutes, or - Keep at 900°C or below for at least 30 minutes.

2. The method for manufacturing a semiconductor device according to claim 1, wherein, The peak temperature is between 1050℃ and 1250℃.

3. The method for manufacturing a semiconductor device according to claim 1, wherein, The rapid heat treatment and the corrective heat treatment are performed in situ in the rapid thermal annealing layout.

4. The method for manufacturing a semiconductor element according to claim 1, wherein, The corrective heat treatment is performed in a different layout than that used for applying rapid heat treatment.

5. The method for manufacturing a semiconductor device according to claim 4, wherein, The corrective heat treatment is performed in a vertical furnace.

6. The method for manufacturing a semiconductor element according to claim 1, wherein, The corrective heat treatment is carried out in a neutral atmosphere, a reducing atmosphere, or an oxidizing atmosphere.

7. The method for manufacturing a semiconductor device according to claim 1, wherein, The substrate (1) further includes a charge trapping layer (3) between the substrate (2) and the insulating layer (4).

8. The method for manufacturing a semiconductor device according to claim 7, wherein, The charge trapping layer (3) is a polycrystalline silicon layer.

9. The method for manufacturing a semiconductor device according to claim 1, wherein, A protective layer is formed on the substrate (1) prior to the corrective heat treatment.

10. The method for manufacturing a semiconductor device according to claim 1, wherein, The substrate (2) is made of silicon.

11. The method for manufacturing a semiconductor device according to claim 1, wherein, The semiconductor element is a radio frequency device.

12. The method for manufacturing a semiconductor device according to claim 1, wherein, The semiconductor element is a silicon wafer on an insulator with a diameter of 200 mm or 300 mm.

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