A power device termination structure of lateral cell structure and a manufacturing method thereof

By introducing a lateral cell structure into the terminal structure of the IGBT chip, the problem of low terminal efficiency in large-area chip design is solved, higher current carrying capacity and withstand voltage level are achieved, and the manufacturing process is simplified.

CN108054206BActive Publication Date: 2026-07-21GLOBAL ENERGY INTERCONNECTION RES INST CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
GLOBAL ENERGY INTERCONNECTION RES INST CO LTD
Filing Date
2017-10-24
Publication Date
2026-07-21

AI Technical Summary

Technical Problem

Existing IGBT chip terminal structure designs are prone to defects in large-area applications, leading to decreased chip yield and low terminal efficiency, which affects the device's withstand voltage rating and on-state voltage drop.

Method used

A power device termination structure with a lateral cell structure was designed, including a substrate, a front doped region, an isolation insulating layer, a gate electrode, an emitter, and a cutoff ring field plate. The lateral cell structure is formed by utilizing the edge region of the substrate to increase the current carrying capacity of the chip.

Benefits of technology

It improves the chip's current carrying capacity and terminal efficiency, reduces on-state voltage drop, enhances the device's withstand voltage rating, and simplifies the manufacturing process.

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Abstract

The application provides a power device terminal structure of a lateral cell structure and a manufacturing method thereof. Taking an insulated gate bipolar transistor (IGBT) as an example, the structure comprises a substrate, a back doped region, a front doped region, an isolation insulating layer, an emitter, a collector and a gate electrode structure. The application provides a vertical power chip structure design and a manufacturing method thereof, in which a terminal structure of an original vertical power semiconductor device is designed as a lateral device structure, the terminal area can be effectively utilized to form an additional current passing area, and the current passing capacity of the chip is increased.
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Description

Technical Field

[0001] This invention relates to a conductor chip structure, specifically to a power semiconductor chip structure with a lateral cell structure and its fabrication method. Background Technology

[0002] Power semiconductor chips (such as IGBTs, MOSFETs, and MCTs) consist of an active region and a termination region. The active region is the main current-carrying area of ​​the chip, and the voltage-resistant termination region, designed to reduce the electric field on the surface of the semiconductor chip, surrounds the active region. The transition region between the active and termination regions is encircled by a gate busbar, which is used to uniformly transmit the gate PAD signal to each cell.

[0003] Taking the commonly used IGBT as an example, the structure of an IGBT (Insulated Gate Bipolar Transistor) device is very similar to that of a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The main difference is that the IGBT uses a P+ substrate instead of the N+ buffer layer of a MOSFET, creating a PN junction between the P+ and N- regions. It has three terminals: gate (G), emitter (E), and collector (C). IGBT devices are voltage-controlled devices. In addition to advantages such as low power consumption, high frequency, high voltage, and high current, they require simple drive and control circuits and have low drive power consumption. They are considered a representative product of the third revolution in power electronics technology and are core devices for intelligent power management and energy conservation and emission reduction.

[0004] With the sustained rapid economic development, the energy crisis is becoming increasingly severe, and a serious contradiction exists between supply and demand, making the development of energy-saving and new energy industries an urgent priority. Power electronic devices play a crucial role in energy conservation, serving as key components for mechanical automation and intelligent control, and are also energy-saving semiconductor devices. Therefore, vigorously developing the design and manufacturing of power electronic devices, as well as the development and application of modules, is an important measure for saving energy. IGBTs, as a representative of power electronic devices, are the preferred product for improving the performance and energy efficiency of overall systems.

[0005] The design of the termination structure is one of the key technologies in semiconductor devices, closely related to parameters such as breakdown voltage and on-state voltage drop. As the chip area increases to a certain extent, the probability of internal defects rises significantly, leading to a substantial decrease in chip yield. Therefore, chip area is limited by material defects. With a fixed chip area, higher termination efficiency and a smaller area result in a larger current-carrying area in the active region and a lower on-state voltage drop. Simultaneously, higher voltage ratings require larger termination sizes. Therefore, the efficiency of the termination in high-voltage devices directly affects the on-state voltage drop of the chip. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art. Taking IGBT as an example, this invention designs a lateral cell structure with current-carrying capacity for the terminal structure, which can effectively utilize the terminal area to form an additional current-carrying area and increase the current-carrying capacity of the chip.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A power device termination structure with a lateral cell structure includes:

[0009] A substrate 101 and a front doped region 103 and 104, an isolation insulating layer 107, a gate electrode 105, an emitter 106 and a cutoff ring field plate 109 are disposed on the substrate 101, and a collector electrode 108 is disposed below the substrate 101.

[0010] Among them, the gate electrode 105 is electrically isolated from the substrate 101; the emitter 106 is in ohmic contact with the front doped regions 103 and 104; the collector 108 is in ohmic contact with the back doped region 102; and the cutoff ring field plate 109 is in ohmic contact with the front doped region 103.

[0011] A vertical cell structure 110 is provided in the central region of the substrate 101;

[0012] The edge region of the substrate 101 is provided with a lateral cell structure 111.

[0013] A first preferred embodiment of a power device termination structure with a lateral cell structure.

[0014] The substrate 101 is n-type, the back doped region 102 and the front doped region 104 are p-type, and the front doped region 103 is n-type.

[0015] A second preferred embodiment of a power device termination structure with a lateral cell structure.

[0016] The substrate 101 is p-type, the back doped region 102 and the front doped region 104 are n-type, and the front doped region 103 is p-type.

[0017] A third preferred embodiment of a power device termination structure with a lateral cell structure.

[0018] The gate electrode 105 in the horizontal cell structure 111 and the gate electrode 105 in the vertical cell structure 110 are formed simultaneously.

[0019] A fourth preferred embodiment of a power device terminal structure with a lateral cellular structure.

[0020] The positive doped region 103 in the lateral cell structure 111 and the positive doped region 103 in the vertical cell structure 110 are formed simultaneously.

[0021] A fifth preferred embodiment of a power device terminal structure with a lateral cellular structure.

[0022] The lateral cell structure 111 is used in lateral MOSFETs, IGBTs, superjunction devices or bipolar transistor structures.

[0023] A sixth preferred embodiment of a power device terminal structure with a lateral cell structure.

[0024] The terminal structure is used for IGBT, MCT and BJT three-terminal devices based on Si, SiC and GaN semiconductor materials.

[0025] A method for fabricating a power device termination structure with a lateral cell structure includes the following steps:

[0026] (1) A terminal back-side doped region 102 is formed on the lower surface of the substrate 101;

[0027] (2) Forming front doped regions 103 and 104 of the terminal region on the upper surface of the substrate 101;

[0028] (3) An isolation insulating layer 107, a gate electrode 105, an emitter 106 and a cutoff ring field plate 109 are sequentially deposited and etched on the upper surface of the substrate 101.

[0029] (4) A collector 108 structure is formed on the lower surface of the substrate.

[0030] Compared with the closest existing technology, the technical solution provided by this invention has the following superior effects:

[0031] 1. The high-efficiency terminal structure of the vertical high-voltage power device provided by the present invention has the advantages of high efficiency, low stress in the isolation insulation layer, and good stability;

[0032] 2. The method for manufacturing a high-efficiency terminal structure for vertical high-voltage power devices provided by this invention has the advantage of being easy to process. Attached Figure Description

[0033] Figure 1: A schematic diagram of a vertical power chip structure in which horizontal cells replace terminals in an embodiment of the present invention.

[0034] Among them, 101 is the substrate; 102 is the back doped region; 103 and 104 are the front doped regions; 105 is the gate electrode; 106 is the emitter; 107 is the isolation insulating layer; 108 is the collector; 109 is the cutoff ring field plate; 110 is the vertical cell structure; and 111 is the lateral cell structure. Detailed Implementation

[0035] The following is in conjunction with the appendix Figure 1 The present invention will be further described in detail with specific embodiments, providing a clear and complete description of the technical solutions. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0036] This embodiment presents a power device termination structure with a lateral cell structure, including...

[0037] Substrate 101;

[0038] Front-side doped regions 103 and 104 are disposed on the upper surface of the substrate 101;

[0039] A back-side doped region 102 is disposed on the lower surface of the substrate 101;

[0040] An insulating layer 107 is disposed on the upper surface of the substrate 101;

[0041] A gate electrode 105 is disposed on the upper surface of the substrate 101 and is electrically isolated from the substrate;

[0042] Emitter 106 is disposed on the upper surface of the substrate 101 and is in ohmic contact with the front doped regions 103 and 104;

[0043] Collector 108 is disposed on the lower surface of the substrate 101 and is in ohmic contact with the back doped region 102;

[0044] The cutoff ring plate 109 is disposed on the upper surface of the substrate 101 and is in ohmic contact with the doped region 103;

[0045] A vertical cell structure 110 is disposed in the central region of the substrate 101;

[0046] A lateral cell structure 111 is disposed at the edge of the substrate 101.

[0047] Example 1

[0048] If substrate 101 is n-type, then doped regions 102 and 104 are p-type, and doped region 103 is n-type;

[0049] The lateral cell structure 111 can be a lateral MOSFET, IGBT, superjunction device, bipolar transistor, or other structures; the gate electrode in the lateral cell structure 111 and the gate electrode 105 in the vertical cell structure 110 are formed simultaneously; the doped region 103 in the lateral cell structure 111 can be formed simultaneously with the doped region 103 in the vertical cell structure 110.

[0050] This structure is applicable to a variety of materials and device types, such as IGBTs, MCTs, and BJTs, which are three-terminal devices based on semiconductor materials such as Si, SiC, and GaN.

[0051] Example 2

[0052] If substrate 101 is p-type, then doped regions 102 and 104 are n-type, and doped region 103 is p-type;

[0053] The lateral cell structure 111 can be a lateral MOSFET, IGBT, superjunction device, bipolar transistor, or other structures; the gate electrode in the lateral cell structure 111 and the gate electrode 105 in the vertical cell structure 110 are formed simultaneously; the doped region 103 in the lateral cell structure 111 can be formed simultaneously with the doped region 103 in the vertical cell structure 110.

[0054] This structure is applicable to a variety of materials and device types, such as IGBTs, MCTs, and BJTs, which are three-terminal devices based on semiconductor materials such as Si, SiC, and GaN.

[0055] In this invention, a vertical power chip with lateral cells replacing terminals can be prepared according to the following steps:

[0056] 1. A terminal region is formed on the lower surface of the substrate and back-side doped with 102.

[0057] 2. Form a terminal region on the upper surface of the substrate with positive doping of 103 and 104.

[0058] 3. An isolation insulating layer 102, a gate electrode 105, an emitter 107, and a cutoff ring field plate 109 are sequentially deposited and etched on the upper surface of the substrate.

[0059] 4. An electrode structure 108 is formed on the lower surface of the substrate.

[0060] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the specific implementation of the present invention with reference to the above embodiments. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention are within the protection scope of the pending claims.

Claims

1. A power device termination structure with a lateral cell structure, characterized in that, The structure includes: A substrate (101) and a first front doped region (103) and a second front doped region (104), an isolation insulating layer (107), a gate electrode (105), an emitter (106) and a cutoff ring field plate (109) are provided on the substrate (101), and a collector electrode (108) is provided below the substrate (101). The gate electrode (105) is electrically isolated from the substrate (101); the emitter (106) is ohmically in contact with the first front doped region (103) and the second front doped region (104); the collector electrode (108) is ohmically in contact with the back doped region (102); and the cutoff ring field plate (109) is ohmically in contact with the first front doped region (103). The central region of the substrate (101) is provided with a vertical cell structure (110); The edge region of the substrate (101) is provided with a transverse cell structure (111); The substrate (101) is n-type, the back doped region (102) and the second front doped region (104) are p-type, and the first front doped region (103) is n-type; The gate electrode (105) in the horizontal cell structure (111) and the gate electrode (105) in the vertical cell structure (110) are formed simultaneously; The first positive doped region (103) in the lateral cell structure (111) and the first positive doped region (103) in the vertical cell structure (110) are formed simultaneously; The lateral cell structure (111) is used in lateral MOSFETs, IGBTs, superjunction devices or bipolar transistor structures; The terminal structure is used for IGBT, MCT and BJT three-terminal devices based on Si, SiC and GaN semiconductor materials.

2. A power device termination structure with a lateral cell structure, characterized in that, The structure includes: A substrate (101) and a first front doped region (103) and a second front doped region (104), an isolation insulating layer (107), a gate electrode (105), an emitter (106) and a cutoff ring field plate (109) are provided on the substrate (101), and a collector electrode (108) is provided below the substrate (101). The gate electrode (105) is electrically isolated from the substrate (101); the emitter (106) is ohmically in contact with the first front doped region (103) and the second front doped region (104); the collector electrode (108) is ohmically in contact with the back doped region (102); and the cutoff ring field plate (109) is ohmically in contact with the first front doped region (103). The central region of the substrate (101) is provided with a vertical cell structure (110); The edge region of the substrate (101) is provided with a transverse cell structure (111); The substrate (101) is p-type, the back doped region (102) and the second front doped region (104) are n-type, and the first front doped region (103) is p-type; The gate electrode (105) in the horizontal cell structure (111) and the gate electrode (105) in the vertical cell structure (110) are formed simultaneously; The first positive doped region (103) in the lateral cell structure (111) and the first positive doped region (103) in the vertical cell structure (110) are formed simultaneously; The lateral cell structure (111) is used in lateral MOSFETs, IGBTs, superjunction devices or bipolar transistor structures; The terminal structure is used for IGBT, MCT and BJT three-terminal devices based on Si, SiC and GaN semiconductor materials.

3. A method for fabricating a power device terminal structure with a lateral cell structure as described in claim 1 or 2, characterized in that, The method includes the following steps: (1) A terminal back-side doped region (102) is formed on the lower surface of the substrate (101); (2) A first front-side doped region (103) and a second front-side doped region (104) of the terminal region are formed on the upper surface of the substrate (101); (3) An isolation insulating layer (107), a gate electrode (105), an emitter (106), and a cutoff ring field plate (109) are sequentially deposited and etched on the upper surface of the substrate (101); (4) A collector (108) structure is formed on the lower surface of the substrate.