Structure and method for detecting twin cell memories

Abstract

The present invention relates to a circuit and method for detecting time-dependent dielectric breakdown short circuits and signal residue testing. The present disclosure relates to a structure including a twin-cell memory configured to program a plurality of write operations, a current sense amplifier connected to the twin-cell memory and configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source connected to the current sense amplifier and configured to add an offset current to the current sense amplifier to generate the differential voltage.

Description

Technical Field

[0001] This disclosure relates to detecting time-dependent dielectric breakdown (TDDB) shorts and signal margin testing, and more particularly, to circuits and methods for detecting time-dependent dielectric breakdown (TDDB) shorts and signal margin testing for non-volatile memory arrays. Background Art

[0002] There are various types of one-time programmable memory (OTPM) arrays that represent embedded non-volatile memory (NVM) technology. In a particular type of OTPM, write operations occur over multiple write verification cycles to achieve a large threshold voltage shift of memory twin-cells. Additionally, depending on the mismatch within the OTPM twin-cells, the number of write verification cycles can vary significantly. Each of the write operations includes a write followed by a bitline leakage test to check for dielectric breakdown and a verification (i.e., read) to check if the cell has been written.

[0003] In an OTPM system, operations of the memory are performed one address at a time. For example, a single write operation may take approximately 8 milliseconds. Additionally, programming occurs at a high wordline voltage (about 2 volts) and an elevated (i.e., raised) source line (about 1.5 volts), and the elevated source line causes a current of approximately 2 mA to flow through the programmed transistor. This high-stress operation forces electrons to be trapped in the oxide of the programmed transistor, thereby shifting the threshold voltage of the transistor. This type of OTPM is referred to as a charge trap memory. In this case, time-dependent dielectric breakdown (TDDB) results in a short circuit from the wordline with resistance to the bitline, which causes defective wordlines for other parallel cells during programming and reading. Summary of the Invention

[0004] In one aspect of the present disclosure, a structure includes a twin-cell memory configured to program multiple write operations, a current sense amplifier connected to the twin-cell memory and configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source connected to the current sense amplifier and configured to add an offset current to the current differential to generate the differential voltage.

[0005] In another aspect of the present disclosure, a method includes offsetting a sense amplifier connected to a twin-cell memory array to a known logic state, reading an output of the sense amplifier with multiple wordlines connected to the twin-cell memory array turned off, and detecting a time-dependent dielectric breakdown (TDDB) fault of the twin-cell memory in response to the output of the sense amplifier being a logic state opposite to the known logic state.

[0006] In another aspect of the present disclosure, a method includes programming a twin cell at a predetermined programming interval, offsetting a sense amplifier connected to the twin cell memory array to a known logic state, reading an output of the sense amplifier with a plurality of word lines connected to the twin cell memory array turned off, and detecting a time-dependent dielectric breakdown (TDDB) fault of the twin cell memory array in response to the output of the sense amplifier being a logic state opposite to the known logic state. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the following detailed description, the present disclosure is described with reference to the plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.

[0008] Figure 1 A multi-step write operation according to an aspect of the present disclosure is shown.

[0009] Figure 2 A current sense amplifier with redundancy adjustment according to an aspect of the present disclosure is shown.

[0010] Figure 3 Testing a current sense amplifier with redundancy adjustment according to an aspect of the present disclosure is shown.

[0011] Figure 4 A method of a programming operation according to an aspect of the present disclosure is shown.

[0012] Figure 5 A true / complementary view of a programming operation according to an aspect of the present disclosure is shown. DETAILED DESCRIPTION

[0013] The present disclosure relates to detecting time-dependent dielectric breakdown (TDDB) shorts and signal redundancy testing, and more particularly, to circuits and methods for detecting time-dependent dielectric breakdown (TDDB) shorts and signal redundancy testing for non-volatile memory arrays. In more specific embodiments, bit line leakage testing within each write verification cycle will ensure that programmed transistors are tested for TDDB shorts. Advantageously, by implementing bit line leakage testing, programmed transistors will stop being written for remaining write operations, thereby preventing further stress on the transistors and allowing other cells to continue being written.

[0014] In a non-volatile element, the threshold voltage (Vt) shift depends on the charge trapped in the oxide of a pair of field effect transistors (FETs). Programming the FET increases the threshold voltage (Vt), which increases the likelihood of damaging the oxide (i.e., the gate of the FET is shorted to the source). When a TDDB failure occurs, depending on the bias condition, the gate is shorted to the source or drain in the FET. In addition, a one-time programmable memory (OTPM) array uses twin elements and a pair of FETs to program the OTPM array. The twin element of the OTPM is a pair of thin-oxide high-threshold voltage (HVT) NFET-based devices.

[0015] In addition, the twin element of the OTPM includes a true NFET transistor and a complementary NFET transistor. Each gate of the true NFET transistor and the complementary NFET transistor is connected to the word line WL. The source of the true NFET transistor is connected to the source of the complementary NFET transistor, and the sources of both the true NFET transistor and the complementary NFET transistor are connected to the source line SL. The drain of the true NFET transistor is connected to the true bit line (BLT), and the drain of the complementary NFET transistor is connected to the complementary bit line (BLC).

[0016] In the twin element of the OTPM array, programming is performed using the word line WL and the elevated source line SL (i.e., the elevated source line (ESL)). In addition, one of the bit lines (i.e., BLT or BLC) is kept grounded and the other bit line is floating. During programming, charge trapping will shift the threshold voltage (Vt) of one of the NFETs in the twin element (i.e., the complementary NFET transistor or the true NFET transistor) upward, thereby weakening the transistor. Then, the sense amplifier can compare the differential current between the true bit line (BLT) and the complementary bit line (BLC). In addition, in the OTPM array, before programming, the initial data state is unknown (i.e., the array data is "x").

[0017] The OTPM write operation can be performed over a number of write verification cycles to achieve a large (e.g., 10's of mV) threshold voltage (Vt) shift of the primitive. Additionally, depending on the mismatch in the OTPM high threshold voltage (HVT) twin primitives, the number of write verification cycles can vary significantly. It is desired that each write operation takes approximately 8 milliseconds. Thus, a margin is incorporated into the write operation such that charge loss due to thermal stress (e.g., baking), etc. until end of life (e.g., 10 years) does not erase the primitive. Additionally, over time, charge loss may result in an approximate loss of about 30% threshold voltage (Vt) shift at the end of the OTPM array life. To address these issues of TDDB failures when programming non-volatile OTPM arrays, the operations of embodiments will follow a write, leakage, and verification process. Thus, in an embodiment, a primitive suffering from a TDDB (i.e., word line WL to bit line BL short) failure is masked from future programming, which enables other primitives in parallel to be programmed at an optimal voltage (e.g., no defective word line due to TDDB on another primitive).

[0018] Figure 1 A multi-step write operation in accordance with aspects of the present disclosure is shown. In Figure 1 an embodiment, the multi-step write operation 100 is shown as N writes, labeled #1, #2, ..., #N. Additionally, in the multi-step write operation 100, the x-axis is time in milliseconds and the y-axis is voltage in volts. In the multi-step write operation 100, the first write operation (i.e., labeled #1) includes a programming operation 110, a leakage test 120, and a read (i.e., verification) test 130.

[0019] In Figure 1 an embodiment, in the programming operation 110, a write pulse voltage (i.e., VPP is about 2 volts) is applied to the gates of the twin primitives of the OTPM array. In other words, the VPP voltage (e.g., 2 volts) is applied to the word line connected to the gates of the twin primitives. Additionally, in the programming operation, the true bit line (BLT) is grounded, and the voltage of the source line SL is lower than the VPP voltage, e.g., 1.5 volts. Additionally, as Figure 1 shown. As Figure 1 shown, the word line WL width is the duration of the VPP write pulse. Figure 1 The duration and voltage in an embodiment can be controlled using the eFUSE option set for each chip. Additionally, as described above, the write operation is programmed to complete within a predetermined time (e.g., 8 milliseconds).

[0020] In Figure 1In the leakage test 120, the OTPM array can check for time-dependent dielectric breakdown (TDDB) failures due to programming. To perform the leakage test 120, the sense amplifier is offset to a known state, and a read operation occurs without any word line WL being selected. Additionally, TDDB failures on the NFET devices of the twin cells are detected as read failures attributed to bit line leakage. Thus, the leakage test 120 indicates oxide breakdown in the cells. Further, further writes to cells with TDDB failures will be masked.

[0021] In Figure 1 In the read (i.e., verify) test 130, the OTPM array can check if the cells are passing a margined read (i.e., overwrite protection). In the read (i.e., verify) test 130, the bit lines are sensed (e.g., Vdd of approximately 200 mV), at which time the source line voltage (VSL) is 0 V and the word line WL is approximately 500 mV. In Figure 1 In, the read voltage (i.e., VREAD) of the word line WL is approximately 500 mV. Additionally, in the read (i.e., verify) test 130, cells that will be written to subsequently are masked to protect them from TDDB failures.

[0022] In Figure 1 In, the second write operation (i.e., labeled #2) repeats the same programming operation 110, leakage test 120, and read (i.e., verify) test 130. However, after the first write operation (i.e., labeled #1), subsequent programming operations will mask bits that failed the previous leakage test 120 or passed the previous read (i.e., verify) test 130.

[0023] Still referring to Figure 1 , the leakage test 120 ensures that the bit lines are truly floating and there are no defective paths to ground. Additionally, when there is a shorted array device (i.e., oxide short), the bit line will have a path from the bit line to ground. In an embodiment, this will cause the leakage test 120 to fail. Additionally, the leakage test 120 operates with the word line WL off (i.e., WL = 0 volts). Then, the sense amplifier is tilted to induce a state (i.e., logic state). This sense amplifier offset will produce a known read result unless bit line leakage causes the sense amplifier to go the wrong way (i.e., detect a state opposite to the induced state). If the sense amplifier detects a state opposite to the induced state, the leakage test 120 will fail.

[0024] During a write operation, oxide damage may cause bit line leakage on a bit line (BLT or BLC) that remains grounded. During a read (i.e., verify) test 130, the bit line can be checked to verify that for any word line WL address, the bit line can still go high during a read operation. Additionally, a leakage test 120 can leave the sense amplifier biased in a direction opposite to that of a programming operation 110 (i.e., a write operation) and a read (i.e., verify) test 130. Accordingly, an input / output (I / O) block will invert (compared to the programming operation 110 and the read (i.e., verify) test 130) true write line signals WGDLT and true write line complement signals WGDLC) during the leakage test 120. In an embodiment, during the leakage test 120, the write data is inverted to bias the sense amplifier to facilitate other data states. In other words, the write data will be used to determine the sense amplifier bias.

[0025] In an embodiment of the present disclosure, a method can include biasing a sense amplifier connected to a twin cell memory array to a known logic state, reading an output of the sense amplifier with a plurality of word lines connected to the twin cell memory array turned off, and detecting a time-dependent dielectric breakdown (TDDB) fault of the twin cell memory in response to the output of the sense amplifier being a logic state opposite to the known logic state. Moreover, the method can further include masking bits of the twin cell memory in response to detecting the TDDB fault and programming the twin cell memory at a predetermined programming interval. Additionally, programming the twin cell memory at a predetermined programming interval occurs before offsetting the sense amplifier to the known logic state. The predetermined programming interval is a time interval of approximately 8 milliseconds. Programming the twin cell memory at a predetermined programming interval also includes applying write pulses to a plurality of gates of the twin cell memory array.

[0026] The method can also include masking bits of the twin cell memory in response to verifying that an output of the twin cell memory array is the same value as an input to the twin cell memory array. Additionally, the twin cell memory array is included in a non-volatile one-time programmable memory (OTPM).

[0027] Figure 2 A current sense amplifier with a bias adjustment in accordance with aspects of the present disclosure is shown. In an embodiment of the present disclosure, a structure can include a twin cell memory array configured to program a plurality of write operations, a current sense amplifier 200 connected to the twin cell memory and configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source connected to the current sense amplifier and configured to add an offset current to the current sense amplifier to generate the differential voltage. The offset current causes a cell bias during programming and also simulates a known programming threshold voltage offset in the cell.

[0028] The twin cell memory includes a first NFET device and a second NFET device. In addition, a current sense amplifier 200 is connected to the twin cell memory array via a true bit line (BLT) and a complementary bit line (BLC). At least one current source is configured to add an offset current to the BLT and BLC to generate a differential voltage.

[0029] The current sense amplifier 200 further includes a latch configured to store the differential voltage. The residue adjustment circuit 300 includes a plurality of transistors and at least one current source. The residue adjustment circuit 300 is connected to the current sense amplifier 200 via a true bit line (BLT) and an interposed bit line (BLC). The plurality of transistors determine the magnitude of the offset current based on a plurality of sense amplifier input residue signals. Finally, the plurality of transistors in the residue adjustment circuit 300 are all NFET devices.

[0030] Specifically, Figure 2 The current sense amplifier 200, the OTPM array 250, and the residue adjustment circuit 300 are shown. As Figure 2 shown, the current sense amplifier 200 includes transistors T101 - T106, a latch, a true bit line (BLT), a complementary bit line (BLC), and a current mirror source voltage VCMN. Transistors T101 - T104 are PFET devices, and T105 - T106 are NFET devices. The current sense amplifier 200 performs current sensing, where the differential bit line current is converted to a voltage and latched as a digital "1" or a digital "0". In an embodiment, the true bit line (BLT) side of a selected cell (e.g., one of OTPM cells 0 to OTPM cells n) may have a field effect transistor (FET) with a higher threshold voltage than the corresponding field effect transistor (FET) on the complementary bit line (BLC) side.

[0031] In Figure 2 , the current sense amplifier 200 includes a transistor T101 having a source connected to a voltage source VIO, a drain connected to the true bit line (BLT), and a gate connected to the drain of transistor T103. Transistor T103 has a source connected to the true bit line (BLT), a drain connected to node A, and a gate connected to the gate of transistor T104. Transistor T102 has a source connected to the voltage source VIO, a gate connected to the gate of transistor T104, and a drain connected to the complementary bit line (BLC). Transistor T104 has a source connected to the complementary bit line (BLC) and a drain connected to node B. In Figure 2 , transistor T105 has a drain connected to node A, a gate connected to the gate of transistor T106, and a source connected to ground. Transistor T106 has a drain connected to node B and a source connected to ground.

[0032] InFigure 2 In it, the OTPM array 250 includes a twin cell array, which includes the gates of transistors T107 and T108 connected to word line WL0. In addition, the source of transistor T107 is connected to the source of transistor T108. The drain of transistor T107 is connected to the true bit line (BLT), and the drain of transistor T108 is connected to the complementary bit line (BLC). In the OTPM array 250, another twin cell array includes the gates of transistors T109 and T110 connected to word line WLn. The source of transistor T109 is connected to the source of transistor T110. The drain of transistor T109 is connected to the true bit line (BLT), and the drain of transistor T110 is connected to the complementary bit line (BLC).

[0033] In Figure 2 it, a small bias current can be applied to the true side of the current sense amplifier 200 (i.e., the side with the true bit line (BLT)) and the complementary side of the current sense amplifier 200 (i.e., the side with the complementary bit line (BLC)) through NFET transistors T105 and T106. Then, the conduction to the selected pair of OTPM cells causes the node BLT to drop and mirror the current from transistor T101 to transistor T102. When the currents entering the true bit line (BLT) and the complementary bit line (BLC) do not match the programmed threshold voltage difference in the OTPM cell, a large voltage difference is generated on the signal of the sense amplifier 200 between nodes A and B. The large voltage difference (i.e., the difference between voltage_A and voltage_B) is then latched by a complementary metal oxide semiconductor (CMOS) latch and converted into a full voltage logic level "1" or "0".

[0034] In Figure 2 it, the OTPM array 250 can be a non-volatile memory including groups of OTPM cells along the true bit line (BLT) and the complementary bit line (BLC). Each OTPM cell contains a pair of field effect transistor (FET) devices (e.g., T107 and T108, T109 and T110) having threshold voltages (Vt) different from each other as a result of programming. For example, the first transistor (e.g., T107 or T109) has a threshold voltage different from that of the second transistor (e.g., T108 or T110). In addition, transistors T107 - T110 can be NFET devices.

[0035] In a further embodiment, the OTPM array 250 may include a set of OTPM elements including OTPM element 0 to OTPM n, where n is an integer value representing the last OTPM element of the OTPM array 250. Each OTPM element is coupled to a word line (e.g., one of word lines WL0 to word line WLn). In an embodiment, a plurality of FET storage elements (e.g., OTPM element 0 to OTPM element n) are arranged as differential transistor pairs (e.g., T107 and T108 or T109 and T110) and share a word line (e.g., word lines WL0 to word line WLn).

[0036] In Figure 2 , the redundancy adjustment circuit 300 includes transistors T111 - T120, true write line signal WGDLT, true write line complementary signal WGDLC, true bit line (BLT), complementary bit line (BLC), sense amplifier redundancy SA_MARG<2:0> (which includes SA_MARG<2>, SA_MARG<1>, and SA_MARG<0>), and current mirror source voltage VCMN. In the redundancy adjustment circuit 300, a group of current sources is formed by transistors T116 - T120 and controlled by the current mirror source voltage VCMN, and connected to a common node. Transistors T111 or T112 are selected by the true write line signal WGDLT and the true write line complementary signal WGDLC to conduct an offset current from the BLT or BLC.

[0037] In Figure 2 , the magnitude of the offset current is selected by transistors T113, T114, and T115 (i.e., current control switches) responsive to SA_MARGIN<2>, SA_MARGIN<1>, and SA_MARGIN<0>. In addition, the binary settings from 0 to 7 are referred to as DAC inputs DAC0 to DAC7. In addition, in Figure 2 's redundancy adjustment circuit 300, one switch enables a current that generates a current offset equivalent to a 10 mV offset of the programming element threshold voltage (Vt), and the other switches generate currents equivalent to 20 mV and 40 mV. By using sequential selection of the DAC inputs, a signal offset in 10 mV increments up to 70 mV can be enabled. In other words, DAC0 is 0 mV (i.e., balance the sense amplifier without skew), DAC1 is 10 mV, DAC2 is 20 mV, DAC3 is 30 mV, DAC4 is 40 mV, DAC5 is 50 mV, DAC6 is 60 mV, and DAC7 is 70 mV. In Figure 2 , DAC1, DAC2, and DAC4 are respectively used to generate threshold voltage offsets of 10 mV, 20 mV, and 40 mV.

[0038] In Figure 2Among them, the transistors T111 - T120 of the redundancy adjustment circuit 300 are all NFET devices. In the redundancy adjustment circuit, the transistor T111 has a drain connected to the true bit line (BLT), a gate connected to the true write line signal WGDLT, and a source connected to the drain of the transistor T113. The transistor T113 has a gate connected to SA_MARGIN<2>, and a source connected to the drain of the transistor T116. The transistor T116 has a gate connected to the current mirror source voltage VCMN and a source connected to the ground. The transistor T114 has a drain connected to the drain of the transistor T113, a gate connected to SA_MARGIN<1>, and a source connected to the drain of the transistor T117. The transistor T117 has a gate connected to the current mirror source voltage VCMN and a source connected to the drain of the transistor T119. The transistor T119 has a gate connected to the current mirror source voltage VCMN and a source connected to the ground.

[0039] In Figure 2 Among them, the transistor T112 has a drain connected to the complementary bit line (BLC), a gate connected to the true write line complementary signal WGDLC, and a source connected to the drain of the transistor T115. The transistor T115 has a gate connected to SA_MARGIN<0> and a source connected to the drain of the transistor T118. The transistor T118 has a gate connected to the current mirror source voltage VCMN and a source connected to the drain of the transistor T120. The transistor T120 has a gate connected to the current mirror source voltage VCMN and a source connected to the ground.

[0040] Figure 3 Shows a current sense amplifier with redundancy adjustment being tested according to aspects of the present disclosure. In Figure 3 Among them, the test circuit 400 includes a plurality of twin cells (i.e., twin cell 0 with corresponding word line <0> to twin cell <n>twin cell element n), current mode sense amplifier 450 (corresponding to sense amplifier 200), true bit line (BLT), complementary bit line (BLC), data readout signal, DAC<2:0> and write signal. The test circuit 400 can perform a leakage test, a tilt test, a sense amplifier test, and a word line test.

[0041] In Figure 3 it, the test circuit 400 can turn off all word lines WL<0> to WL <n>(i.e., no primitive is selected) to perform a leakage test. If the write 0 signal is high and input, the complementary bit line (BLC) goes low and the true bit line (BLT) goes high. In response to the true bit line (BLT) going high, the data is read out as "1" (i.e., the inversion of the write 0 signal). In the leakage test, the test circuit 400 will compensate for the data read out that is inverted from the input signal.

[0042] In Figure 3 , the test circuit 400 can perform a tilt test by performing a read operation combined with sense amplifier tilting (i.e., leaving a margin or skewing) in order to measure primitive mismatch in increments adjusted by the DAC (e.g., equivalent to a 10 mV primitive threshold voltage Vt in this context). The tilt test is performed before programming. In this case, it is desirable that all primitives have an offset less than 70 mV, and thus a "0" or "1" depending on the tilt direction controlled by the written data value should be read. Primitives that do not pass the tilt pass are considered defective and can be repaired with redundancy. In the tilt test, the data read out is also inverted from the input signal (similar to the leakage test inversion). In the sense amplifier test, during the write operation, the input signal (write 1 or write 0) is used to steal the signal from the primitive until the write overcomes the offset. Additionally, in the sense amplifier test, during the read operation, the input signal (write 1 or write 0) will cause the read to have a margin, and the data read out must match the input signal used to write to that address (i.e., the input signal matches the output signal without inversion).

[0043] In Figure 3 , during the word line test and write operation, the input signal is used to steal the signal from the primitive until the write overcomes the offset. Additionally, in the word line test and read operation, the input signal will cause the read to have a margin, and the data read out must match the input signal used to write to that address (i.e., the input signal must match the output signal without inversion). Additionally, as Figure 3 shown, by leaving a margin sense amplifier and tilting the sense amplifier by pulling current from the true bit line (BLT) or the complementary bit line (BLC) to facilitate a "1" or "0", the embodiment can determine whether there is a TDDB failure.

[0044] Figure 4 shows a method of a programming operation according to an additional aspect of the present disclosure. In Figure 4 , the flowchart 500 shows a method of a programming operation according to an embodiment of the present disclosure. In Figure 4 In this method, it starts at step 505. Then, at step 510, the write count is set to "j" and "k" is set to zero. At step 515, the programming cycle "k" is executed. At step 520, the write data is inverted and a leakage test is performed (i.e., reading without activating the word line). At step 525, if the leakage test fails, then at step 530, the write is masked by forcing the write line low. After step 530, the method proceeds to step 535.

[0045] If the leakage test passes at step 525, the method enters step 535. In step 535, the data is restored to the normal state and then a verification test is performed (i.e., reading with the activated word line). At step 540, the data output is compared with the data input. If the data output equals the data input at step 540, then at step 545, the write is masked by forcing the write line low. After step 545, the method proceeds to step 550.

[0046] If the data output does not equal the data input at step 540, the method enters step 550. At step 550, "k" is incremented by 1. Then, at step 555, "k" is compared with "j". If "k" (i.e., the programming cycle) equals "j" (i.e., the total number of writes), then programming is completed at step 560 and the method ends at step 565. However, if "k" does not equal "j", the method returns to step 515 to execute the programming cycle "k", and the method repeats from step 515 to step 555.

[0047] Figure 5 Shows a true / complementary view of the programming operation according to an additional aspect of the present disclosure. For example, Figure 5 Shows a true / complementary view 600 of the programming operation. The true / complementary view 600 includes FIGS. 610, 620, 630, 640, 650, and 660. FIGS. 610 - 660 have the threshold voltage Vt on the x-axis and the number of instances of the threshold voltage Vt (i.e., the sample size) on the y-axis.

[0048] In FIG. 610, before programming, many twin cells in the OTPM array do not match, and the number of instances is the largest near the midpoint of the threshold voltage (Vt). After early programming, as shown by curve 620, some threshold voltages (Vt) increase in both directions, such that the midpoint of the threshold voltage (Vt) has a smaller number and the outer portions away from the midpoint have a larger number of instances. After further programming, at FIG. 630, since the values representing "1" or "0" have been reached, there are several twin cells (shown in darker shading) that no longer require programming (i.e., write operations).

[0049] In FIG. 640, programming continues and more twin cells (shown in darker shading) no longer need to be programmed. In FIG. 650, most of the twin cells (shown in shaded tones) no longer need to be programmed, and some twin cells still need to be programmed. Additionally, in FIG. 660, all twin cells have been programmed and they no longer need to be programmed. As shown at FIG. 660, the threshold voltage (Vt) has been shifted from the midpoint towards the left (representing "1") or the right (representing "0").

[0050] As should now be understood, in embodiments of the present disclosure, a bit line leakage test can be incorporated in each "write-verify" cycle such that programmed transistors are tested for time-dependent dielectric breakdown (TDDB) faults. If a cell suffers a TDDB fault (word line WL to bit line BL short), the cell is masked from future programming to allow other cells in parallel to be programmed at an optimal word line voltage.

[0051] The circuits and methods of the present disclosure for detecting time-dependent dielectric breakdown (TDDB) shorts and signal retention testing for non-volatile memory arrays can be fabricated in many different ways using many different tools. Generally, methods and tools are used to form structures on the micron and nanometer scale. Methods (i.e., techniques) for fabrication have been adopted from integrated circuit (IC) technology for the circuits and methods of the present disclosure for detecting time-dependent dielectric breakdown (TDDB) shorts and signal retention testing for non-volatile memory arrays. For example, these structures are built on a wafer and realized by a film of material patterned by a lithography process on top of the wafer. In particular, the fabrication of the circuits and the methods for detecting time-dependent dielectric breakdown (TDDB) shorts and signal retention testing for non-volatile memory arrays use three basic building blocks: (i) depositing a thin film of material on a substrate, (ii) applying a patterned mask on top of the film by lithographic imaging, and (iii) selectively etching the film to the mask.

[0052] The methods as described above are used for the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of the original wafer (i.e., as a single wafer with multiple unpackaged chips) as a bare chip or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier where leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier which has either or both surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be a product including the integrated circuit chip, ranging from toys and other low-end applications to high-end computer products with a display, a keyboard, or other input devices and a central processor.

[0053] The description of the various embodiments of the present disclosure has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen to best explain the principles of the embodiments, the practical application or technical improvement of technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.< / n> < / n>

Claims

1. A structure for detecting a twin cell memory, comprising: A twin cell memory configured to program multiple write operations; A current sense amplifier connected to the twin cell memory and configured to sense a current differential and latch a differential voltage based on the current differential; And At least one current source connected to the current sense amplifier and configured to add an offset current to the current differential to generate the differential voltage.

2. The structure according to claim 1, wherein the twin cell memory includes a first NFET device and a second NFET device.

3. The structure according to claim 2, wherein the current sense amplifier is connected to the twin cell memory array through a true bit line and a complementary bit line.

4. The structure according to claim 3, wherein the at least one current source is configured to add the offset current to the true bit line and the complementary bit line of the current sense amplifier to generate the differential voltage.

5. The structure according to claim 1, wherein the current sense amplifier includes a latch configured to store the differential voltage.

6. The structure according to claim 1, further comprising a redundancy adjustment circuit, which includes a plurality of transistors and the at least one current source, and the redundancy adjustment circuit is connected to the current sense amplifier through a true bit line and a complementary bit line.

7. The structure according to claim 6, wherein the plurality of transistors determine the amplitude of the offset current based on a plurality of sense amplifier input redundancy signals.

8. The structure according to claim 7, wherein the plurality of transistors in the redundancy adjustment circuit are all NFET devices.

9. A method for detecting a twin cell memory, comprising: Offsetting a sense amplifier connected to a twin cell memory array to a known logic state; Reading the output of the sense amplifier with a plurality of word lines connected to the twin cell memory array turned off; Detecting a time-dependent dielectric breakdown fault of the twin cell memory in response to the output of the sense amplifier being a logic state opposite to the known logic state; And Masking the bits of the twin cell memory in response to detecting the time-dependent dielectric breakdown fault.

10. The method according to claim 9, further comprising programming the twin cell memory at a predetermined programming interval.

11. The method according to claim 10, wherein, Programming the twin cell memory at the predetermined programming interval before offsetting the sense amplifier to the known logic state.

12. The method according to claim 10, wherein the predetermined programming interval is a time interval less than 8 milliseconds.

13. The method according to claim 10, wherein programming the twin cell memory at the predetermined programming interval further includes applying a write pulse to a plurality of gates of the twin cell memory array.

14. The method according to claim 10, further comprising: In response to not detecting the time-dependent dielectric breakdown fault, verifying that the output of the twin cell memory array is the same value as the input of the twin cell memory array.

15. The method according to claim 14, further comprising masking bits of the twin cell memory in response to verifying that the output of the twin cell memory array is the same value as the input of the twin cell memory array.

16. The method according to claim 9, wherein the twin cell memory array is included in a non-volatile one-time programmable memory.

17. A method for detecting a twin cell memory, comprising: Programming the twin cell memory at a predetermined programming interval; Offsetting a sense amplifier connected to the twin cell memory to a known logic state; Reading an output of the sense amplifier with a plurality of word lines connected to the twin cell memory array turned off; Detecting a time-dependent dielectric breakdown fault of the twin cell memory array in response to the output of the sense amplifier being a logic state opposite to the known logic state; And Masking bits of the twin cell memory in response to detecting the time-dependent dielectric breakdown fault.

18. The method according to claim 17 further comprises: In response to not detecting the time-dependent dielectric breakdown fault, verifying that the output of the twin cell memory array is the same value as the input of the twin cell memory array, and masking bits of the twin cell memory array in response to verifying that the output of the twin cell memory array is the same value as the input of the twin cell memory array.

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