Multi-chip packaging structure with a cavity for accommodating filter chips and manufacturing method thereof

Abstract

The present invention discloses a multi-chip packaging structure with a cavity for accommodating a filter chip and a manufacturing method thereof, wherein the packaging structure comprises: a packaging substrate having a cavity; a filter chip arranged in the cavity, wherein the first upper surface and the upper surface of the substrate are located on the same side, and the first upper surface has a plurality of first electrodes; a functional chip arranged above the packaging substrate, wherein the second lower surface and the upper surface of the substrate are arranged face to face, and the second lower surface has a plurality of second electrodes; and a plurality of interconnect structures for conducting the plurality of first electrodes and the plurality of second electrodes. The present invention utilizes packaging technology to package two different chips in the same packaging substrate, thereby realizing a high degree of integration of multiple chips; the filter chip and the functional chip are distributed up and down, and the functional chip located above the packaging substrate does not occupy the space of the packaging substrate, thereby further improving the utilization rate of the packaging substrate and simplifying the interconnect structure; the filter chip is embedded in the cavity, thereby making the packaging structure thinner and lighter.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a multi-chip packaging structure with a cavity for accommodating a filter chip and a manufacturing method thereof. Background Art

[0002] To cater to the development trend of increasingly thin and light electronic products, filters, RF transmitting components and receiving components need to be highly integrated in a packaging structure with limited area to form a system-in-package (SIP) structure to reduce the size of the hardware system.

[0003] Regarding the packaging integration technology of filters and RF front-end modules in the system-level packaging structure, there are still many technical problems in the industry that need to be solved urgently, such as the protection structure of the filter, the connection structure between multiple chips, the layout of multiple chips, etc. Summary of the invention

[0004] The object of the present invention is to provide a multi-chip packaging structure with a cavity for accommodating a filter chip and a manufacturing method thereof.

[0005] To achieve one of the above-mentioned purposes of the invention, an embodiment of the present invention provides a multi-chip packaging structure with a cavity for accommodating a filter chip, comprising:

[0006] A packaging substrate, comprising an upper substrate surface and a lower substrate surface which are arranged opposite to each other, wherein the packaging substrate has a cavity;

[0007] A filter chip is disposed in the chamber, wherein the filter chip has a first upper surface and a first lower surface that are disposed opposite to each other, the first upper surface and the upper surface of the substrate are located on the same side, and the first upper surface has a plurality of first electrodes;

[0008] A functional chip is disposed above the packaging substrate, the functional chip has a second upper surface and a second lower surface that are disposed opposite to each other, the second lower surface is disposed face to face with the upper surface of the substrate, and the second lower surface has a plurality of second electrodes;

[0009] A plurality of interconnection structures are used to conduct a plurality of first electrodes and a plurality of second electrodes.

[0010] As a further improvement of an embodiment of the present invention, the functional chip is located above the chamber, and a plurality of first electrodes and a plurality of second electrodes are arranged face to face.

[0011] As a further improvement of one embodiment of the present invention, one side of the lower surface of the substrate has a plurality of external pins, the packaging substrate has a plurality of through holes, and the interconnection structure conducts the first electrode, the second electrode and the external pins through the through holes.

[0012] As a further improvement of an embodiment of the present invention, the through hole and the second electrode are spaced apart from each other.

[0013] As a further improvement of one embodiment of the present invention, the interconnection structure includes a metal column, solder and an electroplating layer structure, the metal column is connected to the bottom of the second electrode, the electroplating layer structure conducts the first electrode, and the electroplating layer structure extends through the through hole to the bottom of the packaging substrate to conduct the external pin, and the solder is used to conduct the metal column and the electroplating layer structure.

[0014] As a further improvement of one embodiment of the present invention, the electroplating layer structure includes an upper redistribution layer, an intermediate wiring layer and a lower redistribution layer that are electrically connected to each other, the upper redistribution layer is located above the packaging substrate and is conductive to the first electrode, the lower redistribution layer is located below the packaging substrate and is conductive to the external pin, the intermediate wiring layer includes a first electroplating layer located on the upper surface of the substrate, a second electroplating layer located on the inner wall of the through hole, and a third electroplating layer located on the lower surface of the substrate, the first electroplating layer is connected to the upper redistribution layer, and the third electroplating layer is connected to the lower redistribution layer.

[0015] As a further improvement of one embodiment of the present invention, the multi-chip packaging structure includes a first insulating layer located on the upper surface of the substrate, above the first upper surface, an upper rewiring layer that conducts the first electroplating layer and the first electrode through holes on the first insulating layer, and a second insulating layer connecting the first insulating layer and the second lower surface, the second insulating layer having a groove that exposes the upper rewiring layer and accommodates solder.

[0016] As a further improvement of an embodiment of the present invention, the first insulating layer and the second insulating layer cooperate to form a cofferdam, and the cofferdam cooperates with the second lower surface and the first upper surface to enclose and form a cavity.

[0017] As a further improvement of one embodiment of the present invention, the cofferdam includes a first cofferdam located inside the first electrodes and a second cofferdam located outside the first electrodes, and the first cofferdam cooperates with the second lower surface and the first upper surface to form a cavity.

[0018] As a further improvement of an embodiment of the present invention, the second cofferdam extends in a direction away from the first cofferdam until an outer edge of the second cofferdam is flush with an outer edge of the packaging substrate, and the second cofferdam exposes the through hole.

[0019] As a further improvement of one embodiment of the present invention, the multi-chip packaging structure also includes a first plastic packaging layer located on the side of the packaging substrate away from the lower surface of the substrate, the first plastic packaging layer simultaneously covers the exposed upper surface area of ​​the second cofferdam and the functional chip, and the first plastic packaging layer fills the through hole.

[0020] As a further improvement of one embodiment of the present invention, the multi-chip packaging structure includes a third insulating layer covering the third electroplating layer and the lower surface of the substrate, a lower redistribution layer that conducts the third electroplating layer through holes on the third insulating layer and extends toward the lower surface of the third insulating layer, and a fourth insulating layer covering the third insulating layer and the lower redistribution layer, the external pins are connected to the lower redistribution layer, and the fourth insulating layer exposes the external pins.

[0021] As a further improvement of one embodiment of the present invention, a second plastic packaging layer is provided on the gap between the filter chip and the cavity, the lower surface of the substrate and the first lower surface, and the first upper surface is flush with the upper surface of the substrate.

[0022] To achieve one of the above-mentioned purposes of the invention, an embodiment of the present invention provides a method for manufacturing a multi-chip package structure with a cavity for accommodating a filter chip, comprising the steps of:

[0023] S1: providing a packaging substrate, which has a substrate upper surface and a substrate lower surface arranged opposite to each other;

[0024] S2: forming a cavity on the packaging substrate;

[0025] S3: providing a filter chip, wherein the filter chip has a first upper surface and a first lower surface arranged opposite to each other, and the first upper surface has a plurality of first electrodes;

[0026] S4: loading the filter chip into the chamber, with the first upper surface and the upper surface of the substrate being located on the same side;

[0027] S5: forming a first interconnection structure on the packaging substrate, wherein the first interconnection structure is connected to the first electrode;

[0028] S6: providing a functional chip, wherein the functional chip has a second upper surface and a second lower surface that are oppositely arranged, and the second lower surface has a plurality of second electrodes;

[0029] S7: loading the functional chip on the top of the packaging substrate, disposing the second lower surface face to face with the upper surface of the substrate, and forming a second interconnection structure connecting the second electrode and the first interconnection structure;

[0030] S8: forming a third interconnection structure connecting the external pins and the first interconnection structure.

[0031] As a further improvement of an embodiment of the present invention, step S4 specifically includes:

[0032] Providing a temporary bonding plate;

[0033] Laminating the upper surface of the package substrate to a temporary laminating plate;

[0034] Loading the filter chip into the chamber, with the first upper surface and the upper surface of the substrate located on the same side;

[0035] forming a second plastic packaging layer covering the gap between the filter chip and the chamber, the lower surface of the substrate and the first lower surface;

[0036] removing the temporary bonding plate;

[0037] inverting the packaging substrate;

[0038] Forming a plurality of through holes on the packaging substrate, wherein the through holes penetrate the second plastic packaging layer;

[0039] Step S5 specifically includes:

[0040] Forming a first electroplating layer on the upper surface of the substrate, forming a second electroplating layer on the inner wall of the through hole, and forming a third electroplating layer below the second plastic sealing layer;

[0041] Arranging a first insulating layer on the upper surface of the substrate;

[0042] Forming an upper rewiring layer above the first insulating layer, which is connected to the first electrode and the first electroplating layer through holes in the first insulating layer;

[0043] A second insulating layer is arranged above the first insulating layer and the upper rewiring layer, the first insulating layer and the second insulating layer cooperate to form a cofferdam, the cofferdam includes a first cofferdam and a second cofferdam, the first cofferdam is located at the periphery of the cavity, the outer edge of the second cofferdam is flush with the outer edge of the packaging substrate, the second cofferdam exposes the through hole, and the cofferdam has a groove exposing the upper rewiring layer;

[0044] Steps S7 and S8 specifically include:

[0045] forming a metal column on the lower surface of the second electrode;

[0046] Setting solder in the slot;

[0047] The functional chip is mounted on the packaging substrate, the second lower surface is arranged face to face with the upper surface of the substrate, the first cofferdam cooperates with the second lower surface and the first upper surface to enclose and form a cavity, the metal column is aligned with the groove, and the solder is connected to the metal column;

[0048] Forming a first plastic encapsulation layer on a side of the packaging substrate away from the lower surface of the substrate, wherein the first plastic encapsulation layer simultaneously covers the upper surface area of ​​the second cofferdam exposed to the outside and the functional chip, and the first plastic encapsulation layer fills the through hole;

[0049] forming a third insulating layer below the third electroplating layer and the second plastic sealing layer;

[0050] Forming a lower redistribution layer below the third insulating layer, which is connected to the third electroplating layer through holes on the third insulating layer;

[0051] forming a fourth insulating layer covering the third insulating layer and the lower redistribution layer, wherein the fourth insulating layer exposes the lower redistribution layer;

[0052] A ball grid array is formed on the exposed lower redistribution layer.

[0053] Compared with the prior art, the beneficial effects of the present invention are as follows: one embodiment of the present invention utilizes packaging technology to package two different chips in the same packaging substrate, which can achieve high integration of multiple chips, improve the utilization rate of the packaging substrate, and further achieve miniaturization of the multi-chip packaging structure; in addition, the filter chip and the functional chip are distributed up and down, and the functional chip located above the packaging substrate does not occupy the space of the packaging substrate, which can further improve the utilization rate of the packaging substrate, and the spacing between the filter chip and the functional chip becomes smaller, which facilitates the interconnection between the filter chip and the functional chip and simplifies the interconnection structure; moreover, the filter chip is embedded in the cavity, making the multi-chip packaging structure lighter and thinner. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 It is a radio frequency front-end module of an example of the present invention;

[0055] Figure 2 is another example of a radio frequency front-end module of the present invention;

[0056] Figure 3 is a cross-sectional view of a multi-chip package structure according to an embodiment of the present invention;

[0057] Figure 4 is a schematic diagram of a cofferdam, a through hole and a first electrode according to an embodiment of the present invention;

[0058] Figure 5is a step diagram of a method for manufacturing a multi-chip packaging structure according to an embodiment of the present invention;

[0059] Figure 6a to Figure 6z-13 It is a flow chart of a method for manufacturing a multi-chip package structure according to one embodiment of the present invention. DETAILED DESCRIPTION

[0060] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0061] In various drawings of the present application, for the convenience of illustration, some sizes of structures or parts are exaggerated relative to other structures or parts, and thus, are only used to illustrate the basic structure of the subject matter of the present application.

[0062] In addition, terms such as "upper", "above", "lower", "below", etc. used herein to indicate spatial relative positions are used for the purpose of convenience to describe the relationship of one unit or feature relative to another unit or feature as shown in the accompanying drawings. Terms of spatial relative position may be intended to include different orientations of the device in use or operation other than the orientation shown in the drawings. For example, if the device in the figure is turned over, the units described as being "below" or "beneath" other units or features will be located "above" the other units or features. Therefore, the exemplary term "below" can encompass both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatially related descriptors used herein interpreted accordingly.

[0063] Ginseng Figure 1 and Figure 2 An embodiment of the present invention provides a universal radio frequency front-end module, which can be used in mobile devices such as mobile phones, computers, or other electronic devices.

[0064] Combination Figure 1 In one example, the RF front-end module includes a power amplifier module 200 (Power Amplifier Module, PAM), and the power amplifier module 200 includes a first amplifier unit 201, a first RF switch unit 202 and a first RF filter unit 203 electrically connected in sequence, and the first amplifier unit 201 is a multi-mode-wide bandwidth power amplifier unit.

[0065] In actual operation, the first amplifier unit 201 is used to receive the modulated signal output by other components, and after being modulated, amplified and filtered by the power amplifier module 200 , the modulated signal is output by the filter unit 203 .

[0066] Combination Figure 2 In another example, the RF front-end module includes a receive diversity module 300 (Receive Diversity Module, RDM), and the receive diversity module 300 includes a low noise amplifier multiplexer 301 (LNA Multiplexer Module, LMM), a second RF filter unit 302 and an RF antenna switch unit 303 electrically connected in sequence, wherein the low noise amplifier multiplexer 301 includes an electrically connected second amplifier unit 3011 and a second RF switch unit 3012, the second amplifier unit 3011 is a multi-mode-wide bandwidth low noise amplifier unit, and the two ends of the second RF switch unit 3012 are respectively connected to the second amplifier unit 3011 and the second RF filter unit 302.

[0067] In actual operation, the signal is divided into a high-frequency signal and a low-frequency signal through the antenna duplexer 304. Here, taking the high-frequency signal as an example, the high-frequency signal enters the RF antenna switch unit 303, and then passes through the filtering, modulation, and amplification operations of the second RF filter unit 302 and the low-noise amplifier multiplexer 301 in sequence, and is output by the second amplifier unit 3011.

[0068] It can be understood that the electrical connection between the above-mentioned RF switch unit, filter unit, amplifier unit and other units can be achieved through a packaging process, that is, the RF switch chip, amplifier chip, filter chip and the like are packaged together to achieve various functions.

[0069] This embodiment is described by taking the packaging structure and process of an RF switch chip, an amplifier chip, and a filter chip as examples.

[0070] Ginseng Figure 3 , is a cross-sectional view of a multi-chip package structure 100 with a cavity for accommodating a filter chip according to an embodiment of the present invention.

[0071] The multi-chip package structure 100 includes a package substrate 10 , a filter chip 20 , a functional chip 30 and a plurality of interconnect structures 50 .

[0072] The packaging substrate 10 has a substrate upper surface 11 and a substrate lower surface 12 which are oppositely disposed, and the packaging substrate 10 has a cavity 101 .

[0073] Here, the packaging substrate 10 is a carrier board for carrying the chip. The packaging substrate 10 may be a printed circuit board made of organic resin, or a glass substrate, a ceramic substrate, or the like.

[0074] The chamber 101 may be a through hole penetrating the packaging substrate 10 , but is not limited thereto.

[0075] The filter chip 20 is disposed in the chamber 101 . The filter chip 20 has a first upper surface 21 and a first lower surface 22 that are oppositely disposed. The first upper surface 21 and the substrate upper surface 11 are located on the same side, and the first upper surface 21 has a plurality of first electrodes 211 .

[0076] The first electrode 211 protrudes out of the first upper surface 21 in a direction away from the first lower surface 22 , but the present invention is not limited thereto.

[0077] The filter chip 20 can be a surface acoustic wave filter chip (SAW) or a bulk acoustic wave filter chip (BAW), but is not limited to this. The active area (Active Zone) on the surface of the filter chip 20 needs to be free from contact or coverage by foreign objects in order to work normally. In other words, a cavity needs to be formed under the filter chip 20 to protect the active area.

[0078] The function chip 30 is disposed above the packaging substrate 10 . The function chip 30 has a second upper surface 31 and a second lower surface 32 that are oppositely disposed. The second lower surface 32 is disposed face to face with the substrate upper surface 11 , and has a plurality of second electrodes 321 .

[0079] The second electrode 321 protrudes out of the second lower surface 32 in a direction away from the second surface 31 , but the present invention is not limited thereto.

[0080] The function chip 30 is an amplifier chip or an RF switch chip, but is not limited thereto.

[0081] The interconnection structures 50 are used to conduct the first electrodes 211 and the second electrodes 321 .

[0082] Here, “a plurality of interconnection structures 50 for conducting a plurality of first electrodes 211 and a plurality of second electrodes 321 ” refers to electrical connection between the first electrodes 211 and the second electrodes 321 , that is, interconnection between the filter chip 20 and the functional chip 30 is realized.

[0083] This embodiment utilizes packaging technology to package two different chips (filter chip 20 and functional chip 30) into the same packaging substrate 10, which can achieve high integration of multiple chips, improve the utilization rate of the packaging substrate 10, and further realize the miniaturization of the multi-chip packaging structure 100.

[0084] In addition, the filter chip 20 and the functional chip 30 are distributed up and down. The functional chip 30 located above the packaging substrate 10 does not occupy the space of the packaging substrate 10, which can further improve the utilization rate of the packaging substrate 10. The spacing between the filter chip 20 and the functional chip 30 becomes smaller, which facilitates the interconnection between the filter chip 20 and the functional chip 30 and simplifies the interconnection structure.

[0085] Furthermore, the filter chip 20 is embedded in the cavity 101 , making the multi-chip packaging structure 100 thinner and lighter.

[0086] It should be noted that the multi-chip packaging structure 100 of this embodiment takes a filter chip 20 and a functional chip 30 mounted on a packaging substrate 10 as an example. It can be understood that in actual use, reference Figure 1 and Figure 2 , may include multiple filter chips 20 and multiple functional chips 30. For example, multiple functional chips 30 may be electrically connected around the filter chip 20 (including three-dimensional directions of up, down, front, back, left, and right).

[0087] In this embodiment, the functional chip 30 is located above the chamber 101 , and a plurality of first electrodes 211 and a plurality of second electrodes 321 are disposed face to face.

[0088] That is to say, the filter chip 20 and the functional chip 30 are arranged correspondingly in the upper and lower directions, and the first electrode 211 and the second electrode 321 are also arranged face to face. In this way, in the horizontal direction, the setting of the filter chip 20 will not occupy too much horizontal space of the packaging substrate 10, and the size of the packaging substrate 10 can be made small.

[0089] Here, the size of the function chip 30 is larger than that of the filter chip 20 , and the function chip 30 covers the upper area of ​​the cavity 101 .

[0090] That is to say, the vertical projection of the outer contour of the functional chip 30 on the packaging substrate 10 completely covers the cavity 101 .

[0091] In this embodiment, one side of the package substrate 10 has a plurality of external pins 121 , and the interconnection structure 50 is used to conduct the first electrode 211 , the second electrode 321 and the external pins 121 .

[0092] The external pins 121 may be a ball grid array (BGA), a pad, etc. The multi-chip packaging structure 100 may be electrically connected to other chips or substrates through the external pins 121. Here, the external pins 121 take the ball grid array 121 as an example, and the external pins 121 protrude from the bottom surface of the multi-chip packaging structure 100.

[0093] In addition, here, it is taken as an example that a plurality of external pins 121 are located on one side of the lower surface 12 of the substrate, but the present invention is not limited thereto, and the external pins 121 may also be located in other areas.

[0094] The package substrate 10 has a plurality of through holes 13 , and the interconnection structure 50 conducts the first electrode 211 , the second electrode 321 and the external pin 121 through the through holes 13 .

[0095] In this embodiment, the through holes 13 and the second electrodes 321 are spaced apart from each other.

[0096] Here, the through hole 13 is located on the outside of the second electrode 321, and the through hole 13 is located on the outside of the chamber 101. At this time, the external pins 121 located on one side of the lower surface 12 of the substrate can be moved outward on both sides of the functional chip 30, which is convenient for arranging the space for burying other chips in advance, thereby facilitating the realization of high-performance and small-size multi-chip 2.5D or 3D stacked integrated packaging and modules.

[0097] In this embodiment, the interconnection structure 50 includes a metal pillar 51 , a solder 52 and an electroplating layer structure 53 .

[0098] The metal column 51 is connected to the bottom of the second electrode 321 , the electroplating layer structure 53 is connected to the first electrode 211 , and the electroplating layer structure 53 extends to the bottom of the package substrate 10 through the through hole 13 to connect to the external pin 121 , and the solder 52 is used to connect the metal column 51 and the electroplating layer structure 53 .

[0099] Specifically, the electroplating layer structure 53 includes an upper redistribution layer 531 , an intermediate wiring layer 532 , and a lower redistribution layer 533 that are interconnected.

[0100] The upper redistribution layer 531 is located above the package substrate 10 and is connected to the first electrode 211 .

[0101] The middle wiring layer 532 includes a first electroplating layer 5321 located on the upper surface 11 of the substrate, a second electroplating layer 5322 located on the inner wall of the through hole 13 , and a third electroplating layer 5323 located on the lower surface 12 of the substrate.

[0102] The first electroplating layer 5321 is connected to the upper redistribution layer 531 .

[0103] The width of the first electroplating layer 5321 connected to the upper redistribution layer 531 extending to the upper surface 11 of the substrate is substantially equal to the width of the corresponding third electroplating layer 5323 extending to the lower surface 12 of the substrate.

[0104] Here, on the one hand, both the upper surface 11 and the lower surface 12 of the substrate are provided with electroplating layers, which can improve the reliability of the combination of the electroplating layer and the packaging substrate 10; on the other hand, the first electroplating layer 5321 extends toward the first electrode 211, which is convenient for the upper rewiring layer 531 to connect to the first electroplating layer 5321, and because the solder 52 does not enter the through hole 13 at this time, the through hole 13 can move outward on both sides, thereby allowing the external pin 121 of the lower surface 12 of the substrate to move outward.

[0105] The lower redistribution layer 533 is located below the package substrate 10 and is connected to the external pins 121 , and the lower redistribution layer 533 is connected to the third electroplating layer 5323 .

[0106] Here, the multi-chip packaging structure 100 includes a first insulating layer 70 located above the upper surface 11 of the substrate and the first upper surface 21, an upper rewiring layer 531 that conducts the first electroplating layer 5321 and the first electrode 211 through holes on the first insulating layer 70, and a second insulating layer 71 connecting the first insulating layer 70 and the second lower surface 32. The second insulating layer 71 has a groove 43 that exposes the upper rewiring layer 531 and accommodates the solder 52, and the groove 43 is arranged corresponding to the second electrode 321.

[0107] The multi-chip packaging structure 100 includes a third insulating layer 72 covering the third electroplating layer 5323 and the lower surface 12 of the substrate, a lower redistribution layer 533 that conducts the third electroplating layer 5323 through holes on the third insulating layer 72 and extends toward the lower surface of the third insulating layer 72, and a fourth insulating layer 73 covering the third insulating layer 72 and the lower redistribution layer 533, the external pin 121 is connected to the lower redistribution layer 533, and the fourth insulating layer 73 exposes the external pin 121.

[0108] The provision of the lower redistribution layer 533 can not only expand the redistribution range and improve the degree of freedom of subsequent external pin 121 layout, but also further assist the external pin 121 to move outward.

[0109] The metal pillar 51 is a copper pillar, and the upper redistribution layer 531 , the middle redistribution layer 532 and the lower redistribution layer 533 are all copper layers.

[0110] This embodiment adopts a simple redistribution layout (RDL) solution to achieve electrical connection between the first electrode 211, the second electrode 321 and the external pin 121, and the process is stable and the reliability is high.

[0111] The metal wire material for the rewiring is copper (i.e., the upper rewiring layer 531, the middle wiring layer 532 and the lower rewiring layer 533 are all copper layers). A metal or alloy film that enhances the mutual adhesion between the rewiring copper and the chip electrodes (including the first electrode 211 and the second electrode 321) can be arranged between the rewiring copper and the chip electrodes. The metal or alloy material can be nickel, titanium, nickel-chromium, titanium tungsten, etc.

[0112] A first insulating layer 70 , a second insulating layer 71 and a third insulating layer 72 are sandwiched between the package substrate 10 , the upper redistribution layer 531 and the lower redistribution layer 533 , so as to achieve electrical isolation between the various components.

[0113] It can be understood that the upper rewiring layer 531 in the rewiring scheme is not limited to the above-mentioned layer, and the lower rewiring layer 533 is not limited to the above-mentioned layer, and can be determined according to actual conditions.

[0114] In addition, the advantages of setting the metal pillar 51 and the solder 52 in this embodiment are: (1) the solder 52 is in a molten state during the reflow soldering process, which is convenient for combining with the metal pillar 51, and the combining effect is better; (2) the contact area between the solder 52 and the upper rewiring layer 531 is large, which can improve the electrical transmission performance and also improve the reliability of the combination of the solder 52 and the upper rewiring layer 531; (3) the metal pillar 51 has already occupied a part of the space. At this time, when the solder 52 is set, the amount of raw materials used in the solder 52 can be reduced, the difficulty of the solder 52 welding process is reduced, the welding time is shortened, and the welding capacity is improved; (4) the metal pillar 51 has a significant appearance and can be used as an identification part to improve the recognition efficiency, thereby facilitating automated appearance inspection and possible defect recognition.

[0115] In this embodiment, the first insulating layer 70 and the second insulating layer 71 cooperate to form a dam 40 , and the dam 40 cooperates with the second lower surface 32 and the first upper surface 21 to enclose a cavity S corresponding to the active area on the surface of the filter chip 20 .

[0116] In this embodiment, the cofferdam 40 is provided to form the cavity S, which can effectively prevent foreign matter from entering the cavity S during the manufacturing process of the packaging structure or during the use of the packaging structure and affecting the normal use of the filter chip 20, thereby improving the overall performance of the multi-chip packaging structure 100.

[0117] In this embodiment, the cavity S is located inside the plurality of first electrodes 211 .

[0118] The cofferdam 40 includes a first cofferdam 41 located inside the first electrodes 211 and a second cofferdam 42 located outside the first electrodes 211 . The first cofferdam 41 cooperates with the second lower surface 32 and the first upper surface 21 to enclose a cavity S.

[0119] Here, the first cofferdam 41 is located inside the through hole 13 , and the second cofferdam 42 is partially located inside the through hole 13 and partially located outside the through hole 13 .

[0120] Since the cofferdam 40 has a certain height, when the lower surface area of ​​the cofferdam 40 is too small, it may be unable to support the cofferdam 40 of this height, thereby causing the cofferdam 40 to collapse. The cofferdam 40 of this embodiment includes a first cofferdam 41 and a second cofferdam 42. The cofferdam 40 has a sufficiently large lower surface, which improves the stability of the entire cofferdam 40; in addition, the lower surface of the cofferdam 40 can be combined with the entire area of ​​the upper surface of the filter chip 20 outside the cavity S area on the upper surface of the filter chip 20, further improving the molding stability of the cavity S.

[0121] Combination Figure 4 A plurality of through holes 13 are distributed in an array on the upper surface 11 of the substrate, and there is a gap between adjacent through holes 13. There is a space between two rows of through holes 13. The chamber 101 is located in the space, and there is a gap between the chamber 101 and the through hole 13. The first cofferdam 41 corresponds to the internal area of ​​the chamber 101, and the first cofferdam 41 is actually located on the inner side of the first electrode 211. The second cofferdam 42 extends from the internal area corresponding to the chamber 101 toward the through hole 13, and the groove 43 is located above the cofferdam 40.

[0122] In addition, the second cofferdam 42 extends in a direction away from the first cofferdam 41 until the outer edge of the second cofferdam 42 is flush with the outer edge of the package substrate 10 , and the second cofferdam 42 exposes the through hole 13 .

[0123] Of course, since the packaging substrate 10 is a quadrilateral structure, the outer edge also includes the front side edge and the rear side edge of the packaging substrate 10, and the second cofferdam 42 will also extend to the front side edge and the rear side edge, but it is not limited to this, and the packaging substrate 10 can also be a structure of other shapes.

[0124] It should be noted that the first cofferdam 41 and the second cofferdam 42 can be independent of each other. For example, the first cofferdam 41 is a first annular structure located on the inner side of the first electrodes 211 , and the second cofferdam 42 is a second annular structure located on the outer side of the first electrodes 211 .

[0125] Of course, the first cofferdam 41 and the second cofferdam 42 may also be interconnected. In this case, the first cofferdam 41 and the second cofferdam 42 are interconnected through the third cofferdam 45. The third cofferdam 45 is located between adjacent through holes 13, adjacent first electrodes 211, adjacent second electrodes 321 or other areas. That is to say, the cofferdam 40 at this time covers all other areas above the upper surface 11 of the substrate and the first upper surface 21 except the cavity S and the through hole 13 area.

[0126] In this embodiment, the second lower surface 32 of the functional chip 30 covers the upper surface of the first cofferdam 41, and the second lower surface 32 partially overlaps with the upper surface of the second cofferdam 42, and the first upper surface 21 and the substrate upper surface 11 together cover the lower surface of the first cofferdam 41 and the lower surface of the second cofferdam 42.

[0127] The cofferdam 40 is made of a light-sensitive insulating material, but is not limited thereto.

[0128] In this embodiment, the multi-chip package structure 100 further includes a first plastic encapsulation layer 60 that simultaneously covers the exposed upper surface area of ​​the second cofferdam 42 and the functional chip 30 , and the first plastic encapsulation layer 60 fills the through hole 13 .

[0129] The first plastic encapsulation layer 60 is located on a side of the package substrate 10 away from the substrate lower surface 12 .

[0130] That is to say, at this time, the first plastic encapsulation layer 60 is located above the second cofferdam 42 and inside the through hole 13 , and the first plastic encapsulation layer 60 covers all open areas around the functional chip 30 and the inner area of ​​the through hole 13 .

[0131] The first plastic encapsulation layer 60 can be an EMC (Epoxy Molding Compound) plastic encapsulation layer. Since the present embodiment utilizes the cofferdam 40 to prevent foreign substances from entering the cavity S, there is no need to consider whether the first plastic encapsulation layer 60 will affect the protection area in the cavity S due to material problems. Therefore, the selection range of the first plastic encapsulation layer 60 material is greatly expanded, thereby avoiding the selection of specific plastic encapsulation materials, greatly widening the plastic encapsulation process window, and effectively reducing costs.

[0132] In this embodiment, the first upper surface 21 of the filter chip 20 is flush with the substrate upper surface 11 , and the second plastic packaging layer 61 is disposed on the gap between the filter chip 20 and the cavity 101 , the substrate lower surface 12 , and the first lower surface 22 .

[0133] That is to say, the third electroplating layer 5323 is substantially located below the second plastic layer 61, and the third insulating layer 72 is substantially located below the second plastic layer 61. Other descriptions of the second plastic layer 61 can refer to the description of the first plastic layer 60 and will not be repeated here.

[0134] Here, by setting the second plastic encapsulation layer 61, on the one hand, the thickness difference between the filter chip 20 and the packaging substrate 10 can be compensated, so that the first upper surface 21 is flush with the substrate upper surface 11, so as to facilitate the subsequent molding of the first insulating layer 70, the third insulating layer 72 and other structures; on the other hand, the second plastic encapsulation layer 61 can protect the filter chip 20 and fix the relative position of the filter chip 20 and the cavity 101.

[0135] An embodiment of the present invention further provides a method for manufacturing a multi-chip package structure 100. Figure 5 , Figure 6a to Figure 6z-13 , the preparation method comprises the steps of:

[0136] S1: Reference Figure 6a , providing a packaging substrate 10, which has a substrate upper surface 11 and a substrate lower surface 12 arranged opposite to each other;

[0137] S2: Figure 6b , forming a cavity 101 on the packaging substrate 10;

[0138] S3: Reference Figure 6c , providing a filter chip 20, the filter chip 20 having a first upper surface 21 and a first lower surface 22 arranged opposite to each other, the first upper surface 21 having a plurality of first electrodes 211;

[0139] S4: Reference Figure 6d to Figure 6j , loading the filter chip 20 into the chamber 101 , with the first upper surface 21 and the substrate upper surface 11 located on the same side;

[0140] Step S4 is specifically as follows:

[0141] Ginseng Figure 6d , providing a temporary bonding plate 90;

[0142] Ginseng Figure 6e , attaching the substrate upper surface 11 of the packaging substrate 10 to the temporary bonding plate 90;

[0143] Ginseng Figure 6f , loading the filter chip 20 into the chamber 101 , with the first upper surface 21 and the substrate upper surface 11 located on the same side;

[0144] Here, the first upper surface 21 is also attached to the temporary attaching plate 90 , so that the first upper surface 21 can be flush with the upper surface 11 of the substrate.

[0145] Ginseng Figure 6g , forming a second plastic packaging layer 61 covering the gap between the filter chip 20 and the chamber 101 , the lower surface 12 of the substrate and the first lower surface 22 ;

[0146] Ginseng Figure 6h , removing the temporary bonding plate 90;

[0147] Ginseng Figure 6i , and invert the packaging substrate 10 .

[0148] Ginseng Figure 6j , a plurality of through holes 13 are formed on the packaging substrate 10 , and the through holes 13 penetrate the second plastic packaging layer 61 .

[0149] S5: Reference Figure 6k to Figure 6v , forming a first interconnection structure on the packaging substrate 10, wherein the first interconnection structure is connected to the first electrode 211;

[0150] Step S5 is specifically as follows:

[0151] Ginseng Figure 6k to Figure 6n , forming a first electroplating layer 5321 on the upper surface 11 of the substrate, forming a second electroplating layer 5322 on the inner wall of the through hole 13, and forming a third electroplating layer 5323 below the second plastic sealing layer 61;

[0152] The details are as follows:

[0153] Ginseng Figure 6k , forming a first photoresist layer 81 and a second photoresist layer 82 above the upper surface 11 of the substrate and below the second plastic packaging layer 61 respectively;

[0154] Ginseng Figure 6l , exposing and developing the first photoresist layer 81 to form a first opening 811, the first opening 811 exposing the through hole 13 and the upper surface 11 of the substrate, exposing and developing the second photoresist layer 82 to form a second opening 821, the second opening 821 exposing the through hole 13 and the second plastic sealing layer 61;

[0155] Ginseng Figure 6m , forming a first electroplating layer 5321 on the exposed upper surface 11 of the substrate, forming a second electroplating layer 5322 on the exposed inner wall of the through hole 13, and forming a third electroplating layer 5323 on the exposed second plastic sealing layer 61;

[0156] Ginseng Figure 6n , remove the first photoresist layer 81 and the second photoresist layer 82.

[0157] Ginseng Figure 6o , a first insulating layer 70 is disposed on the upper surface 11 of the substrate;

[0158] Ginseng Figure 6p to Figure 6t , forming an upper redistribution layer 531 on the first insulating layer 70 to conduct the first electrode 211 and the first electroplating layer 5321 through the holes on the first insulating layer 70;

[0159] The details are as follows:

[0160] Ginseng Figure 6p , exposing and developing the first insulating layer 70 to form a first hole 701, wherein the first hole 701 exposes the first electrode 211, the through hole 13, the first electroplating layer 5321 and the protection area, wherein the protection area is located on the first upper surface 21, and the protection area is located inside a plurality of first electrodes 211;

[0161] Ginseng Figure 6q , forming a third photoresist layer 83 on the first insulating layer 70;

[0162] Ginseng Figure 6r , exposing and developing the third photoresist layer 83 to form a third opening 831 , wherein the third opening 831 exposes the first electrode 211 , the first electroplating layer 5321 and the first insulating layer 70 ;

[0163] Ginseng Figure 6s , forming an upper redistribution layer 531 in the third opening 831;

[0164] Ginseng Figure 6t , remove the third photoresist layer 83.

[0165] Ginseng Figure 6u to Figure 6v , a second insulating layer 71 is disposed above the first insulating layer 70 and the upper rewiring layer 531, the first insulating layer 70 and the second insulating layer 71 cooperate to form a cofferdam 40, the cofferdam 40 includes a first cofferdam 41 and a second cofferdam 42, the first cofferdam 41 is located at the periphery of the cavity S, the outer edge of the second cofferdam 42 is flush with the outer edge of the package substrate 10, the second cofferdam 42 exposes the through hole 13, and the cofferdam 40 has a groove 43 that exposes the upper rewiring layer 531;

[0166] The details are as follows:

[0167] Ginseng Figure 6u , disposing a second insulating layer 71 above the first insulating layer 70 , the upper redistribution layer 531 and the protection area;

[0168] Ginseng Figure 6v , the second insulating layer 71 is exposed and developed to form a second hole 711, the second hole 711 exposes the through hole 13, the upper rewiring layer 531 and the protection area, the first insulating layer 70 and the second insulating layer 71 cooperate to form a cofferdam 40, the cofferdam 40 includes a first cofferdam 41 and a second cofferdam 42, the first cofferdam 41 is located at the periphery of the protection area, the outer edge of the second cofferdam is flush with the outer edge of the packaging substrate 10, the second cofferdam 42 exposes the through hole 13, and the cofferdam 40 has a groove 43 exposing the upper rewiring layer 531.

[0169] It should be noted that the cofferdam 40 may include a third cofferdam 45 connecting the first cofferdam 41 and the second cofferdam 42 . That is, at this time, the cofferdam 40 is formed on the surface area of ​​the substrate top surface 11 except the area corresponding to the cavity S and the through hole 13 .

[0170] In addition, since the independent packaging substrate 10 can be formed by dividing a large wafer-level substrate, when forming the cofferdam 40, multiple cofferdams 40 can be directly formed on the large substrate, and then the large substrate is divided to obtain a single packaging substrate 10 with a single cofferdam 40. In this way, the packaging efficiency can be greatly improved. Of course, the cofferdam 40 can also be formed on the functional chip 30.

[0171] S6: Participation Figure 6w , providing a functional chip 30, the functional chip 30 having a second upper surface 31 and a second lower surface 32 arranged opposite to each other, and the second lower surface 32 having a plurality of second electrodes 321;

[0172] S7: Participation Figure 6x to Figure 6z-10 , the functional chip 30 is mounted on the packaging substrate 10, the second lower surface 32 is arranged face to face with the substrate upper surface 11, and a second interconnection structure connecting the second electrode 321 and the first interconnection structure is formed;

[0173] S8: Participation Figure 6z-11 to Figure 6z-13 , forming a third interconnection structure connecting the external pin 121 and the first interconnection structure.

[0174] Steps S7 and S8 are specifically as follows:

[0175] Ginseng Figure 6x to Figure 6z-1 , forming a metal column 51 on the lower surface of the second electrode 321;

[0176] The details are as follows:

[0177] Ginseng Figure 6x , forming a fourth photoresist layer 84 on the second lower surface 32;

[0178] Ginseng Figure 6y , exposing and developing the fourth photoresist layer 84 to form a fourth opening 841 , wherein the fourth opening 841 exposes the second electrode 321 ;

[0179] Ginseng Figure 6z , forming a metal column 51 in the fourth opening 841;

[0180] Ginseng Figure 6z-1 , remove the fourth photoresist layer 84.

[0181] Ginseng Figure 6z-2 , solder 52 is disposed in the slot 43;

[0182] Ginseng Figure 6z-3 The functional chip 30 is loaded on top of the packaging substrate 10, the second lower surface 32 is arranged face to face with the substrate upper surface 11, the first cofferdam 41 cooperates with the second lower surface 32 and the first upper surface 21 to enclose and form a cavity S, and the metal column 51 is aligned with the groove 43, and the solder 52 and the metal column 51 are connected to each other.

[0183] Ginseng Figure 6z-4 , forming a first plastic encapsulation layer 60 on a side of the packaging substrate 10 away from the lower surface 12 of the substrate, the first plastic encapsulation layer 60 simultaneously covers the upper surface area of ​​the second cofferdam 42 exposed to the outside and the functional chip 30, and the first plastic encapsulation layer 60 fills the through hole 13;

[0184] Ginseng Figure 6z-5, forming a third insulating layer 72 below the third electroplating layer 5323 and the second plastic packaging layer 61;

[0185] Ginseng Figure 6z-6 to Figure 6z-10 , forming a lower redistribution layer 533 below the third insulating layer 72 and connecting to the third electroplating layer 5323 through the holes on the third insulating layer 72;

[0186] The details are as follows:

[0187] Ginseng Figure 6z-6 , exposing and developing the third insulating layer 72 to form a third hole 721 , wherein the third hole 721 exposes the third electroplating layer 5323 ;

[0188] Ginseng Figure 6z-7 , forming a fifth photoresist layer 85 below the third insulating layer 72;

[0189] Ginseng Figure 6z-8 , exposing and developing the fifth photoresist layer 85 to form a fifth opening 851 , wherein the fifth opening 851 exposes the third hole 721 and the third insulating layer 72 ;

[0190] Ginseng Figure 6z-9 , forming a lower redistribution layer 533 in the fifth opening 851;

[0191] Ginseng Figure 6z-1 0, remove the fifth photoresist layer 85.

[0192] Ginseng Figure 6z-1 1 and Figure 6z-1 2. Forming a fourth insulating layer 73 covering the third insulating layer 72 and the lower redistribution layer 533, wherein the fourth insulating layer 73 exposes the lower redistribution layer 533;

[0193] The details are as follows:

[0194] Ginseng Figure 6z-1 1. Forming a fourth insulating layer 73 below the lower redistribution layer 533 and the third insulating layer 72;

[0195] Ginseng Figure 6z-1 2. The fourth insulating layer 73 is exposed and developed to form a fourth hole 731 . The fourth hole 731 exposes the lower redistribution layer 533 .

[0196] Ginseng Figure 6z-1 3. Forming a ball grid array 121 on the exposed lower redistribution layer 533 , that is, forming a ball grid array 121 in the fourth hole 731 .

[0197] For other descriptions of the method for manufacturing the multi-chip package structure 100 of this embodiment, reference may be made to the description of the multi-chip package structure 100 described above, which will not be repeated here.

[0198] The cofferdam 40 of the present invention is located on the inner and outer sides of the first electrode 211, and the outer edge of the second cofferdam 42 is flush with the outer edge of the packaging substrate 10. In other embodiments, the cofferdam 40 may also be located on the inner side of the first electrode 211, or the outer edge of the second cofferdam 42 is flush with the outer edge of the functional chip 30, or the outer edge of the second cofferdam 42 is located between the outer edge of the functional chip 30 and the outer edge of the packaging substrate 10, and so on.

[0199] In summary, this embodiment forms a cavity S by setting a cofferdam 40, which can effectively prevent foreign matter from entering the cavity S during the packaging structure manufacturing process or during the use of the packaging structure and affecting the normal use of the filter chip 20, thereby improving the overall performance of the multi-chip packaging structure 100.

[0200] In addition, this embodiment utilizes packaging technology to package two different chips (filter chip 20 and functional chip 30) into the same packaging substrate 10, which can achieve high integration of multiple chips, improve the utilization rate of the packaging substrate 10, and further realize the miniaturization of the multi-chip packaging structure 100.

[0201] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0202] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A multi-chip package structure with a cavity for accommodating a filter chip, characterized in that: include: A packaging substrate, comprising an upper substrate surface and a lower substrate surface which are arranged opposite to each other, wherein the packaging substrate has a cavity; A filter chip is disposed in the chamber, wherein the filter chip has a first upper surface and a first lower surface that are disposed opposite to each other, the first upper surface and the upper surface of the substrate are located on the same side, and the first upper surface has a plurality of first electrodes; A functional chip is disposed above the packaging substrate, the functional chip has a second upper surface and a second lower surface that are disposed opposite to each other, the second lower surface is disposed face to face with the upper surface of the substrate, and the second lower surface has a plurality of second electrodes; A plurality of interconnect structures, used for conducting a plurality of first electrodes and a plurality of second electrodes; The functional chip is located above the chamber, and a plurality of first electrodes and a plurality of second electrodes are arranged face to face; a plurality of external pins are provided on one side of the lower surface of the substrate, and the package substrate has a plurality of through holes, and the interconnection structure conducts the first electrode, the second electrode and the external pins through the through holes; the interconnection structure includes a metal column, solder and an electroplating layer structure, the metal column is connected to the bottom of the second electrode, the electroplating layer structure conducts the first electrode, and the electroplating layer structure extends to the bottom of the package substrate through the through holes to conduct the external pins, and the solder Used to conduct the metal pillar and the electroplating layer structure, the electroplating layer structure includes an upper rewiring layer, an intermediate wiring layer and a lower rewiring layer that are mutually conductive, the upper rewiring layer is located above the packaging substrate and conducts the first electrode, the lower rewiring layer is located below the packaging substrate and conducts the external pin, the intermediate wiring layer includes a first electroplating layer located on the upper surface of the substrate, a second electroplating layer located on the inner wall of the through hole and a third electroplating layer located on the lower surface of the substrate, the first electroplating layer is connected to the upper rewiring layer, and the third electroplating layer is connected to the lower rewiring layer; The packaging structure includes a first insulating layer located on the upper surface of the substrate and above the first upper surface, an upper rewiring layer that conducts the first electroplating layer and the first electrode through holes on the first insulating layer, and a second insulating layer connecting the first insulating layer and the second lower surface, the second insulating layer has a groove that exposes the upper rewiring layer and accommodates solder, the first insulating layer and the second insulating layer cooperate to form a dam, and the dam cooperates with the second lower surface, the upper surface of the substrate, and the first upper surface to enclose a cavity, the dam includes a first dam located on the inner side of a plurality of first electrodes and a second dam located on the outer side of a plurality of first electrodes, the first dam cooperates with the second lower surface and the first upper surface to enclose a cavity, the multi-chip packaging structure includes a third insulating layer covering the third electroplating layer and the lower surface of the substrate, a lower rewiring layer that conducts the third electroplating layer through holes on the third insulating layer and extends toward the lower surface of the third insulating layer, and a fourth insulating layer covering the third insulating layer and the lower rewiring layer, the external pins are connected to the lower rewiring layer, and the fourth insulating layer exposes the external pins.

2. The multi-chip package structure according to claim 1, characterized in that: The through hole and the second electrode are spaced apart from each other.

3. The multi-chip package structure according to claim 1, characterized in that: The second cofferdam extends in a direction away from the first cofferdam until an outer edge of the second cofferdam is flush with an outer edge of the packaging substrate, and the second cofferdam exposes the through hole.

4. The multi-chip package structure according to claim 1, characterized in that: The multi-chip packaging structure also includes a first plastic packaging layer located on a side of the packaging substrate away from the lower surface of the substrate, the first plastic packaging layer simultaneously covers the exposed upper surface area of ​​the second cofferdam and the functional chip, and the first plastic packaging layer fills the through hole.

5. The multi-chip package structure according to claim 1, characterized in that: A second plastic packaging layer is provided between the gap between the filter chip and the chamber, the lower surface of the substrate and the first lower surface, and the first upper surface is flush with the upper surface of the substrate.

6. A method for manufacturing a multi-chip packaging structure with a cavity for accommodating a filter chip, characterized in that: Includes steps: S1: providing a packaging substrate, which has a substrate upper surface and a substrate lower surface arranged opposite to each other; S2: forming a cavity on the packaging substrate; S3: providing a filter chip, wherein the filter chip has a first upper surface and a first lower surface arranged opposite to each other, and the first upper surface has a plurality of first electrodes; S4: loading the filter chip into the chamber, with the first upper surface and the upper surface of the substrate being located on the same side; S5: forming a first interconnection structure on the packaging substrate, wherein the first interconnection structure is connected to the first electrode; S6: providing a functional chip, wherein the functional chip has a second upper surface and a second lower surface that are oppositely arranged, and the second lower surface has a plurality of second electrodes; S7: loading the functional chip on the top of the packaging substrate, disposing the second lower surface face to face with the upper surface of the substrate, and forming a second interconnection structure connecting the second electrode and the first interconnection structure; S8: forming a third interconnection structure that conducts the external pins and the first interconnection structure, step S4 specifically includes: Providing a temporary bonding plate; Laminating the upper surface of the package substrate to a temporary laminating plate; Loading the filter chip into the chamber, with the first upper surface and the upper surface of the substrate located on the same side; forming a second plastic packaging layer covering the gap between the filter chip and the chamber, the lower surface of the substrate and the first lower surface; removing the temporary bonding plate; inverting the packaging substrate; Forming a plurality of through holes on the packaging substrate, wherein the through holes penetrate the second plastic packaging layer; Step S5 specifically includes: Forming a first electroplating layer on the upper surface of the substrate, forming a second electroplating layer on the inner wall of the through hole, and forming a third electroplating layer below the second plastic sealing layer; Arranging a first insulating layer on the upper surface of the substrate; Forming an upper rewiring layer above the first insulating layer, which is connected to the first electrode and the first electroplating layer through holes in the first insulating layer; A second insulating layer is arranged above the first insulating layer and the upper rewiring layer, the first insulating layer and the second insulating layer cooperate to form a cofferdam, the cofferdam includes a first cofferdam and a second cofferdam, the first cofferdam is located at the periphery of the cavity, the outer edge of the second cofferdam is flush with the outer edge of the packaging substrate, the second cofferdam exposes the through hole, and the cofferdam has a groove exposing the upper rewiring layer; Steps S7 and S8 specifically include: forming a metal column on the lower surface of the second electrode; Setting solder in the slot; The functional chip is mounted on the packaging substrate, the second lower surface is arranged face to face with the upper surface of the substrate, the first cofferdam cooperates with the second lower surface and the first upper surface to enclose and form a cavity, the metal column is aligned with the groove, and the solder is connected to the metal column; Forming a first plastic encapsulation layer on a side of the packaging substrate away from the lower surface of the substrate, wherein the first plastic encapsulation layer simultaneously covers the upper surface area of ​​the second cofferdam exposed to the outside and the functional chip, and the first plastic encapsulation layer fills the through hole; forming a third insulating layer below the third electroplating layer and the second plastic sealing layer; Forming a lower redistribution layer below the third insulating layer, which is connected to the third electroplating layer through holes on the third insulating layer; forming a fourth insulating layer covering the third insulating layer and the lower redistribution layer, wherein the fourth insulating layer exposes the lower redistribution layer; A ball grid array is formed on the exposed lower redistribution layer.

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