Automatic synchronization source selection circuit for power meter

Abstract

The present invention relates to a synchronous source automatic selection circuit for a power meter, comprising a power supply, an external voltage input signal, an external current input signal, a channel selection circuit, an input signal frequency conditioning circuit, a phase-locked loop frequency multiplication circuit, an input signal detection circuit, and a channel switching control circuit. The present invention determines the presence or absence of an input channel signal through an output level signal of a frequency selection network, and uses the output level signal and a logic gate circuit to realize fast, accurate, and real-time control of a channel selection analog switch, thereby realizing automatic switching and detection of a voltage channel and a current channel in a hardware manner, solving the defects of unstable software operation and untimely ADC sampling triggering caused by the traditional control of the voltage channel and the current channel in a software manner, and at the same time can realize automatic selection of a channel signal with small distortion and stable waveform as an input signal of a PLL phase-locked loop, thereby improving the efficiency and accuracy of digital power meter measurement to a certain extent.

Description

Technical Field

[0001] The invention relates to the field of electronic measurement, in particular to a synchronous source automatic selection circuit for a power meter. Background Art

[0002] With the rapid development of the modern power electronics industry, there are more and more power supply and load products. Most power electronics systems are inseparable from power supplies and loads. Since power conversion efficiency, load power consumption and other related issues directly affect the performance of related products, it is necessary to use special measuring instruments to detect the energy consumption of these systems. Therefore, the demand for home appliance manufacturers to use digital power meters to detect power products and home appliances has increased; the speed requirements for digital power meters to detect products have also been further improved.

[0003] The digital power meter needs to sample the instantaneous values ​​of the input voltage and current signals within the entire cycle at the same time, and use the numerical calculation formula to calculate the effective value, peak value, power, power factor and other values ​​of the input voltage and current through the instantaneous values ​​sampled during the entire cycle, and finally qualitatively analyze the performance indicators of the device under test through the calculated values.

[0004] In order to completely and accurately sample the instantaneous values ​​of the input voltage and current signals within the entire cycle, digital power meters mainly use the following two methods: The first is a timer-based software control method. Patent CN201621367496.7 "A device for reducing power calculation errors" uses a dual A / D microcontroller to synchronously sample the voltage and current signals. In the actual operation of this patent, the sampling method is timer sampling. The timer timing cycle must be determined based on the frequency of the sampled signal and the number of sampling points required for a sampling cycle. The instantaneous value of the entire cycle is completed by triggering the ADC sampling through the timer. Sampling; The second software control method based on the PLL phase-locked loop hardware circuit, this method first needs to detect the frequency value of the voltage channel input signal through the frequency detection circuit, if the voltage signal exists, the frequency signal of the voltage channel is used as the synchronization source of the PLL phase-locked loop, if not, the frequency detection circuit is switched to the current channel, if the current signal exists, the frequency signal of the current channel is used as the synchronization source of the PLL phase-locked loop, if not, the frequency signal of the voltage channel is used as the synchronization source of the PLL phase-locked loop by default, and the PLL phase-locked loop uses the multiplied signal of the synchronization source as the sampling trigger synchronization signal of the ADC through the frequency multiplication circuit.

[0005] However, due to the instability of the software program and the short timing time of the timer for high-frequency input signals, there are shortcomings such as timing delay and reduced timing accuracy. At the same time, this timer sampling method is limited by the input signal frequency, and the timing period and sampling points must be accurately configured according to the input signal frequency. The PLL phase-locked loop hardware circuit method also requires software calculation to measure the input signal frequency to determine whether the input signal exists. These shortcomings affect the timeliness and accuracy of ADC sampling on the one hand, and on the other hand, measuring the frequency signal takes extra measurement time, affecting the instrument test speed, which goes against the customer's production line demand for test speed. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a synchronous source automatic selection circuit for a power meter, which is mainly used in digital power meters and other fields that require the use of a phase-locked loop to synchronously send input signals to an ADC for precise sampling.

[0007] The technical solution adopted by the present invention to solve its technical problems is: a synchronous source automatic selection circuit for a power meter, comprising a power supply, an external voltage input signal, an external current input signal, a channel selection circuit, an input signal frequency conditioning circuit, a phase-locked loop frequency multiplication circuit, an input signal detection circuit and a channel switching control circuit; the external voltage input signal and the external current input signal are connected to the input end of the channel selection circuit; the output end of the channel selection circuit is connected to the input end of the input signal frequency conditioning circuit; the output end of the input signal frequency conditioning circuit is connected to the input end of the phase-locked loop frequency multiplication circuit and the input signal detection circuit; the output end of the input signal detection circuit is connected to the input end of the channel switching control circuit; the output end of the channel switching control circuit is connected to the control end of the channel selection circuit; the output of the phase-locked loop frequency multiplication circuit is used as a trigger signal for ADC sampling.

[0008] Furthermore, the power supply described in the present invention supplies power to the channel selection circuit, the input signal frequency conditioning circuit, the phase-locked loop frequency multiplication circuit and the input signal detection circuit.

[0009] Furthermore, the channel selection circuit of the present invention includes a first analog switch, and two input terminals of the first analog switch are respectively connected to an external voltage input signal and an external current input signal.

[0010] Furthermore, the input signal frequency conditioning circuit described in the present invention conditions the input periodic signal into a square wave signal of the same frequency; the input signal frequency conditioning circuit includes a power supply of +5V, a first resistor, a first capacitor, a first pair of diodes, a second resistor, a third resistor, a second capacitor, a first operational amplifier, a first voltage regulator, a second voltage regulator, a fourth resistor, a third capacitor, a second pair of diodes, a fifth resistor, a second operational amplifier, a sixth resistor, a seventh resistor, and a fourth capacitor; one end of the first resistor is connected to the output end of the first analog switch, the other end of the first resistor is connected to the first capacitor, the first pair of diodes, the second capacitor, one end of the third resistor, and the anode of the first voltage regulator, the other end of the first resistor is simultaneously connected to the reverse end of the first operational amplifier, the other end of the first pair of diodes is connected to one end of the second resistor, the other end of the first pair of diodes is simultaneously connected to the same direction end of the first operational amplifier, and the other end of the second resistor Connected to the digital signal ground GND, the cathode of the first voltage regulator is connected to the anode of the second voltage regulator, the output end of the first operational amplifier is connected to the second capacitor, the other end of the third resistor, and the anode of the second voltage regulator, the output end of the first operational amplifier is simultaneously connected to one end of the fourth resistor, the other end of the fourth resistor is connected to the third capacitor and one end of the second pair of diodes, the other end of the fourth resistor is simultaneously connected to the same direction end of the second operational amplifier, the other end of the third capacitor is connected to the digital signal ground GND, the other end of the second pair of diodes is connected to one end of the fifth resistor, the other end of the second pair of diodes is simultaneously connected to the reverse end of the second operational amplifier, the other end of the fifth resistor is connected to the digital signal ground GND, the output end of the second operational amplifier is connected to one end of the sixth resistor and the seventh resistor, the other end of the sixth resistor is connected to the power supply +5V, the other end of the seventh resistor is connected to one end of the fourth capacitor, and the other end of the fourth capacitor is connected to the digital signal ground GND.

[0011] Furthermore, the input signal detection circuit of the present invention includes an LM567 audio decoder, and the input signal detection circuit detects whether there is an input signal within a specified bandwidth; including a power supply +5V, a fifth capacitor, an eighth resistor, a third voltage regulator, a fourth voltage regulator, a ninth resistor, a tenth resistor, an eleventh resistor, a third operational amplifier, a twelfth resistor, a thirteenth resistor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a first audio decoder, a fourteenth resistor, a fifteenth resistor, and a tenth capacitor; one end of the fifth capacitor is connected to one end of the fourth capacitor, the other end of the fifth capacitor is connected to one end of the eighth resistor, the other end of the eighth resistor is connected to the cathode of the third voltage regulator, the anode of the fourth voltage regulator, and one end of the ninth resistor, the other end of the eighth resistor is simultaneously connected to the reverse end of the third operational amplifier, the anode of the third voltage regulator is connected to the digital signal ground GND, the cathode of the fourth voltage regulator is connected to the digital signal ground GND, the other end of the ninth resistor is connected to the digital signal ground GND, one end of the tenth resistor is connected to the digital signal ground GND, the other end of the tenth resistor is connected to one end of the eleventh resistor, and the other end of the tenth resistor is simultaneously connected to the same direction end of the third operational amplifier, and the third operational amplifier The output end of the amplifier is connected to the other end of the eleventh resistor, the output end of the third operational amplifier is also connected to one end of the twelfth resistor, the other end of the twelfth resistor is connected to one end of the sixth capacitor, the other end of the sixth capacitor is connected to the 3-pin end of the first audio decoder, one end of the eighth capacitor is connected to the digital signal ground GND, the other end of the eighth capacitor is connected to the 2-pin end of the first audio decoder, one end of the ninth capacitor is connected to the digital signal ground GND, the other end of the ninth capacitor is connected to the 1-pin end of the first audio decoder, one end of the thirteenth resistor is connected to the power supply +5V, the other end of the thirteenth resistor is connected to the 4-pin end of the first audio decoder, the other end of the thirteenth resistor is also connected to one end of the seventh capacitor, the other end of the seventh capacitor is connected to the digital signal ground GND, one end of the fourteenth resistor is connected to the power supply +5V, the other end of the fourteenth resistor is connected to the 8-pin end of the first audio decoder, the 7-pin end of the first audio decoder is connected to the digital signal ground GND, one end of the fifteenth resistor is connected to the 5-pin end of the first audio decoder, the other end of the fifteenth resistor is connected to the 6-pin end of the first audio decoder, the other end of the fifteenth resistor is also connected to one end of the tenth capacitor, and the other end of the tenth capacitor is connected to the digital signal ground GND.

[0012] Furthermore, the channel switching control circuit described in the present invention includes an XOR gate circuit, one input end of the XOR gate circuit is connected to the output end of the audio decoder, and the other input end of the XOR gate circuit is connected to the output end of the XOR gate; the channel switching control circuit performs a logical operation on the signal output by the input signal detection circuit and the control signal of the current first analog switch, and the generated output signal continues to be used to control the switching of the analog switch of the channel selection circuit.

[0013] Furthermore, the phase-locked loop frequency multiplication circuit part of the present invention is responsible for conditioning the frequency signal obtained by the input signal frequency conditioning circuit to a frequency signal of a specified multiple as a trigger signal for ADC sampling, including a power supply +5V, a first counter, an eleventh capacitor, a first phase-locked loop, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, and a twelfth capacitor; the 16th pin of the first counter is connected to the power supply +5V, the 8th pin and the 11th pin of the first counter are connected to the digital signal ground GND, the 13th pin of the first counter is connected to the 3rd pin of the first phase-locked loop, the 10th pin of the first counter is connected to the 4th pin of the first phase-locked loop, the 5th pin and the 8th pin of the first phase-locked loop are connected to the digital signal ground GND, and the 11th capacitor is connected to the digital signal ground GND. One end is connected to the 6-pin terminal of the first phase-locked loop, the other end of the eleventh capacitor is connected to the 7-pin terminal of the first phase-locked loop, the 16-pin terminal of the first phase-locked loop is connected to the voltage +5V, one end of the sixteenth resistor is connected to the 13-pin terminal of the first phase-locked loop, the other end of the sixteenth resistor is connected to the 9-pin terminal of the first phase-locked loop, the other end of the sixteenth resistor is also connected to one end of the nineteenth resistor, one end of the seventeenth resistor is connected to the 12-pin terminal of the first phase-locked loop, the other end of the seventeenth resistor is connected to one end of the eighteenth resistor, the other end of the seventeenth resistor is also connected to the digital signal ground GND, the other end of the eighteenth resistor is connected to the 11-pin terminal of the first phase-locked loop, the other end of the nineteenth resistor is connected to one end of the twelfth capacitor, and the other end of the twelfth capacitor is connected to the digital signal ground GND.

[0014] The voltage input signal or the current input signal is selected by the first analog switch, the first resistor and the first capacitor form an RC low-pass filter circuit, the first pair of diodes protect the same-direction end and the reverse end of the first operational amplifier, the second resistor, the third resistor, the second capacitor, the first voltage regulator, the second voltage regulator, and the first operational amplifier form an amplifier circuit, and the output signal Vsg1 is generated after amplification and voltage stabilization; the fourth resistor and the third capacitor form an RC filter circuit, the output signal of the first operational amplifier is sent to the same-direction end of the second operational amplifier after RC filtering, the second pair of diodes, the fifth resistor, the second operational amplifier, the sixth resistor, the seventh resistor, and the fourth capacitor are built into a zero-crossing comparison circuit, and the comparison circuit outputs a signal Vsg2; the signal Vsg2 output by the comparator is sent to the input signal detection circuit part on the one hand, and is sent to the reverse end of the third operational amplifier through the fifth capacitor and the eighth resistor, the eighth resistor, the ninth resistor, the tenth resistor, the eleventh resistor, and the third operational amplifier form a reverse amplifier circuit, and the output is generated after amplification. signal Vsg3; the sixth capacitor, the seventh capacitor, the eighth capacitor, the ninth capacitor, the tenth capacitor, the twelfth resistor, the thirteenth resistor, the fourteenth resistor, the fifteenth resistor, and the first audio decoder form an input signal detection circuit to detect the Vsg3 signal, and generate an output signal Vsg4 after the detection; the first XOR gate chip constitutes a channel switching control circuit to perform a logic operation on the output signal Vsg4 and the first analog switch control signal, and the operation result generates an output signal Vsg5, and at the same time, the output signal Vsg5 is used as an input signal of the first XOR gate, and this output signal Vsg5 is sent to the channel selection circuit to realize the control of the first analog switch; on the other hand, the signal Vsg2 output by the comparator is sent to the phase-locked loop frequency multiplication circuit part, and the first counter, the first phase-locked loop, the eleventh capacitor, the twelfth capacitor, the sixteenth resistor, the seventeenth resistor, the eighteenth resistor, and the nineteenth resistor together form a phase-locked loop frequency multiplication circuit, which multiplies the input signal Vsg2 and outputs the Vsg6 signal as the ADC sampling trigger signal.

[0015] Furthermore, the first analog switch of the present invention first selects the voltage input signal to generate the output signal Vsg1 through the amplification circuit composed of the first operational amplifier, and the signal Vsg1 generates the output signal Vsg2 through the zero-crossing comparison circuit composed of the second operational amplifier;

[0016] If the voltage input signal exists, the signal Vsg2 is a square wave signal of the same frequency, and the output signal Vsg2 is output through the amplifier circuit composed of the third operational amplifier to output the output signal Vsg3 of the same frequency but different amplitude as the input signal Vsg2, which is sent to the first audio decoder circuit; the output signal Vsg3 outputs a low-level signal Vsg4 through the first audio decoder circuit, and the low-level signal Vsg4 and the low-level signal Vsg5 are logically operated to output the low-level signal Vsg5 to control the first analog switch to continue selecting the voltage channel signal; if the voltage input signal does not exist, the signal Vsg2 is a fixed-level output signal, and the signal Vsg2 is output through the amplifier circuit composed of the third operational amplifier to output the fixed-level output signal Vsg3 of different amplitude from the input signal Vsg2, and the signal Vsg3 outputs a high-level signal Vsg4 through the first audio decoder circuit, and the high-level signal Vsg4 and the low-level signal Vsg5 are logically operated to output the high-level signal Vsg5 to control the first analog switch to switch to select the current channel signal.

[0017] Furthermore, if the current input signal exists, the signal Vsg2 is a square wave signal of the same frequency, and the signal Vsg2 is output through the amplification circuit composed of the third operational amplifier to output an output signal Vsg3 of the same frequency but different amplitude as the input signal Vsg2, and the signal Vsg3 outputs a low-level signal Vsg4 through the first audio decoder circuit, and the low-level signal Vsg4 and the high-level signal Vsg5 are logically operated to output a high-level signal Vsg5 to control the first analog switch to continue selecting the current channel signal; if the current input signal does not exist, the signal Vsg2 is a fixed-level output signal, and the signal Vsg2 is output through the amplification circuit composed of the third operational amplifier to output a fixed-level output signal Vsg3 of different amplitude from the input signal Vsg2, and the signal Vsg3 outputs a high-level signal Vsg4 through the first audio decoder circuit, and the high-level signal Vsg4 and the high-level signal Vsg5 are logically operated to output a low-level signal Vsg5 to control the first analog switch to switch to select the voltage channel signal.

[0018] The working principle of the present invention is as follows: by selecting a tone decoder chip LM567 and matching it with peripheral devices to form a frequency selection network, when it receives an input signal located in the selected frequency band, the internal switch is turned on and a fixed level is output; the presence or absence of the input channel signal is judged by the output level signal of the frequency selection network, and the output level signal is used to operate with the logic gate circuit to realize fast, accurate and real-time control of the channel selection analog switch, thereby realizing automatic switching and detection of the voltage channel and the current channel in a hardware manner, solving the defects of unstable software operation and untimely ADC sampling triggering caused by the traditional control of the voltage channel and the current channel in a software manner, and at the same time, it can realize automatic selection of the channel signal with small distortion and stable waveform as the input signal of the PLL phase-locked loop, which improves the efficiency and accuracy of the digital power meter measurement to a certain extent.

[0019] The beneficial effects of the present invention are as follows: without the involvement of software programming, the automatic selection and switching of the synchronization source can be realized in a hardware manner, so that the phase-locked frequency multiplication speed is faster, the accuracy and real-time performance of the ADC sampling trigger signal are improved, and the problems of unstable program operation and inaccurate trigger sampling caused by program operation delay existing in the software manner are avoided, thereby improving the measurement efficiency and accuracy of the instrument. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a circuit structure principle block diagram of the present invention;

[0021] Figure 2 It is a circuit schematic diagram of the present invention. DETAILED DESCRIPTION

[0022] The present invention will now be described in further detail in conjunction with the accompanying drawings and preferred embodiments. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0023] like Figure 1 The figure shows a synchronous source automatic selection circuit for a power meter, including a power supply, an external voltage input signal, an external current input signal, a channel selection circuit, an input signal frequency conditioning circuit, a phase-locked loop frequency multiplication circuit, an input signal detection circuit, and a channel switching control circuit. The external voltage input signal and the external current input signal are connected to the input end of the channel selection circuit; the output end of the channel selection circuit is connected to the input end of the input signal frequency conditioning circuit; the output end of the input signal frequency conditioning circuit is connected to the input end of the phase-locked loop frequency multiplication circuit and the input signal detection circuit; the output end of the input signal detection circuit is connected to the input end of the channel switching control circuit; the output end of the channel switching control circuit is connected to the control end of the channel selection circuit; and the output of the phase-locked loop frequency multiplication circuit is used as a trigger signal for ADC sampling.

[0024] Circuit diagram Figure 2 As shown:

[0025] The channel selection circuit selects the voltage input channel and the current input channel based on an analog switch, and sends the signal output by the analog switch to the input signal frequency conditioning circuit part; the input signal frequency conditioning circuit is mainly constructed based on an operational amplifier circuit and a zero-crossing comparator circuit. If the input periodic signal exists, it is converted into a square wave signal with the same frequency for output. If the input periodic signal does not exist, it is output at a stable level. On the one hand, the output signal is sent to the input end of the input signal detection circuit part, and on the other hand, the output signal is sent to the input end of the phase-locked loop frequency multiplication circuit part; the input signal detection circuit is mainly constructed by an operational amplifier and an audio decoder, which detects whether the signal sent by the input signal detection circuit part exists, and sends the output detection result signal to the input end of the channel switching control circuit part; the channel switching control circuit is implemented based on an XOR gate circuit, which realizes the logical operation of the output signal of the input signal detection circuit part and the control signal of the channel selection circuit part as the output signal, and the output signal is sent to the channel selection circuit as the latest control signal of the analog switch; the phase-locked loop frequency multiplication circuit is mainly constructed based on a counter and a phase-locked loop circuit, and the output signal of the input signal frequency conditioning circuit is multiplied and output as a trigger signal for ADC sampling.

[0026] As attached Figure 2 As shown, U1 is a four-to-one analog switch model 74HCT4052, U2 is an integrated operational amplifier chip model LF353, U3 is a comparator chip model LM311, U4 is an integrated operational amplifier chip model AD8512, U5 is an audio decoder model LM567, U6 is an AND-OR gate logic chip model 74HC86, U7 is a counter chip model 74HC4040D, U8 is a phase-locked loop chip model 74HC4046, R1 to R19 are resistors, C1 to C12 are capacitors, D1 to D2 are protection diode pairs model BAV99, and W1 to W4 are voltage regulator tubes model LM385-1.2V.

[0027] Working process:

[0028] The U1 analog switch selects the voltage or current input signal V1 according to the control signal. Assuming that the voltage channel signal is selected first, the analog switch control signal is low level, and R1, C1, D1, R2, W1, W2, C2, R3, and U2 form an inverse proportional operational amplifier. The operational relationship between the output signal and the input signal is:

[0029]

[0030] If there is a periodic voltage signal in the voltage channel, due to the action of the voltage regulator tubes W1 and W2, the output of the amplifier circuit U2 is clamped at ±1.2V, so the output of the amplifier circuit U2 is a square wave signal with a period amplitude of 1.2V in the same phase; R4, C3, D2, R5, U3, R6, R7, and C4 form a zero-crossing comparison circuit, and the output of the operational amplifier U3 is a square wave signal with a period amplitude of 0-5V and the same as the input signal; C5 is a filter capacitor, which plays the role of blocking direct current and passing alternating current; R8, W3, W4, R9, R10, R11, and U4 form a reverse proportional operational amplifier, and the operational relationship between the output signal and the input signal is:

[0031]

[0032] Therefore, the output of operational amplifier U4 is a square wave signal with the same period and amplitude of 200mV as the input signal; C6, C7, C8, C9, C10, R12, R13, R14, R15, and U5 form an audio decoder circuit. The combination of peripheral resistors and capacitors can detect the presence of narrowband signals. The formula for setting the center frequency of the input signal to detect the audio decoder is as follows:

[0033] The oscillator center frequency is

[0034] f0=1.1 / (R15×C12) (3)

[0035] According to formula (1), the value of capacitor C12 is

[0036] C12=1.1 / (f0×R15) (4)

[0037] Here, the unit of resistance is (KΩ), the unit of capacitance is (uF), and the unit of f0 is (KHz). The value of resistor R15 should be in the range of 2 to 20KΩ, and then the value of capacitor C10 is determined by (4); C9 is mainly used to determine the detection bandwidth of the audio decoder. Increasing the value of C9 can reduce the bandwidth, and reducing the value of C9 can increase the bandwidth. C10 is mainly used to determine the output switch delay. Generally, C10 is roughly twice that of C9, and C9 is generally twice that of C12. Here, the oscillator center frequency can be determined according to the values ​​of the circuit resistors and capacitors:

[0038] f0=1.1 / (R15×C12)=1.1 / (4.7KΩ×4.7uF)≈0.05KHz=50Hz

[0039] If the input periodic signal exists, a stable low-level signal is output; if the input periodic signal does not exist, a fixed high-level signal is output. Here, since the voltage channel signal exists, the audio decoder U5 outputs a low level; the U6 logic chip performs an XOR operation on the output signal of the audio decoder and the control signal of the analog switch U1 as the latest control signal of the analog switch U1. The logic operation truth table is as follows:

[0040]

[0041] A: Analog switch control signal before logic operation

[0042] B: Audio decoder output signal

[0043] C: Analog switch control signal after logic operation

[0044] Since the control signal of the analog switch U1 is at a low level before the logic operation, and the output signal of the audio decoder U5 is low, the output signal of U6 is low, the analog switch U1 does not act, and continues to select the voltage channel; the phase-locked loop frequency multiplication circuit composed of U7 and U8 uses the square wave signal output by U3 as the input signal and multiplies the frequency output as the ADC sampling trigger signal.

[0045] If there is no periodic voltage signal in the voltage channel, the output of the amplifier circuit U2 is a stable DC level signal; the output of the operational amplifier U3 is a stable DC level signal; since the output of the operational amplifier U4 is also a stable DC level signal, the audio decoder circuit composed of C6, C7, C8, C9, C10, R12, R13, R14, R15, and U5 cannot detect the signal within the specified narrow band, so the audio decoder U5 outputs a high level; since the control signal of the analog switch is a low level before the logic operation, and the output signal of the audio decoder is a high level, U6 outputs a level signal, the analog switch U1 is actuated, and the channel selection current signal is switched.

[0046] If there is a periodic current signal in the current channel, due to the action of the voltage regulators W1 and W2, the output of the amplifier circuit U2 is clamped at ±1.2V, so the output of the amplifier circuit U2 is a square wave signal with a same phase period and amplitude of 1.2V; the output of the operational amplifier U3 is a square wave signal with the same period and amplitude of 0-5V as the input signal; the output of the operational amplifier U4 is a square wave signal with the same period and amplitude of 200mV as the input signal; here, due to the existence of the current channel signal, the audio decoder U5 outputs a low level, and since the control signal of the analog switch U1 is a high level before the logic operation, and the output signal of the audio decoder is a low level, U6 outputs a high level signal, the analog switch U1 does not act, and continues to select the current channel; the phase-locked loop frequency multiplication circuit composed of U7 and U8 uses the square wave signal output by U3 as the input signal for frequency multiplication and output as the ADC sampling trigger signal.

[0047] If there is no periodic current signal in the current channel, the output of the amplifier circuit U2 is a stable DC level signal; the output of the operational amplifier U3 is a stable DC level signal; since the output of the operational amplifier U4 is also a stable DC level signal, the audio decoder circuit composed of C6, C7, C8, C9, C10, R12, R13, R14, R15, and U5 cannot detect the signal within the specified narrow band, so the audio decoder circuit outputs a high level; since the control signal of the analog switch U1 is a high level before the logic operation, and the output signal of the audio decoder is a high level, U6 outputs a low level signal, the analog switch U1 is actuated, and the channel selection voltage signal is switched.

[0048] Therefore, the audio decoder circuit is used to detect whether there is an input signal in the input channel, and the logical operation result of the XOR gate logic chip is used to realize the automatic selection function of the hardware circuit of the voltage or current channel, so as to achieve real-time, fast and accurate measurement effect.

[0049] The above description only describes the specific implementation mode of the present invention. Various examples do not limit the essential content of the present invention. After reading the description, ordinary technicians in the relevant technical field can modify or deform the specific implementation modes described above without departing from the essence and scope of the invention.

Claims

1. A synchronous source automatic selection circuit for a power meter, characterized in that: It includes a power supply, an external voltage input signal, an external current input signal, a channel selection circuit, an input signal frequency conditioning circuit, a phase-locked loop frequency multiplication circuit, an input signal detection circuit and a channel switching control circuit; the external voltage input signal and the external current input signal are connected to the input end of the channel selection circuit; the output end of the channel selection circuit is connected to the input end of the input signal frequency conditioning circuit; the output end of the input signal frequency conditioning circuit is connected to the input end of the phase-locked loop frequency multiplication circuit and the input signal detection circuit; the output end of the input signal detection circuit is connected to the input end of the channel switching control circuit; the output end of the channel switching control circuit is connected to the control end of the channel selection circuit; the output of the phase-locked loop frequency multiplication circuit is used as a trigger signal for ADC sampling; The channel selection circuit comprises a first analog switch, two input terminals of the first analog switch are respectively connected to an external voltage input signal and an external current input signal; The input signal frequency conditioning circuit conditions the input periodic signal into a square wave signal of the same frequency; The input signal detection circuit includes an LM567 audio decoder, and the input signal detection circuit detects whether there is an input signal within a specified bandwidth; The channel switching control circuit comprises an XOR gate circuit, one input end of the XOR gate circuit is connected to the output end of the audio decoder, and the other input end of the XOR gate circuit is connected to the output end of the XOR gate; the channel switching control circuit performs a logic operation on the signal output by the input signal detection circuit and the control signal of the current first analog switch, and the generated output signal is continuously used to control the switching of the analog switch of the channel selection circuit; The phase-locked loop frequency multiplication circuit adjusts the frequency signal obtained by the input signal frequency conditioning circuit to a frequency signal of a specified multiple, and serves as a trigger signal for ADC sampling.

2. The automatic synchronization source selection circuit for a power meter according to claim 1, characterized in that: The power supply is used to supply power to the channel selection circuit, the input signal frequency conditioning circuit, the phase-locked loop frequency multiplication circuit and the input signal detection circuit.

3. The automatic synchronization source selection circuit for a power meter according to claim 1, characterized in that: The first analog switch first selects the voltage input signal to generate an output signal Vsg1 through the amplifier circuit composed of the first operational amplifier, and the signal Vsg1 generates an output signal Vsg2 through the zero-crossing comparison circuit composed of the second operational amplifier; if the voltage input signal exists, the signal Vsg2 is a square wave signal of the same frequency, and the output signal Vsg2 is output through the amplifier circuit composed of the third operational amplifier to output an output signal Vsg3 with the same frequency but different amplitude as the signal Vsg2, which is sent to the first audio decoder circuit; the output signal Vsg3 outputs a low-level signal Vsg4 through the first audio decoder circuit, and the low-level signal Vsg2 is output. g4 outputs a low-level signal Vsg5 after a logic operation with the low-level signal Vsg5 to control the first analog switch to continue selecting the voltage channel signal; if the voltage input signal does not exist, the signal Vsg2 is a fixed-level output signal, and the signal Vsg2 is output through the amplification circuit composed of the third operational amplifier to output a fixed-level output signal Vsg3 with a different amplitude from the signal Vsg2, and the signal Vsg3 outputs a high-level signal Vsg4 through the first audio decoder circuit, and the high-level signal Vsg4 outputs a high-level signal Vsg5 after a logic operation with the low-level signal Vsg5 to control the first analog switch to switch to select the current channel signal.

4. The automatic synchronization source selection circuit for a power meter as claimed in claim 3, characterized in that: If the current input signal exists, the signal Vsg2 is a square wave signal of the same frequency. The signal Vsg2 is output through the amplification circuit composed of the third operational amplifier to output an output signal Vsg3 of the same frequency but different amplitude as the signal Vsg2. The signal Vsg3 outputs a low-level signal Vsg4 through the first audio decoder circuit. The low-level signal Vsg4 and the high-level signal Vsg5 are logically operated to output a high-level signal Vsg5 to control the first analog switch to continue selecting the current channel signal. If the current input signal does not exist, the signal Vsg2 is a fixed-level output signal. The signal Vsg2 is output through the amplification circuit composed of the third operational amplifier to output a fixed-level output signal Vsg3 of different amplitude from the signal Vsg2. The signal Vsg3 outputs a high-level signal Vsg4 through the first audio decoder circuit. The high-level signal Vsg4 and the high-level signal Vsg5 are logically operated to output a low-level signal Vsg5 to control the first analog switch to switch to select the voltage channel signal.

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