QC-LDPC decoder, cyclic shift matrix partitioning method and storage device

Abstract

Embodiments of the present invention provide a QC-LDPC decoder, a cyclic shift matrix partitioning method, and a storage device. The QC-LDPC decoder includes: a matrix partitioning circuit for reducing a cyclic shift matrix by a preset compression factor to obtain a sub-matrix of smaller size; a plurality of check node processing circuits; a plurality of variable node processing circuits and a check circuit. The number of the check node processing circuits and the variable node processing circuits matches the size of the sub-matrix. It reduces the cyclic shift matrix constituting the check matrix into a sub-matrix of smaller size, and the number of check node processing circuits and variable node processing circuits is greatly reduced, thereby effectively reducing the cost of the QC-LDPC decoder and improving the utilization of the chip area while maintaining the decoding performance.

Description

Technical Field

[0001] The present invention relates to the technical field of LDPC codes, and in particular to a QC-LDPC decoder, a cyclic shift matrix partitioning method and a storage device. Background Art

[0002] Low-density parity-check (LDPC) code is a forward error correction code. It uses iterative decoding to encode through a pre-constructed sparse check matrix. Although LDPC code has great advantages in performance, its application is limited by the high complexity of the coding implementation method and the difficulty of implementing it in hardware circuits.

[0003] In order to overcome the obstacles in the application of LDPC codes, Marc PC Fossorier proposed a quasi-cyclic low-density parity-check (QC-LDPC) code, which combines the characteristics of structure and randomness, and simplifies the coding circuit while having the superior performance of LDPC codes.

[0004] Although the QC-LDPC code proposed above simplifies the coding circuit. However, due to the limitations of practical application scenarios (such as the long length of the QC-LDPC code), the QC-LDPC decoder still has problems such as large chip area, large storage requirements, complex internal wiring, and high power consumption. How to achieve a compromise between decoding efficiency and resource consumption of the decoder and obtain better decoder performance at a lower resource cost is still an urgent problem to be solved. Summary of the invention

[0005] The main technical problem solved by the embodiments of the present invention is to provide a QC-LDPC decoder, a cyclic shift matrix partitioning method and a storage device that can achieve high decoding performance at low hardware cost.

[0006] In order to solve the above technical problems, an embodiment of the present invention provides a method for partitioning a cyclic shift matrix. The method comprises the following steps:

[0007] The rth row and r+fth row in the identity matrix z The rows are compressed into one row, generating a compressed matrix where f z is a compression factor, r is an integer greater than or equal to 0; the cyclic shift matrix is ​​defined by a unit matrix and a cyclic shift factor of the unit matrix.

[0008] A modulo of the cyclic shift factor of the unit matrix and the compression factor is obtained to obtain a first cyclic shift factor corresponding to the compression matrix.

[0009] Optionally, the method further includes: dividing the compressed matrix into two or more sub-matrices according to the compression factor; the second cyclic shift factor corresponding to the sub-matrix is ​​the modulo result of the cyclic shift factor of the unit matrix and the compression factor.

[0010] Optionally, the size of the submatrix is ​​f z ⅹf z .

[0011] Optionally, the size of the unit matrix is ​​z×z; the cyclic shift factor is a positive integer greater than or equal to 0 and less than z;

[0012] The cyclic shift matrix generated based on the identity matrix and the cyclic shift factor satisfies the following conditions: the elements in the rth row and the r+sth column are non-zero elements; and s is the value of the cyclic shift factor.

[0013] Optionally, the rth row and the r+fth row in the identity matrix z Lines are compressed into one line, including: r+f z The elements of the row are added to the r-th row to generate the r-th row of the compressed identity matrix.

[0014] In order to solve the above technical problems, an embodiment of the present invention further provides a QC-LDPC decoder. The QC-LDPC decoder comprises:

[0015] A matrix segmentation circuit, the matrix segmentation circuit is used to segment the cyclic shift matrix into smaller sub-matrices with a preset compression factor; the cyclic shift matrix is ​​used to construct a check matrix of a QC-LDPC code; a plurality of check node processing circuits, the check node processing circuit is used to calculate the check information of the check node through the check matrix according to the variable information of the variable node; a plurality of variable node processing circuits, the variable node processing circuit is used to update the variable information of the variable node through the check matrix according to the check information returned by the check node, and a check circuit, the check circuit is used to determine that the variable information is decoded information when the variable information meets the check standard; and when the number of times the variable information is updated exceeds a preset threshold and still does not meet the check standard, it is determined that the decoding fails;

[0016] The number of the check node processing circuits and the variable node processing circuits matches the size of the sub-matrix.

[0017] Optionally, the rth row and the r+fth row of the cyclic shift matrix z The check nodes corresponding to the rows share the same check node processing circuit; where f z is the compression factor, and r is an integer greater than or equal to 0.

[0018] Optionally, the matrix segmentation circuit includes: a compression unit, the compression unit being used to separate the rth row and the r+fth row in the unit matrix according to the compression factor. z The rows are compressed into one row to generate a compressed matrix; the cyclic shift matrix is ​​defined by a unit matrix and a cyclic shift factor of the unit matrix and a cyclic shift factor calculation unit, and the cyclic shift factor calculation unit is used to calculate the remainder of the cyclic shift factor of the unit matrix and the compression factor to obtain a first cyclic shift factor corresponding to the compressed matrix.

[0019] Optionally, the cth column and the c+fth column in the cyclic shift matrix z The variable nodes corresponding to the columns share the same variable node processing circuit, where f z is the compression factor, and c is an integer greater than or equal to 0.

[0020] Optionally, the matrix segmentation circuit includes:

[0021] A compression unit, the compression unit is used to convert the rth row and the r+fth row in the unit matrix according to the compression factor. z The row is compressed into one row to generate a compressed matrix; the cyclic shift matrix is ​​defined by a unit matrix and a cyclic shift factor of the unit matrix; a cyclic shift factor calculation unit, the cyclic shift factor calculation unit is used to calculate the remainder of the cyclic shift factor of the unit matrix and the compression factor to obtain a first cyclic shift factor corresponding to the compressed matrix; and a matrix partitioning unit, the matrix partitioning unit is used to partition the compressed matrix into sub-matrices according to the compression factor; the size of the sub-matrix is ​​f z ⅹf z .

[0022] To solve the above technical problems, an embodiment of the present invention further provides a storage device, including a plurality of storage units and a storage controller, wherein the storage controller includes at least one QC-LDPC decoder as described above.

[0023] The QC-LDPC decoder provided in the embodiment of the present invention is provided with an additional hardware circuit to compress and split the cyclic shift matrix constituting the check matrix to form a plurality of sub-matrices with smaller sizes. In this way, the number of check node processing circuits and variable node processing circuits is greatly reduced, thereby reducing the cost required to improve the QC-LDPC decoding performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0025] Figure 1 Application scenarios of QC-LDPC codes provided by embodiments of the present invention;

[0026] Figure 2 is the Tanner graph of QC-LDPC code;

[0027] Figure 3 It is a schematic diagram of the structure of a typical QC-LDPC decoder;

[0028] Figure 4 A schematic diagram of the structure of a QC-LDPC decoder provided in an embodiment of the present invention;

[0029] Figure 5 A schematic diagram of a compression matrix provided by an embodiment of the present invention;

[0030] Figure 6 A method flow chart of a cyclic shift matrix partitioning method provided by an embodiment of the present invention;

[0031] Figure 7 for Figure 4 The structural schematic diagram of the matrix segmentation circuit shown. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0033] QC-LDPC codes are widely used in many different information transmission scenarios due to their cyclic characteristics, which can effectively reduce the difficulty of hardware circuit implementation, such as channel coding of wireless radio frequency communication channels or storage channel coding of storage devices, to improve the reliability of information transmission.

[0034] Figure 1 The schematic diagram of the application of QC-LDPC code in a storage device (such as a solid state drive) is shown in FIG. The storage device is composed of a storage controller for controlling data reading, writing and compiling and a storage unit for storing data (the storage unit may include one or more FLASH storage blocks 50).

[0035] Among them, Figure 1As shown, the storage controller is composed of an information read and write interface 10, a QC-LDPC encoder 20, a QC-LDPC decoder 30 and a read and write controller 40.

[0036] The information read-write interface 10 is a data interface for writing or outputting data streams, and can be set to a corresponding interface form (such as a USB interface) according to actual use requirements.

[0037] The QC-LDPC encoder 20 is implemented by a hardware circuit such as an FPGA, and is used to encode input information according to a preset generation matrix and a corresponding encoding algorithm. The QC-LDPC decoder 30 is similar to the QC-LDPC encoder, and can also be composed of a hardware circuit, and is used to perform a decoding operation on the input coded information according to a preset decoding algorithm and a check matrix.

[0038] The read / write controller 40 is connected to the FLASH storage block 50 and serves as a control center for data reading and writing, and is used to control data to be written into the corresponding FLASH storage block 50 or read data from a specific location of the FLASH storage block 50 according to control instructions.

[0039] The actual use of storage devices can be roughly divided into the following two aspects:

[0040] 1. When writing data, the data stream is input into the QC-LDPC encoder 20 through the information read-write interface 10, and the QC-LDPC encoder 20 performs QC-LDPC encoding on the data and outputs the data to the read-write controller 40. The read-write controller 40 stores the encoded information in the corresponding storage address of the FLASH storage block 50 in an orderly manner according to the control instruction.

[0041] 2. When reading data, the read / write controller 40 reads the encoding information from the storage address corresponding to the FLASH storage block 50 according to the control instruction, and provides it to the QC-LDPC decoder 30. The QC-LDPC decoder 30 performs QC-LDPC decoding operation on the input encoding information and outputs the decoded information through the information read / write interface 10.

[0042] Through the above encoding and decoding process, the reliability of the storage device can be effectively improved, ensuring that information can be correctly stored and read, and making up for the defects of storage reliability based on FLASH flash memory technology (such as SSD).

[0043] Similarly, a QC-LDPC encoder and a QC-LDPC decoder may be respectively provided between the communication modules that establish the wireless communication channel, for performing QC-LDPC encoding on the transmitted information and performing QC-LDPC decoding on the received information, so as to realize effective information transmission between the sender and the receiver and reduce the influence of various external interferences during the information transmission process.

[0044] Combining the above application scenarios, we can see that when applying QC-LDPC coding, QC-LDPC encoders and QC-LDPC decoders are always expected to have better decoding performance or be implemented under the premise of lower hardware circuit cost. The following describes in detail a QC-LDPC decoder that can reduce the chip area and cost of the QC-LDPC decoder while maintaining decoding performance, combined with the characteristics of QC-LDPC codes.

[0045] In the encoding and decoding process of QC-LDPC code, the core is to construct a suitable check matrix. In this embodiment, H represents the check matrix. Each row of the check matrix H represents a check node of the QC-LDPC code, and each column of the check matrix H represents a variable node of the QC-LDPC code. For example, the check matrix H is as follows:

[0046]

[0047] In the check matrix H, "0" indicates that there is no connection between the corresponding check node and the variable node (such as between v3 and c1), and "1" indicates that there is a connection between the corresponding check node and the variable node (such as between v1 and c1).

[0048] In addition, the check matrix of the QC-LDPC code can also be intuitively represented in the form of a bidirectional graph model called a Tanner graph. Figure 2 As shown, the Tanner graph includes 4 check nodes and 7 variable nodes, which correspond to the 4 rows and 7 columns in the check matrix H. The number of connections between the variable nodes and the check nodes is the same as the number of "1" in the check matrix H.

[0049] In order to facilitate circuit implementation, in QC-LDPC codes, the check matrix H is constructed by a number of cyclic shift matrices and all-zero matrices of the same size. The cyclic shift matrices refer to multiple matrices formed by cyclic shifting of the unit matrix, and the matrices have the characteristic of block circulation.

[0050] Assumption A i,j is a matrix of size zxz. For any 1≤i≤m and 1≤j≤n, the check matrix H of the QC-LDPC code can be expressed as follows:

[0051]

[0052] In the check matrix H of the QC-LDPC code, element "0" is represented by an all-zero matrix, and element "1" is represented by a cyclic shift matrix with a corresponding cyclic shift step (ie, a cyclic shift matrix obtained by shifting the identity matrix rightward once or multiple times).

[0053] For the check matrix of the QC-LDPC code, it can be divided into multiple layers according to the rows of the cyclic shift matrix. Therefore, a very effective decoding method called "layered decoding algorithm" can be used in the decoding process of the QC-LDPC code to perform efficient QC-LDPC decoding.

[0054] Figure 3 This is a schematic diagram of the structure of the QC-LDPC decoder designed based on the layered decoding algorithm. Figure 3 In the QC-LDPC decoder shown, the check node processing circuit CNP represents the hardware circuit for performing horizontal phase processing, and the variable node processing circuit VNP represents the hardware circuit for performing vertical phase processing. The check circuit HDP represents the hardware circuit for performing the check step, which is used to determine whether the variable information on the variable node meets the check standard.

[0055] The horizontal phase processing refers to transferring variable information from each variable node to each check node connected to the variable node, and calculating the check information corresponding to each check node accordingly. The vertical phase processing refers to returning the check information from the check node to each variable node connected to the check node, and calculating the variable information of the variable node accordingly.

[0056] like Figure 3 As shown, the check node processing circuit CNP, the variable node processing circuit VNP and the check circuit HDP are connected in sequence. The variable information output by the variable node processing circuit VNP is respectively provided to the check node processing circuit CNP for decoding work at the next layer and the check circuit HDP for checking steps.

[0057] The idea of ​​the above-mentioned layered decoding algorithm is to divide a complete decoding process into multiple iterative processes by layering the check matrix. And after the last iteration, the final decoded information is output (each iterative process corresponds to each layer of the check matrix, and each iterative process is based on the output result of the previous iterative process).

[0058] In addition, when using very long LDPC codes (such as 4kb or 2kb), the resources or circuit area occupied by executing each iteration process in parallel will be very large. In order to further reduce the circuit area required by the QC-LDPC decoder so that it can have practical application capabilities, it is customary to further divide each iteration process into n segments, and the QC-LDPC decoder completes the decoding of a certain layer through n time slots.

[0059] Based on the above-mentioned layered decoding method, the number of variable node processing circuits and check node processing circuits required by a general QC-LDPC decoder is adapted to the size of the cyclic shift matrix constituting the check matrix (ie, the number of rows and columns contained in the cyclic shift matrix).

[0060] For example, when the size of the cyclic shift matrix is ​​zxz, it indicates that the corresponding number of variable nodes and check nodes are both z. The QC-LDPC decoder needs to set a corresponding number of variable node processing circuits and check node processing circuits to match the bit width required by the cyclic shift matrix in order to process the corresponding variable nodes and check nodes.

[0061] Therefore, as the basis of the layered decoding algorithm, the size of the cyclic shift matrix (i.e., the number of variable nodes and check nodes included) is of great significance to the decoding performance and implementation cost of the QC-LDPC decoder.

[0062] Assuming that the coding bit length of the QC-LDPC code is N and the coding information length is K, the above check matrix H satisfies: N = n x z and (NK) = m x z. It can be intuitively concluded that the more columns and rows the cyclic shift matrix has (i.e., the larger the value of z), the smaller the values ​​of m and n corresponding to the check matrix H can be.

[0063] Choosing a larger z can bring many advantages to the QC-LDPC decoder. For example, the larger the size of the cyclic shift matrix, the fewer time slots the QC-LDPC decoder needs to occupy to complete one iteration. Moreover, the check matrix H constructed by the cyclic shift matrix is ​​more likely to meet the RC constraint and girth requirements (i.e., there cannot be short loops of length 4 in the check matrix).

[0064] However, a larger size of the cyclic shift matrix also means that more check node processing circuits are required to perform check node processing in parallel. More check node processing circuits will bring great challenges to the design, manufacture and application of QC-LDPC decoders.

[0065] To reduce the difficulty of implementing the QC-LDPC decoder, technicians have provided many optimized decoding methods. For example, the minimum sum algorithm or the layered decoding algorithm as described above. In order to better improve the efficiency of the QC-LDPC decoder, the embodiment of the present invention provides a new optimization idea and method to reduce the implementation cost of the QC-LDPC decoder. Figure 4 A structural block diagram of a QC-LDPC decoder designed based on a new optimization idea provided in an embodiment of the present invention.

[0066] like Figure 4 As shown, the QC-LDPC decoder may include: a matrix segmentation circuit 410 , a plurality of check node processing circuits 420 , a plurality of variable node processing circuits 430 and a check circuit 440 .

[0067] The check node processing circuit 410 is used to calculate the check information of the check node through the check matrix of the QC-LDPC code according to the variable information of the variable node. The variable node processing circuit 420 is used to update the variable information of the variable node through the check matrix according to the check information returned by the check node;

[0068] The verification circuit 430 is used to determine that the variable information is decoded information when the variable information meets the verification standard; and when the number of times the variable information is updated exceeds a preset threshold and still does not meet the verification standard, determine that the decoding fails.

[0069] The matrix segmentation circuit 410 is used to segment the cyclic shift matrix into a plurality of sub-matrices with a preset compression factor. In this embodiment, the check matrix of the QC-LDPC code is constructed based on the cyclic shift matrix, and based on the segmentation result of the sub-matrix, the number of the check node processing circuit 410 and the variable node processing circuit 420 is matched with the size of the sub-matrix.

[0070] The compression factor is a value set by a technician, and its value can be determined according to the actual situation. The cyclic shift matrix is ​​the basis of the check matrix, which is obtained by cyclic shifting the unit matrix.

[0071] Based on the characteristics of the cyclic shift matrix, the sub-matrix obtained after the matrix division circuit 410 is reduced will not affect the decoding process, and the number of check node processing circuits 410 and the variable node processing circuits 420 required to be used can be reduced.

[0072] In this embodiment, starting with the size of the basis (circular shift matrix) constituting the check matrix, the circular shift matrix is ​​reasonably reduced, the utilization of the check node processing circuit 410 and the variable node processing circuit 420 is improved, and a wider search range is covered based on a sub-matrix of a smaller size. In this way, the working efficiency of the QC-LDPC decoder is higher, and the fast convergence and low bit error rate of the decoding process are achieved.

[0073] Under the same cost constraints, the QC-LDPC decoder provided by the embodiment of the present invention can have a larger cyclic shift matrix, thereby obtaining the good effects that can be brought by the large-sized cyclic shift matrix.

[0074] Moreover, the optimization ideas provided by the embodiments of the present invention are different from the existing optimization methods in terms of entry point and optimization direction. Therefore, in actual use, the existing optimization methods can be combined with the QC-LDPC decoder provided by the embodiments of the present invention to obtain better decoder performance at a lower implementation cost.

[0075] The following describes in detail the process of reducing the size of the cyclic shift matrix with reference to a specific example. The cyclic shift matrix is ​​a matrix obtained by shifting a unit matrix of a certain size to the right once or multiple times, and can be defined by two parameters: the unit matrix and the cyclic shift factor of the unit matrix.

[0076] In this embodiment, the cyclic shift factor represents the column where the first non-zero element in the first row of the cyclic shift matrix is ​​located, and is used to represent the number of times the unit matrix is ​​shifted to the right.

[0077] Assuming the size of the unit matrix is ​​zxz, the cyclic shift matrix generated by the unit matrix and the cyclic shift factor can be determined by the following condition: the elements in the rth row and the r+sth column are non-zero elements.

[0078] Wherein, s is a cyclic shift factor, and its value range is a positive integer greater than or equal to 0 and less than z; and r is a positive integer greater than or equal to 0 and less than z.

[0079] Figure 5 This is a schematic diagram of a 4x4 cyclic shift matrix. Figure 5 As shown, the cyclic shift factor s has four values ​​of 0, 1, 2 and 3, which are respectively used to represent the number of times the unit matrix is ​​shifted to the right. Thus, 4 different cyclic shift matrices corresponding to the 4 cyclic shift factors can be obtained.

[0080] Based on the properties of the above cyclic shift matrix, such as Figure 6 As shown, the segmentation method includes:

[0081] 610. The rth row and the r+fth row in the unit matrix z The rows are compressed into one row to generate a compressed matrix. z is the compression factor, and r is an integer greater than or equal to 0.

[0082] The compression factor is a pre-selected parameter value, which can be set according to actual conditions. The compression factor determines the reduction amplitude of the cyclic shift matrix and the size of the sub-matrix.

[0083] “Compression” is a technical term used in this embodiment to vividly express the processing process of the rows in the unit matrix, which means that the rth row and the r+fth row are compressed. z The process of combining elements in rows into one row without affecting the non-zero elements in the two rows.

[0084] Specifically, the “compression” can be to convert the first r+f z The elements included in the row are correspondingly superimposed on the positions corresponding to the rth row to generate the rth row of the compressed identity matrix. For example, if the compression factor is 2, Figure 5 As shown, the rth row and r+fth row of each cyclic shift matrix z All rows are compressed and the corresponding compressed matrices are generated.

[0085] 620. Calculate the modulus of the cyclic shift factor of the unit matrix and the compression factor to obtain a first cyclic shift factor corresponding to the compression matrix.

[0086] The compression matrix obtained based on the cyclic shift matrix also has the characteristic of cyclic block. The first cyclic shift factor corresponding to the compression matrix can be calculated by the following formula (1):

[0087] s′=s mod f z (1)

[0088] Among them, s' is the first cyclic shift factor, s is the cyclic shift factor of the identity matrix, and f z is the compression factor.

[0089] After the above compression processing, those skilled in the art can understand that the rth row and the r+fth row in the cyclic shift matrix z The check nodes corresponding to the rows can actually share the same check node processing circuit for processing.

[0090] Therefore, in some embodiments, the QC-LDPC decoding uses the same check node processing circuit and the rth row and r+fth row in the cyclic shift matrix. z The check nodes of the rows correspond to each other, which can reduce the number of check node processing circuits required.

[0091] Furthermore, the compressed matrix obtained in step 610 can be further divided into smaller sub-matrices based on the number of columns of the compressed matrix according to the selected compression factor. In some embodiments, the size of the sub-matrices after division can be f z ⅹf z .

[0092] Similarly, after the segmentation process, we can see that the cth column and c+fth column in the cyclic shift matrix z The variable nodes corresponding to the columns can actually also share the same variable node processing circuit for processing.

[0093] Therefore, in some embodiments, the QC-LDPC decoder uses the same variable node processing circuit as the cth column and the c+fth column in the cyclic shift matrix. z The corresponding variable node of the column.

[0094] Through the above compression and segmentation steps, the cyclic shift matrix of size zxz can be decomposed into a matrix of size f z ⅹf z The sub-matrix of the network is constructed to dig out the check node processing circuits and variable node processing circuits that can be shared, which effectively improves the utilization efficiency of the circuit and achieves the effect of reducing the circuit area.

[0095] Based on the cyclic shift matrix compression method disclosed in the above method embodiment, Figure 7 Schematic diagram of a corresponding matrix segmentation circuit provided by an embodiment of the present invention. Figure 7 As shown, the matrix segmentation circuit 410 may specifically include: a compression unit 411, a cyclic shift factor calculation unit 412 and a matrix segmentation unit 413.

[0096] The compression unit 411 is used to convert the rth row and the r+fth row in the unit matrix into z The rows are compressed into one row, producing a compressed matrix.

[0097] The unit matrix is ​​the basis for forming a cyclic shift matrix, which is generated by right shifting the unit matrix once or several times each time. The larger the size of the unit matrix, the more different cyclic shift matrices can be generated. In this embodiment, the number of right shifts is represented by the cyclic shift factor.

[0098] The cyclic shift factor calculation unit 412 is used to calculate the modulus of the cyclic shift factor of the unit matrix and the compression factor to obtain a first cyclic shift factor corresponding to the compression matrix.

[0099] Each cyclic shift matrix can be compressed into a corresponding compressed matrix. Therefore, the compressed matrix also has the property of cyclic shift and can be represented by a corresponding cyclic shift factor. In this embodiment, the cyclic shift factor corresponding to the compressed matrix is ​​represented by a first cyclic shift factor.

[0100] Through the compression process of the compression unit 411, the number of rows of the original cyclic shift matrix is ​​compressed. That is, the rth row and the r+fth row of the cyclic shift matrix are compressed. z The check nodes corresponding to the rows can actually share the same check node processing circuit for processing.

[0101] The matrix segmentation unit 413 is used to segment the compressed matrix into smaller sub-matrices according to the compression factor. The size of the sub-matrix finally segmented is determined by the pre-set compression factor. In this embodiment, the size of the sub-matrix is ​​f z ⅹf z .

[0102] Similarly, the sub-matrix also has a corresponding second cyclic shift factor, which can be calculated and determined by the following formula (2):

[0103] s″=s mod f z (2)

[0104] Where, s`` is the second cyclic shift factor, s is the cyclic shift factor of the identity matrix, and f z is the compression factor.

[0105] After the matrix partitioning unit 413 has partitioned the compressed matrix, the number of columns in the compressed matrix is ​​reduced accordingly. z The variable nodes corresponding to the columns can actually share the same variable node processing circuit for processing.

[0106] It should be noted that in the embodiment of the present invention, only the hardware circuits in the QC-LDPC decoder are described in a functional naming manner (such as matrix segmentation circuit 410, check node processing circuit 420, variable node processing circuit 430 and check circuit 440, etc.).

[0107] Those skilled in the art can select, adjust or combine the commonly used circuit structures in the art based on the functions to be performed by the hardware circuits disclosed in the embodiments of the present invention and the inventive ideas disclosed in the above embodiments to obtain actual circuit structures that can perform one or more functions. The actual circuit structures used to perform these functions are well known to those skilled in the art and are not used to limit the present invention.

[0108] In summary, based on the method for reducing the cyclic shift matrix provided in the embodiment of the present invention, the original cyclic shift matrix of size zxz can be divided into a matrix of size f z ⅹf z The number of check node processing circuits 420 and variable node processing circuits 430 required is also reduced.

[0109] Such a QC-LDPC decoder structure setting can, on the one hand, reduce the number of check node processing circuits 420 and variable node processing circuits 430 required by the QC-LDPC decoder under the unit matrix of the same size, thereby effectively reducing the circuit area and implementation cost.

[0110] On the other hand, under the premise of having the same circuit area and implementation cost, the QC-LDPC decoder is also allowed to use a larger unit matrix (that is, the value of the parameter z can be larger), which helps to construct and design a check matrix with better performance, achieve more reliable encoding and decoding of QC-LDPC codes, and apply technical effects such as masking methods (a method for eliminating short loops in the check matrix and increasing the perimeter of the check matrix) and simpler searches in a large spatial range.

[0111] The professionals should further realize that the exemplary steps described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the composition and steps of each example according to the function. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution.

[0112] Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention. The computer software may be stored in a computer-readable storage medium, and when the program is executed, it may include the process of the embodiments of the above methods. The storage medium may be a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0113] The above description is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A QC-LDPC decoder, characterized in that: include: Matrix partitioning circuit, the cyclic shift matrix is ​​used to construct the check matrix of the QC-LDPC code; The cyclic shift matrix is ​​defined by an identity matrix and a cyclic shift factor of the identity matrix; The matrix segmentation circuit comprises: The first compression unit is used to compress the rth row and the r+fth row in the unit matrix according to the compression factor. z The rows are compressed into one row to generate a compressed matrix; where f z is the compression factor, r is an integer greater than or equal to 0; a cyclic shift factor calculation unit, the cyclic shift factor calculation unit being used to calculate the remainder of the cyclic shift factor of the unit matrix and the compression factor to obtain a first cyclic shift factor corresponding to the compression matrix; a plurality of check node processing circuits, the check node processing circuits being used to calculate check information of the check node through the check matrix according to the variable information of the variable node; A plurality of variable node processing circuits, wherein the variable node processing circuits are used to update the variable information of the variable node through the check matrix according to the check information returned by the check node; A verification circuit, wherein the verification circuit is used to determine that the variable information is decoded information when the variable information meets the verification standard; and when the number of times the variable information is updated exceeds a preset threshold and still does not meet the verification standard, determine that the decoding fails; The number of the check node processing circuits and the variable node processing circuits matches the size of the compression matrix.

2. The QC-LDPC decoder according to claim 1, characterized in that: The rth row and r+fth row of the cyclic shift matrix z The check nodes corresponding to the rows share the same check node processing circuit; where f z is the compression factor, and r is an integer greater than or equal to 0.

3. The QC-LDPC decoder according to claim 1, characterized in that: The cth column and the c+fth column in the cyclic shift matrix z The variable nodes corresponding to the columns share the same variable node processing circuit, where f z is the compression factor, and c is an integer greater than or equal to 0.

4. The QC-LDPC decoder according to claim 3, characterized in that: The matrix segmentation circuit further includes: A matrix division unit, wherein the matrix division unit is used to divide the compressed matrix into sub-matrices according to the compression factor; the second cyclic shift factor corresponding to the sub-matrix is ​​the result of the modulus of the cyclic shift factor of the unit matrix and the compression factor; the size of the sub-matrix is ​​f z ⅹf z ; The number of the check node processing circuits and the variable node processing circuits matches the size of the sub-matrix.

5. A storage device, comprising a plurality of storage units and a storage controller, characterized in that: The storage controller includes at least one QC-LDPC decoder as described in any one of claims 1-4.

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