Device and method for conjugate multiplication between complex numbers

Abstract

An apparatus and method for multiplying packed real and imaginary components of a complex number. The processor includes: a decoder; a first source register; a second source register; and an execution circuit, the execution circuit including: a multiplier circuit that selects real and imaginary data elements in the first source register and the second source register for multiplication to generate a plurality of imaginary products; an adder circuit that adds a first subset of the plurality of imaginary products and subtracts a second subset of the plurality of imaginary products to generate a first temporary result, and adds a third subset of the plurality of imaginary products and subtracts a fourth subset of the plurality of imaginary products to generate a second temporary result; an accumulation circuit that combines the first temporary result with first data from a destination register to generate a first final result, combines the second temporary result with second data from the destination register to generate a second final result, and stores the first final result and the second final result back into the destination register.

Description

Field of the Invention

[0001] Embodiments of the present invention generally relate to the field of computer processors. More specifically, embodiments relate to apparatuses and methods for conjugate multiplication between complex numbers and complex numbers. Background Art

[0002] An instruction set or instruction set architecture (ISA) is a part of a computer architecture related to programming, including native data types, instructions, register architectures, addressing modes, memory architectures, interrupt and exception handling, and external input and output (I / O). It should be noted that the term "instruction" generally refers to a macro-instruction in this document - which is an instruction provided to the processor for execution - as opposed to a micro-instruction or micro-operation - which is the result of decoding a macro-instruction by the processor's decoder. A micro-instruction or micro-operation can be configured to instruct an execution unit on the processor to perform an operation to achieve the logic associated with the macro-instruction.

[0003] The ISA is different from the microarchitecture which is a set of processor design techniques for implementing the instruction set. Processors with different microarchitectures can share a common instruction set. For example, the Intel® Pentium 4 processor, the Intel® CoreTM™ processor, and processors from Advanced Micro Devices, Inc. in Sunnyvale, California, implement nearly the same version of the x86 instruction set (with newer versions having incorporated some extensions), but have different internal designs. For example, the same register architecture of an ISA can be implemented in different ways in different microarchitectures using well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., using a register alias table (RAT), a reorder buffer (ROB), and a retirement register file). Unless otherwise specified, the phrases register architecture, register file, and register are used in this document to refer to things visible to software / programmers and the way instructions specify registers. In cases where a distinction is required, the adjectives "logical", "architectural", or "software visible" will be used to indicate registers / files in the register architecture, while different adjectives will be used to specify registers in a given microarchitecture (e.g., physical registers, reorder buffers, retirement registers, register pools).

[0004] Multiply-accumulate is a common digital signal processing operation that computes the product of two numbers and adds that product to an accumulation value. Existing single instruction multiple data (SIMD) microarchitectures implement the multiply-accumulate operation by executing a sequence of instructions. For example, a multiply instruction can be used to perform the multiply-accumulate, followed by a 4-way add, and then an accumulation with a destination quadword data to generate two 64-bit saturated results. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] A better understanding of the present invention can be obtained from the following detailed description in conjunction with the accompanying drawings, in which:

[0006] Figure 1A and 1B is a block diagram illustrating a general vector-friendly instruction format and its instruction templates according to an embodiment of the present invention;

[0007] Figure 2A -C is a block diagram illustrating an exemplary VEX instruction format according to an embodiment of the present invention;

[0008] Figure 3 is a block diagram of a register architecture according to an embodiment of the present invention; and

[0009] Figure 4A is a block diagram illustrating both an exemplary in-order fetch, decode, retire pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to an embodiment of the present invention;

[0010] Figure 4B is a block diagram illustrating both an exemplary in-order fetch, decode, retire core to be included in a processor and an exemplary register renaming, out-of-order issue / execution architecture core according to an embodiment of the present invention;

[0011] Figure 5A is a block diagram of a single processor core and its connection to an on-die interconnect network;

[0012] Figure 5B illustrates according to an embodiment of the present invention Figure 5A an expanded view of a portion of the processor core in

[0013] Figure 6 is a block diagram of a single-core processor and a multi-core processor with an integrated memory controller and graphics according to an embodiment of the present invention;

[0014] Figure 7 illustrates a block diagram of a system according to an embodiment of the present invention;

[0015] Figure 8Illustrates a block diagram of a second system according to an embodiment of the present invention;

[0016] Figure 9 Illustrates a block diagram of a third system according to an embodiment of the present invention;

[0017] Figure 10 Illustrates a block diagram of a system on a chip (SoC) according to an embodiment of the present invention;

[0018] Figure 11 Illustrates a block diagram for converting binary instructions in a source instruction set into binary instructions in a target instruction set in contrast to the use of a software instruction converter according to an embodiment of the present invention;

[0019] Figure 12 Illustrates a processor architecture on which embodiments of the present invention may be implemented;

[0020] Figure 13 Illustrates a plurality of packed data elements containing real and complex values according to one embodiment;

[0021] Figure 14A -B Illustrates different architectures on which embodiments of the present invention may be implemented;

[0022] Figure 15 Illustrates a method according to an embodiment of the present invention;

[0023] Figure 16 Illustrates a method according to another embodiment of the present invention. Detailed Description

[0024] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention described below. However, those skilled in the art will appreciate that embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of embodiments of the invention.

[0025] Exemplary Processor Architectures, Instruction Formats, and Data Types

[0026] An instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, bit positions) to specify, among other things, the operation to be performed (opcode) and the operands (on which the operation is to be performed). Some instruction formats are further decomposed by the definition of instruction templates (or sub-formats). For example, an instruction template of a given instruction format can be defined to have different subsets of the fields of the instruction format (the included fields typically being in the same order, but at least some having different bit positions since fewer fields are included) and / or can be defined to have a given field interpreted differently. Thus, each instruction of the ISA is represented using a given instruction format (and, if defined, a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field for specifying that opcode and operand fields for selecting the operands (source1 / destination and source2); and an occurrence of that ADD instruction in an instruction stream will have specific contents in the operand fields that select the specific operands.

[0027] Embodiments of the instructions described herein may be implemented in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instructions may execute on such systems, architectures, and pipelines, but are not limited to those detailed.

[0028] General vector-friendly instruction format

[0029] A vector-friendly instruction format is an instruction format suitable for vector instructions (e.g., there are certain fields specific to vector operations). While embodiments are described in which both vector and scalar operations are supported by the vector-friendly instruction format, alternative embodiments use only vector operations with the vector-friendly format.

[0030] Figure 1A-1B is a block diagram that shows a general vector-friendly instruction format and its instruction templates according to an embodiment of the present invention. Figure 1A is a block diagram that shows a general vector-friendly instruction format and its Category A instruction template according to an embodiment of the present invention; while Figure 1B is a block diagram that shows a general vector-friendly instruction format and its Category B instruction template according to an embodiment of the present invention. Specifically, for the general vector-friendly instruction format 100, Category A and Category B instruction templates are defined, both of which include a no-memory-access 105 instruction template and a memory-access 120 instruction template. The term "general" in the context of the vector-friendly instruction format means that the instruction format is not tied to any particular instruction set.

[0031] While embodiments of the present invention will be described where a vector-friendly instruction format supports the following: a 64-byte vector operand length (or size) with 32-bit (4-byte) or 64-bit (8-byte) data element widths (or sizes) (and thus, a 64-byte vector is composed of 16 double-word sized elements or alternatively 8 quad-word sized elements); a 64-byte vector operand length (or size) with 16-bit (2-byte) or 8-bit (1-byte) data element widths (or sizes); a 32-byte vector operand length (or size) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes); and a 16-byte vector operand length (or size) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes); alternative embodiments may support more, fewer, and / or different vector operand sizes (e.g., a 256-byte vector operand) with more, fewer, or different data element widths (e.g., a 128-bit (16-byte) data element width).

[0032] Figure 1A The class A instruction templates in include: 1) within the no-memory-access 105 instruction template, a no-memory-access, full round control type operation 110 instruction template and a no-memory-access, data transformation type operation 115 instruction template are shown; and 2) within the memory-access 120 instruction template, a memory-access, temporary 125 instruction template and a memory-access, non-temporary 130 instruction template are shown. Figure 1B The class B instruction templates in Figure 1B include: 1) within the no-memory-access 105 instruction template, a no-memory-access, write mask control, partial round control type operation 112 instruction template and a no-memory-access, write mask control, vsize type operation 117 instruction template are shown; and 2) within the memory-access 120 instruction template, a memory-access, write mask control 127 instruction template is shown.

[0033] The general vector-friendly instruction format 100 includes Figure 1A-1B the following fields listed in order as shown in Figure 1A-1B .

[0034] Format field 140 - The specific value (instruction format identifier value) in this field uniquely identifies the vector-friendly instruction format and thus identifies the occurrence of an instruction in the vector-friendly instruction format in an instruction stream. Thus, this field is optional in the sense that it is not needed for an instruction set that only has the general vector-friendly instruction format.

[0035] Base operation field 142 - Its content differentiates different base operations.

[0036] Register index field 144 - Its content directly or through address generation specifies the locations of source and destination operands (whether they are in registers or in memory). These include a sufficient number of bits for selecting N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. Although in one embodiment N can be up to three source and one destination register, alternative embodiments can support more or fewer source and destination registers (e.g., can support up to two sources, where one of these sources also serves as the destination; can support up to three sources, where one of these sources also serves as the destination; can support up to two sources and one destination).

[0037] Modifier field 146 - Its content distinguishes the occurrence of instructions that specify memory access in the general vector instruction format from those that do not; that is, it distinguishes between the no-memory-access 105 instruction template and the memory-access 120 instruction template. Memory access operations read and / or write to the memory hierarchy (in some cases using values in registers to specify source and / or destination addresses), while non-memory access operations do not (e.g., source and destination are registers). Although in one embodiment this field also selects between three different ways to perform memory address arithmetic, alternative embodiments can support more, fewer, or different ways to perform memory address arithmetic.

[0038] Augmentation operation field 150 - Its content distinguishes which of a variety of different operations are to be performed in addition to the base operation. This field is context specific. In one embodiment of the present invention, this field is divided into a category field 168, an alpha field 152, and a beta field 154. The augmentation operation field 150 allows a general group of operations to be performed in a single instruction rather than in 2, 3, or 4 instructions.

[0039] Scale field 160 - Its content allows the scaling of the content of the index field used for memory address generation (e.g., for address generation using 2 * scale * index + base).

[0040] Displacement field 162A - Its content is used as part of memory address generation (e.g., for address generation using 2 * scale * index + base + displacement).

[0041] Displacement factor field 162B (note that the juxtaposition of displacement field 162A directly over displacement factor field 162B indicates that one or the other is used)—its content is used as part of address generation; it specifies the displacement factor to be scaled by the size (N) of the memory access—where N is the number of bytes in the memory access (e.g., for address generation using 2 * index + base address + scaled displacement). Redundant low-order bits are ignored, and thus, the content of the displacement factor field is multiplied by the total size (N) of the memory operand to generate the final displacement to be used in the effective address calculation. The value of N is determined by the processor hardware at runtime based on the full opcode field 174 (described later herein) and the data manipulation field 154C. The displacement field 162A and the displacement factor field 162B are optional in the sense that they are not used for the memoryless access 105 instruction template and / or different embodiments may implement only one or none of the two.

[0042] Data element width field 164—its content identifies which of a plurality of data element widths is to be used (in some embodiments for all instructions; in other embodiments for only some of the instructions). This field is optional in the sense that if only one data element width is supported and / or some aspect of the opcode is used to support the data element width, then this field is not required.

[0043] Write mask field 170 - Its content controls on a data element location basis whether that data element location in the destination vector operand reflects the results of the base operation and the augmentation operation. The category A instruction templates support merge write masking, while the category B instruction templates support both merge and zeroing write masking. In merge, the vector mask allows any set of elements in the destination to be protected from being updated during the execution of any operation (specified by the base operation and the augmentation operation); in another embodiment, the old value of each element of the destination where the corresponding mask bit has 0 is saved. In contrast, in zeroing, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one embodiment, the elements of the destination are set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of the elements being modified, from the first to the last); however, the elements being modified need not be contiguous. Thus, the write mask field 170 allows partial vector operations, including loads, stores, arithmetic, logical, and so on. While embodiments of the present invention are described where the content of the write mask field 170 selects one of a plurality of write mask registers containing the write mask to be used (and thus the content of the write mask field 170 indirectly identifies the masking to be performed), alternative embodiments instead or additionally allow the content of the mask write field 170 to directly specify the masking to be performed.

[0044] Immediate number field 172 - Its content allows the specification of an immediate number. This field is optional in the sense that it does not exist in implementations that do not support the general vector friendly format for immediates and it does not exist in instructions that do not use immediates.

[0045] Category field 168 - Its content discriminates between different categories of instructions. Refer to Figure 1A -B, the content of this field selects between category A and category B instructions. In Figure 1A -B, rounded rectangles are used to indicate the specific values presented in the field (e.g., category A 168A and category B 168B corresponding to the category field 168 in Figure 1A -B).

[0046] Instruction templates for category A

[0047] In the case of the non-memory access 105 instruction template of category A, the α field 152 is decoded as the RS field 152A, the content of which identifies which of the different amplification operation types is to be performed (e.g., rounding 152A.1 and data transformation 152A.2 are correspondingly specified for the non-memory access, rounding type operation 110, and non-memory access, data transformation type operation 115 instruction templates), while the β field 154 identifies which of the operations of the specified type is to be performed. In the non-memory access 105 instruction template, the scale field 160, the displacement field 162A, and the displacement scale field 162B do not exist.

[0048] Non-memory access instruction template - full rounding control type operation

[0049] In the non-memory access full rounding control type operation 110 instruction template, the β field 154 is decoded as the rounding control field 154A, the content of which provides static rounding. Although in the described embodiments of the present invention, the rounding control field 154A includes the suppression of all floating-point exceptions (SAE) field 156 and the rounding operation control field 158, alternative embodiments may support encoding both of these concepts into the same field, or having only one or the other of these concepts / fields (e.g., may have only the rounding operation control field 158).

[0050] SAE field 156 - the content of which identifies whether to disable the reporting of exception events; when the content of the SAE field 156 indicates that suppression is enabled, a given instruction does not report any kind of floating-point exception flag and does not raise any floating-point exception handler.

[0051] Rounding operation control field 158 - the content of which identifies which of a set of rounding operations is to be performed (e.g., round up, round down, round towards zero, and round to nearest). Thus, the rounding operation control field 158 allows for a change in the rounding mode on an instruction-by-instruction basis. In one embodiment of the present invention, where the processor includes a control register for specifying the rounding mode, the content of the rounding operation control field 150 overrides that register value.

[0052] Non-memory access instruction template - data transformation type operation

[0053] In the non-memory access data transformation type operation 115 instruction template, the β field 154 is decoded as the data transformation field 154B, the content of which identifies which of the multiple data transformations is to be performed (e.g., no data transformation, swizzle, broadcast).

[0054] In the case of the memory access 120 instruction template of category A, the α field 152 is decoded as the eviction hint field 152B, the content of which identifies which of the eviction hints is to be used (inFigure 1A In it, the temporary 152B.1 and non-temporary 152B.2 are respectively designated for memory access, temporary 125 instruction templates, and memory access, non-temporary 130 instruction templates), while the β field 154 is decoded as a data manipulation field 154C, the content of which identifies which of a plurality of data manipulation operations (also known as primitives) is to be executed (e.g., no manipulation; broadcast; up-conversion of the source; and down-conversion of the destination). The memory access 120 instruction template includes a scale field 160 and optionally includes a displacement field 162A or a displacement scale field 162B.

[0055] Vector memory instructions perform vector loads from memory and vector stores to memory through conversion support. As with conventional vector instructions, vector memory instructions transfer data to / from memory in a data element-wise manner, and the elements actually transferred are indicated by the content of a vector mask selected as a write mask.

[0056] Memory access instruction template - temporary

[0057] Temporary data is data that is likely to be reused quickly enough to benefit from caching. However, this is a hint, and different processors may implement it in different ways, including completely ignoring the hint.

[0058] Memory access instruction template - non-temporary

[0059] Non-temporary data is data that is unlikely to be reused quickly enough to benefit from caching in the level 1 cache and should be given priority for eviction. However, this is a hint, and different processors may implement it in different ways, including completely ignoring the hint.

[0060] Instruction templates of category B

[0061] In the case of the instruction template of category B, the α field 152 is decoded as a write mask control (Z) field 152C, the content of which identifies whether the write masking controlled by the write mask field 170 should be merged or zeroed.

[0062] In the case of the non-memory access 105 instruction template of class B, a portion of the β field 154 is decoded as the RL field 157A, the content of which identifies which of the different amplification operation types is to be performed (e.g., rounding 157A.1 and vector length (VSIZE) 157A.2 are correspondingly specified for the non-memory access, write mask control, partial rounding control type operation 112 instruction template, and the non-memory access, write mask control, VSIZE type operation 117 instruction template), while the remaining portion of the β field 154 identifies which operation of the specified type is to be performed. In the non-memory access 105 instruction template, the scale field 160, the displacement field 162A, and the displacement scale field 162B do not exist.

[0063] In the non-memory access, write mask control, partial rounding control type operation 110 instruction template, the remaining portion of the β field 154 is decoded as the rounding operation field 159A, and exception event reporting is disabled (the given instruction does not report any kind of floating-point exception flag and does not invoke any floating-point exception handler).

[0064] The rounding operation control field 159A - like the rounding operation control field 158, its content identifies which of a set of rounding operations is to be performed (e.g., round up, round down, round towards zero, and round to nearest). Thus, the rounding operation control field 159A allows for a change in the rounding mode on an instruction-by-instruction basis. In one embodiment of the present invention, where the processor includes a control register for specifying the rounding mode, the content of the rounding operation control field 150 overrides that register value.

[0065] In the non-memory access, write mask control, VSIZE type operation 117 instruction template, the remaining portion of the β field 154 is decoded as the vector length field 159B, the content of which identifies which of the multiple data vector lengths is to be performed (e.g., 128, 256, or 512 bytes).

[0066] In the case of the memory access 120 instruction template of class B, a portion of the β field 154 is decoded as the broadcast field 157B, the content of which identifies whether a broadcast type data manipulation operation is to be performed, while the remaining portion of the β field 154 is decoded as the vector length field 159B. The memory access 120 instruction template includes the scale field 160 and optionally includes the displacement field 162A or the displacement scale field 162B.

[0067] Regarding the general vector friendly instruction format 100, the full opcode field 174 is shown, including a format field 140, a base operation field 142, and a data element width field 164. Although one embodiment is shown in which the full opcode field 174 includes all of these fields, in embodiments that do not support all of these fields, the full opcode field 174 includes fewer than all of these fields. The full opcode field 174 provides an operation code (opcode).

[0068] The expand operation field 150, the data element width field 164, and the write mask field 170 allow these features to be specified on a per-instruction basis in the general vector friendly instruction format.

[0069] The combination of the write mask field and the data element width field creates typed instructions because they allow the mask to be applied based on different data element widths.

[0070] The various instruction templates established within categories A and B are beneficial in different contexts. In some embodiments of the present invention, different processors or different cores within a processor may support only category A, only category B, or both categories. For example, a high-performance general out-of-order core intended for general computing may support only category B, a core intended primarily for graphics and / or scientific (throughput) computing may support only category A, and a core intended for both may support both categories (of course, a core with some mix of templates and instructions from both categories but not all templates and instructions from both categories is within the bounds of the present invention). Similarly, a single processor may include multiple cores, all of which support the same category or where different cores support different categories. For example, in a processor with separate graphics and general cores, one of the graphics cores intended primarily for graphics and / or scientific computing may support only category A, while one or more of the general cores may be high-performance general cores with out-of-order operation and register renaming intended for general computing that support only category B. Another processor without a separate graphics core may include more than one general in-order or out-of-order core that supports both categories A and B. Of course, features from one category may also be implemented in the other category in different embodiments of the present invention. Programs written in a high-level language will be translated (e.g., just-in-time compiled or statically compiled) into multiple different runnable forms, including: 1) a form with only instructions of the category supported by the target processor for running; or 2) a form with alternative routines written using different combinations of instructions from all categories and having control flow code that selects a routine to run based on the instructions supported by the processor (which is currently running the code).

[0071] VEX instruction format

[0072] VEX encoding allows instructions to have more than two operands and allows SIMD vector registers to be longer than 28 bits. The use of the VEX prefix provides a three-operand (or more) syntax. For example, a previous two-operand instruction performed an operation such as A = A + B, which overwrote the source operand. The use of the VEX prefix enables the operands to perform a non-destructive operation such as A = B + C.

[0073] Figure 2A Illustrates an exemplary AVX instruction format, including a VEX prefix 202, a true opcode field 230, a Mod R / M byte 240, a SIB byte 250, a displacement field 262, and an IMM8 272. Figure 2B Illustrates which fields from Figure 2A constitute the complete opcode field 274 and the base operation field 241. Figure 2C Illustrates which fields from Figure 2A constitute the register index field 244.

[0074] The VEX prefix (bytes 0-2) 202 is encoded in a three-byte form. The first byte is the format field 290 (VEX byte 0, bits [7:0]), which contains an explicit C4 byte value (a unique value for differentiating C4 instruction formats). The second and third bytes (VEX bytes 1-2) include multiple bit fields that provide specific capabilities. Specifically, the REX field 205 (VEX byte 1, bits [7-5]) consists of the VEX.R bit field (VEX byte 1, bit [7] - R), the VEX.X bit field (VEX byte 1, bit [6] - X), and the VEX.B bit field (VEX byte 1, bit [5] - B). The other fields of the instruction are encoded as the lower three bits of the register index known in the art (rrr, xxx, and bbb), such that Rrrr, Xxxx, and Bbbb can be formed by adding VEX.R, VEX.X, and VEX.B. The opcode mapping field 215 (VEX byte 1, bits [4:0] - mmmmm) includes the content encoding the leading opcode byte meant. The W field 264 (VEX byte 2, bit [7] – W) is denoted by the notation VEX.X and provides different functions according to the instruction. The function of VEX.vvvv 220 (VEX byte 2, bits [6:3] - vvvv) can include the following items: 1) VEX.vvvv encodes the first source register operand specified in inverted (1s complement) form and is valid for instructions with two or more source operands; 2) VEX.vvvv encodes the destination register operand specified in 1s complement form for certain vector shifts; or 3) VEX.vvvv does not encode any operand, this field is reserved and should contain 1111b. If the VEX.L 268 size field (VEX byte 2, bit [2] - L) = 0, it indicates a 28-bit vector; if VEX.L = 1, it indicates a 256-bit vector. The prefix encoding field 225 (VEX byte 2, bits [1:0] - pp) provides additional bits for the base operation field 241.

[0075] The true opcode field 230 (byte 3) is also known as the opcode byte. Parts of the opcode are specified in this field.

[0076] The MOD R / M field 240 (byte 4) includes the MOD field 242 (bits [7-6]), the Reg field 244 (bits [5-3]), and the R / M field 246 (bits [2-0]). The functions of the Reg field 244 can include the following items: encoding a destination register operand or a source register operand (the rrr of Rrrr), or being treated as an opcode extension and not being used to encode any instruction operand. The functions of the R / M field 246 can include the following items: encoding an instruction operand that references a memory address, or encoding a destination register operand or a source register operand.

[0077] The content of the Scale, Index, Base (SIB)-scale field 250 includes SS252 (bits [7-6]), which is used for memory address generation. The content of SIB.xxx 254 (bits [5-3]) and SIB.bbb 256 (bits [2-0]) has been previously mentioned with respect to the register indices Xxxx and Bbbb.

[0078] The displacement field 262 and the immediate field (IMM8) 272 contain data.

[0079] Exemplary Register Architecture

[0080] Figure 3 is a block diagram of a register architecture 300 according to an embodiment of the present invention. In the illustrated embodiment, there are 32 vector registers 310 that are 512 bits wide; these registers are referred to as zmm0 through zmm31. The lower-order 256 bits of the lower 6 zmm registers are overlaid on the registers ymm0-15. The lower-order 128 bits of the lower 6 zmm registers (the lower-order 128 bits of the ymm registers) are overlaid on the registers xmm0-15.

[0081] General-purpose registers 325 - In the illustrated embodiment, there are sixteen 64-bit general-purpose registers that are used together with the existing x86 addressing modes to address memory operands. These registers are referred to by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0082] The scalar floating-point stack register file (x87 stack) 345, on which the MMX packed integer flat register file 350 is aliased - In the illustrated embodiment, the x87 stack is an eight-element stack for performing scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set extension; and the MMX registers are used to perform operations on 64-bit packed integer data and are also used to save operands for some operations performed between the MMX and XMM registers.

[0083] Alternative embodiments of the present invention may use wider or narrower registers. Additionally, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0084] Exemplary Core Architectures, Processors, and Computer Architectures

[0085] Processor cores may be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) general-purpose in-order cores intended for general-purpose computing; 2) high-performance general-purpose out-of-order cores intended for general-purpose computing; 3) specialized cores intended primarily for graphics and / or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more specialized cores intended primarily for graphics and / or scientific (throughput). Such different processors result in different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor on a separate die in the same package as the CPU; 3) a coprocessor on the same die as the CPU (in which case, such a coprocessor is sometimes referred to as specialized logic, such as integrated graphics and / or scientific (throughput) logic, or is referred to as a specialized core); and 4) a system-on-chip that may include the described CPU (sometimes referred to as an application core or application processor), the coprocessor described above, and additional functionality on the same die. The exemplary core architectures are described next, followed by a description of exemplary processors and computer architectures. Specific details herein are circuits (units) including exemplary cores, processors, etc.

[0086] Exemplary Core Architectures

[0087] Figure 4A is a block diagram that shows both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline in accordance with an embodiment of the present invention. Figure 4B is a block diagram that shows both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor in accordance with an embodiment of the present invention. Figure 4A The solid boxes in -B show the in-order pipeline and in-order core, while the optional additional of the dashed boxes shows the register renaming, out-of-order issue / execution pipeline and core. Given that the in-order aspects are a subset of the out-of-order aspects, the out-of-order aspects will be described.

[0088] In Figure 4AIn it, the processor pipeline 400 includes an instruction fetch stage 402, a length decoding stage 404, a decoding stage 406, an allocation stage 408, a renaming stage 410, a scheduling (also known as dispatch or issue) stage 412, a register read / memory read stage 414, an execution stage 416, a write-back / memory write stage 418, an exception handling stage 422, and a commit stage 424.

[0089] Figure 4B A processor core 490 is shown, which includes a front-end unit 430 coupled to an execution engine unit 450, and both are coupled to a memory unit 470. The core 490 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core 490 can be a specialized core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, and so on.

[0090] The front-end unit 430 includes a branch prediction unit 432 coupled to an instruction cache unit 434, the instruction cache unit 434 is coupled to an instruction translation lookaside buffer (TLB) 436, which is coupled to an instruction fetch unit 438, and the instruction fetch unit 438 is coupled to a decoding unit 440. The decoding unit 440 (or decoder) can decode instructions and generate as output one or more micro-operations, microcode entry points, micro-instructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from the original instructions. Using a variety of different mechanisms, the decoding unit 440 can be implemented. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), and so on. In one embodiment, the core 490 includes a microcode ROM or another medium (e.g., in the decoding unit 440 or otherwise within the front-end unit 430) that stores microcode for certain macro-instructions. The decoding unit 440 is coupled to a rename / allocator unit 452 in the execution engine unit 450.

[0091] The execution engine unit 450 includes a rename / allocator unit 452 coupled to a retirement unit 454 and a set of one or more scheduler units 456. The scheduler units 456 represent any number of different schedulers, including reservation stations, a central instruction window, and the like. The scheduler units 456 are coupled to a physical register file unit 458. Each of the physical register file units 458 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., an instruction pointer that is the address of the next instruction to be executed), and the like. In one embodiment, the physical register file unit 458 includes a vector register unit and a scalar register unit. These register units may provide architected vector registers, vector mask registers, and general-purpose registers. The physical register file unit 458 is overlapped with the retirement unit 454 to show various ways in which register renaming and out-of-order execution can be implemented (e.g., using a reorder buffer and a retirement register file; using a future file, a history buffer, and a retirement register file; using a register map and a pool of registers; etc.). The retirement unit 454 and the physical register file unit 458 are coupled to an execution cluster 460. The execution cluster 460 includes a set of one or more execution units 462 and a set of one or more memory access units 464. The execution units 462 may perform various operations (e.g., shift, add, subtract, multiply) and operate on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include multiple execution units or only one execution unit that all perform all functions. The scheduler units 456, the physical register file unit 458, and the execution cluster 460 are shown as potentially plural because certain embodiments create separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline, each having its own scheduler unit, physical register file unit, and / or execution cluster—and in the case of a separate memory access pipeline, where certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit 464). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, and the remainder are in-order.

[0092] The set of memory access units 464 is coupled to the memory unit 470, which includes a data TLB unit 472 coupled to a data cache unit 474, and the data cache unit 474 is coupled to a level 2 (L2) cache unit 476. In one exemplary embodiment, the memory access units 464 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 472 in the memory unit 470. An instruction cache unit 434 is further coupled to the level 2 (L2) cache unit 476 in the memory unit 470. The L2 cache unit 476 is coupled to one or more other levels of cache and ultimately to main memory.

[0093] By way of example, an exemplary register renaming, out-of-order issue / execution core architecture may implement a pipeline 400 as follows: 1) an instruction fetch 438 performs a fetch and length decoding stage 402 and 404; 2) a decode unit 440 performs a decoding stage 406; 3) a rename / allocator unit 452 performs an allocation stage 408 and a rename stage 410; 4) a scheduler unit 456 performs a scheduling stage 412; 5) a physical register file unit 458 and a memory unit 470 perform a register read / memory read stage 414; an execution cluster 460 performs an execution stage 416; 6) the memory unit 470 and the physical register file unit 458 perform a write-back / memory write stage 418; 7) various units may be involved in an exception handling stage 422; and 8) a retirement unit 454 and the physical register file unit 458 perform a commit stage 424.

[0094] The core 490 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added with more recent versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, CA; the ARM instruction set of ARM Holdings of Sunnyvale, CA (with optional additional extensions such as NEON)), including the instructions described herein. In one embodiment, the core 490 includes logic for supporting packed data instruction set extensions (e.g., AVX1, AVX2), thus allowing operations used by many multimedia applications to be performed using packed data.

[0095] It should be understood that the core may support multithreading (two or more parallel sets of running operations or threads), and may do so in a variety of ways, including time-sliced multithreading, simultaneous multithreading (wherein in the case where a single physical core provides a logical core for each of the threads, that physical core is performing simultaneous multithreading), or a combination thereof (e.g., time-sliced fetching and decoding followed by simultaneous multithreading such as in Intel® Hyper-Threading Technology).

[0096] Although register renaming is described in the context of out-of-order operation, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated embodiments of the processor also include separate instruction and data cache units 434 / 474 and a shared L2 cache unit 476, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a level 1 (L1) internal cache, or multiple levels of internal caches. In some embodiments, the system may include a combination of an internal cache and an external cache external to the core and / or the processor. Alternatively, all caches may be external to the core and / or the processor.

[0097] Specific exemplary in-order core architecture

[0098] Figure 5A -B shows a more specific exemplary in-order core architecture of a core that will be one of several logic blocks in a chip (including other cores of the same type and / or different types). The logic blocks communicate via a high-bandwidth interconnect network (e.g., a ring network) with some fixed functional logic, a memory I / O interface, and other necessary I / O logic depending on the application.

[0099] Figure 5A is a block diagram of a single processor core according to an embodiment of the present invention, along with its connections to the on-die interconnect network 502 and a local subset of its level 2 (L2) cache 504. In one embodiment, the instruction decoder 500 supports the x86 instruction set with packed data instruction set extensions. The L1 cache 506 allows low-latency access to cache memory into scalar and vector units. Although in one embodiment (for simplicity of design), the scalar unit 508 and the vector unit 510 use separate register sets (correspondingly, scalar registers 512 and vector registers 514), and the data transferred between them is written to memory and then read back from the level 1 (L1) cache 506, alternative embodiments of the present invention may use different means (e.g., using a single register set or including a communication path that allows data to be transferred between the two register banks without being written and read back).

[0100] The local subset of the L2 cache 504 is part of the global L2 cache, which is partitioned into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache 504. Data read by a processor core is stored in its L2 cache subset 504 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 504 and purged from other subsets if necessary. The ring network ensures the consistency of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. In some embodiments, each ring data-path is 1024-bits wide in each direction.

[0101] Figure 5B is part of a processor core according to an embodiment of the present invention Figure 5A expanded view. Figure 5B includes a portion of the L1 data cache 506A including the L1 cache 504, and more details regarding the vector unit 510 and vector registers 514. Specifically, the vector unit 510 is a 6-wide vector processing unit (VPU) (see 16-wide ALU 528) that operates on one or more of integer, single-precision floating, and double-precision floating instructions. The VPU supports shuffling register inputs via a shuffle unit 520 on memory inputs, numerical conversion via numerical conversion units 522A-B, and replication via a replication unit 524.

[0102] Processor with integrated memory controller and graphics

[0103] Figure 6 is a block diagram of a processor 600 according to an embodiment of the present invention that may have more than one core, may have an integrated memory controller, and may have integrated graphics. Figure 6 The solid boxes in show a processor 600 with a collection including a single core 602A, a system agent 610, and one or more bus controller units 616, while the optional additional dashed boxes show an alternative processor 600 with a collection including multiple cores 602A-N, one or more integrated memory controller units 614 in the system agent unit 610, and dedicated logic 608.

[0104] Thus, different implementations of the processor 600 may include: 1) a CPU with dedicated logic 608 that is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and cores 602A-N that are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, a combination of the two); 2) a coprocessor with cores 602A-N that are a large number of dedicated cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor with cores 602A-N that are a large number of general-purpose in-order cores. Thus, the processor 600 can be a general-purpose processor, a coprocessor, or a special-purpose processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, and so on. The processor can be implemented on one or more chips. Using any one of a number of processing technologies (such as, for example, BiCMOS, CMOS, or NMOS), the processor 600 can be implemented on one or more substrates and / or as part thereof.

[0105] The memory hierarchy includes one or more levels of cache within the cores 604A-N, a collection of shared cache units 606, or one or more, and external memory (not shown) coupled to a collection of integrated memory controller units 614. The collection of shared cache units 606 can include one or more mid-level caches, such as a level 2 (L2), level 3 (L3), level 4 (L4), or other level of cache, a last-level cache (LLC), and / or a combination thereof. Although in one embodiment, a ring-based interconnect unit 612 interconnects the integrated graphics logic 608, the collection of shared cache units 606, and the system agent unit 610 / integrated memory controller unit 614, alternative embodiments can use any number of well-known techniques for interconnecting such units. In one embodiment, coherence is maintained between one or more cache units 606 and the cores 602-A-N.

[0106] In some embodiments, one or more of the cores 602A-N have multi-threading capabilities. The system agent 610 includes those components that coordinate and operate the cores 602A-N. The system agent unit 610 can include, for example, a power control unit (PCU) and a display unit. The PCU can be or include the logic and components needed to regulate the power states of the integrated graphics logic 608 and the cores 602A-N. The display unit is used to drive one or more externally connected displays.

[0107] The core 602A-N can be homogeneous or heterogeneous with respect to the architectural instruction set; that is, two or more cores of the core 602A-N can have the ability to run the same instruction set, while other cores can have the ability to run a different instruction set or only a subset of that instruction set.

[0108] Exemplary Computer Architecture

[0109] Figures 7-10 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptop computers, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular telephones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices that can incorporate the processors and / or other operational logic disclosed herein are generally suitable.

[0110] Now referring to Figure 7 , shown is a block diagram of a system 700 in accordance with one embodiment of the present invention. System 700 may include one or more processors 710, 715 coupled to a controller hub 720. In one embodiment, controller hub 720 includes a Graphics Memory Controller Hub (GMCH) 790 and an Input / Output Hub (IOH) 750 (which may be on separate chips); GMCH 790 includes a memory and graphics controller to which memory 740 and a coprocessor 745 are coupled; IOH 750 couples input / output (I / O) devices 760 to GMCH 790. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), and memory 740 and coprocessor 745 are directly coupled to processors 710, and controller hub 720 in a single chip with IOH 750.

[0111] The optional nature of additional processor 715 is denoted by a broken line in Figure 7 . Each processor 710, 715 may include one or more of the processing cores described herein and may be a version of processor 600.

[0112] Memory 740 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two memories. For at least one embodiment, controller hub 720 communicates with processors 710, 715 via a multi-drop bus such as a front side bus (FSB), a point-to-point interface, or a similar connection 795.

[0113] In one embodiment, the coprocessor 745 is a special-purpose processor such as, for example, a high-throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and the like. In one embodiment, the controller hub 720 may include an integrated graphics accelerator.

[0114] There can be a wide variety of differences between the physical resources 710, 7155 in terms of a spectrum of specifications including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

[0115] In one embodiment, the processor 710 executes instructions that control general types of data processing operations. Coprocessor instructions may be embedded within the instructions. The processor 710 identifies these coprocessor instructions as being of a type to be executed by an attached coprocessor 745. Accordingly, the processor 710 issues these coprocessor instructions (or control signals representative of the coprocessor instructions) to the coprocessor 745 on a coprocessor bus or other interconnect. The coprocessor 745 receives and executes the received coprocessor instructions.

[0116] Now refer Figure 8 , shown is a block diagram of a first more specific exemplary system 800 in accordance with an embodiment of the present invention. As Figure 8 shown, the multi-processor system 800 is a point-to-point interconnect system and includes a first processor 870 and a second processor 880 coupled via a point-to-point interconnect 850. Each of processors 870 and 880 may be some version of the processor 600. In one embodiment of the present invention, processors 870 and 880 are respectively processors 710 and 715, and the coprocessor 838 is the coprocessor 745. In another embodiment, processors 870 and 880 are respectively processors 710, coprocessor 745.

[0117] Processors 870 and 880 are shown respectively including integrated memory controller (IMC) units 872 and 882. Processor 870 also includes point-to-point (P-P) interfaces 876 and 878 as part of its bus controller unit; similarly, the second processor 880 includes P-P interfaces 886 and 888. Using P-P interface circuits 878, 888, processors 870, 880 may exchange information via the point-to-point (P-P) interface 850. As Figure 8 shown, the IMCs 872 and 882 couple the processors to respective memories (i.e., memory 832 and memory 834), which may be portions of the main memory locally attached to the respective processors.

[0118] Using point-to-point interface circuits 876, 894, 886, 898, processors 870, 880 can each exchange information with chipset 890 via respective P-P interfaces 852, 854. Chipset 890 can optionally exchange information with coprocessor 838 via high performance interface 892. In one embodiment, coprocessor 838 is a dedicated processor such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and so on.

[0119] A shared cache (not shown) can be included in either processor or outside of both processors and connected to the processors via a P-P interconnect such that if a processor is placed in a low power mode, local cache information of either or both processors can be stored in the shared cache.

[0120] Chipset 890 can be coupled to first bus 816 via interface 896. In one embodiment, first bus 816 can be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another I / O interconnect bus, although the scope of the present invention is not so limited.

[0121] As Figure 8 shown, various I / O devices 814 can be coupled to first bus 816 along with bus bridge 818, which couples first bus 816 to second bus 820. In one embodiment, one or more additional processors 815 such as a coprocessor, a high throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or a Digital Signal Processing (DSP) unit), a Field Programmable Gate Array, or any other processor are coupled to first bus 816. In one embodiment, second bus 820 can be a Low Pin Count (LPC) bus. Various devices can be coupled to second bus 820 including, for example, a keyboard and / or mouse 822, a communication device 827, and a storage unit 828 such as a hard disk drive or other mass storage device, which can include instructions / code and data 830 (in one embodiment). Further, audio I / O 824 can be coupled to second bus 816. Note that other architectures are possible. For example, instead of Figure 8 the point-to-point architecture, the system can implement a multi-drop bus or another such architecture.

[0122] Now referring Figure 9 to, shown is a block diagram of a second more specific exemplary system 900 in accordance with an embodiment of the present invention. Figure 8 and 9 Similar elements in Figure 8 are labeled with like reference numerals, and Figure 9 certain aspects ofFigure 9 Other aspects are difficult to understand.

[0123] Figure 9 It is shown that processors 870, 880 may respectively include integrated memories and I / O control logic ("CL") 972 and 982. Thus, CL 972, 982 includes an integrated memory controller unit and includes I / O control logic. Figure 9 It is shown that not only memories 832, 834 are coupled to CL 872, 882, but also I / O device 914 is coupled to control logic 872, 882. Legacy I / O device 915 is coupled to chipset 890.

[0124] Now refer to Figure 10 , what is shown is a block diagram of SoC 1000 according to an embodiment of the present invention. Figure 6 Similar elements in are labeled with like reference numerals. Also, the dashed boxes are optional features on more advanced SoCs. In Figure 10 , interconnect unit 1002 is coupled to: an application processor 1010, which includes a set of one or more cores 102A-N, cache units 604A-N, and a shared cache unit 606; a system agent unit 610; a bus controller unit 616; an integrated memory controller unit 614; a set of co-processors 1020 or one or more, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 1030; a direct memory access (DMA) unit 1032; and a display unit 1040 for coupling to one or more external displays. In one embodiment, co-processor 1020 includes a dedicated processor, such as, for example, a network or communication processor, a compression engine, a GPGPU, a high throughput MIC processor, an embedded processor, and the like.

[0125] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation means. Embodiments of the present invention may be implemented as program code or a computer program running on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memories and / or storage elements), at least one input device, and at least one output device.

[0126] Such as Figure 8The program code of code 830 shown can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor (such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor).

[0127] The program code can be implemented in a high-level procedural or object-oriented programming language to communicate with the processing system. If desired, the program code can also be implemented in assembly or machine language. In fact, the mechanisms described herein are not limited to any specific programming language. In any case, the language can be a compiled or interpreted language.

[0128] One or more aspects of at least one embodiment can be implemented by representative instructions stored on a machine-readable medium, the representative instructions representing various logics within a processor, which when read by the machine cause the machine to fabricate logics for performing the techniques described herein. Such representations (known as "IP cores") can be stored on a tangible, machine-readable medium and supplied to various customers or manufacturing facilities to be loaded into the manufacturing machines that actually make the logics or processors.

[0129] Such machine-readable storage media can include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media (such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memory (CD-ROM), rewritable compact disk (CD-RW), and magneto-optical disks), semiconductor devices (such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM), magnetic or optical cards, or any other type of medium suitable for storing electronic instructions).

[0130] Accordingly, embodiments of the present invention also include non-transitory, tangible machine-readable media that contain instructions or contain design data, such as a hardware description language (HDL), that define the structures, circuits, devices, processors, and / or system features described herein. Such embodiments can also be referred to as program products.

[0131] Emulation (including binary conversion, code morphing, etc.)

[0132] In some cases, an instruction converter may be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter may transform (e.g., using static binary translation, dynamic binary translation including dynamic compilation), mutate, emulate, or otherwise convert instructions into one or more other instructions to be processed by a core. The instruction converter is implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on the processor, off the processor, or partly on and partly off the processor.

[0133] Figure 11 is a block diagram that illustrates the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 11 shows that using a first compiler 1104, a program in a high-level language 1102 can be compiled to generate first binary code (e.g., x86) 1106, which can be natively run by a processor 1116 with at least one first instruction set core. In some embodiments, the processor 1116 with at least one first instruction set core represents any processor that can generally perform the same functions as an Intel processor with at least one x86 instruction set core, either by compatibly running or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core, or (2) an object code version of an application or other software targeted to run on an Intel processor with at least one x86 instruction set core, so as to obtain generally the same results as an Intel processor with at least one x86 instruction set core. The first compiler 1104 represents a compiler operable to generate binary code 1106 (e.g., object code) of a first instruction set, and the binary code 1106 can be run on the processor 1116 with at least one first instruction set core with or without additional linking processing. Similarly, Figure 11It is shown that with an alternative instruction set compiler 1108, a program in a high-level language 1102 can be compiled to generate alternative instruction set binary code 1110, which can be natively run by a processor 1114 without at least one first instruction set core (e.g., a processor with cores running the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and / or the ARM instruction set of ARM Holdings of Sunnyvale, CA). An instruction converter 1112 is used to convert the first binary code 1106 into code that can be natively run by the processor 1114 without the first instruction set core. This converted code is unlikely to be the same as the alternative instruction set binary code 1110 because it is difficult to make an instruction converter that can do so; however, the converted code will perform general operations and consist of instructions from the alternative instruction set. Thus, the instruction converter 1112 represents software, firmware, hardware, or a combination thereof that allows a processor or another electronic device without a first instruction set processor or core to run the first binary code 1106 through emulation, simulation, or any other process.

[0134] Devices and methods for digital signal processing instructions

[0135] The following describes digital signal processing (DSP) instructions. In one embodiment, the circuits and logic for performing DSP operations are integrated within the execution engine unit 450 shown in Figure 4B , within the various cores described above (e.g., see the cores 602A-N in Figure 6 and 10 ) and / or within the vector unit 510 shown in Figure 5A . For example, the various source and destination registers can be SIMD registers within the physical register file unit 458 in Figure 4B and / or within the vector registers 310 in Figure 3 . The multiplication circuits, adder circuits, accumulator circuits, and other circuits described below can be integrated into the execution components of the architectures described above, by way of example and not limitation, including the execution unit 462 in Figure 4B . However, it should be noted that the basic principles of the present invention are not limited to these particular architectures.

[0136] One embodiment of the present invention includes circuitry and / or logic for processing Digital Signal Processing (DSP) instructions. Specifically, one embodiment includes a multiply-accumulate (MAC) architecture having eight 16x16 bit multipliers and two 64 bit accumulators. The Instruction Set Architecture (ISA) described below can process various multiplication and MAC operations on 128-bit packed (8-bit, 16-bit, or 32-bit data elements) integer, fixed-point, and complex data types. In addition, certain instructions have direct support for high-efficiency Fast Fourier Transform (FFT) and Finite Impulse Response (FIR) filtering, as well as post-processing of the accumulated data through shift, round, and saturation operations.

[0137] One embodiment of the new DSP instructions uses opcode encoding based on the VEX.128 prefix and several SSE / SSE2 / AVX instructions for handling post-processing of data are used together with the DSP ISA. VEX-encoded 128-bit DSP instructions with memory operands may have relaxed memory alignment requirements.

[0138] In one embodiment, the instructions also support a variety of integer and fixed-point data types, including:

[0139] 1) Q31 data type, for signals requiring analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC) with more than 16 bits;

[0140] 2) Q15 data type, which is common in DSP algorithms;

[0141] 3) Complex 16-bit data type; and

[0142] 4) Complex 32-bit data type.

[0143] The Instruction Set Architecture described herein targets a wide range of standard DSP (e.g., FFT, filtering, pattern matching, correlation, polynomial evaluation, etc.) and statistical operations (e.g., mean, moving average, variance, etc.).

[0144] Target applications of embodiments of the present invention include sensors, audio, classification tasks for computer vision, and speech recognition. The DSP ISA described herein includes a wide range of instructions suitable for Deep Neural Networks (DNN), Automatic Speech Recognition (ASR), sensors fused with Kalman filtering, and other major DSP applications. Given weight sequences {w1, w2, … w k} and input sequences {x1, x2, x3, … x n}, many image processing and machine learning tasks require computing y i = w1x i + w2x i+1+……………+w k x i+k-1 The defined result sequence {y1, y2, y3, … y n+1-k}.

[0145] Figure 12 FIG. shows an exemplary processor 1255 on which embodiments of the present invention may be implemented, which includes a plurality of cores 0-N for simultaneously executing multiple instruction threads. The illustrated embodiment includes DSP instruction decoding circuitry / logic 1231 within decoder 1230 and DSP instruction execution circuitry / logic 1341 within execution unit 1240. These pipelined components may perform the operations described herein in response to the decoding and execution of DSP instructions. Although Figure 12 only the details of a single core (core 0) are shown, it will be understood that each of the other cores of processor 1255 may include similar components.

[0146] Before describing the specific details of embodiments of the present invention, a description of the various components of exemplary processor 1255 is provided directly below. Each of the plurality of cores 0-N may include a memory management unit 1290 for performing memory operations (e.g., such as load / store operations), a set of general-purpose registers (GPRs) 1205, a set of vector registers 1206, and a set of mask registers 1207. In one embodiment, multiple vector data elements are packed into each vector register 1206, and the vector register 1206 may be 512 bits wide for storing two 256-bit values, four 128-bit values, eight 64-bit values, sixteen 32-bit values, etc. However, the basic principles of the present invention are not limited to any specific size / type of vector data. In one embodiment, the mask register 1207 includes eight 64-bit operand mask registers for performing bit masking operations on the values stored in the vector register 1206 (e.g., implemented as mask registers k0-k7 described herein). However, the basic principles of the present invention are not limited to any specific mask register size / type.

[0147] Each core 0-N may include dedicated level 1 (L1) cache 1212 and level 2 (L2) cache 1211 for caching instructions and data according to a specified cache management policy. The L1 cache 1212 includes a separate instruction cache 1220 for storing instructions and a separate data cache 1221 for storing data. The instructions and data stored in each processor cache are managed in cache line granularity, which may be of a fixed size (e.g., 64, 128, 512 bytes in length). Each core of this exemplary embodiment has an instruction fetch unit 1210 for fetching instructions from the main memory 1200 and / or the shared level 3 (L3) cache 1216. The instruction fetch unit 1210 includes various well-known components, including: a next instruction pointer 1203 for storing the address of the next instruction to be fetched from the memory 1200 (or one of the caches); an instruction translation lookaside buffer (ITLB) 1204 for storing mappings of recently used virtual to physical instruction addresses to speed up address translation; a branch prediction unit 1202 for inferentially predicting instruction branch addresses; and a branch target buffer (BTB) 1201 for storing branch addresses and target addresses.

[0148] As mentioned, the decoding unit 1230 includes DSP instruction decoding circuitry / logic 1231 for decoding the DSP instructions described herein into micro-operations or "uops", and the execution unit 1240 includes DSP instruction execution circuitry / logic 1241 for executing the DSP instructions. The write-back / retirement unit 1250 retires the executed instructions and writes back the results.

[0149] Conjugate multiply-add and accumulation of the imaginary part between vector-pack double complex and complex numbers

[0150] One embodiment of the present invention uses Figure 14A the architecture shown in to perform conjugate multiply-add and accumulation between double complex and complex numbers (using packed real and imaginary data elements). The described embodiment performs operations on signed words in a 128-bit packed data register. For example, one embodiment stores the packed data values in xmm2 and xmm3 / m128, where xmm2 stores the complex conjugate and xmm3 / m128 stores the complex number.

[0151] In one embodiment, the first accumulator performs the following operation: imaginary((16 + 16i) x (16 - 16i)) + imaginary((16 + 16i) x (16 - 16i)) + 64i = 64i to arithmetic and accumulate the first imaginary component, and the second accumulator performs the following operation: imaginary((16 + 16i) x (16 - 16i)) + imaginary((16 + 16i) x (16 - 16i)) + 64i = 64i to arithmetic and accumulate the second imaginary component (e.g., such as xmm1, xmm2, and xmm3 / m128). However, it should be noted that the basic principle of the present invention is not limited thereto. In the foregoing notation, the numbers represent the number of bits for representing the real and imaginary components of each complex number (e.g., 16 + 16i means a complex number represented by a 16-bit real component and a 16-bit imaginary component).

[0152] A specific embodiment decodes and executes a single instruction to perform conjugate multiply-add and accumulate between a double complex number and a complex number (using packed real and imaginary data elements), which is identified herein by the mnemonic VPCCDPWQIMM. The following code specifies the individual operations performed in one embodiment, where TEMP0 and TEMP1 are registers or memory locations for storing intermediate values and DEST is the destination register:

[0153] TEMP0[33:0] ← (((SRC2[47:32] * SRC3[63:48]) - (SRC2[63:48] * SRC3[47:32])) + ((SRC2[15:0] * SRC3[31:16]) - (SRC2[31:16] * SRC3[15:0])));

[0154] TEMP1[33:0] ← (((SRC2[111:96] * SRC3[127:112]) - (SRC2[127:112] * SRC3[111:96])) + ((SRC2[79:64] * SRC3[95:80]) - (SRC2[95:80] * SRC3[79:64])));

[0155] DEST[63:0] ← AddToQuadword({{30{TEMP0

[33] }}, TEMP0[33:0]}, DEST[63:0]);

[0156] DEST[127:64] ← AddToQuadword({{30{TEMP1

[33] }}, TEMP1[33:0]}, DEST[127:64]);

[0157] Thus, TEMP0 uses data elements from the lower half-precision (i.e., bits 63:0) of SRC2 and SRC3 to store the results of the above multiplications, additions, and subtractions, and TEMP1 uses data elements from the upper half-precision (i.e., bits 127:64) of SRC2 and SRC3 to store the results of the multiplications, additions, and subtractions. Imaginary numbers are generated by these operations because each product involves multiplying an imaginary number by a real number.

[0158] Then, the result in TEMP0 is accumulated with the existing quadword in the lower 64 bits (i.e., 63:0) of DEST, and the result in TEMP1 is accumulated with the existing quadword in the upper 64 bits (i.e., 127:64) of DEST. In one embodiment, the results in TEMP0 and TEMP1 are sign-extended or zero-extended to an appropriate size for accumulating the results with the value from the destination register (e.g., 64 bits). In the specific example shown in the above code, the results are sign-extended. Regardless of the type of extension performed, the final result includes the accumulated imaginary components.

[0159] Back to Figure 14A , the first source register SRC2 1401 stores data elements S2A - S2H, and the second source register SRC3 1402 stores data elements S3A - S3H (S2 is used here as an abbreviation for SCR2, and S3 for SRC3). In one embodiment, elements A, C, E, and G are real numbers, and data elements B, D, F, and H are imaginary numbers. Eight multipliers 1405 multiply each real data element in SRC2 by an imaginary data element in SRC3 and multiply each imaginary data element in SRC2 by a real data element in SRC3 to generate eight imaginary products. In this embodiment, the products are added / subtracted, and what is stored in TEMP0 is S2C*S3D - S2D*S3C + S2A*S3B - S2B*S3A, and what is stored in TEMP1 is S2G*S3H - S2H*S3G + S2E*S3F - S2F*S3E. The first and second sets of adder networks 1410 - 1411 add and subtract the respective imaginary products according to the above code. For example, adder network 1410 performs the addition and subtraction operations:

[0160] S2C*S3D - S2D*S3C + S2A*S3B - S2B*S3A;

[0161] And adder network 1411 performs the addition operation:

[0162] S2G*S3H - S2H*S3G + S2E*S3F - S2F*S3E.

[0163] The result from adder network 1410 is stored in TEMP0, and the result from adder network 1411 is stored in TEMP1. In one embodiment, prior to accumulation, these results are sign-extended or zero-extended to an appropriate size for accumulating the result with the value from the destination register (e.g., 64 bits). In the specific example shown in the code above, the result is sign-extended.

[0164] Accumulation circuitry including adders 1420 - 1421 adds the above results to the previously accumulated result (if any) stored in the SRC1 / DEST register 1460. Specifically, the result generated by adder network 1410 (after being extended) is added to the accumulated data stored in element locations A - D (i.e., lower 64 bits) of the SRC1 / DEST register 1460. The imaginary result is saturated by saturation circuitry 1440 (i.e., if one or more values are greater than the maximum supported value, the maximum value is output). The accumulated result is then stored back into the SRC1 / DEST register 1460 at element locations A - D (lower 64 bits). Similarly, the output of adder network 1411 (after being extended) is added to the accumulated data stored in element locations E - H (higher 64 bits) of the SRC1 / DEST register 1460. The accumulated imaginary result is saturated by saturation circuitry 1441 (if necessary) and stored back into data element locations E - H (higher 64 bits) of the SRC1 / DEST register 1460.

[0165] Figure 15 illustrates a method according to one embodiment. The method may be implemented within the context of the processor architectures described herein, but is not limited to any specific processor architecture.

[0166] At 1501, a first instruction is fetched, which has fields for an opcode and first and second packed data source operands (representing complex numbers with real and imaginary values) and a packed data destination operand. At 1502, the first instruction is decoded. At 1503, the real and imaginary values associated with the first and second source operands are stored as packed data elements in the first and second source registers and the first instruction is scheduled for execution. As mentioned, in one embodiment, the first and second source operands are stored in a 128 - bit packed data register that stores 16 - bit packed data elements, where each packed data element includes a real or imaginary value.

[0167] At 1504, the first decoded instruction is executed to multiply the real value selected from the first operand by the imaginary value selected from the second operand to generate a first imaginary product and to multiply the imaginary value selected from the first operand by the real value selected from the second operand to generate a second imaginary product.

[0168] At 1505, the first and second imaginary products of the selected combination are added and subtracted to respectively generate first and second temporary results. As described above, in one embodiment, this includes the following operations: S2C*S3D - S2D*S3C + S2A*S3B - S2B*S3A and S2G*S3H - S2H*S3G + S2E*S3F - S2F*S3E, where S2C*S3D, S2D*S3C, S2A*S3B, and S2B*S3A are imaginary products of the first set and S2G*S3H, S2H*S3G, S2E*S3F, and S2F*S3E are imaginary products of the second set.

[0169] In one embodiment, at 1505, the first temporary result is zero-extended or sign-extended and combined with the lower 64-bit packed data elements from the destination register (overwriting the 16-bit data elements A - D), and the accumulated result is stored back into the lower four packed data element locations in the destination register. Similarly, the second temporary result is combined with the higher 64-bit packed data elements from the destination register (overwriting the 16-bit data elements E - H) and the accumulated result is stored back into the higher 64 bits in the destination register. In one embodiment, if necessary, the accumulated result is saturated before being stored back into the destination register.

[0170] At 1506, the result of the first instruction is committed to memory (e.g., made globally visible).

[0171] Although the above real and imaginary values are 16 bits in length, the basic principles of the present invention can be implemented using data elements of any size. For example, the real and imaginary components can be 8 bits, 32 bits, or 64 bits while still conforming to the basic principles of the present invention.

[0172] Conjugate multiply and add, negate and sum, and accumulate imaginary parts between vector-packed double complex numbers and complex numbers

[0173] One embodiment of the present invention uses Figure 14A the architecture shown in, to perform conjugate multiply and add, negate and sum, and accumulate imaginary components (using packed real and imaginary values) between double complex numbers and complex numbers. As described below, one embodiment also performs two's complement negation by inverting the bits of the temporary result and adding 1, and can also perform sign extension or zero extension before accumulation. The described embodiment operates on signed words in a 128-bit packed data register. For example, one embodiment stores the packed data values in xmm2 and xmm3 / m128, where xmm2 stores the complex conjugate and xmm3 / m128 stores the complex number.

[0174] In one embodiment, the first accumulator performs the following operation: imaginary -((16 + 16i) x (16 - 16i)) + imaginary ((16 + 16i) x (16 - 16i)) + 64i = 64i to arithmetic and accumulate the first imaginary component and the second accumulator performs the following operation: imaginary -((16 + 16i) x (16 - 16i)) + imaginary ((16 + 16i) x (16 - 16i)) + 64i = 64i to arithmetic and accumulate the second imaginary component (e.g., such as xmm1, xmm2, and xmm3 / m128). However, it should be noted that the basic principle of the present invention is not limited thereto. As mentioned, in the foregoing notation, the numbers represent the number of bits used to represent each number (e.g., 16 + 16i means a complex number represented by a 16-bit real component and a 16-bit imaginary component).

[0175] A specific embodiment decodes and executes a single instruction to perform conjugate multiply-add, negate-sum, and accumulate between a double complex number and a complex number (using packed real and imaginary data elements), identified herein by the mnemonic VPNCCDPWQIMM. The following code specifies the individual operations performed in one embodiment, where TEMP0, TEMP1, TEMP2, and TEMP3 are registers or memory locations for storing intermediate values and DEST is the destination register:

[0176] TEMP0[33:0] ← (((SRC2[47:32] * SRC3[63:48]) - (SRC2[63:48] * SRC3[47:32])) + ((SRC2[15:0] * SRC3[31:16]) - (SRC2[31:16] * SRC3[15:0])));

[0177] TEMP1[33:0] ← (((SRC2[111:96] * SRC3[127:112]) - (SRC2[127:112] * SRC3[111:96])) + ((SRC2[79:64] * SRC3[95:80]) - (SRC2[95:80] * SRC3[79:64])));

[0178] TEMP2[33:0] ← (~TEMP0 [33:0] + 1’b1);

[0179] TEMP3[33:0] ← (~TEMP1 [33:0] + 1’b1);

[0180] (*Two's complement negate*)

[0181] DEST[63:0] ← AddToQuadword({{30{TEMP2

[33] }}, TEMP2[33:0]}, DEST[63:0]);

[0182] DEST[127:64] ← AddToQuadword({{30{TEMP3

[33] }}, TEMP3[33:0]}, DEST[127:64]);

[0183] Thus, TEMP0 uses the data elements from the lower half-precision (i.e., bits 63:0) of SRC2 and SRC3 to store the results of the above multiplications, additions, and subtractions, and TEMP1 uses the data elements from the higher half-precision (i.e., bits 127:64) of SRC2 and SRC3 to store the results of the multiplications, additions, and subtractions. Imaginary numbers are generated by these operations because each product includes an imaginary number multiplied by a real number.

[0184] In one embodiment, according to the property of two's complement negation, the results stored in TEMP0 and TEMP1 are each inverted, and binary 1 is added to the inverted values to negate the temporary results. The negated results are then stored in TEMP2 and TEMP3.

[0185] The negated result in TEMP2 is then accumulated with the existing quadword in the lower 64 bits (i.e., 63:0) of DEST, and the result in TEMP3 is accumulated with the existing quadword in the higher 64 bits (i.e., 127:64) of DEST. Thus, the final result includes multiple accumulated imaginary components.

[0186] Back to Figure 14A, the first source register SRC2 1401 stores data elements S2A - S2H and the second source register SRC3 1402 stores data elements S3A - S3H (S2 is used here as an abbreviation for SRC2 and S3 is SRC3). In one embodiment, elements A, C, E, and G are real numbers and data elements B, D, F, and H are imaginary numbers. Eight multipliers 1405 multiply each real data element in SRC2 by an imaginary data element in SRC3, and multiply each imaginary data element in SRC2 by a real data element in SRC3 to generate eight imaginary products. In this embodiment, the products are added / subtracted and what is stored in TEMP0 is S2C*S3D - S2D*S3C + S2A*S3B - S2B*S3A and, what is added / subtracted and stored in TEMP1 is S2G*S3H - S2H*S3G + S2E*S3F - S2F*S3E. The first and second sets of adder networks 1410 - 1411 add and subtract the respective imaginary products according to the above code. For example, adder network 1410 performs the addition and subtraction operations:

[0187] S2C*S3D - S2D*S3C + S2A*S3B - S2B*S3A;

[0188] And adder network 1411 performs the addition operation:

[0189] S2G*S3H - S2H*S3G + S2E*S3F - S2F*S3E.

[0190] Adder networks 1410 - 1411 or other circuitry / logic (not shown) invert the above temporary results and add binary 1 to the inverted results to generate the final temporary results stored in TEMP2 and TEMP3. As mentioned above, this operation is called two's complement negation, which is used to negate the temporary results.

[0191] An accumulation circuit including adders 1420 - 1421 adds the above results to the previously accumulated results (if any) stored in the SRC1 / DEST register 1460. Specifically, the outputs AN0_A to AN0_D of adder network 1410 are respectively added to the accumulated data elements A - D in the SRC1 / DEST register 1460. The imaginary results are saturated by saturation circuit 1440 (i.e., if one or more values are greater than the maximum supported value, the maximum value is output). The results are then stored back into the destination data elements A - D. Similarly, the outputs AN1_A to AN1_D of adder network 1411 are respectively added to the accumulated data elements E - H in the SRC1 / DEST register 1460. The imaginary results are saturated by saturation circuit 1441 and output back to the destination data elements E - H

[0192] Figure 14B The figure shows additional details of an embodiment including two's complement negation circuits 1470 and 1471 that use two's complement negation to negate the product sums resulting from the respective operations of adder networks 1410 and 1411. Extension circuits 1480 and 1481 receive the negated product sums and correspondingly zero-extend or sign-extend these values to generate results of appropriate size for accumulation with the current SRC1 / DEST 1460 register value (e.g., 64 bits). Zero-extension includes adding a plurality of zeros to a value in one embodiment, while sign-extension includes copying the bit value. Accumulators 1490 - 1491 then use the 64-bit temporary results from the SRC1 / DEST register 1460 and the packed 64-bit values to perform the accumulation operations described herein.

[0193] Figure 16 The figure shows a method according to one embodiment. The method may be implemented within the context of the processor architectures described herein, but is not limited to any specific processor architecture.

[0194] At 1601, a first instruction is fetched that has fields for an opcode and first and second packed data source operands (representing complex numbers with real and imaginary values) and a packed data destination operand. At 1602, the first instruction is decoded. At 1603, the real and imaginary values associated with the first and second source operands are stored as packed data elements in first and second source registers and the first instruction is scheduled for execution. As mentioned, in one embodiment, the first and second source operands are stored in 128-bit packed data registers that store 16-bit packed data elements, where each packed data element includes a real or imaginary value.

[0195] At 1604, the first decoded instruction is executed to multiply the real value selected from the first operand by the imaginary value selected from the second operand to generate a first imaginary product and to multiply the imaginary value selected from the first operand by the real value selected from the second operand to generate a second imaginary product.

[0196] At 1605, the selected combined first and second imaginary products are added and subtracted to correspondingly generate first and second sets of temporary results. As described above, in one embodiment, this includes the operations: S2C*S3D - S2D*S3C + S2A*S3B - S2B*S3A and S2G*S3H - S2H*S3G + S2E*S3F - S2F*S3E, where S2C*S3D, S2D*S3C, S2A*S3B, and S2B*S3A are the imaginary products of the first set and S2G*S3H, S2H*S3G, S2E*S3F, and S2F*S3E are the imaginary products of the second set.

[0197] In 1606, the bits of the first and second temporary results are inverted, and 1 is added to each to correspondingly generate third and fourth temporary results. As mentioned, this can be done using third and fourth storage locations (e.g., TEMP2 and TEMP3).

[0198] In one embodiment, in 1607, after the third and fourth temporary results are sign-extended (or zero-extended), the third temporary result is combined with the packed 64-bit data element in the lower 64 bits of the destination register (16-bit elements A-D) and the accumulated result is stored back into the lower 64 bits of the destination register. Similarly, the fourth temporary result is combined with the packed 64-bit data element in the upper 64 bits of the destination register (16-bit elements E-H) and the accumulated result is stored back into the upper 64 bits of the destination register. In one embodiment, if necessary, the accumulated result is saturated before being stored back into the destination register.

[0199] In 1608, the result of the first instruction is committed to memory (e.g., made globally visible).

[0200] Although the above real and imaginary values are 16 bits in length, the basic principles of the present invention can be implemented using data elements of any size. For example, the real and imaginary components can be 8 bits, 32 bits, or 64 bits while still conforming to the basic principles of the present invention.

[0201] The present disclosure provides a set of technical solutions as follows:

[0202] 1. A processor, comprising:

[0203] A decoder for decoding a first instruction to generate a decoded instruction;

[0204] A first source register for storing a first plurality of packed real and imaginary data elements;

[0205] A second source register for storing a second plurality of packed real and imaginary data elements; and

[0206] An execution circuit for executing the decoded instruction, the execution circuit comprising:

[0207] A multiplier circuit that is configured to select real and imaginary data elements from the first source register and the second source register for multiplication, the multiplier circuit being configured to multiply each selected imaginary data element in the first source register by a selected real data element in the second source register, and to multiply each selected real data element in the first source register by a selected imaginary data element in the second source register, to generate a plurality of imaginary products.

[0208] An adder circuit that is configured to add a first subset of the plurality of imaginary products and subtract a second subset of the plurality of imaginary products to generate a first intermediate result, and to add a third subset of the plurality of imaginary products and subtract a fourth subset of the plurality of imaginary products to generate a second intermediate result.

[0209] An accumulator circuit that is configured to combine the first intermediate result with first data from a destination register to generate a first final result, and to combine the second intermediate result with second data from the destination register to generate a second final result, and to store the first final result and the second final result back into the destination register.

[0210] 2. The processor according to claim 1, wherein the real and imaginary values are stored as 16-bit data elements in the first and second source registers, each imaginary value being stored in a data element location adjacent to the data element location of the corresponding real value, and each combination of a real and an imaginary value representing a complex number.

[0211] 3. The processor according to claim 2, wherein the first and second source registers comprise 128-bit packed data registers that are configurable to store data elements A, B, C, D, E, F, G, and H in respective data element locations A, B, C, D, E, F, G, and H, and wherein data elements A, C, E, and G are real data elements and data elements B, D, F, and H are corresponding imaginary data elements.

[0212] 4. The processor according to claim 3, wherein, to execute the decode instruction, the multiplier circuit performs multiplications S1C*S2D, S1D*S2C, S1A*S2B, S1B*S2A, S1G*S2H, S1H*S2G, S1E*S2F, S1F*S2E to generate the plurality of imaginary products, where S1 identifies the first source register, S2 identifies the second source register, and A-H respectively identify the packed data elements in data element locations A-H in the first and second source registers.

[0213] 5. The processor as described in Technical Solution 4, wherein adding and subtracting the first and second subsets of the plurality of imaginary products respectively includes S1C*S2D - S1D*S2C + S1A*S2B - S1B*S2A, and adding and subtracting the third and fourth subsets of the plurality of imaginary products respectively includes S1G*S2H - S1H*S2G + S1E*S2F - S1F*S2E, to respectively generate the first temporary result and the second temporary result.

[0214] 6. The processor as described in Technical Solution 5 further includes:

[0215] An inversion circuit for inverting the first temporary result and the second temporary result before accumulation by the accumulation circuit; and

[0216] An extension circuit for zero-extending or sign-extending the third temporary result and the fourth temporary result to a 64-bit value before accumulation respectively corresponding to the first and second data from the destination register.

[0217] 7. The processor as described in Technical Solution 6, wherein the inversion circuit performs two's complement inversion on the first temporary result and the second temporary result.

[0218] 8. The processor as described in Technical Solution 6, wherein the extension circuit adds zeros to the first temporary result and the second temporary result.

[0219] 9. The processor as described in Technical Solution 6, wherein the values in the most significant bit positions of the first temporary result and the second temporary result are repeated multiple times to convert the first temporary result and the second temporary result into 64-bit values.

[0220] 10. A method includes:

[0221] Decoding a first instruction to generate a decoded instruction;

[0222] Storing a first plurality of packed real and imaginary data elements in a first source register;

[0223] Storing a second plurality of packed real and imaginary data elements in a second source register;

[0224] Selecting real and imaginary data elements in the first source register and the second source register for multiplication;

[0225] Multiply each selected imaginary data element in the first source register by a selected real data element in the second source register, and multiply each selected real data element in the first source register by a selected imaginary data element in the second source register to generate a plurality of imaginary products;

[0226] Add the plurality of imaginary products of the first subset and subtract the plurality of imaginary products of the second subset to generate a first temporary result, and add the plurality of imaginary products of the third subset and subtract the plurality of imaginary products of the fourth subset to generate a second temporary result;

[0227] Add the first temporary result to the first data from the destination register to generate a first final result, and add the second temporary result to the second data from the destination register to generate a second final result; and

[0228] Store the first final result and the second final result back into the destination register.

[0229] 11. The method according to claim 10, wherein the real and imaginary values are stored as 16-bit data elements in the first and second source registers, each imaginary value is stored in a data element location adjacent to the data element location of the real value corresponding to the data element location, and each combination of real and imaginary values represents a complex number.

[0230] 12. The method according to claim 11, wherein the first and second source registers comprise 128-bit packed data registers, the 128-bit packed data registers are configurable with data element locations A, B, C, D, F, G, and H for storing data elements A, B, C, D, E, F, G, and H respectively, and wherein data elements A, C, E, and G are real data elements and data elements B, D, F, and H are corresponding imaginary data elements.

[0231] 13. The method according to claim 12, wherein in order to execute the decoding instruction, the multiplier circuit will perform multiplications S1C*S2D, S1D*S2C, S1A*S2B, S1B*S2A, S1G*S2H, S1H*S2G, S1E*S2F, S1F*S2E to generate the plurality of imaginary products, where S1 identifies the first source register, S2 identifies the second source register, and A-H respectively identify the packed data elements in data element locations A-H in the first and second source registers.

[0232] 14. The method as described in Technical Solution 13, wherein adding the plurality of imaginary products of the first subset includes S1C * S2D + S1D * S2C + S1A * S2B + S1B * S2A, and adding the plurality of imaginary products of the second subset includes S1G * S2H + S1H * S2G + S1E * S2F + S1F * S2E, so as to correspondingly generate the first temporary result and the second temporary result.

[0233] 15. The method as described in Technical Solution 14 further includes:

[0234] inverting the first temporary result and the second temporary result before accumulation by the accumulation circuit; and

[0235] zero-extending or sign-extending the third temporary result and the fourth temporary result to 64-bit values before accumulating them correspondingly with the first and second data from the destination register.

[0236] 16. The method as described in Technical Solution 15, wherein two's complement inversion is performed on the first temporary result and the second temporary result.

[0237] 17. The method as described in Technical Solution 15, wherein zero is added to the first temporary result and the second temporary result.

[0238] 18. The method as described in Technical Solution 15, wherein the values in the most significant bit positions of the first temporary result and the second temporary result are repeated multiple times to convert the first temporary result and the second temporary result into 64-bit values.

[0239] 19. A machine-readable medium having program code stored thereon, the program code when executed by a machine causes the machine to perform the operations of the following items:

[0240] Decode a first instruction to generate a decoded instruction;

[0241] Store a first plurality of packed real and imaginary data elements in a first source register;

[0242] Store a second plurality of packed real and imaginary data elements in a second source register;

[0243] Select real and imaginary data elements in the first source register and the second source register for multiplication;

[0244] Multiply each selected imaginary data element in the first source register by the selected real data element in the second source register, and multiply each selected real data element in the first source register by the selected imaginary data element in the second source register to generate a plurality of imaginary products;

[0245] Sum the plurality of imaginary products of the first subset and subtract the plurality of imaginary products of the second subset to generate a first temporary result, and sum the plurality of imaginary products of the third subset and subtract the plurality of imaginary products of the fourth subset to generate a second temporary result;

[0246] Add the first temporary result to the first data from the destination register to generate a first final result, and add the second temporary result to the second data from the destination register to generate a second final result; and

[0247] Store the first final result and the second final result back into the destination register.

[0248] 20. The machine-readable medium as described in technical solution 19, wherein the real and imaginary values are stored as 16-bit data elements in the first and second source registers, and each imaginary value is stored in a data element location adjacent to the data element location of the real value corresponding to the data element location, and each combination of real and imaginary values represents a complex number.

[0249] 21. The machine-readable medium as described in technical solution 20, wherein the first and second source registers include 128-bit packed data registers, and the 128-bit packed data registers can be configured with data element locations A, B, C, D, F, G, and H for storing data elements A, B, C, D, E, F, G, and H respectively, and wherein data elements A, C, E, and G are real data elements and data elements B, D, F, and H are corresponding imaginary data elements.

[0250] 22. The machine-readable medium as described in technical solution 21, wherein to execute the decoding instruction, the multiplier circuit will perform multiplications S1C*S2D, S1D*S2C, S1A*S2B, S1B*S2A, S1G*S2H, S1H*S2G, S1E*S2F, S1F*S2E to generate the plurality of imaginary products, where S1 identifies the first source register, S2 identifies the second source register, and A-H respectively identify the packed data elements in data element locations A-H in the first and second source registers.

[0251] 23. The machine-readable medium as described in technical solution 22, wherein adding the plurality of imaginary products of the first subset includes S1C*S2D+S1D*S2C+S1A*S2B+S1B*S2A, and adding the plurality of imaginary products of the second subset includes S1G*S2H+S1H*S2G+S1E*S2F+S1F*S2E to respectively generate the first temporary result and the second temporary result.

[0252] 24. The machine-readable medium as described in technical solution 23 further includes program code to cause the machine to perform operations of the following items:

[0253] invert the first temporary result and the second temporary result before accumulation by the accumulation circuit; and

[0254] zero-extend or sign-extend the third temporary result and the fourth temporary result to a 64-bit value before accumulating them with the first and second data from the destination register respectively.

[0255] 25. The machine-readable medium as described in technical solution 24, wherein two's complement inversion is performed on the first temporary result and the second temporary result.

[0256] 26. The machine-readable medium as described in technical solution 24, wherein zeros are added to the first temporary result and the second temporary result.

[0257] 27. The machine-readable medium as described in technical solution 24, wherein the values in the most significant bit positions of the first temporary result and the second temporary result are repeated multiple times to convert the first temporary result and the second temporary result into 64-bit values.

[0258] In the foregoing specification, embodiments of the present invention have been described with reference to specific exemplary embodiments. However, it will be apparent that various modifications and changes can be made thereto without departing from the broader spirit and scope of the present invention as set forth in the appended claims. Therefore, the specification and the drawings are to be considered in an illustrative rather than a restrictive sense.

[0259] Embodiments of the present invention may include the various steps described above. These steps may be implemented in machine-executable instructions that may be used to cause a general-purpose or special-purpose processor to execute the steps. Alternatively, these steps may be performed by specific hardware components containing hardwired logic for executing the steps, or by any combination of programmed computer components and custom hardware components.

[0260] As described herein, an instruction may relate to a particular configuration of hardware, such as an application specific integrated circuit (ASIC) configured to perform certain operations or having pre-determined functionality or software instructions stored in a memory implemented on a non-transitory computer-readable medium. Thus, the techniques shown in the figures can be implemented using code and / or data stored and executed on one or more electronic devices (e.g., a terminal station, a network element, etc.). Such electronic devices use computer machine-readable media, such as non-transitory computer machine-readable storage media (e.g., magnetic disks, optical disks, random access memory, read-only memory, flash memory devices, phase change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustic, or other forms of propagated signals - such as carrier waves, infrared signals, digital signals, etc.), to store and transfer (internally and / or over a network with other electronic devices) code and data. Additionally, such electronic devices generally include a collection of one or more processors coupled to one or more other components such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., a keyboard, a touchscreen, and / or a display), and a network connection. The coupling of the collection of processors to the other components is generally through one or more buses and bridges (also referred to as bus controllers). Signals carrying network traffic and storage devices represent one or more machine-readable communication media and machine-readable storage media, respectively. Thus, the storage device of a given electronic device generally stores code and / or data for execution on one or more processors of the collection of processors of the electronic device. Of course, different combinations of software, firmware, and / or hardware can be used to implement one or more portions of embodiments of the present invention. Throughout this detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, those skilled in the art will understand that the present invention can be practiced without some of these specific details. In some instances, well-known structures and functions are not described in detail so as not to obscure the subject matter of the present invention. Thus, the scope and spirit of the present invention should be judged according to the following claims.

Claims

1. A processor, comprising: a decoder for decoding a first instruction to generate a decoded instruction; A first source register for storing a first plurality of complex numbers including a first plurality of packed real and imaginary data elements; A second source register for storing a second plurality of complex numbers including a second plurality of packed real and imaginary data elements, wherein each complex number in the second plurality of complex numbers includes the complex conjugate of the corresponding complex number in the first plurality of complex numbers; A plurality of temporary registers including first, second, third, and fourth temporary registers; And An execution circuit for executing the decoded instruction, the execution circuit including: A multiplier circuit for selecting real and imaginary data elements in the first source register and the second source register for multiplication, the multiplier circuit for multiplying each selected imaginary data element in the first source register by the selected real data element in the second source register, and for multiplying each selected real data element in the first source register by the selected imaginary data element in the second source register to generate a plurality of imaginary products; An adder circuit for adding a first subset of the plurality of imaginary products and subtracting a second subset of the plurality of imaginary products to generate a first temporary result, and for adding a third subset of the plurality of imaginary products and subtracting a fourth subset of the plurality of imaginary products to generate a second temporary result, the adder circuit further for storing the first temporary result in the first temporary register and storing the second temporary result in the second temporary register; An inverter circuit for inverting the first temporary result to generate a first inverted temporary result and inverting the second temporary result to generate a second inverted temporary result, the inverter circuit further for storing the first inverted temporary result in the third temporary register and storing the second inverted temporary result in the fourth temporary register; And An accumulator circuit for combining the first inverted temporary result with first data from a destination register to generate a first final result, and for combining the second inverted temporary result with second data from the destination register to generate a second final result, and for storing the first final result and the second final result back in the destination register.

2. The processor according to claim 1, wherein the first and second pluralities of packed real and imaginary data elements are stored as 16-bit data elements in the first and second source registers, each imaginary data element being stored in a data element location adjacent to the data element location of the corresponding real data element, and each combination of real and imaginary data elements representing a complex number.

3. The processor according to claim 1 or 2, wherein the first and second source registers include 128-bit packed data registers, the 128-bit packed data registers being configurable with data element locations A, B, C, D, E, F, G, and H for storing data elements A, B, C, D, E, F, G, and H respectively, and wherein data elements A, C, E, and G are real data elements and data elements B, D, F, and H are corresponding imaginary data elements.

4. The processor according to claim 3, wherein, in order to execute the decoded instruction, the multiplier circuit will perform multiplications S1C*S2D, S1D*S2C, S1A*S2B, S1B*S2A, S1G*S2H, S1H*S2G, S1E*S2F, S1F*S2E to generate the pluralities of imaginary products, where S1 identifies the first source register, S2 identifies the second source register, and A-H respectively identify the packed data elements in data element locations A-H in the first and second source registers.

5. The processor according to claim 4, wherein adding and subtracting the first and second subsets of the pluralities of imaginary products respectively includes S1C*S2D - S1D*S2C + S1A*S2B - S1B*S2A, and adding and subtracting the third and fourth subsets of the pluralities of imaginary products respectively includes S1G*S2H - S1H*S2G + S1E*S2F - S1F*S2E to respectively generate the first and second temporary results.

6. The processor as claimed in claim 1 further comprises: An extension circuit for zero-extending or sign-extending the third and fourth temporary results to a 64-bit value before accumulating them with the first and second data from the destination register respectively.

7. The processor as claimed in claim 6, wherein the negation circuit performs two's complement negation on the first and second temporary results.

8. The processor as claimed in claim 6 or 7, wherein the extension circuit adds zeros to the first and second temporary results.

9. The processor as claimed in claim 6 or 7, wherein the values in the most significant bit positions of the first and second temporary results are repeated multiple times to convert the first and second temporary results to 64-bit values.

10. A method comprising: Decoding a first instruction to generate a decoded instruction; Storing a first plurality of complex numbers including a first plurality of packed real and imaginary data elements in a first source register; Storing a second plurality of complex numbers including a second plurality of packed real and imaginary data elements in a second source register, wherein each complex number in the second plurality of complex numbers includes the complex conjugate of the corresponding complex number in the first plurality of complex numbers. Select real and imaginary data elements in the first source register and the second source register for multiplication; Multiply each selected imaginary data element in the first source register by the selected real data element in the second source register, and multiply each selected real data element in the first source register by the selected imaginary data element in the second source register to generate a plurality of imaginary products; Add a first subset of the plurality of imaginary products and subtract a second subset of the plurality of imaginary products to generate a first temporary result, and add a third subset of the plurality of imaginary products and subtract a fourth subset of the plurality of imaginary products to generate a second temporary result; Store the first temporary result in a first temporary register and store the second temporary result in a second temporary register; Invert the first temporary result to generate a first inverted temporary result and invert the second temporary result to generate a second inverted temporary result; Store the first inverted temporary result in a third temporary register and store the second inverted temporary result in a fourth temporary register; Add the first inverted temporary result to first data from a destination register to generate a first final result, and add the second inverted temporary result to second data from the destination register to generate a second final result; and Store the first final result and the second final result back in the destination register.

11. The method as claimed in claim 10, wherein the first and second plurality of packed real and imaginary data elements are stored in the first and second source registers as 16-bit data elements, and each imaginary data element is stored in a data element location adjacent to the data element location of the corresponding real data element, and each combination of a real and an imaginary data element represents a complex number.

12. The method according to claim 10 or 11, wherein the first and second source registers comprise 128-bit packed data registers, the 128-bit packed data registers being configurable with data element positions A, B, C, D, E, F, G, and H for storing data elements A, B, C, D, E, F, G, and H respectively, and wherein data elements A, C, E, and G are real data elements and data elements B, D, F, and H are corresponding imaginary data elements.

13. The method according to claim 12, wherein in order to execute the decoding instruction, a multiplier circuit will perform multiplications S1C*S2D, S1D*S2C, S1A*S2B, S1B*S2A, S1G*S2H, S1H*S2G, S1E*S2F, S1F*S2E to generate the plurality of imaginary products, where S1 identifies the first source register, S2 identifies the second source register, and A - H respectively identify the packed data elements in data element positions A - H in the first and second source registers.

14. The method according to claim 13, wherein adding the plurality of imaginary products of the first subset and subtracting the plurality of imaginary products of the second subset comprises S1C*S2D - S1D*S2C + S1A*S2B - S1B*S2A, and adding the plurality of imaginary products of the third subset and subtracting the plurality of imaginary products of the fourth subset comprises S1G*S2H - S1H*S2G + S1E*S2F - S1F*S2E to respectively generate the first temporary result and the second temporary result.

15. The method according to claim 10 further comprises: Zero-extending or sign-extending a third temporary result and a fourth temporary result to 64-bit values before accumulating them with the first and second data from the destination register respectively.

16. The method according to claim 15, wherein performing a two's complement inversion on the first temporary result and the second temporary result.

17. The method according to claim 15 or 16, wherein zero is added to the first temporary result and the second temporary result.

18. The method according to claim 15 or 16, wherein the values in the most significant bit positions of the first temporary result and the second temporary result are repeated a number of times to convert the first temporary result and the second temporary result to 64-bit values.

19. A machine-readable medium having program code stored thereon, the program code when executed by a machine causes the machine to perform operations of: Decoding a first instruction to generate a decoded instruction; Store a first plurality of complex numbers including a first plurality of packed real and imaginary data elements in a first source register; Store a second plurality of complex numbers including a second plurality of packed real and imaginary data elements in a second source register, wherein each complex number in the second plurality of complex numbers includes the complex conjugate of the corresponding complex number in the first plurality of complex numbers; Select real and imaginary data elements in the first source register and the second source register for multiplication; Multiply each selected imaginary data element in the first source register by a selected real data element in the second source register, and multiply each selected real data element in the first source register by a selected imaginary data element in the second source register to generate a plurality of imaginary products; Add a first subset of the plurality of imaginary products and subtract a second subset of the plurality of imaginary products to generate a first temporary result, and add a third subset of the plurality of imaginary products and subtract a fourth subset of the plurality of imaginary products to generate a second temporary result; Store the first temporary result in a first temporary register and store the second temporary result in a second temporary register; Invert the first temporary result to generate a first inverted temporary result and invert the second temporary result to generate a second inverted temporary result; Store the first inverted temporary result in a third temporary register and store the second inverted temporary result in a fourth temporary register; Add the first inverted temporary result to first data from a destination register to generate a first final result, and add the second inverted temporary result to second data from the destination register to generate a second final result; and Store the first final result and the second final result back in the destination register.

20. The machine-readable medium of claim 19, wherein the first and second plurality of packed real and imaginary data elements are stored in the first and second source registers as 16-bit data elements, each imaginary data element is stored in a data element location adjacent to the data element location of the real data element corresponding to the data element location, and each combination of real and imaginary data elements represents a complex number.

21. The machine-readable medium of claim 20, wherein the first and second source registers include 128-bit packed data registers, the 128-bit packed data registers are configurable with data element locations A, B, C, D, E, F, G, and H for storing data elements A, B, C, D, E, F, G, and H respectively, and wherein data elements A, C, E, and G are real data elements and data elements B, D, F, and H are corresponding imaginary data elements.

22. The machine-readable medium of claim 21, wherein to execute the decoding instruction, a multiplier circuit will perform multiplications S1C*S2D, S1D*S2C, S1A*S2B, S1B*S2A, S1G*S2H, S1H*S2G, S1E*S2F, S1F*S2E to generate the plurality of imaginary products, where S1 identifies the first source register, S2 identifies the second source register, and A-H respectively identify the packed data elements in data element locations A-H in the first and second source registers.

23. The machine-readable medium according to claim 22, wherein adding the plurality of imaginary products of the first subset and subtracting the plurality of imaginary products of the second subset includes S1C*S2D - S1D*S2C + S1A*S2B - S1B*S2A, and adding the plurality of imaginary products of the third subset and subtracting the plurality of imaginary products of the fourth subset includes S1G*S2H - S1H*S2G + S1E*S2F - S1F*S2E, to correspondingly generate the first temporary result and the second temporary result.

24. The machine-readable medium according to claim 19 or 23 further includes program code to cause the machine to perform operations of the following items: Zero-extend or sign-extend the third temporary result and the fourth temporary result to a 64-bit value before accumulating them correspondingly with the first and second data from the destination register.

25. The machine-readable medium according to claim 24, wherein a two's complement inversion is performed on the first temporary result and the second temporary result.

26. An apparatus, comprising: A component for decoding a first instruction to generate a decoded instruction; A component for storing a first plurality of complex numbers including a first plurality of packed real and imaginary data elements in a first source register; A component for storing a second plurality of complex numbers including a second plurality of packed real and imaginary data elements in a second source register, wherein each complex number in the second plurality of complex numbers includes the complex conjugate of the corresponding complex number in the first plurality of complex numbers; A component for selecting real and imaginary data elements in the first source register and the second source register for multiplication; A component for performing the following operations: multiplying each selected imaginary data element in the first source register by a selected real data element in the second source register, and multiplying each selected real data element in the first source register by a selected imaginary data element in the second source register to generate a plurality of imaginary products; A component for performing the following operations: adding a first subset of the plurality of imaginary products and subtracting a second subset of the plurality of imaginary products to generate a first temporary result, and adding a third subset of the plurality of imaginary products and subtracting a fourth subset of the plurality of imaginary products to generate a second temporary result; A component for storing the first temporary result in a first temporary register and storing the second temporary result in a second temporary register; A component for inverting the first temporary result to generate a first inverted temporary result and inverting the second temporary result to generate a second inverted temporary result; A component for storing the first inverted temporary result in a third temporary register and storing the second inverted temporary result in a fourth temporary register; A component for performing the following operations: adding the first inverted temporary result to first data from a destination register to generate a first final result, and adding the second inverted temporary result to second data from the destination register to generate a second final result; And A component for storing the first final result and the second final result back into the destination register.

27. The apparatus according to claim 26, wherein the first and second plurality of packed real and imaginary data elements are stored as 16-bit data elements in the first and second source registers, each imaginary data element is stored in a data element location adjacent to the data element location of the real data element corresponding to the data element location, and each combination of real and imaginary data elements represents a complex number.

28. The apparatus according to claim 26 or 27, wherein the first and second source registers comprise 128-bit packed data registers, the 128-bit packed data registers being configurable with data element positions A, B, C, D, E, F, G, and H for storing data elements A, B, C, D, E, F, G, and H respectively, and wherein data elements A, C, E, and G are real data elements and data elements B, D, F, and H are corresponding imaginary data elements.

29. The apparatus according to claim 28, wherein in order to execute the decoding instruction, the multiplier circuit will perform multiplications S1C*S2D, S1D*S2C, S1A*S2B, S1B*S2A, S1G*S2H, S1H*S2G, S1E*S2F, S1F*S2E to generate the plurality of imaginary products, where S1 identifies the first source register, S2 identifies the second source register, and A - H respectively identify the packed data elements in data element positions A - H in the first and second source registers.

30. The apparatus according to claim 29, wherein adding the plurality of imaginary products in the first subset and subtracting the plurality of imaginary products in the second subset comprises S1C*S2D - S1D*S2C + S1A*S2B - S1B*S2A, and adding the plurality of imaginary products in the third subset and subtracting the plurality of imaginary products in the fourth subset comprises S1G*S2H - S1H*S2G + S1E*S2F - S1F*S2E to respectively generate the first temporary result and the second temporary result.

31. The apparatus according to claim 26 further comprises: means for performing the following operations: zero-extending or sign-extending the third and fourth temporary results to 64-bit values before accumulating them with the first and second data from the destination register respectively.

32. The apparatus according to claim 31, wherein one's complement inversion is performed on the first and second temporary results.

33. The apparatus according to claim 31 or 32, wherein zero is added to the first and second temporary results.

34. The apparatus according to claim 31 or 32, wherein the values in the most significant bit positions of the first and second temporary results are repeated multiple times to convert the first and second temporary results to 64-bit values.

35. A computer program product, comprising a computer program, characterized in that The computer program, when executed by a processor, implements multiple steps of the method according to any one of claims 10 - 18.

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