Apparatus and method for performing double signed and unsigned multiplication of packed data elements

Abstract

Apparatuses and methods for performing double signed and unsigned multiplication of packed data elements are disclosed. Apparatuses and methods for performing double simultaneous multiplication of packed data elements. For example, one embodiment of a processor includes a decoder to decode a first instruction to generate a decoded instruction, a first source register to store a first plurality of packed byte data elements, a second source register to store a second plurality of packed byte data elements, an execution circuit to execute the decoded instruction, the execution circuit including a multiplier circuit to simultaneously multiply each of the first plurality of packed byte data elements with a corresponding packed byte data element of the second plurality of packed byte data elements to generate a plurality of products, an adder circuit to add a specified set of the products to generate a temporary result for each set of products, a zero or sign extension circuit to zero or sign extend the temporary result for each set to generate an extended temporary result for each set, an accumulation circuit to combine each of the extended temporary results with a selected packed data value stored in a third source register to generate a plurality of final results, and a destination register to store the plurality of final results as a plurality of packed data elements in a specified data element location.

Description

BACKGROUND TECHNICAL FIELD

[0002] Embodiments of the present invention relate generally to the field of computer processors. More specifically, embodiments relate to apparatuses and methods for performing double signed and unsigned multiplication of packed data elements.

[0003] Description of Related Art

[0004] An instruction set or instruction set architecture (ISA) is the portion of a computer architecture that is relevant to programming, including native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I / O). It should be noted that the term "instruction" generally refers herein to macroinstructions - i.e., instructions provided to a processor for execution - as opposed to microinstructions or micro-ops - i.e., microinstructions or micro-ops are the result of a processor's decoder decoding macroinstructions. Microinstructions or micro-ops can be configured to instruct execution units on the processor to perform operations to implement the logic associated with the macroinstructions.

[0005] An ISA is distinct from microarchitecture, which is the collection of processor design techniques used to implement an instruction set. Processors with different microarchitectures can share a common instruction set. For example, Pentium 4 processors, Core TM (Core TM ) processors, and multiple processors from Advanced Micro Devices, Inc. of Sunnyvale, California implement nearly identical versions of the x86 instruction set (with some extensions added with updated versions), but have different internal designs. For example, the same register architecture of the ISA can be implemented in different microarchitectures using well-known techniques in different ways, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., using a register alias table (RAT), a reorder buffer (ROB), and a retirement register file). Unless otherwise specified, the phrases "register architecture," "register file," and "registers" are used herein to refer to the register architecture, register file, and registers that are visible to software / programmers and to the way in which registers are specified by instructions. Where differentiation is needed, the adjective "logical," "architectural," or "software-visible" will be used to indicate registers / register file in the register architecture, while a different adjective will be used to specify registers in a given microarchitecture (e.g., physical registers, reorder buffers, retirement registers, register pool).

[0006] Multiply-accumulate is a common digital signal processing operation that computes the product of two numbers and adds the product to an accumulation value. Existing single instruction multiple data (SIMD) microarchitectures implement multiply-accumulate operations by executing sequences of instructions. For example, multiply-accumulate can be performed with a multiply instruction, followed by a 4-way add, and then an accumulate with the destination quadword data to generate two 64-bit saturated results. BRIEF DESCRIPTION OF DRAWINGS

[0007] A better understanding of the present application can be obtained from the following detailed description in conjunction with the following drawings, in which:

[0008] Figure 1A and Figure 1B is a block diagram illustrating a generic vector friendly instruction format and its instruction templates according to embodiments of the application;

[0009] Figures 2A-2C is a block diagram illustrating an exemplary VEX instruction format according to embodiments of the application;

[0010] Figure 3 is a block diagram of a register architecture according to one embodiment of the application; and

[0011] Figure 4A is a block diagram illustrating both an exemplary in-order fetch, decode, retire pipeline and an exemplary register rename, out-of-order issue / execution pipeline according to embodiments of the application;

[0012] Figure 4B is a block diagram illustrating an exemplary embodiment of an in-order fetch, decode, retire core to be included in a processor and an exemplary register rename, out-of-order issue / execution architecture core according to embodiments of the application;

[0013] Figure 5A is a block diagram of a single processor core and its connection to an on-die interconnection network;

[0014] Figure 5B is a block diagram illustrating a portion of a processor core in Figure 5A according to embodiments of the application;

[0015] Figure 6 is a block diagram of a single processor core and a multi-processor core with integrated memory controller and graphics according to embodiments of the application;

[0016] Figure 7 is a block diagram illustrating a system according to one embodiment of the application;

[0017] Figure 8 is a block diagram illustrating a second system according to embodiments of the application;

[0018] Figure 9 Figure illustrates a block diagram of a third system in accordance with an embodiment of the application;

[0019] Figure 10 Figure illustrates a block diagram of a system-on-a-chip (SoC) in accordance with an embodiment of the application;

[0020] Figure 11 Figure illustrates a block diagram of converting binary instructions in a source instruction set to binary instructions in a target instruction set using a software instruction translator in accordance with an embodiment of the application;

[0021] Figure 12 Figure illustrates a processor architecture on which embodiments of the application can be implemented;

[0022] Figure 13 Figure illustrates a plurality of packed data elements containing real and complex values in accordance with one embodiment;

[0023] Figures 14A-14B Figure illustrates an embodiment of a packed data processing architecture;

[0024] Figure 15 Figure illustrates a method in accordance with one embodiment of the application;

[0025] Figure 16 Figure illustrates a method in accordance with another embodiment of the application;

[0026] Figure 17 Figure illustrates one embodiment for right shifting a plurality of data elements based on an immediate and writing a specified portion to a destination;

[0027] Figure 18 Figure illustrates one embodiment for right shifting a plurality of data elements based on a source value and writing a specified portion to a destination;

[0028] Figure 19 Figure illustrates one embodiment for left shifting a plurality of data elements based on an immediate and writing a specified portion to a destination;

[0029] Figure 20 Figure illustrates one embodiment for left shifting a plurality of data elements based on a source value and writing a specified portion to a destination;

[0030] Figure 21 Figure illustrates a method in accordance with one embodiment of the application; and

[0031] Figure 22 Figure illustrates a method in accordance with another embodiment of the application. DETAILED DESCRIPTION

[0032] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the application described below. However, it will be apparent to one skilled in the art that embodiments of the present application can be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of embodiments of the present application.

[0033] Exemplary processor architectures, instruction formats, and data types

[0034] An instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, location of bits) to specify, among other things, the operation to be performed (opcode) and the operand(s) upon which that operation is to be performed. Some instruction formats are further decomposed through the definition of instruction templates (or subformats). For example, instruction templates of a given instruction format can be defined to have different subsets of the fields of that instruction format (included fields are generally in the same order, but at least some fields have different bit locations because fewer fields are included), and / or to have given fields interpreted in different ways. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format), and includes fields to specify the operation and operands. For example, an exemplary ADD (addition) instruction has a particular opcode and instruction format that includes an opcode field to specify that opcode and operand fields to select the operands (source 1 / destination and source 2); and an occurrence of that ADD instruction in an instruction stream will have the particular contents in the operand fields that select the particular operands.

[0035] Embodiments of the instruction(s) described herein can be embodied in different formats. In addition, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instruction(s) can be performed on such systems, architectures, and pipelines, but are not limited to those detailed.

[0036] General vector friendly instruction format

[0037] A vector friendly instruction format is an instruction format that is amenable to vector instructions (e.g., there are specific fields dedicated to vector operations). Although embodiments are described in which both vector and scalar operations are supported through the vector friendly instruction format, alternative embodiments use only vector operations through the vector friendly instruction format.

[0038] Figures 1A-1B Figure 1 is a block diagram illustrating a general vector friendly instruction format and its instruction templates according to embodiments of the present application. Figure 1AThis is a block diagram illustrating a general vector-friendly instruction format and its Class A instruction template according to an embodiment of the present invention; and Figure 1B This is a block diagram illustrating a general vector-friendly instruction format and its Class B instruction template according to an embodiment of the present invention. Specifically, Class A and Class B instruction templates are defined for the general vector-friendly instruction format 100, both of which include instruction templates for no memory access 105 and instruction templates for memory access 120. In the context of the vector-friendly instruction format, the term "general" means an instruction format that is not bound to any particular instruction set.

[0039] Although embodiments of the invention described herein support the following in the case of vector-friendly instruction formats: 64-byte vector operand length (or size) with a 32-bit (4-byte) or 64-bit (8-byte) data element width (or size) (and thus, the 64-byte vector consists of 16 double-word-sized elements, or alternatively, 8 quad-word-sized elements); 64-byte vector operand length (or size) with a 16-bit (2-byte) or 8-bit (1-byte) data element width (or size); 32-byte vector operand length (or size) with a 32-bit (4-byte) or 64-bit (8-byte) data element width (or size); Byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes); and 16-byte vector operand lengths (or sizes) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes); however, alternative embodiments may support larger, smaller, and / or different vector operand sizes (e.g., 256-byte vector operands) with larger, smaller, or different data element widths (e.g., 128-bit (16-byte) data element widths).

[0040] Figure 1A The Class A instruction templates include: 1) within the instruction template for no memory access 105, an instruction template showing a full rounding control operation 110 without memory access and an instruction template showing a data transformation operation 115 without memory access; and 2) within the instruction template for memory access 120, an instruction template showing the timeliness of memory access 125 and the timelessness of memory access 130. Figure 1B The B-type instruction templates include: 1) within the instruction template for no memory access 105, an instruction template showing a partial rounding control type operation 112 for write mask control without memory access and an instruction template showing a vsize type operation 117 for write mask control without memory access; and 2) within the instruction template for memory access 120, an instruction template showing write mask control 127 for memory access.

[0041] The general vector-friendly instruction format 100 includes the following as listed in Figures 1A-1B The fields in the order shown in the diagram are as follows.

[0042] Format field 140 - a particular value in this field (instruction format identifier value) uniquely identifies the vector friendly instruction format, and thereby identifies that the instruction appears in the instruction stream in the vector friendly instruction format. This field is thus optional in the sense that it is not needed for an instruction set that has only the general purpose vector friendly instruction format.

[0043] Base operation field 142 - its content distinguishes different base operations.

[0044] Register index field 144 - its content specifies the location of a source or destination operand in a register or in memory, either directly or through address generation. These fields include a sufficient number of bits to select N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. Although N can be up to three source registers and one destination register in one embodiment, alternative embodiments can support more or fewer source and destination registers (e.g., up to two sources, with one of the sources also used as a destination; up to three sources, with one of the sources also used as a destination; up to two sources and one destination).

[0045] Modifier field 146 - its content distinguishes instructions in the general purpose vector instruction format that specify memory access from those that do not; i.e., distinguishes between instruction templates with no memory access 105 and instruction templates with memory access 120. Memory access operations read and / or write to the memory hierarchy (in some cases, using values in registers to specify source and destination addresses), while non-memory access operations do not (e.g., the source and / or destination is a register). Although this field also selects between three different ways to perform memory address computation in one embodiment, alternative embodiments can support more, fewer, or different ways to perform memory address computation.

[0046] Augment operation field 150 - its content distinguishes which of a variety of different operations is to be performed in addition to the base operation. This field is context dependent. In one embodiment of the invention, this field is divided into class field 168, alpha field 152, and beta field 154. Augment operation field 150 allows a number of groups of common operations to be performed in a single instruction rather than 2, 3, or 4 instructions.

[0047] Scale field 160 - its content allows scaling of the content of the index field for memory address generation (e.g., for address generation using (2 比例 *index + base).

[0048] Displacement field 162A - whose content is used as part of memory address generation (e.g., for address generation using (2 比例 *index + base + displacement).

[0049] Displacement factor field 162B (note that collocation of displacement field 162A directly over displacement factor field 162B indicates use of one or the other) - whose content is used as part of address generation; it specifies a displacement factor by which to scale the size (N) of the memory access - where N is the number of bytes in the memory access (e.g., for address generation using (2 比例 *index + base + scaled displacement). Redundant low-order bits are ignored, and thus the content of the displacement factor field is multiplied by the total size of the memory operand (N) to generate the final displacement to be used in computing the effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field 174 (described later in this document) and the data manipulation field 154C. Displacement field 162A and displacement factor field 162B are optional in the sense that they are not used for instruction templates with no memory access 105 and / or different embodiments can implement only one of these two or neither of these two.

[0050] Data element width field 164 - whose content distinguishes which of a number of data element widths is to be used (in some embodiments for all instructions; in other embodiments for only some of the instructions). This field is not needed if only one data element width is supported and / or the use of a certain aspect of the opcode supports the data element width, in which case this field is optional.

[0051] Write mask field 170 - its content controls, on a data element position by data element position basis, whether a data element position in the destination vector operand reflects the result of the base operation and the augmentation operation. Class A instruction templates support merge-write masking, while class B instruction templates support both merge-write masking and zeroing-write masking. When merging, the vector mask allows any set of elements in the destination to be protected from update during the execution of any operation (specified by the base operation and the augmentation operation); in another embodiment, the old value of each element of the destination where the corresponding mask bit has a zero is preserved. Conversely, when zeroing, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one embodiment, the elements of the destination are set to zero when the corresponding mask bit has a zero value. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span from the first to the last element being modified), however, the elements being modified do not have to be contiguous. Thus, the write mask field 170 allows partial vector operations, including loads, stores, arithmetic, logic, etc. While embodiments of the present application are described in which the content of the write mask field 170 selects one of a plurality of write mask registers containing the write mask to be used (and thus, the content of the write mask field 170 indirectly identifies the masking to be performed), alternative embodiments alternatively or additionally allow the content of the mask write field 170 to directly specify the masking to be performed.

[0052] Immediate field 172 - its content allows the specification of an immediate number. This field is not present in generic vector friendly formats that do not support immediate numbers and is not present in instructions that do not use an immediate number, in this sense, the field is optional.

[0053] Class field 168 - its content distinguishes between different classes of instructions. Referring to Figures 1A-1B , the content of this field selects between class A and class B instructions. In Figures 1A-1B , a rounded square is used to indicate that a particular value is present in the field (e.g., class A 168A and class B 168B for the class field 168 in Figures 1A-1B , respectively).

[0054] Class A instruction templates

[0055] In the case of class A non-memory access 105 instruction templates, the alpha field 152 is interpreted as an RS field 152A whose content distinguishes which of the different augmentation operation types are to be performed (e.g., round 152A.1 and data transform 152A.2 are specified for the no memory access round type operation 110 and no memory access data transform type operation 115 instruction templates, respectively), while the beta field 154 distinguishes which of the operations of the specified type are to be performed. In the no memory access 105 instruction templates, the scale field 160, the displacement field 162A, and the displacement scale field 162B are not present.

[0056] No memory access instruction templates - full round control type operations

[0057] In the no memory access full round control type operation 110 instruction templates, the beta field 154 is interpreted as its content(s) provide a static round control field 154A for the round. Although the round control field 154A includes a suppress all floating point exceptions (SAE) field 156 and a round operation control field 158 in the described embodiment of the invention, alternative embodiments can support both of these concepts, can encode both of these concepts as the same field, or have only one or the other of these concepts / fields (e.g., can have only the round operation control field 158).

[0058] SAE field 156 - whose content distinguishes whether or not exception event reporting is disabled; when the content of the SAE field 156 indicates that suppression is enabled, the given instruction does not report any kind of floating point exception flags, and does not invoke any floating point exception handlers.

[0059] Round operation control field 158 - whose content distinguishes which of a set of rounding operations are to be performed (e.g., round up, round down, round towards zero, and round towards nearest). As such, the round operation control field 158 allows the rounding mode to be changed on a per-instruction basis. In one embodiment of the invention in which the processor includes a control register for specifying the rounding mode, the content of the round operation control field 150 overrides that register value.

[0060] No memory access instruction templates - data transform type operations

[0061] In the no memory access data transform type operation 115 instruction templates, the beta field 154 is interpreted as a data transform field 154B whose content distinguishes which of a number of data transforms are to be performed (e.g., no data transform, permute, broadcast).

[0062] In the case of class A memory access 120 instruction templates, the alpha field 152 is interpreted as an eviction hint field 152B whose content distinguishes which of the eviction hints are to be used (in the case of the load instruction templates, the eviction hint field 152B distinguishes between no hint, hint not taken, and hint taken).Figure 1A In the case of the memory access non-temporal 130 instruction template, the alpha field 152 is interpreted as a data manipulation field 152C whose content distinguishes which of a number of data manipulation operations (also called primitives) is to be performed (e.g., no manipulation, broadcast, upcast of source, and downcast of destination). The memory access 120 instruction template includes a scale field 160 and optionally a displacement field 162A or a displacement scale field 162B.

[0063] Vector memory instructions use conversion support to perform vector loads from memory and vector stores to memory. Like ordinary vector instructions, vector memory instructions transfer data from / to memory in a data element-wise fashion, where the elements actually transferred are dictated by the contents of a vector mask selected as a write mask.

[0064] Instruction templates for memory access - temporal

[0065] Temporal data is data that is likely to be reused quickly enough to benefit from cache operations. However, this is a hint, and different processors can implement it in different ways, including completely ignoring the hint.

[0066] Instruction templates for memory access - non-temporal

[0067] Non-temporal data is data that is unlikely to be reused quickly enough to benefit from cache operations in a first level cache and should be given eviction priority. However, this is a hint, and different processors can implement it in different ways, including completely ignoring the hint.

[0068] Class B instruction templates

[0069] In the case of the class B instruction templates, the alpha field 152 is interpreted as a write mask control (Z) field 152C whose content distinguishes whether the write masking controlled by the write mask field 170 should be merge or zero.

[0070] In the case of class B non-memory access 105 instruction templates, a portion of the beta field 154 is interpreted as an RL field 157A, whose content distinguishes which of the different augmentation operation types are to be performed (e.g., round 157A.1 and vector length (VSIZE) 157A.2 are specified for the write mask control partial round control type operation 112 and the write mask control VSIZE type operation 117, respectively, of the no memory access instruction templates), while the remainder of the beta field 154 distinguishes which of the operations of the specified type are to be performed. In the no memory access 105 instruction templates, the scale field 160, the displacement field 162A, and the displacement scale field 162B are not present.

[0071] In the write mask control partial round control type operation 110 instruction templates, the remainder of the beta field 154 is interpreted as a round operation field 159A, and exception event reporting is disabled (the given instruction does not report any kind of floating point exception flags, and does not invoke any floating point exception handlers).

[0072] The round operation control field 159A, like the round operation control field 158, has a content that distinguishes which of a set of round operations are to be performed (e.g., round up, round down, round to zero, and round to nearest). As such, the round operation control field 159A allows the round mode to be changed on a per-instruction basis. In one embodiment of the application in which the processor includes a control register for specifying the round mode, the content of the round operation control field 150 overrides the register value.

[0073] In the write mask control VSIZE type operation 117 instruction templates, the remainder of the beta field 154 is interpreted as a vector length field 159B, whose content distinguishes which of a plurality of data vector lengths are to be performed (e.g., 128 bytes, 256 bytes, or 512 bytes).

[0074] In the case of class B memory access 120 instruction templates, a portion of the beta field 154 is interpreted as a broadcast field 157B, whose content distinguishes whether a broadcast type data manipulation operation is to be performed, while the remainder of the beta field 154 is interpreted as a vector length field 159B. The memory access 120 instruction templates include the scale field 160, and optionally include the displacement field 162A or the displacement scale field 162B.

[0075] For the generic vector friendly instruction format 100, the full opcode field 174 is shown to include the format field 140, the base operation field 142, and the data element width field 164. Although one embodiment is shown in which the full opcode field 174 includes all of these fields, in embodiments that do not support all of these fields, the full opcode field 174 includes fewer than all of these fields. The full opcode field 174 provides the operation code (opcode).

[0076] The extension operation field 150, the data element width field 164, and the writemask field 170 allow these features to be specified on a per-instruction basis with the generic vector friendly instruction format.

[0077] The combination of the writemask field and the data element width field create various types of instructions, as these instructions allow the mask to be applied based on different data element widths.

[0078] The various instruction templates that occur within class A and class B are beneficial in different scenarios. In some embodiments of the invention, different processors or different cores within a processor can support only class A, only class B, or both classes. For example, a high-performance general-purpose out-of-order core intended for general-purpose computing can support only class B, a core intended primarily for graphics and / or scientific (throughput) computing can support only class A, and a core intended for both general-purpose computing and graphics and / or scientific (throughput) computing can support both class A and class B (of course, a core that has some mixture of templates and instructions from both classes, but not all templates and instructions from both classes, is within the scope of the invention). Likewise, a single processor can include multiple cores, all of which support the same class, or where different cores support different classes. For example, in a processor with separate graphics and general-purpose cores, one core in the graphics core intended primarily for graphics and / or scientific computing can support only class A, while one or more of the general-purpose cores can be a high-performance general-purpose core with out-of-order execution and register renaming intended for general-purpose computing that supports only class B. Another processor without separate graphics cores can include one or more general-purpose in-order or out-of-order cores that support both class A and class B. Of course, features from one class can also be implemented in the other class in different embodiments of the invention. Programs written in a high-level language will be compiled into various different executable forms, including: 1) a form with only the instructions of the class(es) supported by the target processor for execution; or 2) a form with alternative routines written using different combinations of instructions of all classes, and control flow code that selects the routines to execute based on the instructions supported by the processor on which the code is currently executing.

[0079] VEX instruction format

[0080] VEX encoding allows instructions to have more than two operands, and allows SIMD vector registers to be longer than 28 bits. The use of the VEX prefix provides a three-operand (or more) syntax. For example, the previous two-operand instruction performs an overwrite source operand operation such as A = A + B. The use of the VEX prefix enables the operands to perform a non-destructive operation such as A = B + C.

[0081] Figure 2A An exemplary AVX instruction format is illustrated, including a VEX prefix 202, a real opcode field 230, a Mod R / M byte 240, a SIB byte 250, a displacement field 262, and an IMM8 272. Figure 2B Figure 2 illustrates which fields from Figure 2A make up the full opcode field 274 and the base operation field 241. Figure 2C Figure 3 illustrates which fields from Figure 2A make up the register index field 244.

[0082] The VEX prefix (bytes 0-2) 202 is encoded in three bytes. The first byte is a format field 290 (VEX byte 0, bits [7:0]) that contains an explicit C4 byte value (the only value used to distinguish the C4 instruction format). The second-third bytes (VEX bytes 1-2) include a number of bit fields that provide specialized capabilities. Specifically, the REX field 205 (VEX byte 1, bits [7-5]) is composed of a VEX.R bit field (VEX byte 1, bit [7] - R), a VEX.X bit field (VEX byte 1, bit [6] - X), and a VEX.B bit field (VEX byte 1, bit [5] - B). Other fields of the instruction encode the lower three bits of the register indexes (rrr, xxx, and bbb) as known in the art, such that Rrrr, Xxxx, and Bbbb can be formed by adding VEX.R, VEX.X, and VEX.B. The opcode map field 215 (VEX byte 1, bits [4:0] - mmmmm) includes content used to encode an implied leading opcode byte. The W field 264 (VEX byte 2, bit [7] - W) - denoted by the notation VEX.W, and provides different functionality depending on the instruction. The role of VEX.vvvv 220 (VEX byte 2, bits [6:3] - vvvv) can include the following: 1) VEX.vvvv encodes the first source register operand, designated in inverted (1's complement) form, and is valid for instructions with two or more source operands; 2) VEX.vvvv encodes the destination register operand, designated in 1's complement form for certain vector shifts; or 3) VEX.vvvv does not encode any operand, the field is reserved and should contain 1111b. If the VEX.L 268 size field (VEX byte 2, bit [2] - L) = 0, it indicates 28-bit vectors; if VEX.L = 1, it indicates 256-bit vectors. The prefix encoding field 225 (VEX byte 2, bits [1:0] - pp) provides additional bits for the base operation field 241.

[0083] The real opcode field 230 (byte 3) is also referred to as the opcode byte. A portion of the opcode is specified in this field.

[0084] The MOD R / M field 240 (byte 4) includes a MOD field 242 (bits [7-6]), a Reg field 244 (bits [5-3]), and an R / M field 246 (bits [2-0]). The Reg field 244 can function to encode a destination register operand or a source register operand (rrr of Rrrr); or be treated as opcode extension and not used to encode any instruction operand. The R / M field 246 can function to encode an instruction operand that references a memory address; or to encode a destination register operand or a source register operand.

[0085] Scale, Index, Base (SIB) - The contents of the scale field 250 (byte 5) include SS 252 (bits [7-6]) for memory address generation. The contents of SIB.xxx 254 (bits [5-3]) and SIB.bbb 256 (bits [2-0]) have been previously mentioned with respect to the register indexes Xxxx and Bbbb.

[0086] The displacement field 262 and the immediate field (IMM8) 272 contain data.

[0087] Exemplary register architecture

[0088] Figure 3 is a block diagram of a register architecture 300 according to one embodiment of the present application. In the illustrated embodiment, there are 32 512-bit wide vector registers 310; these registers are referenced as zmm0 through zmm31. The lower order 256 bits of the lower 6 zmm registers overlay on the registers ymm0-15. The lower order 128 bits of the lower 6 zmm registers (the lower order 128 bits of the ymm registers) overlay on the registers xmm0-15.

[0089] General purpose registers 325 - In the illustrated embodiment, there are sixteen 64-bit general purpose registers that are used with the existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0090] Scalar floating point stack register file (x87 stack) 345, on top of which is overlaid an MMX packed integer flat register file 350 - in the illustrated embodiment, the x87 stack is an eight element stack for performing scalar floating point operations using the x87 instruction set extensions on 32 / 64 / 80 bit floating point data; while the MMX registers are used to perform operations on 64 bit packed integer data, and to hold operands for some operations performed between MMX and XMM registers.

[0091] Alternative embodiments of the present invention can use wider or narrower registers. In addition, alternative embodiments of the present invention can use more, fewer, or different register files and registers.

[0092] Exemplary core architecture, processor, and computer architecture

[0093] Processor cores can be implemented in different ways, for different purposes, in different processors. For example, implementations of such cores can include: 1) general-purpose in-order cores, 2) general-purpose out-of-order cores, 3) special-purpose cores, e.g., graphics, physics, and / or scientific (throughput) computing cores. Implementations of different processors can include: 1) CPUs with one or more general-purpose in-order cores, 2) CPUs with one or more general-purpose out-of-order cores, 3) CPUs with one or more special-purpose cores, e.g., graphics, physics, and / or scientific (throughput) cores, and 4) chips that combine some number of general-purpose in-order cores with one or more special-purpose cores. Such different processors can lead to different computer architectures. For example: 1) a computer architecture with just a CPU with one or more general-purpose in-order cores; 2) a computer architecture with a CPU that includes one or more general-purpose out-of-order cores; 3) a computer architecture with a CPU that includes one or more special-purpose cores, e.g., graphics, physics, and / or scientific (throughput) cores; and 4) a computer architecture with a CPU that includes some number of general-purpose in-order cores combined with one or more special-purpose cores. Exemplary core, processor, and computer architectures are described below. Circuitry (units) including exemplary cores, processors, etc. are described in detail herein.

[0094] Exemplary core architecture

[0095] Figure 4A is a block diagram illustrating an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to embodiments of the application. Figure 4B is a block diagram illustrating an exemplary in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to embodiments of the application. Figures 4A-4B The solid lined boxes in illustrate an in-order pipeline and an in-order core, whereas the dashed lined boxes represent an optional register renaming, out of order issue / execution pipeline and core. Had the need arisen, the solid lined boxes and the dashed lined boxes can be combined to form a single, integrated logic device. In an optional implementation, an efficient integration scheme with more than one core, and / or with storage is desired. The core can be a single core; or a plurality of cores, e.g., 2, 4, 8, or 16. Those skilled in the art will recognize that the number of illustrative cores is a non-limiting example only, and embodiments of the application are applicable to any number of cores. Moreover, these cores can be heterogeneous cores comprising of cores of different

[0096] In Figure 4AIn particular embodiments, the processor pipeline 400 includes a fetch stage 402, a length decode stage 404, a decode stage 406, an allocation stage 408, a rename stage 410, a dispatch (also referred to as issue or issue) stage 412, a register read / memory read stage 414, an execution stage 416, a write back / memory write stage 418, an exception handling stage 422, and a commit stage 424.

[0097] Figure 4B A processor core 490 is shown including a front-end unit 430 coupled to an execution engine unit 450, and both the front-end unit 430 and the execution engine unit 450 are coupled to a memory unit 470. The core 490 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core 490 can be a special-purpose core, such as, for example, a network or communication core, compression engine, co-processor core, general-purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0098] The front-end unit 430 includes a branch prediction unit 432 coupled to an instruction cache unit 434 which is coupled to an instruction translation lookaside buffer (TLB) 436 which is coupled to an instruction fetch unit 438 which is coupled to a decode unit 440. The decode unit 440 (or decoder) can decode instructions, and generate one or more micro-operations, microcode entries, microinstructions, other instructions, or other control signals from the original instructions as an output. A variety of different mechanisms can be used to implement the decode unit 440. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), etc. In one embodiment, the core 490 includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in the decode unit 440 or otherwise within the front-end unit 430). The decode unit 440 is coupled to a rename / allocator unit 452 in the execution engine unit 450.

[0099] The execution engine unit 450 includes a rename / allocator unit 452 that is coupled to a retirement unit 454 and a set of one or more scheduler units 456. The scheduler unit(s) 456 represents any number of different schedulers, including a reservation station, a central instruction window, etc. The scheduler unit(s) 456 is coupled to the physical register file(s) unit 458. Each physical register file unit 458 represents one or more physical register files, where different physical register files store one or more different types of data (e.g., scalar integer, scalar floating point, packed data (e.g., SIMD) integer, packed data (e.g., SIMD) floating point, etc.). In one embodiment, the physical register file(s) unit 458 includes a vector register unit and a scalar register unit. The register units can provide architectural vector registers, vector mask registers, and general purpose registers for use in the processing circuitry as needed. The physical register file(s) unit 458 is overlapped by the retirement unit 454 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using a

[0100] The set of memory access units 464 is coupled to a memory unit 470, which includes a data TLB unit 472 coupled to a data cache unit 474 coupled to a level 2 (L2) cache unit 476. In one exemplary embodiment, the memory access units 464 can include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 472 in the memory unit 470. The instruction cache unit 434 is also coupled to the level 2 (L2) cache unit 476 in the memory unit 470. The L2 cache unit 476 is coupled to one or more other levels of cache, and ultimately to main memory.

[0101] As an example, an exemplary register-renaming, out-of-order issue / execution core architecture can implement the pipeline 400 as follows: 1) the instruction fetch 438 performs fetch and length decode stages 402 and 404, respectively; 2) the decode unit 440 performs a decode stage 406; 3) the rename / allocator unit 452 performs a re- name stage 408, a schedule stage 410 and a rename stage 410; 4) the (multiple) scheduler unit(s) 456 perform a schedule stage 412; 5) the (multiple) physical register

[0102] The core 490 can support one or more instruction sets (e.g., an x86 instruction set (with some extensions that have been added with newer versions); MIPS instruction set; ARM instruction set (with optional additional extensions such as NEON)); including the (multiple) instruction(s) described herein. In one embodiment, the core 490 includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), which allows for operations using packed data (e.g., single instruction multiple data - SIMD extensions). In one embodiment, the instruction set includes AVX instructions to support big data cluster (BDC) programming.

[0103] It should be understood that a core can support multithreading (executing two or more parallel sets of threads) and can do so in any manner (time-sliced, simultaneous multiple threads, etc.). While multithreading is an example of parallelism, parallelism can also be achieved by way of single-threaded units through, for example, instruction-level parallelism. Simultaneous multithreading (SMT) in the context of hyperthreading technology.

[0104] Although register renaming is described in the context of out-of-order execution, it should be appreciated that register renaming can be used in in-order architectures. Although the illustrated processor includes separate instruction and data cache units 434 / 474 and a shared L2 cache unit 476, alternative embodiments can have a single internal cache for both instruction and data, such as for example, a first level (LI) internal cache or a multi-level internal cache. In some embodiments, the system can include a combination of internal caches and external caches outside the core and / or processor. Alternatively, all of the caching can be external to the core and / or processor.

[0105] A specific exemplary in-order core architecture

[0106] Figures 5A-5B A block diagram of a more specific exemplary in-order core architecture is shown in FIG. 5, which can be a core of a single processor or of a plurality of processors in a chip. Depending on the application, the logic blocks can communicate with some fixed function logic, memory I / O interface, and other necessary I / O logic through a high bandwidth interconnect network (for example, a ring network) of the chip.

[0107] Figure 5A A block diagram of a single processor core according to an embodiment of the application and its connection to the interconnect network 502 of the die and its local subset of the second level (L2) cache 504. In one embodiment, the instruction decoder 500 supports the x86 instruction set with the SSE2 instruction set extension. The LI cache 506 allows low latency access to cached memory for instructions and data into the scalar and vector units. Although in one embodiment (for simplicity of design), the scalar unit 508 and vector unit 510 use separate register sets (scalar registers 512 and vector registers 514, respectively), and data transferred between these registers is written to memory and subsequently read back from the first level (LI) cache 506, alternative embodiments of the application can use a different approach (for example, using a single register set or including a communication path that allows data to be transferred between the two register files without being written to and read back from memory).

[0108] The local subset 504 of L2 cache is part of a global L2 cache that is partitioned into multiple separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset 504 of L2 cache. Data read by a processor core is stored in its L2 cache subset 504 and can be quickly accessed in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 504 and is flushed from other subsets if necessary. A ring network ensures coherency of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 cache, and other logic blocks to communicate with each other within the chip. In some embodiments, each ring data path is 1024 bits wide for each direction.

[0109] Figure 5B is a block diagram of a portion of a processor core in Figure 5A according to embodiments of the application. Figure 5B includes an L1 data cache 506A portion of L1 cache 504, and more details regarding vector units 510 and vector registers 514. In particular, vector units 510 are 16-wide vector processing units (VPUs) (see 16-wide ALUs 528) that execute one or more integer, single precision floating point, and double precision floating point instructions. The VPUs support a mix of register inputs through a mix unit 520, value conversion through value conversion units 522A-B, and replication of memory inputs through a replication unit 524.

[0110] Processor with integrated memory controller and graphics device

[0111] Figure 6 is a block diagram of a processor 600 that can have more than one core, that can have an integrated memory controller, and that can have an integrated graphics device, according to embodiments of the application. Figure 6 The solid line block diagram of processor 600 in

[0112] Thus, different implementations of the processor 600 can include: 1) a CPU with the special purpose logic 608 being integrated graphics and / or scientific (throughput) logic (which can include one or more cores), and the cores 602A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, combinations thereof); 2) a coprocessor with the cores 602A-N being a large number of special purpose cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor with the cores 602A-N being a large number of general purpose in-order cores. Thus, the processor 600 can be a general-purpose processor, coprocessor or a special-purpose processor, such as for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics-processing unit), a High-Throughput

[0113] The memory hierarchy includes one or more cache levels within the cores 604A-N and a set of shared cache units 606, as well as an outermost memory (not shown), such as individual or shared banked memory, that is coupled to the set of integrated memory controller units 614. The set of shared cache units 606 can include one or more levels of cache, such as a level two (L2), a level three (L3), a level four (L4) or other level cache, a last level cache (LLC), and / or combinations thereof. In one embodiment, the ring-based interconnect unit 612 interconnects the integrated graphics logic 608, the set of shared cache units 606, and the system agent unit 610 / integrated memory controller(s) unit 614, although alternative embodiments can use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between the one or more cache units 606 and the cores 602A-N.

[0114] In some embodiments, one or more of the cores 602A-N are capable of multi -threading. The system agent 610 includes those components coordinating and operating cores 602A-N. The system agent unit 610 can include for example a power control unit (PCU) and a display unit. The PCU can be or include the logic and

[0115] The cores 602A-N can be homogeneous or heterogeneous in terms of architectural instruction sets; that is, two or more of the cores 602A-N can be capable of executing the same instruction set, while other cores can be capable of executing only a subset of that instruction set or a different instruction set.

[0116] Example Computer Architecture

[0117] Figures 7-10 is a block diagram of an example computer architecture. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of interfacing to a processor and / or other execution logic as is disclosed herein, are generally suitable.

[0118] Referring now to the Figure 7 , a block diagram of a system 700 according to one embodiment of the application is shown. The system 700 can include one or more processors 710, 715, which are coupled to a controller hub 720. In one embodiment the controller hub 720 includes a graphics memory controller hub (GMCH) 790 and an input / output hub (IOH) 750 (which can be on separate chips) ; the GMCH 790 includes memory and graphics controllers; the memory 740 and a co-processor 745 are coupled to the memory and graphics controllers; the IOH 750 is coupled to the GMCH 790 and to I / O devices 760. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory 740 and the co-processor 745 are coupled directly to the processor 710, and the controller hub 720 is on a single chip with the IOH 750.

[0119] The optional nature of additional processors 715 is denoted by a dashed line in Figure 7 . Each processor 710, 715 can include one or more of the processing cores described herein, and can be some version of the processor 600.

[0120] The memory 740 can be, for example, a dynamic random access memory (DRAM), a phase change memory (PCM), or a combination of both. For at least one embodiment, the controller hub 720 communicates with the processor(s) 710, 715 via a multi -dropped bus, point-to-point interface, or similar connection 795, such as a frontside bus (FSB), a link, or the like.

[0121] In one embodiment, coprocessor 745 is a special-purpose processor, such as, for example, a high-throughput MIC processor, network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, etc. In one embodiment, controller hub 720 can include an integrated graphics processor.

[0122] There can be various differences between the physical resources 710, 715 in terms of a spectrum of metrics of merit, such as architectural, micro-architectural, thermal, power consumption characteristics, and the like.

[0123] In one embodiment, processor 710 executes instructions to perform general- purpose processing operations. Embedded within those instructions can be coprocessor instructions. Processor 710 recognizes these coprocessor instructions as being of a type that should be executed by attached coprocessor 745. Accordingly, processor 710 issues these coprocessor instructions (or control signals representing the coprocessor instructions) on coprocessor bus or other interconnect to coprocessor 745. Coprocessor(s) 745 accept and execute the received coprocessor instructions.

[0124] Referring now to the Figure 8 , a block diagram of a first more specific exemplary system 800 is shown in accordance with an embodiment of the present application. As Figure 8 shown in , system 800 is a point-to-point interconnect system, and includes a first processor 870 and a second processor 880 coupled via a point-to-point (PtP) interface 850. Processors 870 and 880 can be some version of the processors 600. In one embodiment of the application, processors 870 and 880 are processors 710 and 715, respectively, while coprocessor 838 is coprocessor 745. In another embodiment, processors 870 and 880 are processors 710 and coprocessor 745, respectively.

[0125] Figure 8 Processors 870 and 880 are shown including integrated memory controller (IMC) units 872 and 882, respectively. Processor 870 also includes point-to-point (PtP) interfaces 876 and 878 as part of the bus controller units of the processor; similarly, second processor 880 includes PtP interfaces 886 and 888. Processors 870, 880 can exchange information via a PtP interface 850 using PtP interface circuits 878, 888.

[0126] Processors 870, 880 can each exchange information with a chipset 890 via individual P-P interfaces 852, 854 using point to point interface circuits 876, 894, 886, 898. Chipset 890 can optionally exchange information with a graphics processor 838 via a high-performance interface 892. In one embodiment, graphics processor 838 is a stand-alone processor that is not integrated into either processor 870 or 880. Chipset 890 can also exchange information with a network controller 839 via a network interface circuit 840.

[0127] A shared cache (not shown) can be included in either processor or outside of both processors and connected with those processors via P-P interconnects, such that each processor's local cache information can be stored in the shared cache if processors are placed into a low power mode.

[0128] Chipset 890 can be coupled to a first bus 816 via an interface 896. In one embodiment, first bus 816 can be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another I / O interconnect bus, although the scope of the application is not so limited.

[0129] As shown in Figure 8 , various I / O devices 814 can be coupled to first bus 816, along with a bus bridge 818, which couples first bus 816 to a second bus 820. In one embodiment, one or more additional processors 815 such as co-processors, high-speed MIC processors, GPGPU, accelerator (such as, for example, a graphics accelerator or a digital signal processor (DSP) unit), field programmable gate arrays, or any other processor, can be coupled to first bus 816. In one embodiment, second bus 820 can be a low pin count (LPC) bus. Various devices can be coupled to second bus 820, shown as a storage device 828, such as a disk drive coupled to store data and instructions 830 in working memory or elsewhere on computing device 800, and a wireless transceiver 827 coupled to communicate wirelessly with other devices. In one embodiment, various input / output devices 822 can be coupled to second bus 820, such as a keyboard and / or mouse 822, or a modem 827. Furthermore, an audio I / O 824 can be coupled to second bus 820. Note that other architectures are possible. For example, a system can implement a bus architecture as opposed to a point-to-point architecture. In one embodiment, a system can implement a multi-drop bus rather than a point-to-point bus, and can implement other architectures. Figure 8

[0130] Referring now to Figure 9 , shown is a block diagram of a second more specific exemplary system 900 in accordance with an embodiment of the present application. Figure 8 and 9 like elements in Figure 9 are numbered similarly, and Figure 8 ​to avoid confusion Figure 9 other aspects.

[0131] Figure 9 The illustrated processors 870, 880 can include integrated memory and I / O control logic ("CL") 971 and 982, respectively. Thus, the CL 972, 982 includes integrated memory controller units and includes I / O control logic. Figure 9 The illustrated processors 870, 880 can include integrated memory and I / O control logic ("CL") 971 and 982, respectively. Thus, the CL 972, 982 includes integrated memory controller units and includes I / O control logic.

[0132] Referring now to the drawings, and more particularly to FIG. 1, a block diagram of a SoC 1000 according to an embodiment of the present application is shown. Figure 10 Referring now to the drawings, and more particularly to FIG. 1, a block diagram of a SoC 1000 according to an embodiment of the present application is shown. Figure 6 Similar elements in FIG. 1 have been given the same reference numerals in FIG. 10. Additionally, dashed lined boxes are optional features on more advanced SoCs. In Figure 10 In FIG. 1, interconnect units 1002 are coupled to: an application processor 1010 which includes a set of one or more cores 602A-N, a set of caches 604A-N, and a shared cache unit 606; a system agent unit 610; a bus controller unit 616; an integrated memory controller unit 614; a set of one or more coprocessors 1020A-N which can include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 1030; a direct memory access (DMA) unit 1032; and a display unit 1040 for coupling to one or more external displays. In one embodiment, coprocessor(s) 1020 include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, or embedded processor for audio, video, or

[0133] Embodiments of the mechanisms disclosed herein can be implemented in hardware, software, firmware, or combinations thereof. Embodiments of the application can be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0134] Program code, such as code 1122 illustrated in FIG. 11, can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices, in known fashion. Figure 8The code 830 in the illustrations can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as, for example; a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0135] The program code can be implemented in a high level of procedural or object oriented programming language to communicate with a processing system. The program code can also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language can be a compiled or interpreted language.

[0136] One or more aspects of at least one embodiment can be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as "IP cores" can be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that make the logic or processor.

[0137] Such machine readable storage media can include, without limitation, non- transitory, tangible arrangements making a program stored thereon, such as a hard disk; any other type of disk including floppy, optical, compact disk read-only memory (CD-ROM), compact disk read and write memory (CD-RW), and magneto-optical disks; semiconductor devices such as read-only memory (ROM), such as dynamic random access memory (DRAM), such as static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory; phase change memory (PCM); magnetic or optical cards; or any other type of media suitable for storing electronic instructions.

[0138] Accordingly, embodiments of the application also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and / or system features described herein. Such embodiments can also be referred to as program products.

[0139] Emulation (including binary translation, code morphing, etc.)

[0140] In some cases, an instruction translator can be used to translate instructions from a source instruction set to a target instruction set. For example, an instruction translator can transform (e.g., using static binary translation, dynamic binary translation including just-in-time compilation), morph, emulate, or otherwise convert instructions to one or more other instructions to be processed by a core. An instruction translator can be implemented in software, hardware, firmware, or combinations thereof. An instruction translator can be on a processor, off a processor, or partially on and partially off a processor.

[0141] Figure 11 is a block diagram of translating a binary instruction in a source instruction set to a binary instruction in a target instruction set in accordance with an embodiment of the present application using a software instruction translator. In the illustrated embodiment, the instruction translator is a software instruction translator, but the instruction translator can alternatively be implemented in software, firmware, hardware, or various combinations thereof. Figure 11 It is shown that a program in a high-level language 1102 can be compiled using a first compiler 1104 to generate first binary code (e.g., x86) 1106, which can be natively executed by a processor with at least one first instruction set core 1116. In some embodiments, a processor with at least one first instruction set core 1116 refers to any processor that performs substantially the same functions as an Intel processor with at least one x86 instruction set core by virtue of Figure 11A program of the form of a high-level language 1102 can be compiled using an alternative instruction set compiler 1108 to generate alternative instruction set binary code 1110 that can be natively executed by a processor 1114 that does not have at least one first instruction set core (e.g., a processor with a core that executes the MIPS instruction set of MIPS Technologies, Inc., Sunnyvale, California, and / or the ARM instruction set of ARM Holdings, Inc., Sunnyvale, California). An instruction converter 1112 is used to translate the first binary code 1106 into code that can be natively executed by the processor 1114 that does not have a first instruction set core. This translated code is unlikely to be identical to the alternative instruction set binary code 1110 because an instruction converter capable of doing so would be difficult to manufacture; however, the translated code will perform general operations and consists of instructions from the alternative instruction set. Therefore, the instruction converter 1112 represents, through emulation, simulation, or any other process, software, firmware, hardware, or a combination thereof that allows a processor or other electronic device without a first instruction set processor or core to execute the first binary code 1106.

[0142] Apparatus and method for digital signal processing instructions

[0143] The following describes digital signal processing (DSP) instructions. In one embodiment, the circuitry and logic for performing DSP operations are integrated into... Figure 4B The execution engine unit 450 shown is integrated within the various cores described above (see, for example, Figure 6 and Figure 10 (in the nucleus 602A-N) and / or in Figure 5A Within the vector unit 510 shown in the diagram. For example, various source and destination registers can be... Figure 4B SIMD registers and / or physical register file units 458 in (multiple) Figure 3 Vector register 310 in the above-described architecture. Multiplication circuitry, adder circuitry, accumulator circuitry, and other circuitry described below can be integrated within the execution component of the architecture described above, by way of example and not limitation, which includes... Figure 4B The invention comprises (multiple) execution units 462. However, it should be noted that the basic principles of the invention are not limited to these specific architectures.

[0144] One embodiment of the invention includes circuitry and / or logic for processing digital signal processing (DSP) instructions. In particular, one embodiment includes a multiply- accumulate (MAC) architecture with eight 16x16-bit multipliers and two 64-bit accumulators. The instruction set architecture (ISA) described below can handle various multiply and MAC operations on 128-bit packed (8-bit, 16-bit, or 32-bit data elements) integer, fixed-point, and complex data types. In addition, certain instructions have direct support for highly efficient fast Fourier transform (FFT) and finite impulse response (FIR) filtering, as well as post-processing of accumulated data through shift, round, and saturation operations.

[0145] One embodiment of the new DSP instructions uses VEX.128 prefix based opcode encoding, and several of the SSE / SSE2 / AVX instructions that handle post-processing of data are used with the DSP ISA. VEX-encoded 128-bit DSP instructions with memory operands can have relaxed memory alignment requirements.

[0146] In one embodiment, the instructions also support various integer and fixed-point data types, including:

[0147] 1) Q31 data type with more than 16 bits for signals that require analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC);

[0148] 2) Q15 data type commonly used in DSP algorithms;

[0149] 3) 16-bit complex data type; and

[0150] 4) 32-bit complex data type.

[0151] The instruction set architecture described herein targets a wide range of standard DSP (e.g., FFT, filtering, pattern matching, correlation, polynomial estimation, etc.) and statistical operations (e.g., mean, moving average, variance, etc.).

[0152] Target applications for embodiments of the invention include sensors, audio, classification tasks for computer vision, and speech recognition. The DSP ISA described herein includes a wide range of instructions suitable for deep neural networks (DNN), automatic speech recognition (ASR), sensor fusion with Kalman filtering, other major DSP applications, etc. Given a sequence of weights {w1, w2,... w k} and an input sequence {x1, x2, x3,... x n}, many image processing, machine learning tasks require computing y i = w1x i + w2xi+1 +... + w k x i+k-1 defined result sequence {y1, y2, y3,... y n+1-k}.

[0153] Figure 12 An exemplary processor 1255 including multiple cores 0-N for simultaneously executing multiple instruction threads is shown including a DSP instruction decode circuit / logic 1231 within a decoder 1230 and a DSP instruction execution circuit / logic 1241 within an execution unit 1240. These pipeline components can perform the operations described herein in response to the decoding and execution of DSP instructions. Although details of only a single core (core 0) are shown in Figure 12 , it will be understood that each of the other cores of the processor 1255 can include similar components.

[0154] Before turning to the details of the specific details of the embodiments of the present application, a description of the components of the exemplary processor 1255 is provided directly below. The multiple cores 0-N can each include a memory management unit 1290 for performing memory operations (e.g., load / store operations), a set of general purpose registers (GPRs) 1205, a set of vector registers 1206, and a set of mask registers 1207. In one embodiment, packing multiple vector data elements into each vector register 1206, each vector register 1206 can have a 512-bit width for storing two 256-bit values, four 128-bit values, eight 64-bit values, sixteen 32-bit values, etc. However, the underlying principles of the present application are not limited to any particular size / type of vector data. In one embodiment, the mask registers 1207 include eight 64-bit operand mask registers (e.g., implemented as the mask registers k0-k7 described herein) for performing bit masking operations on values stored in the vector registers 1206. However, the underlying principles of the present application are not limited to any particular mask register size / type.

[0155] Each core 0-N can include a dedicated first level (LI) cache 1212 and a second level (L2) cache 1211 for caching instructions and data according to the designated cache management policy. The LI cache 1212 includes a separate instruction cache 1220 for storing instructions and a separate data cache 1221 for storing data. Instructions and data stored within the respective processor caches are managed at the granularity of a cache line, which can be a fixed size (e.g., 64 bytes, 128 bytes, 512 bytes in length). Each core of the example embodiment has an instruction fetch unit 1210 for fetching instructions from the main memory 1200 and / or a shared third level (L3) cache 1216. The instruction fetch unit 1210 includes various well-known components, including a next instruction pointer 1203 for storing an address of a next instruction to be fetched from the memory 1200 (or one of the caches), an instruction translation lookaside buffer (ITLB) 1204 for storing recently used virtual-to-physical instruction addresses to improve address translation speed, a branch prediction unit 1202 for speculatively predicting instruction branch addresses, and a branch target buffer (BTB) 1201 for storing branch addresses and target addresses.

[0156] As noted, the decode unit 1230 includes DSP instruction decode circuitry / logic 1231 for decoding the DSP instructions described herein into micro-operations or "uops" and DSP instruction execution circuitry / logic 1241 for executing the DSP instructions. A write back / retirement unit 1250 retires executed instructions and writes back results.

[0157] Embodiments for performing signed and unsigned multiplication of packed data elements

[0158] One embodiment of the invention includes a first instruction for performing a vector packed unsigned double multiply operation. Specifically, execution of the first instruction multiplies a first packed unsigned doubleword (32-bit) selected from a packed quadword in a first source register with a second packed signed doubleword selected from another packed quadword in a second source register. In one embodiment, a 64-bit unsigned result is written into each of two quadwords (64-bit) of a destination register, which can be a 128-bit register. One embodiment of the first instruction is represented as VPMULUDHHQ xmm0, xmm1, xmm2 / m128, where xmm1 and xmm2 are the two source registers and xmm0 is the destination register.

[0159] One embodiment includes a second instruction for performing a vector packed double signed multiply operation. Execution of the second instruction will multiply a first packed signed doubleword (32-bit) selected from a packed quadword in a first source register with a second packed signed doubleword selected from a packed quadword in a second source register. In one implementation, a 64-bit signed result is written into each of two quadwords (64-bit) of a destination register, which can be a 128-bit register. One embodiment of the second instruction is represented as VPMULDHHQ xmmO, xmmI, xmm2 / m128, where xmmI and xmm2 are two source registers and xmmO is a destination register.

[0160] Figure 13 Figure illustrates exemplary data elements and bit distribution for exemplary source and / or destination registers (SRCx / DESTx). As illustrated, data elements can be packed into source and / or destination registers in words (16-bit), doublewords (32-bit), and / or quadwords (64-bit). In some embodiments that process complex numbers, real and imaginary parts can be stored in adjacent data element locations. For example, a real part can be stored as data element A, and a corresponding imaginary part can be stored as data element B. However, in other embodiments described herein, such as the 32x32 packed doubleword multiply instruction, packed data elements B-A, D-C, F-E, and H-G do not represent complex numbers.

[0161] Figure 14A Figure illustrates an exemplary architecture for executing packed multiply instructions. As mentioned, these instructions can use two packed source data operands stored in registers SRC1 1401 and SRC2 1402 in Figure 14A In the illustrated embodiment, SRC1 1401 stores doubleword data elements B-A and F-E, and source register SRC2 1402 stores doubleword data elements B-A and F-E.

[0162] Note that in some embodiments, certain components such as accumulators 1420-1421 and saturation circuits 1440-1441 shown in Figure 14A

[0163] ​In one embodiment, multiplier 1405 performs two doubleword multiplications simultaneously. For example, a first and second doubleword from the higher portion of each quadword in SRC1 (e.g., SRC1[63:32] and SRC1[127:96]) is multiplied by a corresponding first and second doubleword from the higher portion of each quadword in SRC2 (e.g., SRC2[63:32] and SRC2[127:96]). The 64-bit results of these multiplications are then stored in each quadword of a 128-bit destination. For example, the result of the multiplication SRC1[63:32]*SRC2[63:32] can be stored in DEST[63:0], while the result of the multiplication SRC1[127:96]*SRC2[127:96] can be stored in DEST[127:64]. This can be represented as:

[0164] DEST[63:0] SRC1[63:32]*SRC2[63:32];

[0165] DEST[127:64] SRC1[127:96]*SRC2[127:96];

[0166] As noted, one instruction can be executed to perform unsigned multiplication, where the source values SRC1[63:32], SRC2[63:32], SRC1[127:96], and SRC2[127:96], and the resulting data elements DEST[63:0] and DEST[127:64] are unsigned. Another instruction can be executed to perform signed multiplication, where the source values and the resulting data elements are signed. For example, VPMULUDHHQ can perform unsigned multiplication, while VPMULDHHQ can perform signed multiplication.

[0167] In one embodiment, the following described shift operations can be implemented on the quadword results stored in the destination register. For example, the results can be right or left shifted, and the most significant portion of the shifted results can be stored to the least significant portion of the destination register. Additionally, saturation and / or routing can be performed to generate the final results.

[0168] A method according to one embodiment of the present application is illustrated in Figure 15 The method can be implemented within the context of the processor and system architectures described above, but is not limited to any particular system architecture.

[0169] At 1501, a first instruction is fetched, the first instruction having fields for an opcode, first and second packed data source operands, and a packed data destination operand. At 1502, the first instruction is decoded to generate a first decoded instruction (e.g., decoded into multiple micro-ops). At 1503, two unsigned doubleword values associated with each of the first and second operands are fetched and stored as double packed doubleword data elements in each of the first and second source registers, respectively. As noted, in one embodiment, the source operands are stored in packed data registers having 128 bits of packed doubleword (32-bit) data elements.

[0170] At 1504, the first decoded instruction is executed to multiply the first unsigned doubleword data element from the first source register with the second unsigned doubleword data element from the second source register to generate a first unsigned quadword product, and simultaneously multiply the third unsigned doubleword data element from the first source register with the fourth unsigned doubleword data element from the second source register to generate a second unsigned quadword product.

[0171] At 1505, the shift operations described herein can be performed on the first and second quadword results. For example, the results can be right or left shifted, and the most significant portion of the shifted results can be stored to the least significant portion of the destination register. Additionally, saturation and / or routing can be performed to generate the final results.

[0172] At Figure 16 A method according to one embodiment of the application is illustrated in FIG. 16. The method can be implemented in the context of the processor and system architectures described above, but is not limited to any particular system architecture.

[0173] At 1601, a first instruction is fetched, the first instruction having fields for an opcode, first and second packed data source operands, and a packed data destination operand. At 1602, the first instruction is decoded to generate a first decoded instruction (e.g., decoded into multiple micro-ops). At 1603, two signed doubleword values associated with each of the first and second operands are fetched and stored as double packed doubleword data elements in each of the first and second source registers, respectively. As noted, in one embodiment, the source operands are stored in packed data registers having 128 bits of packed doubleword (32-bit) data elements.

[0174] At 1604, the first decoded instruction is executed to multiply a first signed doubleword data element from a first source register with a second signed doubleword data element from a second source register to generate a first signed quadword product, and simultaneously multiply a third signed doubleword data element from the first source register with a fourth signed doubleword data element from the second source register to generate a second signed quadword product.

[0175] At 1605, the shift operations described herein can be performed on the first and second quadword results. For example, the results can be right or left shifted, and the most significant portion of the shifted results can be stored to the least significant portion of the destination register. Additionally, saturation and / or routing can be performed to generate the final results.

[0176] Shifting and extracting data elements

[0177] One embodiment of the present invention includes instructions to perform various right and left shift operations on bits in each of a plurality of unsigned aligned quadwords, such as the results of unsigned multiplications described above. For example, in one embodiment, a quadword in a first packed data register or memory location (e.g., xmm2 / m128) is right shifted by a count of 6 bits specified in imm8[5:0]. The most significant 16 bits [63:48] of each of the shifted quadwords are written into bits [15:0] of the corresponding quadword in a destination register (e.g., xmm1). In one embodiment, a logical right shift of bits in each of the aligned unsigned quadwords in a first source register (e.g., xmm2) is performed by a count of 6 bits specified in a second source register or memory location (e.g., xmm3 / m128[5:0], xmm3 / m128[69:64]). The most significant 16 bits [63:48] of each of the shifted quadwords are written into bits [15:0] of the corresponding quadword in a destination register (e.g., xmm1). In one embodiment, a zero is shifted into the most significant bits during the right shift of each of the aligned unsigned quadwords.

[0178] The upper word results can be extracted from each of the right shifted quadwords without affecting the arithmetic flags. The shifted upper 16 bits from each of the quadwords can be rounded based on the round control and saturated to a word. If saturation occurs, a saturation flag can be set (e.g., in the MXCSR status register).

[0179] One embodiment also includes an instruction to perform a logical left shift of bits in each of the unsigned quadwords. For example, using a count of 6 bits specified in imm8[5:0], the bits in each of the aligned unsigned quadwords of a source register or memory location (e.g., xmm1 / m128) are logically left shifted. The most significant 16 bits [63:48] of each of the shifted quadwords are written into the corresponding quadword bits [15:0] in a destination register (e.g., xmm1). One embodiment performs a logical left shift of bits in each of the aligned unsigned quadwords of a first source register (e.g., xmm2) using a count of 6 bits specified in a second source register or memory location (e.g., xmm3 / m128[5:0], xmm3 / m128[69:64]). The most significant 16 bits [63:48] of each of the shifted quadwords are written into the corresponding quadword bits [15:0] in a destination register (e.g., xmm1).

[0180] One embodiment shifts 0 into the least significant bits (LSBs) during the left shift of each of the aligned unsigned quadwords. This embodiment extracts the upper word result from each of the left shifted quadwords without affecting the arithmetic flags. The shifted upper 16 bits from each of the quadwords can be rounded based on the round control and saturated to a doubleword. If saturation occurs, a saturation flag can be set in a status / control register (e.g., MXCSR status register).

[0181] The shift operations described herein can be performed in response to execution of a single instruction. These instructions can include VPSRLRSDUQ and VPSRLVRSDUQ to perform a logical right shift of a packed quadword by an amount based on an immediate and a source operand, respectively. In addition, left shift instructions include VPSLLRSDUQ and VPSLLVRSDUQ to perform a logical left shift of a packed quadword by an amount based on an immediate and a source operand, respectively.

[0182] In Figure 17 One embodiment of an architecture to right shift a packed quadword by an amount based on an immediate and write the most significant 32 bits of the resulting quadword to the lower 32 bits of a destination is illustrated in FIG. 17. In particular, two quadwords identified as quadword 0 (stored at bits 63:0) and quadword 1 (stored at bits 127:64) are illustrated in SRC2 1401. In response to a value (e.g., imm8[5:0]) included in immediate 1701, shift unit 1703 shifts the value in each quadword to the right by N bits, storing the result in temporary register or memory location 1720. Given that 6 immediate bits are used in this embodiment to identify the shift amount, N can have a range of values between 0 and 64 (i.e., 2 6 = 64). In this example, the shifted quadword is stored in temporary register or memory location 1720.Figure 17 In the particular example shown in FIG. 17, the bits b64 and b63 are shown shifted by a value N between 0 and 64. In one embodiment, the shift unit 1703 inserts zeros in the positions of the bits from which these values are shifted. Thus, in the illustrated example, the most significant bit positions occupied by b64, b63, and b62 are padded with zeros.

[0183] In one embodiment, after the shift operation, the 32 most significant bits of each shifted quadword are written to the least significant 32 bit positions of the destination register 1460. In the illustrated example, bits b64 and b63 are included in the most significant 32 bits. However, it should be noted that this is not always the case. For example, if the value of N is 32 or greater, then bit b64 will be shifted out of the range of the most significant 32 bits, which will be padded with all zeros. When this occurs, all zeros are written to the least significant bit positions in the destination register 1460.

[0184] As mentioned, in one embodiment, a 32-bit result can be extracted from each of the right-shifted quads without affecting the arithmetic flags in the processor. In addition, the shifted upper 32 bits from each of the quads can be rounded based on the rounding control, if necessary, and saturated to a word, if necessary. If saturation occurs, the saturation flag 1710 can be set (e.g., in the MXCSR status register). The round / saturate circuit 1704 can perform the rounding and / or saturation operations on the values written to the least significant bit positions of each quad.

[0185] In one embodiment, the shift unit 1703 is integrated within the adder network 1410-1411 in Figure 14A and the round / saturate circuit 1704 is integrated in the saturate circuit 1440-1441. Alternatively, the shift unit 1703 and the round circuit can be implemented as circuitry / logic separate from the architecture components shown in Figure 14A

[0186] Figure 18 An embodiment is illustrated in which the shift value (N) specifying the amount by which the shift unit 1703 is to right-shift the two quads is specified in another source register, such as SRC3 1402. A 6-bit value can be stored in the least significant or most significant positions of a packed data element, such as a packed byte or packed word, with the bits outside of the 6 bits being set to zero or ignored. In one embodiment, the operation of the shift unit 1703 is otherwise substantially the same as described above with reference to Figure 17

[0187] In one embodiment, the shift unit 1703 is integrated within the adder network 1410-1411 in Figure 19 ​​The diagram in FIG. 13 illustrates one embodiment of an architecture for shifting a packed four word left based on an immediate value and writing the most significant 32 bits of the resulting four word to the lower 32 bits of the destination. Specifically, two four words are illustrated in SRC1 1301 as four word 0 (stored at bits 63:0) and four word 1 (stored at bits 127:64). In response to a value included in the immediate 1303 (e.g., imm8[5:0]), shift unit 1305 shifts the value in each four word left by N bits, storing the result in temporary register or memory location 1310. Given that 6 immediate bits are used to identify the shift amount in this embodiment, N can have a range of values between 0 and 64 (i.e., 2 6 Figure 19 In the specific example illustrated in FIG. 13, bits b0, bl, and b2 are shown shifted by a value N between 0 and 64. In one embodiment, shift unit 1305 inserts zeros in the position of the bits that are shifted from the four word. Thus, in the illustrated example, the least significant bit positions occupied by b0, bl, and b2 are padded with zeros.

[0188] In one embodiment, after the shift operation, the 32 most significant bits of each shifted four word are written to the least significant 32 bits of the destination register 1360. In the illustrated example, bits b2, bl, and b0 are included in the most significant bits. However, it should be noted that this is not always the case. For example, if the value of N is less than 32, then bit b0 will be in the lower 32 bits of the resulting four word (i.e., bit b0 will not be included in the most significant 32 bits). Similarly, if N is 64, then the shifted four word is padded with all zeros, which will be written to the least significant bit positions in destination register 1360.

[0189] As mentioned, in one embodiment, a 32-bit result can be extracted from each of the left shifted four words without affecting the arithmetic flags in the processor. Additionally, the shifted upper 32 bits from each of the four words can be rounded based on the rounding control and saturated to a word if necessary. If saturation occurs, the saturation flag 1310 can be set (e.g., in the MXCSR status register). The rounding / saturation circuit 1304 can perform the rounding and / or saturation operation on the value written to the least significant bit positions of each four word.

[0190] Figure 20 ​Figure illustrates one embodiment in which the shift value (N) specifying the amount by which the two quadwords are to be right-shifted is specified in another source register, such as SRC2 1402. The 6-bit value can be stored in the least significant or most significant position of a packed data element, such as a packed byte or packed word, with the bits outside of the 6 bits being set to zero or ignored. In one embodiment, the operation of shift unit 1703 is otherwise as described above with reference to Figure 17 substantially the same.

[0191] Signed / unsigned byte vector packed multiply and accumulate

[0192] One embodiment of the present invention includes a first instruction for performing a vector packed unsigned byte multiply operation followed by accumulation with an existing doubleword value. Specifically, execution of the first instruction multiplies 16 packed unsigned bytes from a first source register with 16 corresponding packed unsigned bytes from a second source register to generate 16 unsigned products. Four sets of the 16 unsigned products are accumulated to generate four temporary results. The four temporary results are then accumulated with an unsigned doubleword value from a destination register and the result is stored back to the destination register. In one embodiment, the four temporary results are zero-extended prior to performing the accumulation. One embodiment of the first instruction is represented as VPDPBUUD xmm1, xmm2, xmm3 / m128, where xmm1, xmm2, and xmm3 are source registers and xmm3 is a destination register.

[0193] One embodiment of the present invention includes a second instruction for performing a vector packed signed byte multiply operation followed by accumulation with an existing doubleword value. Specifically, execution of the second instruction multiplies 16 packed signed bytes from a first source register with 16 corresponding packed signed bytes from a second source register to generate 16 signed products. Four sets of the 16 signed products are accumulated to generate four temporary results. The four temporary results are then accumulated with a signed doubleword value from a destination register and the result is stored back to the destination register. In one embodiment, the four temporary results are zero-extended prior to performing the accumulation. One embodiment of the first instruction is represented as VPDPBSSD xmm1, xmm2, xmm3 / m128, where xmm1, xmm2, and xmm3 are source registers and xmm3 is also a destination register.

[0194] Figure 14B Figure illustrates many of the same features as Figure 14AThe same components, one difference being that the output of the destination register 1460 operates as a third source register for the accumulate operation described herein, as indicated by the data lines 1470-1471. In one embodiment, the multiplier 1405 simultaneously performs 16 unsigned / signed byte multiplications by multiplying each byte in SRC1 1401 with the corresponding byte in SRC2 1402 to generate 16 unsigned / signed products. In one embodiment, the adder network 1410-1411 then adds four sets of four unsigned / signed products to generate four temporary results, which can be stored in temporary registers or memory locations. Each of the four temporary results is then zero-extended and added to the corresponding 32-bit data element from the destination register 1460 to generate a final result. These final results are then written back to the corresponding data element locations in the destination register.

[0195] In one embodiment, the vector packed unsigned multiply and accumulate is represented as:

[0196]

[0197]

[0198] In the above code, the multiplier 1405 performs the above multiplication to generate the above products. The adder network 1410 adds the products SRC2[31 :24]*SRC3[31 :24], SRC2[23:16]*SRC3[23:16], SRC2[15:8]*SRC3[15:8], and SRC2[7:0]*SRC3[7:0] to store the 17-bit result in TEMP0, and also adds the products SRC2[63:56]*SRC3[63:56], SRC2[55:48]*SRC3[55:48], SRC2[47:40]*SRC3[47:40], and SRC2[39:32]*SRC3[39:32] to store the 17-bit result in TEMP1.

[0199] Similarly, adder network 1411 adds the products SRC2[95:88]*SRC3[95:88], SRC2[87:80]*SRC3[87:80], SRC2[79:72]*SRC3[79:72], SRC2[71:64]*SRC3[71:64] and stores the 17-bit result in TEMP2, and also adds the products SRC2[127:120]*SRC3[127:120], SRC2[119:112]*SRC3[119:112], SRC2[111:104]*SRC3[111:104], SRC2[103:96]*SRC3[103:96] and stores the 17-bit result in TEMP3.

[0200] AddToDword operation then zero-extends each of these 17-bit results to 32 bits, and adds each resulting 32-bit value to one of the four doublewords stored in the destination register. The final results are then stored back into the corresponding doubleword locations in the destination register.

[0201] In one embodiment, vector packed signed multiply and accumulate is represented as:

[0202]

[0203] In the above code, multiplier 1405 performs the above multiplications to generate the above products. Adder network 1410 adds the products SRC2[31:24]*SRC3[31:24], SRC2[23:16]*SRC3[23:16], SRC2[15:8]*SRC3[15:8], and SRC2[7:0]*SRC3[7:0] and stores the 17-bit result in TEMP0, and also adds the products SRC2[63:56]*SRC3[63:56], SRC2[55:48]*SRC3[55:48], SRC2[47:40]*SRC3[47:40], and SRC2[39:32]*SRC3[39:32] and stores the 17-bit result in TEMP1.

[0204] Similarly, adder network 1411 adds the products SRC2[95:88]*SRC3[95:88], SRC2[87:80]*SRC3[87:80], SRC2[79:72]*SRC3[79:72], SRC2[71:64]*SRC3[71:64] and stores the 17-bit result in TEMP2, and also adds the products SRC2[127:120]*SRC3[127:120], SRC2[119:112]*SRC3[119:112], SRC2[111:104]*SRC3[111:104], SRC2[103:96]*SRC3[103:96] and stores the 17-bit result in TEMP3.

[0205] AddToDword operation then sign-extends each of these 17-bit results to 32 bits and adds each resulting 32-bit value to one of the four doublewords stored in the destination register. The final results are then stored back to the corresponding doubleword locations in the destination register.

[0206] In one embodiment, the shift, round, and saturation operations described herein can be implemented on the doubleword results stored in the destination register. For example, the results can be right or left shifted, and the most significant portion of the shifted results can be stored to the least significant portion of the destination register. In addition, saturation and / or rounding can be performed to generate the final results.

[0207] A method according to one embodiment of the present application is illustrated in Figure 21 The method can be implemented in the context of the processor and system architectures described above, but is not limited to any particular system architecture.

[0208] At 2101, a first instruction is fetched, the first instruction having fields for an opcode, a first packed data source operand, a second packed data source operand, and a third packed data source operand, and a packed data destination operand. At 2102, the first instruction is decoded to generate a first decoded instruction (e.g., decoded into multiple micro-operations). At 2103, a first and second set of 16 unsigned bytes are fetched for each of the first and second operands, respectively, and stored as packed unsigned byte data elements in each of the first and second source registers, respectively.

[0209] At 2104, the first decoded instruction is executed to multiply each byte from the first source register with a corresponding byte in the second source register to generate 16 unsigned products. At 2105, four of the unsigned products are added in each of four groups to generate four temporary results.

[0210] At 2106, each of the four temporary results is zero-extended and accumulated with one of the unsigned doubleword values stored in the third source register, which can be the same physical register as the destination register. For example, each of the four temporary results TEMP0, TEMP1, TEMP2, and TEMP3 can be extended to 32 bits and added to the current values in the doubleword data element locations A-B, C-D, E-F, and G-H, respectively, in the destination register DEST 1460 (see Figure 14A ). At 2107, each of the final unsigned results is stored in a packed doubleword data element location in the destination register DEST 1460.

[0211] Although not shown in Figure 21 , the shift operations described herein can be performed on these final unsigned results. For example, the results can be right-shifted or left-shifted, and the most significant portion of the shifted results can be stored to the least significant portion of the destination register. Additionally, saturation and / or routing can be performed to generate the final results.

[0212] A method according to one embodiment of the application is illustrated in Figure 22 . The method can be implemented within the context of the processor and system architectures described above, but is not limited to any particular system architecture.

[0213] At 2201, a first instruction is fetched, the first instruction having fields for an opcode, a first packed data source operand, a second packed data source operand, and a third packed data source operand, and a packed data destination operand. At 2202, the first instruction is decoded to generate a first decoded instruction (e.g., decoded into multiple micro-operations). At 2203, a first and second set of 16 signed bytes are fetched for each of the first and second operands, respectively, and stored as packed signed byte data elements in each of first and second source registers, respectively.

[0214] At 2204, the first decoded instruction is executed to multiply each byte from the first source register with a corresponding byte in the second source register to generate 16 signed products. At 2205, four of the unsigned products are added in each of four groups to generate four temporary results.

[0215] At 2206, each of the four temporary results is sign-extended and accumulated with one of the signed doubleword values stored in a third source register, which can be the same physical register as the destination register. For example, each of the four temporary results TEMP0, TEMP1, TEMP2, and TEMP3 can be extended to 32 bits and added to the current values in doubleword data element positions A-B, C-D, E-F, and G-H, respectively, in the destination register DEST 1460 (see Figure 14B ). At 2207, each of the final signed results is stored in a packed doubleword data element position in the destination register DEST 1460.

[0216] Although not shown in Figure 22 , the shift operations described herein can be performed on these final signed results. For example, the results can be right-shifted or left-shifted, and the most significant portion of the shifted results can be stored to the least significant portion of the destination register. In addition, saturation and / or routing can be performed to generate the final results.

[0217] In the foregoing specification, embodiments of the application have been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes can be made thereto without departing from the broader spirit and scope of the application as set forth in the appended claims. The Specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

[0218] Embodiments of the application can include each of the steps described above. The steps can be embodied in machine-executable instructions which can be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, the steps can be performed by a special purpose hardware component, or any combination of programmed computer components and custom hardware components.

[0219] As described herein, instructions can refer to specific configurations of hardware such as application specific integrated circuits (ASICs) configured to perform certain operations or having a predetermined functionality or software instructions stored in memory embodied in a non-transitory computer readable medium. Hence, those skilled in the art will appreciate that the technology illustrated in the figures can be implemented using code and data stored and executed on one or more electronic devices (e.g., an end station, a network element, etc.). Such electronic devices store and communicate (internally and / or with other electronic devices over a network) code and data using computer machine- readable media such as non-transitory computer machine-readable storage media (e.g., magnetic disks; optical disks; random access memory; read only memory; flash memory devices; phase-change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustical or other form of propagated signals - such as carrier waves, infrared signals, digital signals, etc.). In addition, such electronic devices typically include a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., a keyboard, a touchscreen, and / or a display), and a network connection. The coupling of the set of processors and other components is typically through one or more busses and bridges (also termed as bus controllers). The storage device and signals carried by the network connection are examples of machine-readable storage media and machine-readable communication media, respectively. Thus, the storage device of a given electronic device typically stores code and / or data for execution on the set of one or more processors of that electronic device. Of course, one or more parts of an embodiment of the application can be implemented using different combinations of software, firmware, and / or hardware. Throughout this detailed description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application can be practiced without some of these specific details. In certain instances, well-known structures and functions were not described in elaborate detail in order to avoid obscuring the subject matter of the present application. Accordingly, the scope and spirit of the application should be judged in terms of the claims and the equivalents thereof, rather than the details of the descriptions.

Claims

1. A processor comprising: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed byte data elements; a second source register to store a second plurality of packed byte data elements; an execution circuit to execute the decoded instruction, the execution circuit comprising: a multiplier circuit to simultaneously multiply each of the first plurality of packed byte data elements with a corresponding packed byte data element of the second plurality of packed byte data elements to generate a plurality of products; an adder circuit to add a specified set of products to generate a temporary result for each set of products; a zero or sign extension circuit to zero or sign extend the temporary result for each set to generate an extended temporary result for each set; an accumulation circuit to combine each of the extended temporary results with a selected packed data value stored in a third source register to generate a plurality of final results; and a destination register to store the plurality of final results as a plurality of packed data elements in a specified data element location.

2. The processor of claim 1, wherein, The zero or sign extension circuit increases a bit width of each temporary result to equal a width of the selected backup data value stored in the third source register.

3. The processor of claim 1 or 2, wherein, The third source register and the destination register are the same physical register.

4. The processor of claim 1, wherein, The specified set of products includes four sets of four products, the adder circuit to add each of the four products in each set to generate four temporary results.

5. The processor of claim 4, wherein, Each of the four temporary results has a width of 17 bits, the zero or sign extension circuit to increase the width of 17 bits to 32 bits to generate an extended temporary result.

6. The processor of claim 5, wherein, The accumulation circuit to add four of the extended temporary results with four different packed doubleword data elements in the third source register.

7. The processor of claim 1 or 6, wherein, The first, second, and third source registers are 128-bit packed data registers, and wherein the first and second source registers store 16 packed byte data elements and the third source register stores 4 packed doubleword data elements.

8. The processor of claim 1, further comprising: a set of temporary registers or other temporary storage locations to store the temporary result for each set of products.

9. A method comprising: decoding a first instruction to generate a decoded instruction; storing a first plurality of packed byte data elements in a first source register; storing a second plurality of packed byte data elements in a second source register; simultaneously multiplying each of the first plurality of packed byte data elements with a corresponding packed byte data element of the second plurality of packed byte data elements to generate a plurality of products; adding a specified set of products to generate a temporary result for each set of products; zero or sign extending the temporary result for each set to generate an extended temporary result for each set; accumulating each of the expanded temporary results with a selected packed data value stored in a third source register to generate a plurality of final results; and storing the plurality of final results as a plurality of packed data elements in the specified data element locations.

10. The method of claim 9, wherein, zero or sign extending the temporary result for each set includes: increasing a bit width of each temporary result to a width equal to a selected packed data value stored in the third source register.

11. The method of claim 9 or 10, wherein, the plurality of final results are stored in the specified data element locations of a destination register, and wherein the third source register and the destination register are the same physical register.

12. The method of claim 9, wherein, the specified set of products includes four sets of four products, and wherein each of the four products in each set are added together to generate four temporary results.

13. The method of claim 12, wherein, each of the four temporary results has a width of 17 bits, and a zero or sign extension circuit increases the width of 17 bits to 32 bits to generate an expanded temporary result.

14. The method of claim 13, wherein, accumulating each of the expanded temporary results with a selected packed data value stored in a third source register includes: adding four of the expanded temporary results with four different packed doubleword data elements in the third source register.

15. The method of claim 9 or 14, wherein, the first source register, the second source register, and the third source register are 128-bit packed data registers, and wherein the first source register and the second source register store 16 packed byte data elements, and the third source register stores 4 packed doubleword data elements.

16. The method of claim 15, further comprising: storing the temporary result for each set of products in a set of temporary registers or other temporary storage locations.

17. A machine-readable medium having stored thereon program code which, when executed by a machine, causes the machine to perform operations comprising: decoding a first instruction to generate a decoded instruction; storing a first plurality of packed byte data elements in a first source register; storing a second plurality of packed byte data elements in a second source register; simultaneously multiplying each of the first plurality of packed byte data elements with a corresponding packed byte data element in the second plurality of packed byte data elements to generate a plurality of products; adding a specified set of products to generate a temporary result for each set of products; zero or sign extending the temporary result for each set to generate an expanded temporary result for each set; accumulating each of the expanded temporary results with a selected packed data value stored in a third source register to generate a plurality of final results; and storing the plurality of final results as a plurality of packed data elements in the specified data element locations.

18. The machine readable medium of claim 17, wherein, the program code, when executed by the machine, causes the machine to perform operations comprising: a zero or sign extension circuit increases a bit width of each temporary result to a width equal to a selected packed data value stored in the third source register.

19. The machine readable medium of claim 17 or 18, wherein, The plurality of final results are stored in the specified data element locations of a destination register, and wherein the third source register and the destination register are the same physical register.

20. The machine readable medium of claim 17, wherein, The specified set of products includes four sets of four products, and wherein each of the four products in each set are added together to generate four temporary results.

21. The machine readable medium of claim 20, wherein, Each of the four temporary results has a width of 17 bits, and a zero-extend or sign-extend circuit increases the width of 17 bits to 32 bits to generate an extended temporary result.

22. The machine readable medium of claim 21, wherein, The program code, when executed by the machine, causes the machine to perform operations of: adding four of the extended temporary results to four different packed doubleword data elements in the third source register.

23. The machine readable medium of claim 17 or 22, wherein, The first source register, the second source register, and the third source register are 128-bit packed data registers, and wherein the first source register and the second source register store 16 packed byte data elements, and the third source register stores 4 packed doubleword data elements.

24. The machine-readable medium of claim 23, the program code, when executed by the machine, causes the machine to perform operations of: storing the temporary results for each set of products in a set of temporary registers or other temporary storage locations.

25. An apparatus comprising: means for decoding a first instruction to generate a decoded instruction; means for storing a first plurality of packed byte data elements in a first source register; means for storing a second plurality of packed byte data elements in a second source register; means for simultaneously multiplying each of the first plurality of packed byte data elements with a corresponding packed byte data element of the second plurality of packed byte data elements to generate a plurality of products; means for adding a specified set of products to generate a temporary result for each set of products; means for zero-extending or sign-extending the temporary result for each set to generate an extended temporary result for each set; means for accumulating each of the extended temporary results with a selected packed data value stored in a third source register to generate a plurality of final results; and means for storing the plurality of final results as a plurality of packed data elements in specified data element locations. means for storing the plurality of final results as a plurality of packed data elements in specified data element locations.

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