Reducing Silent Data Corruption in Error Control Coding

Abstract

One embodiment provides a silent data corruption (SDC) mitigation circuit. The SDC mitigation circuit includes a comparator circuit and SDC mitigation logic. The comparator circuit is used to compare a successful decoded codeword, which has been considered successful by an error correction circuit, with a corresponding received codeword. The SDC mitigation logic is used to reject the successful decoded codeword if the distance between the corresponding received codeword and the successful decoded codeword is greater than or equal to a threshold value.

Description

Technical Field

[0001] The present disclosure relates to silent data corruption, and more particularly to mitigating silent data corruption in error control coding. Background Art

[0002] Error correction codes (ECCs) can be used to facilitate accurate data retrieval from memory devices including, for example, NAND flash memory, NOR flash memory, three-dimensional cross-point memory (3DXP), etc. Error correction codes are configured to mitigate errors that may be caused by non-ideal characteristics of the medium. Error correction codes can provide a reliability with an uncorrectable bit error rate (UBER) less than, for example, 1E-17, where the input (i.e., raw) bit error rate (RBER) is approximately 1E-3. This can be achieved by encoding a sequence of K data bits into a sequence of N codeword bits including N-K parity bits. The N-bit codewords can then be stored on the medium. Errors introduced by non-ideal characteristics of the medium may be included in the data read from the medium. The decoder can be configured to recover the encoded sequence of K bits in the presence of at least some errors.

[0003] The output of the decoder includes three possible results: 1) the data is corrected to the expected codeword and the decoder declares success; 2) the data is not corrected and the decoder declares failure; or 3) the data is decoded into an unexpected codeword and the decoder declares success. The first possible result is preferred. The second possible result is referred to as an "ECC failure" and can be included in the UBER. The third possible result is referred to as a "silent data corruption" (SDC) or "miscorrect" event. SDC events are generally not desired. Brief Description of the Drawings

[0004] The features and advantages of the claimed subject matter will become apparent from the following detailed description of embodiments consistent with the claimed subject matter, which description should be considered in reference to the accompanying drawings, in which:

[0005] Figure 1 A functional block diagram of a silent data corruption (SDC) mitigation system consistent with several embodiments of the present disclosure is shown.

[0006] Figure 2 is a flowchart of a threshold determination operation according to various embodiments of the present disclosure; and

[0007] Figure 3 is a flowchart of an SDC mitigation operation according to various embodiments of the present disclosure.

[0008] While the following detailed description will proceed with reference to illustrative embodiments, many alternatives, modifications, and variations of the illustrative embodiments will be apparent to those skilled in the art. Detailed Description

[0009] For a given input RBER, the probability of an SDC event (“SDC probability”) is typically lower than the UBER at that RBER. Generally, the SDC probability is related to the RBER and increases as the RBER increases. A memory device specification may specify a maximum SDC probability to be met for a range of RBERs, including, for example, an RBER of 0.5 corresponding to a received codeword that is a random sequence. For example, a memory device specification may include a maximum SDC probability of 1E-25. For relatively small RBERs (e.g., when the RBER is less than 1E-3), the specification may be relatively easier to meet, but for relatively large RBERs (e.g., 0.5), the specification is relatively more difficult to meet. Relatively large RBERs are related to the failure modes of the selected memory device (e.g., word line or bit line failures).

[0010] An example technique configured to detect SDC events is by adding cyclic redundancy check (CRC) bits to a data sequence. For example, 32-bit CRC can reduce the SDC probability by ten orders of magnitude. However, the additional bits of the CRC may reduce the overall code rate and thus increase the associated overhead. The circuitry for determining the CRC bits at the encoder may increase complexity and increase latency. Similarly, at the decoder, using the CRC to verify the integrity of the decoded codeword (to detect misdetection) increases complexity and increases latency.

[0011] Generally, the present disclosure relates to mitigating silent data corruption in error control coding. An apparatus, method, and / or system is configured to compare a successfully decoded codeword with the corresponding received codeword. As used herein, a successfully decoded codeword is a codeword that has been considered successful by an error correction circuit. The apparatus, method, and / or system is further configured to: if the distance between the corresponding received codeword and the successfully decoded codeword is greater than or equal to a threshold, reject the successfully decoded codeword.

[0012] The threshold can be determined at least in part based on a specific error correction code (ECC), RBER, and UBER. The threshold is configured to facilitate rejection of a successfully decoded codeword when the number of bit errors between the successfully decoded codeword and the received codeword is relatively large. In this context, relatively large corresponds to the received codeword being relatively close to the decoding sphere boundary of the successfully decoded codeword, i.e., relatively far from the successfully decoded codeword. This distance corresponds to the Hamming distance. A received codeword that is relatively far from the successfully decoded codeword is likely to be relatively more associated with an SDC event compared to a received codeword that is relatively closer to the successfully decoded codeword. In an embodiment, the threshold can be determined at least in part based on the binomial distribution cumulative density function and at least in part based on the variation of UBER, as will be described in more detail below.

[0013] The apparatus, method, and / or system are configured to operate on a successfully decoded codeword that has been considered successful by the error correction circuit and thus do not affect the configuration and / or operation of the error correction circuit. This distance corresponds to the Hamming distance and can thus be determined by performing a bit-by-bit comparison of the two codewords. Such a bit-by-bit comparison can be implemented by a relatively simple comparator circuit, and the comparison operation can be performed relatively quickly, e.g., within two clock cycles. The threshold can be determined at least in part based on the error correction code implemented by the error correction circuit. The threshold can also be determined at least in part based on whether the codeword can be punctured and / or whether there are erasures.

[0014] In one embodiment, the error correction code can conform to and / or be compatible with a low-density parity-check (LDPC) error correction code. In another embodiment, the error correction code can conform to and / or be compatible with a Reed-Solomon error correction code. In this embodiment, the operation of the apparatus, method, and / or system can not affect the symbol correction strength, as will be described in more detail below.

[0015] The apparatus, method, and / or system are configured to achieve a target SDC probability for any RBER, including a random sequence with RBER = 0.5. The target SDC probability can be achieved without a significant increase in the associated UBER. In a non-limiting example, without SDC mitigation, the UBER increment may be less than one percent of the UBER. For example, as described herein, depending on the block length and / or code rate, the SDC probability can be reduced by approximately 10 to 50 orders of magnitude.

[0016] Figure 1 A functional block diagram of a silent data corruption (SDC) mitigation system 100 consistent with several embodiments of the present disclosure is shown. The SDC mitigation system 100 can correspond to and / or be included in a mobile phone, including but not limited to a smart phone (e.g., Based on telephone, Based on telephone, based on telephone, etc.); wearable devices (e.g., wearable computers, "smart" watches, smart glasses, smart clothing, etc.) and / or systems; computing systems (e.g., servers, workstation computers, desktop computers, laptop computers, tablet computers (e.g., etc.), ultra-portable computers, ultra-mobile computers, netbook computers, and / or subnotebook computers); and so on.

[0017] The SDC mitigation system 100 includes a processor circuit 102, a memory controller 104, and a memory device 106. For example, the processor circuit 102 may correspond to a single-core or multi-core general-purpose processor, such as, for example, a general-purpose processor provided by a company, etc. The memory controller 104 may be coupled to the processor circuit 102 and / or included in the processor circuit 102, and is configured to couple the processor circuit 102 to the memory device 106.

[0018] The memory device 106 may include, but is not limited to, NAND flash memory (e.g., triple-level cell (TLC) NAND or any other type of NAND (e.g., single-level cell (SLC), multi-level cell (MLC), quad-level cell (QLC), etc.)), NOR memory, solid-state memory (e.g., planar or three-dimensional (3D) NAND flash memory or NOR flash memory), storage devices using chalcogenide phase change materials (e.g., chalcogenide glass), byte-addressable non-volatile memory devices, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory (e.g., ferroelectric polymer memory), byte-addressable randomly addressable 3D cross-point memory, ferroelectric transistor random access memory (Fe-TRAM), magnetoresistive random access memory (MRAM), phase change memory (PCM, PRAM), resistive memory, ferroelectric memory (F-RAM, FeRAM), spin transfer torque memory (STT), thermally assisted switching memory (TAS), millipede memory, floating gate RAM (FJG RAM), magnetic tunnel junction (MTJ) memory, electro-chemical cell (ECM) memory, binary oxide filament cell memory, interface exchange memory, battery-backed RAM, two-way memory, nanowire memory, electrically erasable programmable read-only memory (EEPROM), etc. In some embodiments, the byte-addressable randomly addressable 3D cross-point memory may include a transistorless stackable cross-point architecture, where memory cells are located at the intersections of word lines and bit lines and are individually addressable, and where bit storage is based on changes in bulk resistance.

[0019] The memory device 106 includes a first plurality of word lines (WLs) WL00, WL01... WL0N, a second plurality of word lines WL10, WL11... WL1N, a plurality of bit lines (BLs) BL0, BL1... BLM, and a plurality of memory cells, e.g., memory cell 116. Each WL may cross a BL at a memory cell (e.g., memory cell 116). For example, the first plurality of WLs WL00, WL01... WL0N, the plurality of BLs BL0, BL1... BLM, and the corresponding plurality of memory cells may correspond to a first deck, and the second plurality of WLs WL10, WL11... WL1N, the plurality of BLs BL0, BL1... BLM, and the corresponding plurality of memory cells may correspond to a second deck of a pair of decks. Thus, each deck may include an array of memory cells, and the memory device 106 may include a plurality of decks.

[0020] The processor circuit 102 may be configured to provide memory access requests to the memory controller 104, e.g., write requests and / or read requests. For example, a read request may include address information for reading data from a memory location in the memory device 106 corresponding to the address information. Then, the memory controller 104 may be configured to manage reading data from the memory device 106.

[0021] The memory controller 104 includes a memory controller control circuit 110, an error correction circuit 112, and an SDC mitigation circuit 114. The memory controller control circuit 110 is configured to determine the address of a target memory cell in response to a memory access request from the processor circuit 102. The memory controller control circuit 110 is configured to identify a corresponding WL and a corresponding BL at least in part based on the determined address. The memory controller control circuit 110 is further configured to select the target memory cell(s) and write to the selected target memory cell(s) or read from the selected target memory cell(s).

[0022] The memory controller control circuit 110 is configured to receive data to be written to the memory device 106 from the processor circuit 102, e.g., in response to a write request. Then, the memory controller circuit 110 may be configured to provide the data to be written to the error correction circuit 112. The error correction circuit 112 may be configured to encode the data to be written with error correction information to generate a corresponding codeword. In one example, the error correction circuit 112 may be configured to implement a low density parity check (LDPC) error correction technique. In another example, the error correction circuit 112 may be configured to implement a Reed - Solomon error correction technique.

[0023] Then, the memory controller control circuit 110 can be configured to store the corresponding codeword in the memory device 106. The memory controller control circuit 110 can be configured to read the codeword in response to a read request and provide the received codeword to the error correction circuit 112. Then, the error correction circuit 112 can be configured to decode the received codeword.

[0024] The codeword can have a block length N, which includes a number of N-k data bits and a number of k error correction bits. The block length corresponds to the total number of bits (N) in the codeword. The data bits correspond to the information bits, and the error correction bits correspond to the parity bits. The block length can be related to the type of the memory device. For example, for a memory device including NAND flash memory, the block length can be 4 kB (kilobytes). In another example, for a memory device including three-dimensional cross-point memory, the block length can be 512 bytes. In another example, the block length can be 64 kB, 128 kB or more. As used herein, the "code rate" corresponds to the fraction of the codeword that is information bits, i.e., the number of information bits divided by the total number of bits in the codeword ((N-k) / N).

[0025] The SDC mitigation circuit 114 includes SDC mitigation logic 120, a comparator circuit 122, SDC mitigation memory 124, and threshold determination logic 126. The SDC mitigation circuit 114 is configured to perform SDC mitigation operations. The SDC mitigation logic 120 is configured to retrieve successful decoded codewords from the error correction circuit 112 and / or the memory controller control circuit 110. The SDC mitigation memory 124 is configured to store one or more SDC mitigation parameters. The SDC mitigation parameters 125 can include but are not limited to RBER, UBER, the maximum change in UBER (i.e., the maximum allowable increment) (ΔUBER), ECC identifiers, puncturing information, and / or erase information.

[0026] The SDC mitigation parameter 125 may also include one or more thresholds. Each threshold may be determined a priori and may be adjusted during operation. The threshold may be determined at least in part based on a particular error correction technique, the amount of puncturing and / or erasure that can be performed on the stored codewords. Puncturing corresponds to including fewer than all of the information bits and / or fewer than all of the parity bits in the stored codeword. Puncturing may be implemented to more closely fit each codeword to the memory device storage architecture and / or capacity. Erasure corresponds to bits that cannot be read due to a failure in the memory device. For example, a word line and / or bit line may render the corresponding bit unavailable. For example, the nominal threshold may be determined a priori at least in part based on the error correction technique. The nominal threshold may be adjusted at least in part based on the amount of puncturing and / or erasure that can be performed on the stored codewords. Whether puncturing can be performed on the stored codewords may be known a priori. The amount of erasure may be known a priori and / or may change over the lifetime of the memory device.

[0027] In an embodiment, the binomial distribution cumulative density function may be used to determine the threshold d. As is known, the cumulative density function is related to the probability mass function. The binomial distribution with parameters N and p corresponds to the discrete probability distribution of a number of first outcomes out of two possible outcomes in a sequence of N independent experiments. Each experiment has a Boolean (i.e., binary) outcome. Each outcome corresponds to a random variable containing a single information bit, e.g., a first outcome with probability p or a second outcome with probability q = 1 - p. As used herein, N corresponds to the number of bits in the codeword, a single information bit corresponds to a bit error / non-bit error, and the probability p corresponds to the RBER.

[0028] The probability of having exactly j first outcomes (i.e., bit errors) in N (i.e., the number of bits in the codeword) trials is given by the binomial distribution probability mass function:

[0029]

[0030] where

[0031]

[0032] The corresponding binomial distribution cumulative density function (CDF) is:

[0033]

[0034] where corresponds to the largest integer less than or equal to j. Thus, the CDF corresponds to the probability of having up to (i.e., less than or equal to) j bit errors in N bits, and

[0035] 1 - Pr(X ≤ j)

[0036] corresponds to the probability of having more than j bit errors in N bits.

[0037] It can be understood that a threshold relatively close to a successfully decoded codeword may cause an increase in UBER and rejection of a correctly decoded successful codeword. Conversely, a threshold relatively far from a successfully decoded codeword may not significantly affect UBER but may correspond to an SDC event. Determining the threshold using the CDF is configured to reduce the likelihood of SDC events without significantly increasing UBER. For example, the probability of having more than j bit errors in N bits can be set to the maximum allowable change (ΔUBER) in UBER, i.e.,

[0038] 1 - Pr(X ≤ j) = ΔUBER

[0039] In one non - limiting example, ΔUBER can be less than or equal to 0.01 * UBER. Then the distance d can be set to j that satisfies 1 - Pr(X ≤ j) = ΔUBER.

[0040] Thus, in operation, the threshold determination logic 126 can be configured to determine the RBER and UBER. For example, the RBER and UBER can be included in the SDC mitigation parameter 125, which is stored in the SDC mitigation memory 124. For example, the threshold determination logic 126 can be configured to retrieve the RBER and UBER from the SDC mitigation memory 124. Then, the threshold determination logic 126 can be configured to identify the ECC implemented by the error correction circuit 112 and the corresponding codeword size N. For example, the SDC mitigation parameter 125 can include an ECC identifier. Then, the threshold determination logic 126 can be configured to determine the maximum allowable change ΔUBER in UBER at least partially based on UBER. Then, as described herein, the threshold determination logic 126 can be configured to determine the threshold d at least partially based on N, RBER, and ΔUBER.

[0041] The threshold (nominal threshold) can initially be determined without puncturing and / or erasure. The SDC mitigation parameter 125 can be configured to include an indicator of whether there is puncturing and / or erasure, and can also include the bit positions of the puncturing and / or erasure. Whether there is puncturing can be known a priori, and whether there is erasure can be determined in operation by, for example, the error correction circuit 112. In some embodiments, if there is puncturing and / or erasure, the threshold can be updated. For example, when determining the threshold, the number of valid bits in the codeword can be used for N (i.e., the number of bits in the codeword minus the number of punctured bits and / or erased bits). Thus, the threshold can be updated to accommodate puncturing and / or erasure. Then a decision to accept or reject a successfully decoded codeword can be made based on the valid bits.

[0042] The SDC mitigation logic 120 is configured to retrieve from the memory controller control circuit 110 the received codeword corresponding to the successfully decoded codeword. The corresponding received codeword is the codeword read from the memory device 106. When the corresponding received codeword is input to the error correction circuit 112, the successfully decoded codeword is the output from the error correction circuit 112. The SDC mitigation logic 120 may be configured to ignore uncorrectable decoded codewords and the corresponding received codewords.

[0043] Then, the SDC mitigation logic 120 may be configured to provide the successfully decoded codeword and the corresponding received codeword to the comparator circuit 122. Then, the comparator circuit 122 may be configured to perform a bit-by-bit comparison of the successfully decoded codeword and the corresponding received codeword. Then, the SDC mitigation logic 120 may be configured to determine the Hamming distance based at least in part on the output of the comparator circuit 122. The Hamming distance corresponds to the number of unequal bits in the bit-by-bit comparison of two codewords.

[0044] Then, the SDC mitigation logic 120 may be configured to determine whether the Hamming distance is greater than or equal to a threshold. For example, the threshold may be retrieved from the SDC mitigation memory 124. If the Hamming distance is greater than or equal to the threshold, the SDC mitigation logic 120 may be configured to reject the successfully decoded codeword and notify of an uncorrectable bit error. For example, the notification may be provided to the memory controller control circuit 110.

[0045] Thus, the SDC mitigation system may be configured to reduce the SDC probability for successfully decoded codewords corresponding to received codewords read from the memory device. The SDC may be mitigated based at least in part on the threshold and the Hamming distance between the successfully decoded codeword and the corresponding received codeword. The corresponding UBER may not increase significantly.

[0046] In one non-limiting example, for an LDPC error correction code without puncturing and having erasures due to die failures, the threshold may be set to 50. Then, an RBER of 0.5 may have a corresponding SDC probability on the order of 1.00E-45. In another non-limiting example, for LDPC error correction without puncturing and without die failures, the threshold may be set to 80. Then, an RBER of 0.5 may have a corresponding SDC probability of 1E-64.

[0047] In a non - limiting example, an LDPC codeword having information of size 4256 (N - k) bits and parity of 800 (k) bits has a block length (N) of 5056 bits. In a memory device (e.g., memory device 106), multiple codewords can be spread across multiple dies. For an 8E - 3 RBER with a block length of 5056 bits, according to the binomial distribution with N = 5056 and p = 8E - 3, the probability of having more than 85 bit errors is approximately 2.7E - 10. In other words, in the above equation, for a ΔUBER of 2.7E - 10, N = 5056 and j = 85. Then, a threshold of 85 bits for an 8E - 3 RBER can result in an UBER of 3.0E - 8+2.7E - 10 = 3.027E - 8. Similarly, at an RBER of 7E - 3, the probability of having more than 85 bit errors is 3.7E - 13. Thus, an 85 - bit threshold can then result in an UBER of 1.2E - 9+3.7E - 13 = 1.20037E - 9 at an RBER of 7E - 3. Table 1 includes the UBER ranges for the LDPC codeword and an 85 - bit threshold for a range of RBERs. Table 1 also includes a column for UBER variation. As described herein, UBER variation corresponds to ΔUBER. According to simulation results, the SDC probability is less than 1.00E - 19 without SDC mitigation as described herein, and the SDC probability is less than 1.00E - 54 with SDC mitigation as described herein.

[0048] Table 1

[0049] RBER UBER UBER Variation 3E-3 2.00000E-18 2.86E-36 4E-3 2.00000E-15 1.16E-27 5E-3 3.00000E-13 1.84E-21 6E-3 2.00001E-11 8.73E-17 7E-3 1.20004E-09 3.67E-13 8E-3 3.02700E-08 2.70E-10 0.5 2.44141E-04 0

[0050] In another example, for an LDPC codeword with a block length of 5056 bits, an UBER of 1E - 18, an RBER of approximately 0.5, and a threshold of 85, the SDC probability is on the order of 1E - 54. Thus, while the SDC mitigation system may slightly increase the UBER for a given RBER, the resulting SDC probability can be significantly reduced.

[0051] In another non - limiting example, a Reed - Solomon codeword can contain 285 symbols, where each symbol contains 9 bits, and the codeword size is 285 * 9 = 2565 bits. For an erasure pattern due to die failure, in addition to erasure recovery, a Reed - Solomon decoder (i.e., an error - correction circuit configured to implement a Reed - Solomon error - correction code) can be configured to have a correction strength of 10 symbols. The correction strength corresponds to the number of correctable symbols (and / or bits) in the received codeword. If one or more bits contained in a symbol are in error, the symbol may be in error. Thus, a single - symbol error can result in errors from 1 bit error to 9 bit errors.

[0052] As described herein, SDC can be mitigated (i.e., the SDC probability can be reduced) while maintaining the symbol correction strength. For this example, the threshold can be 16. If the distance between the first received codeword and the first successfully decoded codeword is greater than or equal to 16 bits, the SDC circuit can reject the first received codeword with 10 symbol errors corresponding to the first successfully decoded codeword. If the distance between the second received codeword and the second successfully decoded codeword is less than 16 bits, the SDC circuit can not reject the second received codeword with 10 symbol errors corresponding to the second successfully decoded codeword. Thus, depending on whether the distance between the respective received codeword and the respective successfully decoded codeword is greater than or equal to or less than the threshold, the SDC circuit can reject or can not reject two successfully decoded codewords with the same number of symbol errors.

[0053] It can be understood that for a relatively small RBER, symbol errors are caused by very few bit errors, while for a relatively large RBER, symbol errors are caused by several bit errors. Compared with an SDC probability of 2.2E-10 without SDC mitigation, the SDC probability of the SDC mitigation system in the erasure mode can be on the order of 1E-20.

[0054] Table 2 shows the RBER and the uncorrectable block error probability of the SDC mitigation system for Reed-Solomon error correction codes. Table 2 also includes the change in the block error probability with and without an SDC circuit and the SDC probability with and without an SDC circuit.

[0055] Table 2

[0056]

[0057] Thus, the SDC mitigation system can be configured to reduce the SDC probability for successfully decoded codewords corresponding to received codewords read from a memory device. SDC can be mitigated at least in part based on a threshold and at least in part based on the Hamming distance between the successfully decoded codeword and the corresponding received codeword. SDC can be mitigated without significantly increasing the corresponding UBER and without reducing the code rate. The comparison can be performed relatively quickly using a relatively simple comparator circuit.

[0058] Figure 2 is a flowchart 200 of a threshold determination operation according to various embodiments of the present disclosure. In particular, flowchart 200 shows determining a threshold. The threshold can be determined at least in part based on RBER, ECC, and / or UBER. For example, it can be determined by Figure 1Components of the SDC mitigation circuit 114 (e.g., SDC mitigation logic 120 and / or threshold determination logic 126) perform operations.

[0059] Operations of this embodiment may begin at operation 202. The RBER may be determined at operation 204. The UBER may be determined at operation 206. The ECC may be identified at operation 208. The codeword size N may be determined at operation 210. The maximum allowable increment of the UBER, i.e., ΔUBER, may be determined at operation 212. The threshold may be determined at operation 214. Whether there are any punctures and / or erasures may be determined at operation 216. If there are no punctures and / or erasures, the program flow may continue at operation 222. If there are punctures and / or erasures, the effective codeword size may be updated at operation 218. Then the threshold may be updated at operation 220. Then, the program flow may proceed to operation 222.

[0060] Thus, the threshold may be determined and / or updated.

[0061] Figure 3 FIG. 300 is a flowchart of SDC mitigation operations according to various embodiments of the present disclosure. In particular, flowchart 300 shows determining whether the distance between a successfully decoded codeword and a corresponding received codeword is greater than or equal to a threshold. A successfully decoded codeword is a codeword that is considered successfully decoded by an error correction circuit. For example, operations may be performed by Figure 1 components of the SDC mitigation circuit 114 (e.g., SDC mitigation logic 120 and / or comparator circuit 122).

[0062] Operations of this embodiment may begin with an indication of error correction success at operation 302. Operation 304 includes retrieving the successfully decoded codeword. Operation 306 includes retrieving the corresponding received codeword. Operation 308 includes comparing the corresponding received codeword with the successfully decoded codeword. At operation 310, it may be determined whether the distance between the received codeword and the successfully decoded codeword is greater than or equal to the threshold. If the distance between the received codeword and the successfully decoded codeword is not greater than or equal to the threshold, the program flow may continue at operation 312. If the distance between the received codeword and the successfully decoded codeword is greater than or equal to the threshold, the successfully decoded codeword may be rejected at operation 314. Then an uncorrectable bit error may be notified at operation 316. Then, the program flow may continue in operation 318.

[0063] Thus, if the distance between the corresponding received codeword and the successfully decoded codeword is greater than or equal to the threshold, the successfully decoded codeword may be rejected.

[0064] AlthoughFigure 2 and Figure 3 The flow diagrams of show operations in accordance with various embodiments, but it should be understood that not all of the operations depicted in Figure 2 and Figure 3 are necessary for other embodiments. Additionally, it is fully contemplated herein that in other embodiments of the present disclosure, Figure 2 and Figure 3 the operations depicted in and / or other operations described herein can be combined in ways not specifically shown in any of the figures in the drawings, and such embodiments can include fewer or more operations than those shown in Figure 2 and Figure 3 . Accordingly, claims directed to features and / or operations not explicitly shown in one of the figures are considered to be within the scope and content of the present disclosure.

[0065] As used in any embodiment herein, the term "logic" can refer to an application, software, firmware, and / or circuitry configured to perform any of the operations described above. The software can be embodied as a software package, code, instructions, an instruction set, and / or data recorded on a non-transitory computer-readable storage medium. The firmware can be embodied as code, instructions, or an instruction set and / or data hard-coded (e.g., non-volatile) in a memory device.

[0066] As used in any embodiment herein, "circuitry" can include, for example, hardware circuitry alone or in any combination, programmable circuitry such as a computer processor including one or more separate instruction processing cores, state machine circuitry, logic, and / or firmware storing instructions executed by the programmable circuitry. The circuitry can be embodied as an integrated circuit, e.g., an integrated circuit chip. In some embodiments, circuitry can be formed at least in part by: a processor circuit 102 executing code and / or an instruction set corresponding to the functions described herein (e.g., software, firmware, etc.), thereby transforming a general-purpose processor into a special-purpose processing environment for performing one or more of the operations described herein. In some embodiments, various components and circuitry of a memory controller circuit or other system can be combined in a system-on-chip (SoC) architecture.

[0067] Example system architectures and methods were provided above; however, modifications to the present disclosure are possible. The processor can include one or more processor cores and can be configured to execute system software. The system software can include, for example, an operating system. The device memory can include an I / O memory buffer configured to store one or more data packets to be sent or received by the network interface.

[0068] The operating system (OS) can be configured to manage system resources and control tasks running on, for example, system 100. For example, can be used HP- or to implement the OS, but other operating systems can also be used. In another example, the OS can use Android TM , iOS, Windows or to implement. In some embodiments, the OS can be replaced by a virtual machine monitor (or hypervisor), which can provide an abstraction layer for the underlying hardware for various operating systems (virtual machines) running on one or more processing units. The operating system and / or virtual machine can implement a protocol stack. The protocol stack can execute one or more programs to process packets. An example of a protocol stack is the TCP / IP (Transmission Control Protocol / Internet Protocol) protocol stack, which includes one or more programs for handling (e.g., processing or generating) packets to be sent and / or received over a network.

[0069] The SDC mitigation memory 124 can include one or more of the following types of memory: semiconductor firmware memory, programmable memory, non-volatile memory, read-only memory, electrically programmable memory, random access memory, flash memory, disk memory, and / or optical disk memory. Additionally or alternatively, the system memory can include other and / or later-developed types of computer-readable memory.

[0070] Embodiments of the operations described herein can be implemented in a computer-readable storage device storing instructions that, when executed by one or more processors, perform the method. The processor can include, for example, a processing unit and / or programmable circuitry. The storage device can include a machine-readable storage device, which includes any type of tangible, non-transitory storage device, such as any type of disk including floppy disks, optical disks, compact disk read-only memory (CD-ROM), rewritable compact disks (CD-RW), and magneto-optical disks, semiconductor devices such as read-only memory (ROM), random access memory (RAM) (e.g., dynamic RAM and static RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic or optical cards, or any type of storage device suitable for storing electronic instructions.

[0071] In some embodiments, a hardware description language (HDL) can be used to specify circuit and / or logical implementations for the various logics and / or circuits described herein. For example, in one embodiment, the hardware description language can conform to or be compatible with the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL), and VHDL can implement semiconductor manufacturing of one or more circuits and / or logics described herein. VHDL can conform to or be compatible with IEEE Standard 1076 - 1987, IEEE Standard 1076.2, IEEE 1076.1, the IEEE draft 3.0 of VHDL - 2006, the IEEE draft 4.0 of VHDL - 2008, and / or other versions of the IEEE VHDL standard and / or other hardware description standards.

[0072] Example

[0073] As discussed below, examples of the present disclosure include subject matter such as methods related to mitigating silent data corruption in error control coding, units, devices, or apparatuses or systems for performing actions of the methods.

[0074] Example 1. According to this example, a silent data corruption (SDC) mitigation circuit is provided. The SDC mitigation circuit includes a comparator circuit and SDC mitigation logic. The comparator circuit is configured to compare a successfully decoded codeword, which has been considered successful by an error correction circuit, with a corresponding received codeword. The SDC mitigation logic is configured to reject the successfully decoded codeword if the distance between the corresponding received codeword and the successfully decoded codeword is greater than or equal to a threshold.

[0075] Example 2. This example includes the elements of Example 1, wherein the distance is a Hamming distance and the comparison is bit - level.

[0076] Example 3. This example includes the elements of Example 1, and further includes threshold determination logic for determining the threshold.

[0077] Example 4. This example includes the elements of Example 1, wherein the threshold is determined at least in part based on a selected error correction code.

[0078] Example 5. This example includes the elements of Example 4, wherein the error correction code is selected from the group including a Low - Density Parity - Check (LDPC) error correction code and a Reed - Solomon error correction code.

[0079] Example 6. This example includes the elements according to any one of Examples 1 to 4, wherein the threshold is determined at least in part based on whether the codeword is punctured and / or contains erasures.

[0080] Example 7. This example includes the elements according to any one of Examples 1 to 4, wherein the threshold is determined at least in part based on the binomial distribution of the raw bit error rate (RBER) of a codeword of size N bits.

[0081] Example 8. This example includes the elements of Example 3, wherein the threshold determination logic is used to update the threshold if there is puncturing and / or erasure, and the update is at least in part based on the effective codeword size.

[0082] Example 9. This example includes the elements according to any one of Examples 1 to 4, wherein the threshold is determined at least in part based on the maximum allowable change in the uncorrectable bit error rate (UBER). Example 10. This example includes the elements of Example 9, wherein the maximum allowable change in the UBER is less than one percent of the UBER.

[0083] Example 11. According to this example, a method is provided. The method includes comparing, by a comparator circuit, a successful decoded codeword, which has been determined to be successful by an error correction circuit, with a corresponding received codeword. The method further includes rejecting, by SDC mitigation logic, the successful decoded codeword if the distance between the corresponding received codeword and the successful decoded codeword is greater than or equal to a threshold.

[0084] Example 12. This example includes the elements of Example 11, wherein the distance is a Hamming distance and the comparison is at the bit level.

[0085] Example 13. This example includes the elements of Example 11, and further includes determining the threshold by threshold determination logic.

[0086] Example 14. This example includes the elements of Example 11, wherein the threshold is determined at least in part based on a selected error correction code.

[0087] Example 15. This example includes the elements of Example 14, wherein the error correction code is selected from the group including a low density parity check (LDPC) error correction code and a Reed - Solomon error correction code.

[0088] Example 16. This example includes the elements of Example 11, wherein the threshold is determined at least in part based on whether the codeword is punctured and / or contains erasures.

[0089] Example 17. This example includes the elements of Example 11, wherein the threshold is determined at least in part based on the binomial distribution of the raw bit error rate (RBER) of a codeword of size N bits.

[0090] Example 18. This example includes the elements of Example 13, and further includes updating, by the threshold determination logic, the threshold if there is puncturing and / or erasure, and the update is at least in part based on the effective codeword size.

[0091] Example 19. This example includes the elements of Example 11, wherein the threshold is determined at least in part based on a maximum allowable change in the uncorrectable bit error rate (UBER).

[0092] Example 20. This example includes the elements of Example 19, wherein the maximum allowable change in the UBER is less than one percent of the UBER.

[0093] Example 21. According to this example, a system is provided. The system includes a processor circuit, a memory device; and a memory controller including a silent data corruption (SDC) mitigation circuit. The SDC mitigation circuit includes a comparator circuit and SDC mitigation logic. The comparator circuit is configured to compare a successfully decoded codeword, which has been determined to be successful by an error correction circuit, with a corresponding received codeword. The SDC mitigation logic is configured to reject the successfully decoded codeword if the distance between the corresponding received codeword and the successfully decoded codeword is greater than or equal to a threshold.

[0094] Example 22. This example includes the elements of Example 21, wherein the distance is a Hamming distance and the comparison is at the bit level.

[0095] Example 23. This example includes the elements of Example 21, wherein the memory controller further includes threshold determination logic for determining the threshold.

[0096] Example 24. This example includes the elements of Example 21, wherein the threshold is determined at least in part based on a selected error correction code.

[0097] Example 25. This example includes the elements of Example 24, wherein the error correction code is selected from the group including a low density parity check (LDPC) error correction code and a Reed-Solomon error correction code.

[0098] Example 26. This example includes the elements according to any one of Examples 21 to 24, wherein the threshold is determined at least in part based on whether the codeword is punctured and / or contains erasures.

[0099] Example 27. This example includes the elements according to any one of Examples 21 to 24, wherein the threshold is determined at least in part based on a binomial distribution of the raw bit error rate (RBER) of a codeword of size N bits.

[0100] Example 28. This example includes the elements of Example 23, wherein the threshold determination logic is configured to update the threshold if there are punctures and / or erasures, the update being at least in part based on the effective codeword size.

[0101] Example 29. This example includes the elements according to any one of Examples 21 to 24, wherein the threshold is determined at least in part based on the maximum allowable change in the uncorrectable bit error rate (UBER). Example 30. This example includes the elements of Example 29, wherein the maximum allowable change in the UBER is less than one percent of the UBER.

[0102] Example 31. According to this example, a computer-readable storage device is provided. Instructions are stored on the device, which when executed by one or more processors cause the following operations, including: comparing a successfully decoded codeword with the corresponding received codeword, the successfully decoded codeword having been considered successful by an error correction circuit; and rejecting the successfully decoded codeword if the distance between the corresponding received codeword and the successfully decoded codeword is greater than or equal to a threshold.

[0103] Example 32. This example includes the elements of Example 31, wherein the distance is a Hamming distance and the comparison is at the bit level.

[0104] Example 33. This example includes the elements of Example 31, wherein the instructions when executed by one or more processors cause the following additional operations including determining a threshold.

[0105] Example 34. This example includes the elements of Example 31, wherein the threshold is determined at least in part based on the selected error correction code.

[0106] Example 35. This example includes the elements of Example 34, wherein the error correction code is selected from the group including a low density parity check (LDPC) error correction code and a Reed-Solomon error correction code.

[0107] Example 36. This example includes the elements according to any one of Examples 31 to 34, wherein the threshold is determined at least in part based on whether the codeword is punctured and / or contains erasures.

[0108] Example 37. This example includes the elements according to any one of Examples 31 to 34, wherein the threshold is determined at least in part based on the binomial distribution of the raw bit error rate (RBER) of a codeword of size N bits.

[0109] Example 38. This example includes the elements of Example 33, wherein the instructions when executed by one or more processors cause the following additional operations including updating the threshold if there are punctures and / or erasures, the update being at least in part based on the effective codeword size.

[0110] Example 39. This example includes the elements according to any one of Examples 31 to 34, wherein the threshold is determined at least in part based on the maximum allowable change in the uncorrectable bit error rate (UBER).

[0111] Example 40. This example includes the elements of Example 39, where the maximum allowable variation of UBER is less than one percent of UBER.

[0112] Example 41. According to this example, a device is provided. The device includes a unit for comparing a successful decoded codeword with a corresponding received codeword by a comparator circuit, where the successful decoded codeword has been considered successful by an error correction circuit. The device further includes a unit for rejecting the successful decoded codeword by SDC mitigation logic if the distance between the corresponding received codeword and the successful decoded codeword is greater than or equal to a threshold.

[0113] Example 42. This example includes the elements of Example 41, where the distance is a Hamming distance and the comparison is at the bit level.

[0114] Example 43. This example includes the elements of Example 41 and further includes a unit for determining the threshold by threshold determination logic.

[0115] Example 44. This example includes the elements of Example 41, where the threshold is determined at least in part based on the selected error correction code.

[0116] Example 45. This example includes the elements of Example 44, where the error correction code is selected from a group including a low density parity check (LDPC) error correction code and a Reed - Solomon error correction code.

[0117] Example 46. This example includes the elements according to any one of Examples 41 to 44, where the threshold is determined at least in part based on whether the codeword is punctured and / or contains erasures.

[0118] Example 47. This example includes the elements according to any one of Examples 41 to 44, where the threshold is determined at least in part based on the binomial distribution of the raw bit error rate (RBER) of a codeword of size N bits.

[0119] Example 48. This example includes the elements of Example 43 and further includes a unit for updating the threshold by threshold determination logic if there are punctures and / or erasures, where the update is at least in part based on the effective codeword size.

[0120] Example 49. This example includes the elements according to any one of Examples 41 to 44, where the threshold is determined at least in part based on the maximum allowable variation of the uncorrectable bit error rate (UBER).

[0121] Example 50. This example includes the elements of Example 49, where the maximum allowable variation of UBER is less than one percent of UBER.

[0122] Example 51. According to this example, a system is provided. The system includes at least one device arranged to perform the method of any one of Examples 11 to 20.

[0123] Example 52. According to this example, a device is provided. The device includes a unit for performing the method of any one of Examples 11 to 20.

[0124] Example 53. According to this example, a computer-readable storage device is provided. Instructions are stored on the device, which when executed by one or more processors cause the following operations, including: according to the method of any one of Examples 11 to 20.

[0125] The terms and expressions used herein are used as terms of description rather than limitation, and in the use of such terms and expressions, it is not intended to exclude any equivalents of the features (or parts thereof) shown and described, and it should be realized that various modifications are possible within the scope of the claims. Therefore, the claims are intended to cover all such equivalents.

[0126] Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are readily combinable with one another as well as subject to variations and modifications, as will be understood by those skilled in the art. Accordingly, the present disclosure should be considered to encompass such combinations, variations, and modifications.

Claims

1. A silent data corruption (SDC) mitigation circuit, comprising: A threshold determination circuit configured to determine a first uncorrectable bit error rate (UBER), the threshold determination circuit further configured to determine a threshold based on a maximum allowable change in the UBER; A comparator circuit configured to compare a successfully decoded codeword with a corresponding received codeword, the successfully decoded codeword having been determined to be successful by an error correction circuit; and SDC mitigation logic configured to reject the successfully decoded codeword if a distance between the corresponding received codeword and the successfully decoded codeword is greater than or equal to the threshold; wherein rejecting the successfully decoded codeword generates a second UBER; wherein a difference between the first UBER and the second UBER is less than or equal to the maximum allowable change in the UBER.

2. The SDC mitigation circuit according to claim 1, wherein, The distance is a Hamming distance, and the comparison is at the bit level.

3. The SDC mitigation circuit according to claim 1, wherein, The threshold is determined at least in part based on a selected error correction code, the error correction code being selected from a group comprising a low density parity check (LDPC) error correction code and a Reed - Solomon error correction code.

4. The SDC mitigation circuit according to any one of claims 1 to 3, wherein, The threshold is determined at least in part based on whether a codeword is punctured and / or contains erasures.

5. The SDC mitigation circuit according to any one of claims 1 to 3, wherein, The threshold is determined at least in part based on a binomial distribution of a raw bit error rate (RBER) of a codeword of size N bits.

6. A method for mitigating silent data corruption, comprising: Determining a first uncorrectable bit error rate (UBER) via a threshold determination circuit; Determining a threshold via the threshold determination circuit based on a maximum allowable change in the UBER; Comparing, by a comparator circuit, a successfully decoded codeword with a corresponding received codeword, the successfully decoded codeword having been determined to be successful by an error correction circuit; And If a distance between the corresponding received codeword and the successfully decoded codeword is greater than or equal to the threshold, rejecting, by SDC mitigation logic, the successfully decoded codeword; wherein rejecting the successfully decoded codeword generates a second UBER; wherein a difference between the first UBER and the second UBER is less than or equal to the maximum allowable change in the UBER.

7. The method according to claim 6, wherein, The distance is a Hamming distance, and the comparison is at the bit level.

8. The method according to claim 6, wherein, The threshold is determined at least in part based on a selected error correction code, the error correction code being selected from a group comprising a low density parity check (LDPC) error correction code and a Reed - Solomon error correction code.

9. The method according to any one of claims 6 to 8, wherein, The threshold is determined at least in part based on whether a codeword is punctured and / or contains erasures.

10. The method according to any one of claims 6 to 8, wherein The threshold is determined at least in part based on a binomial distribution of a raw bit error rate (RBER) of a codeword of size N bits.

11. A system for mitigating silent data corruption, comprising: A processor circuit; A memory device; And A memory controller comprising a silent data corruption (SDC) mitigation circuit, the SDC mitigation circuit comprising: A threshold determination circuit for determining a first uncorrectable bit error rate (UBER), the threshold determination circuit further for determining a threshold based on a maximum allowable change in the UBER; A comparator circuit for comparing a successfully decoded codeword with a corresponding received codeword, the successfully decoded codeword having been determined to be successful by an error correction circuit; and SDC mitigation logic for rejecting the successfully decoded codeword if the distance between the corresponding received codeword and the successfully decoded codeword is greater than or equal to the threshold; wherein rejecting the successfully decoded codeword generates a second UBER; wherein the difference between the first UBER and the second UBER is less than or equal to the maximum allowable change in the UBER.

12. The system according to claim 11, wherein The distance is a Hamming distance and the comparison is at the bit level.

13. The system according to claim 11, wherein, The threshold is determined at least in part based on a selected error correction code selected from the group including a low density parity check (LDPC) error correction code and a Reed - Solomon error correction code.

14. The system according to any one of claims 11 to 13, wherein, The threshold is determined at least in part based on whether the codeword is punctured and / or contains erasures.

15. The system according to any one of claims 11 to 13, wherein, The threshold is determined at least in part based on the binomial distribution of the raw bit error rate (RBER) of a codeword of size N bits.

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