Apparatus and method for multiply-accumulate of packed data elements of complex and real numbers

Abstract

Apparatus and method for multiplying packed real and imaginary components of a complex number. For example, one embodiment of a processor includes: a decoder for decoding a first instruction to generate a decoded instruction; a first source register for storing a first plurality of packed real and imaginary data elements; a second source register for storing a second plurality of packed real and imaginary data elements; an execution circuit for executing the decoded instruction, the execution circuit including: a multiplier circuit, an adder circuit, and an accumulator circuit.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of computer processors. More specifically, the present embodiments relate to apparatuses and methods for multiplying and accumulating data values packed with imaginary and real parts. Background Art

[0002] An instruction set or instruction set architecture (ISA) is a part of a computer architecture related to programming, including native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I / O). It should be noted that the term "instruction" generally refers to a macro-instruction in this document - which is an instruction provided to a processor for execution - as opposed to a micro-instruction or micro-operation - which is the result of a processor's decoder decoding a macro-instruction. A micro-instruction or micro-operation can be configured to instruct an execution unit on a processor to perform an operation to implement the logic associated with the macro-instruction.

[0003] The ISA is different from the microarchitecture which is a set of processor design techniques for implementing an instruction set. Processors with different microarchitectures can share a common instruction set. For example, the Intel® Pentium 4 processor, the Intel® Core TM processor, and processors from Advanced Micro Devices, Inc. of Sunnyvale, California, implement nearly the same version of the x86 instruction set (where newer versions have been adopted to add some extensions), but have different internal designs. For example, the same register architecture of an ISA can be implemented in different ways in different microarchitectures using well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., using a register alias table (RAT), a reorder buffer (ROB), and a retirement register file). Unless otherwise specified, the phrases register architecture, register file, and register are used in this document to refer to things visible to software / programmers and the way instructions specify registers. In cases where a distinction is required, the adjectives "logical", "architectural", or "software visible" will be used to indicate registers / files in a register architecture, while different adjectives will be used to specify registers in a given microarchitecture (e.g., physical registers, reorder buffers, retirement registers, register pools).

[0004] Multiply-accumulate is a common digital signal processing operation that calculates the product of two numbers and adds that product to an accumulated value. Existing single instruction multiple data (SIMD) microarchitectures implement multiply-accumulate operations by executing a series of instructions. For example, multiply-accumulate can be executed with a multiply instruction, followed by a 4-way add, and then an accumulation with the destination quadword data to produce two 64-bit saturated results. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] A better understanding of the present invention can be obtained from the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0006] Figure 1A and 1B is a block diagram illustrating a general vector-friendly instruction format and its instruction templates according to an embodiment of the present invention;

[0007] Figure 2A -C is a block diagram illustrating an exemplary VEX instruction format according to an embodiment of the present invention;

[0008] Figure 3 is a block diagram of a register architecture according to an embodiment of the present invention; and

[0009] Figure 4A is a block diagram illustrating both an exemplary in-order fetch, decode, retire pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to an embodiment of the present invention;

[0010] Figure 4B is a block diagram illustrating an exemplary embodiment of an in-order fetch, decode, retire core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to an embodiment of the present invention;

[0011] Figure 5A is a block diagram of a single processor core and its connection to an on-die interconnect network;

[0012] Figure 5B illustrates according to an embodiment of the present invention Figure 5A an expanded view of a portion of the processor core in

[0013] Figure 6 is a block diagram of a single-core processor and a multi-core processor with an integrated memory controller and graphics according to an embodiment of the present invention;

[0014] Figure 7 illustrates a block diagram of a system according to an embodiment of the present invention;

[0015] Figure 8 illustrates a block diagram of a second system according to an embodiment of the present invention;

[0016] Figure 9 The block diagram of a third system according to an embodiment of the present invention is illustrated;

[0017] Figure 10 The block diagram of a system-on-chip (SoC) according to an embodiment of the present invention is illustrated;

[0018] Figure 11 The block diagram for converting binary instructions in a source instruction set into binary instructions in a target instruction set in contrast to the use of a software instruction converter according to an embodiment of the present invention is illustrated;

[0019] Figure 12 The processor architecture on which embodiments of the present invention can be implemented is illustrated;

[0020] Figure 13 The block diagram of a plurality of packed data elements containing real part values and complex values according to one embodiment is illustrated;

[0021] Figure 14 The block diagram of an embodiment of an architecture for multiplying and accumulating the real and imaginary components of a complex number is illustrated;

[0022] Figure 15 The block diagram of a method according to an embodiment of the present invention; and

[0023] Figure 16 The block diagram of a method according to another embodiment of the present invention is illustrated. Detailed Description

[0024] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present invention described below. However, those skilled in the art will appreciate that embodiments of the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of the embodiments of the present invention.

[0025] Exemplary Processor Architectures, Instruction Formats, and Data Types

[0026] The instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, bit positions) to specify, among other things, the operation to be performed (opcode) and one or more operands (on which the operation is to be performed). Some instruction formats are further decomposed by the definition of instruction templates (or sub-formats). For example, an instruction template of a given instruction format can be defined to have different subsets of the fields of the instruction format (the included fields typically being in the same order, but at least some having different bit positions since fewer fields are included) and / or be defined to have a given field interpreted differently. Thus, each instruction of the ISA is represented using a given instruction format (and, if defined, a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field for specifying that opcode and operand fields for selecting the operands (source 1 / destination and source 2)); and an occurrence of that ADD instruction in the instruction stream will have specific contents in the operand fields that select the specific operands.

[0027] Embodiments of one or more instructions described herein may be implemented in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of one or more instructions may execute on such systems, architectures, and pipelines, but are not limited to those detailed.

[0028] General vector-friendly instruction format

[0029] A vector-friendly instruction format is an instruction format suitable for vector instructions (e.g., there are certain fields specific to vector operations). Although embodiments are described in which both vector and scalar operations are supported by a vector-friendly instruction format, alternative embodiments use only vector operations in the vector-friendly format.

[0030] Figure 1A - 1B is a block diagram that shows a general vector-friendly instruction format and its instruction templates according to an embodiment of the present invention. Figure 1A is a block diagram that shows a general vector-friendly instruction format and its Category A instruction template according to an embodiment of the present invention; while Figure 1B is a block diagram that shows a general vector-friendly instruction format and its Category B instruction template according to an embodiment of the present invention. Specifically, for general vector-friendly instruction format 100, Category A and Category B instruction templates are defined, both of which include a no-memory-access 105 instruction template and a memory-access 120 instruction template. The term "general" in the context of a vector-friendly instruction format means that the instruction format is not tied to any particular instruction set.

[0031] While embodiments of the present invention will be described where a vector-friendly instruction format supports the following: a 64-byte vector operand length (or size) with 32-bit (4-byte) or 64-bit (8-byte) data element widths (or sizes) (and thus, a 64-byte vector consists of 16 double-word-sized elements or alternatively 8 quad-word-sized elements); a 64-byte vector operand length (or size) with 16-bit (2-byte) or 8-bit (1-byte) data element widths (or sizes); a 32-byte vector operand length (or size) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes); and a 16-byte vector operand length (or size) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes); alternative embodiments may support more, fewer, and / or different vector operand sizes (e.g., 256-byte vector operands) with more, fewer, or different data element widths (e.g., 128-bit (16-byte) data element width).

[0032] Figure 1A The category A instruction templates in include: 1) within the no-memory-access 105 instruction template, a no-memory-access, full-round control type operation 110 instruction template and a no-memory-access, data transformation type operation 115 instruction template are shown; and 2) within the memory-access 120 instruction template, a memory-access, temporary 125 instruction template and a memory-access, non-temporary 130 instruction template are shown. Figure 1B The category B instruction templates in Figure 1B include: 1) within the no-memory-access 105 instruction template, a no-memory-access, write mask control, partial-round control type operation 112 instruction template and a no-memory-access, write mask control, vsize type operation 117 instruction template are shown; and 2) within the memory-access 120 instruction template, a memory-access, write mask control 127 instruction template is shown.

[0033] The general vector-friendly instruction format 100 includes Figure 1A - 1B the following fields listed in order as shown in Figure 1A - 1B .

[0034] Format field 140 - The specific value (instruction format identifier value) in this field uniquely identifies the vector-friendly instruction format and thus identifies the occurrence of an instruction in the vector-friendly instruction format in an instruction stream. Thus, this field is optional in the sense that it is not needed for an instruction set that only has the general vector-friendly instruction format.

[0035] Base operation field 142 - Its content differentiates different base operations.

[0036] Register index field 144 - Its content directly or through address generation specifies the location of source and destination operands (whether they are in registers or in memory). These include a sufficient number of bits for selecting N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. While in one embodiment N can be up to three sources and one destination register, alternative embodiments can support more or fewer source and destination registers (e.g., can support up to two sources, where one of these sources also acts as a destination; can support up to three sources, where one of these sources also acts as a destination; can support up to two sources and one destination).

[0037] Modifier field 146 - Its content differentiates the occurrence of instructions that specify memory access in the general vector instruction format from those that do not; that is, it differentiates between the no-memory-access 105 instruction template and the memory-access 120 instruction template. Memory access operations read and / or write to the memory hierarchy (in some cases using values in registers to specify source and / or destination addresses), while non-memory access operations do not (e.g., the source and destination are registers). While in one embodiment this field also selects between three different ways to perform memory address arithmetic, alternative embodiments can support more, fewer, or different ways to perform memory address arithmetic.

[0038] Augmentation operation field 150 - Its content differentiates which one of a variety of different operations is to be performed in addition to the base operation. This field is context specific. In one embodiment of the present invention, this field is divided into a category field 168, an α field 152, and a β field 154. The augmentation operation field 150 allows a general group of operations to be performed in a single instruction rather than in 2, 3, or 4 instructions.

[0039] Scale field 160 - Its content allows for the scaling of the content of the index field used for memory address generation (e.g., for address generation using 2 缩放 *index + base address).

[0040] Displacement field 162A - Its content is used as part of memory address generation (e.g., for address generation using 2 缩放 *index + base address + displacement).

[0041] Displacement factor field 162B (note that the juxtaposition of displacement field 162A directly over displacement factor field 162B indicates that one or the other is used) - its content is used as part of address generation; it specifies the displacement factor to be scaled by the size (N) of the memory access - where N is the number of bytes in the memory access (e.g., for address generation using 2 缩放 *index + base address + scaled displacement). Redundant low-order bits are ignored, and thus, the content of the displacement factor field is multiplied by the total size (N) of the memory operand to generate the final displacement to be used in the effective address calculation. The value of N is determined by the processor hardware at run time based on the full opcode field 174 (described later in this document) and the data manipulation field 154C. The displacement field 162A and the displacement factor field 162B are optional in the sense that they are not used in the memoryless access 105 instruction template and / or different embodiments may implement only one or none of the two.

[0042] Data element width field 164 - its content identifies which of the multiple data element widths is to be used (in some embodiments for all instructions; in other embodiments for only some of the instructions). This field is optional in the sense that if only one data element width is supported and / or some aspect of the opcode is used to support the data element width, then this field is not required.

[0043] Write mask field 170 - Its content controls, on a data element position basis, whether that data element position in the destination vector operand reflects the results of the base and broadcast operations. The class A instruction templates support combined write masking, while the class B instruction templates support both combined and zeroing write masking. In the combined case, the vector mask allows any set of elements in the destination to be protected from being updated during the execution of any operation (specified by the base and broadcast operations); in another embodiment, the old value of each element of the destination where the corresponding mask bit has 0 is saved. In contrast, in the zeroing case, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the base and broadcast operations); in one embodiment, the elements of the destination are set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of the elements being modified, from the first to the last); however, the elements being modified need not be contiguous. Thus, write mask field 170 allows partial vector operations, including loads, stores, arithmetic, logical, etc. While embodiments of the invention are described where the content of write mask field 170 selects one of a plurality of write mask registers containing the write mask to be used (and thus the content of write mask field 170 indirectly identifies the masking to be performed), alternative embodiments instead or additionally allow the content of mask write field 170 to directly specify the masking to be performed.

[0044] Immediate digit field 172 - Its content allows the specification of an immediate number. This field is optional in the sense that it does not exist in implementations that do not support the general vector friendly format for immediates and it does not exist in instructions that do not use immediates.

[0045] Class field 168 - Its content discriminates between different classes of instructions. Refer to Figure 1A -B, the content of this field selects between class A and class B instructions. In Figure 1A -B, rounded rectangles are used to indicate the specific values presented in the field (e.g., class A 168A and class B 168B corresponding to class field 168 in Figure 1A -B).

[0046] Instruction templates for class A

[0047] In the case of a non-memory access 105 instruction template of class A, the α field 152 is decoded as an RS field 152A, the content of which identifies which of the different amplification operation types is to be performed (e.g., rounding 152A.1 and data transformation 152A.2 are correspondingly specified for non-memory access, rounding type operation 110, and non-memory access, data transformation type operation 115 instruction templates), while the β field 154 identifies which of the operations of the specified type is to be performed. In the non-memory access 105 instruction template, the scale field 160, the displacement field 162A, and the displacement scale field 162B do not exist.

[0048] Non-memory access instruction template - full rounding control type operation

[0049] In the non-memory access full rounding control type operation 110 instruction template, the β field 154 is decoded as a rounding control field 154A, the content of which provides static rounding. Although in the described embodiments of the present invention, the rounding control field 154A includes suppression of all floating-point exceptions (SAE) field 156 and rounding operation control field 158, alternative embodiments may support encoding both of these concepts into the same field, or having only one or the other of these concepts / fields (e.g., may have only the rounding operation control field 158).

[0050] SAE field 156 - the content of which identifies whether exception event reporting is disabled; when the content of the SAE field 156 indicates that suppression is enabled, a given instruction does not report any kind of floating-point exception identification and does not raise any floating-point exception handler.

[0051] Rounding operation control field 158 - the content of which identifies which of a set of rounding operations is to be performed (e.g., round up, round down, round towards zero, and round to nearest). Thus, the rounding operation control field 158 allows for a change in the rounding mode on a per-instruction basis. In one embodiment of the present invention, where the processor includes a control register for specifying the rounding mode, the content of the rounding operation control field 150 overwrites that register value.

[0052] Non-memory access instruction template - data transformation type operation

[0053] In the non-memory access data transformation type operation 115 instruction template, the β field 154 is decoded as a data transformation field 154B, the content of which identifies which of the multiple data transformations is to be performed (e.g., no data transformation, swizzle, broadcast).

[0054] In the case of a memory access 120 instruction template of class A, the α field 152 is decoded as an eviction hint field 152B, the content of which identifies which of the eviction hints is to be used (inFigure 1A In it, the temporary 152B.1 and the non-temporary 152B.2 are correspondingly designated for memory access, the temporary 125 instruction template, and memory access, the non-temporary 130 instruction template), while the β field 154 is decoded as the data manipulation field 154C, the content of which distinguishes which one of multiple data manipulation operations (also known as primitives) is to be executed (e.g., no manipulation; broadcast; up-conversion of the source; and down-conversion of the destination). The memory access 120 instruction template includes a scale field 160 and optionally includes a displacement field 162A or a displacement scale field 162B.

[0055] Vector memory instructions perform vector loads from memory and vector stores to memory through conversion support. As with conventional vector instructions, vector memory instructions transfer data to / from memory in a data element-wise manner, and the elements actually transferred are indicated by the content of a vector mask selected as a write mask.

[0056] Memory access instruction template - temporary

[0057] Temporary data is data that is likely to be reused quickly enough to benefit from caching. However, this is a hint, and different processors may implement it in different ways, including completely ignoring the hint.

[0058] Memory access instruction template - non-temporary

[0059] Non-temporary data is data that is unlikely to be reused quickly enough to benefit from caching in the level 1 cache and should be given priority for eviction. However, this is a hint, and different processors may implement it in different ways, including completely ignoring the hint.

[0060] Instruction template for category B

[0061] In the case of the instruction template for category B, the α field 152 is decoded as the write mask control (Z) field 152C, the content of which distinguishes whether the write masking controlled by the write mask field 170 should be merge or zero.

[0062] In the case of the non-memory access 105 instruction template of class B, a portion of the β field 154 is decoded as the RL field 157A, the content of which differentiates which of the different amplification operation types is to be performed (e.g., rounding 157A.1 and vector length (VSIZE) 157A.2 are correspondingly specified for the no-memory access, write mask control, partial rounding control type operation 112 instruction template, and the no-memory access, write mask control, VSIZE type operation 117 instruction template), while the remaining portion of the β field 154 differentiates which operation of the specified type is to be performed. In the no-memory access 105 instruction template, the scale field 160, the displacement field 162A, and the displacement scale field 162B do not exist.

[0063] In the no-memory access, write mask control, partial rounding control type operation 110 instruction template, the remaining portion of the β field 154 is decoded as the rounding operation field 159A, and exception event reporting is disabled (the given instruction does not report any kind of floating-point exception identification and does not invoke any floating-point exception handler).

[0064] The rounding operation control field 159A - like the rounding operation control field 158, its content differentiates which of a set of rounding operations is to be performed (e.g., rounding up, rounding down, rounding towards zero, and rounding to the nearest). Thus, the rounding operation control field 159A allows for a change in the rounding mode on an instruction-by-instruction basis. In one embodiment of the present invention, where the processor includes a control register for specifying the rounding mode, the content of the rounding operation control field 150 overrides that register value.

[0065] In the no-memory access, write mask control, VSIZE type operation 117 instruction template, the remaining portion of the β field 154 is decoded as the vector length field 159B, the content of which differentiates which of the multiple data vector lengths is to be performed (e.g., 128, 256, or 512 bytes).

[0066] In the case of the memory access 120 instruction template of class B, a portion of the β field 154 is decoded as the broadcast field 157B, the content of which differentiates whether a broadcast type data manipulation operation is to be performed, while the remaining portion of the β field 154 is decoded as the vector length field 159B. The memory access 120 instruction template includes the scale field 160 and optionally includes the displacement field 162A or the displacement scale field 162B.

[0067] Regarding the general vector friendly instruction format 100, the full opcode field 174 is shown, including a format field 140, a base operation field 142, and a data element width field 164. While one embodiment is shown in which the full opcode field 174 includes all of these fields, in embodiments that do not support all of these fields, the full opcode field 174 includes fewer than all of these fields. The full opcode field 174 provides an operation code (opcode).

[0068] The expand operation field 150, the data element width field 164, and the write mask field 170 allow these features to be specified on an instruction-by-instruction basis in the general vector friendly instruction format.

[0069] The combination of the write mask field and the data element width field creates typed instructions because they allow the mask to be applied based on different data element widths.

[0070] The various instruction templates found within categories A and B are beneficial in different contexts. In some embodiments of the present invention, different processors or different cores within a processor may support only category A, only category B, or both categories. For example, a high-performance general out-of-order core intended for general computing may support only category B, a core intended primarily for graphics and / or scientific (throughput) computing may support only category A, and a core intended for both may support both categories (of course, a core having some mix of templates and instructions from both categories but not all templates and instructions from both categories is within the bounds of the present invention). Similarly, a single processor may include multiple cores, all of which support the same category or where different cores support different categories. For example, in a processor with separate graphics and general cores, one of the graphics cores intended primarily for graphics and / or scientific computing may support only category A, while one or more of the general cores of the general cores may be high-performance general cores with out-of-order execution and register renaming intended for general computing that support only category B. Another processor without a separate graphics core may include more than one general in-order or out-of-order core that supports both category A and category B. Of course, features from one category may also be implemented in another category in different embodiments of the present invention. Programs written in a high-level language will be translated (e.g., just-in-time compiled or statically compiled) into a variety of different executable forms, including: 1) a form having only instructions of the category supported by the target processor for execution; or 2) a form having alternative routines written using different combinations of instructions from all categories and having control flow code that selects a routine to execute based on the instructions supported by the processor (which is currently executing the code).

[0071] VEX Instruction Format

[0072] VEX encoding allows instructions to have more than two operands and allows SIMD vector registers to be longer than 28 bits. The use of the VEX prefix provides a three-operand (or more) syntax. For example, a previous two-operand instruction performed an operation such as A = A + B, which overwrote the source operand. The use of the VEX prefix enables the operands to perform non-destructive operations such as A = B + C.

[0073] Figure 2A An exemplary AVX instruction format is shown, which includes a VEX prefix 202, a true opcode field 230, a Mod R / M byte 240, a SIB byte 250, a displacement field 262, and an IMM8 272. Figure 2B Shows which fields from Figure 2A constitute the complete opcode field 274 and the basic operation field 241. Figure 2C Shows which fields from Figure 2A constitute the register index field 244.

[0074] The VEX prefix (bytes 0-2) 202 is encoded in a three-byte form. The first byte is the format field 290 (VEX byte 0, bits [7:0]), which contains an explicit C4 byte value (the unique value for the C4 instruction format used for discrimination). The second and third bytes (VEX bytes 1-2) include multiple bit fields that provide specific capabilities. In particular, the REX field 205 (VEX byte 1, bits [7-5]) consists of: the VEX.R bit field (VEX byte 1, bit [7] - R), the VEX.X bit field (VEX byte 1, bit [6] - X), and the VEX.B bit field (VEX byte 1, bit [5] - B). Other fields of the instruction, such as the lower three bits (rrr, xxx, and bbb) that encode register indices known in the art, enable Rrrr, Xxxx, and Bbbb to be formed by adding VEX.R, VEX.X, and VEX.B. The opcode mapping field 215 (VEX byte 1, bits [4:0] - mmmmm) includes content for encoding the implicit leading opcode byte. The W byte 264 (VEX byte 2, bit [7] - W) - denoted by the symbol VEX.W and provides different functions depending on the instruction. The role of VEX.vvvv 220 (VEX byte 2, bits [6:3] - vvvv) can include the following: 1) VEX.vvvv encodes the first source register operand specified in inverted (1s complement) form and is valid for instructions with two or more source operands; 2) VEX.vvvv encodes the destination register operand specified in 1s complement form for certain vector shifts; or 3) VEX.vvvv does not encode any operands, the field is reserved and should contain 1111b. If the VEX.L 268 size field (VEX byte 2, bit [2] - L) = 0, it indicates a 28-bit vector; if VEX.L = 1, it indicates a 256-bit vector. The prefix encoding field 225 (VEX byte 2, bits [1:0] - pp) provides additional bits for the base operation field 241.

[0075] The true opcode field 230 (byte 3) is also referred to as the opcode byte. Parts of the opcode are specified in this field.

[0076] The MOD R / M field 240 (byte 4) includes a MOD field 242 (bits [7-6]), a Reg field 244 (bits [5-3]), and an R / M field 246 (bits [2-0]). The function of the Reg field 244 can include the following items: encoding a destination register operand or a source register operand (rrr of Rrrr), or being treated as an opcode extension and not being used to encode any instruction operand. The function of the R / M field 246 can include the following items: encoding an instruction operand that references a memory address, or encoding a destination register operand or a source register operand.

[0077] The content of the Scale, Index, Base (SIB)-scale field 250 (byte 5) includes SS252 (bits [7-6]), which is used for memory address generation. The content of the SIB.xxx 254 (bits [5-3]) and SIB.bbb 256 (bits [2-0]) fields has been mentioned previously with respect to the register indices Xxxx and Bbbb.

[0078] The displacement field 262 and the immediate number field (IMM8) 272 contain data.

[0079] Exemplary Register Architecture

[0080] Figure 3 is a block diagram of a register architecture 300 according to an embodiment of the present invention. In the illustrated embodiment, there are 32 vector registers 310 that are 512 bits wide; these registers are referred to as zmm0 through zmm31. The lower-order 256 bits of the lower 6 zmm registers are overlaid on the registers ymm0-15. The lower-order 128 bits of the lower 6 zmm registers (the lower-order 128 bits of the ymm registers) are overlaid on the registers xmm0-15.

[0081] General-purpose registers 325 - In the illustrated embodiment, there are sixteen 64-bit general-purpose registers that are used together with existing x86 addressing modes to address memory operands. These registers are referred to by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0082] The scalar floating-point stack register file (x87 stack) 345, on which the MMX packed integer flat register file 350 is aliased - In the illustrated embodiment, the x87 stack is an eight-element stack for performing scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set extension; and the MMX registers are used to perform operations on 64-bit packed integer data and are also used to save operands for some operations performed between the MMX and XMM registers.

[0083] Alternative embodiments of the present invention may use wider or narrower registers. In addition, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0084] Exemplary Core Architecture, Processor, and Computer Architecture

[0085] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) general-purpose in-order cores intended for general-purpose computing; 2) high-performance general-purpose out-of-order cores intended for general-purpose computing; 3) dedicated cores intended primarily for graphics and / or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more dedicated cores intended primarily for graphics and / or science (throughput). Such different processors lead to different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor on a separate die in the same package as the CPU; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or referred to as a dedicated core); and 4) a system on a chip that may include the described CPU (sometimes referred to as an application core or application processor), the coprocessor described above, and additional functionality on the same die. An exemplary core architecture is described next, followed by a description of an exemplary processor and computer architecture. Detailed description herein is circuitry (units) including exemplary cores, processors, etc.

[0086] Exemplary Core Architecture

[0087] Figure 4A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to embodiments of the present invention. Figure 4B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor in accordance with embodiments of the present invention. Figure 4A - The solid line boxes in B show the in-order pipeline and in-order core, while the optional addition of dashed line boxes shows the register renaming, out-of-order issue / execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0088] exist Figure 4AIn [the figure], the processor pipeline 400 includes a fetch stage 402, a length decoding stage 404, a decoding stage 406, an allocation stage 408, a renaming stage 410, a scheduling (also known as dispatch or issue) stage 412, a register read / memory read stage 414, an execution stage 416, a write-back / memory write stage 418, an exception handling stage 422, and a commit stage 424.

[0089] Figure 4B A processor core 490 is shown, which includes a front-end unit 430 coupled to an execution engine unit 450, and both are coupled to a memory unit 470. The core 490 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core 490 can be a specialized core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, and so on.

[0090] The front-end unit 430 includes a branch prediction unit 432 coupled to an instruction cache unit 434, the instruction cache unit 434 being coupled to an instruction translation lookaside buffer (TLB) 436, which is coupled to an instruction fetch unit 438, and the instruction fetch unit 438 being coupled to a decoding unit 440. The decoding unit 440 (or decoder) can decode instructions and generate as output one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from the original instructions. Using a variety of different mechanisms, the decoding unit 440 can be implemented. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), and so on. In one embodiment, the core 490 includes a microcode ROM or another medium (e.g., in the decoding unit 440 or otherwise within the front-end unit 430) that stores microcode for certain macroinstructions. The decoding unit 440 is coupled to a rename / allocator unit 452 in the execution engine unit 450.

[0091] The execution engine unit 450 includes a rename / allocator unit 452 coupled to a retirement unit 454 and a set of one or more scheduler units 456. The scheduler units 456 represent any number of different schedulers, including reservation stations, a central instruction window, and the like. The scheduler units 456 are coupled to a physical register file unit 458. Each of the physical register file units 458 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., an instruction pointer that is the address of the next instruction to be executed), and the like. In one embodiment, the physical register file unit 458 includes a vector register unit and a scalar register unit. These register units may provide architected vector registers, vector mask registers, and general-purpose registers. The physical register file unit 458 is overlapped with the retirement unit 454 to show various ways in which register renaming and out-of-order execution can be implemented (e.g., using a reorder buffer and a retirement register file; using a future heap, a history buffer, and a retirement register file; using a register map and a pool of registers; etc.). The retirement unit 454 and the physical register file unit 458 are coupled to an execution cluster 460. The execution cluster 460 includes a set of one or more execution units 462 and a set of one or more memory access units 464. The execution units 462 may perform various operations (e.g., shift, add, subtract, multiply) and operate on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include multiple execution units or only one execution unit that all perform all functions. The scheduler units 456, the physical register file unit 458, and the execution cluster 460 are shown as potentially plural because certain embodiments create separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline, each of which has its own scheduler unit, physical register file unit, and / or execution cluster—and in the case of a separate memory access pipeline, where certain embodiments are implemented in which only the execution cluster of this pipeline has a memory access unit 464). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, and the remainder are in-order.

[0092] A collection of memory access units 464 is coupled to memory unit 470, which includes a data TLB unit 472 coupled to a data cache unit 474, and the data cache unit 474 is coupled to a level 2 (L2) cache unit 476. In one exemplary embodiment, the memory access units 464 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 472 in the memory unit 470. The instruction cache unit 434 is further coupled to the level 2 (L2) cache unit 476 in the memory unit 470. The L2 cache unit 476 is coupled to one or more other levels of cache and ultimately to main memory.

[0093] By way of example, an exemplary register renaming, out-of-order issue / execution core architecture may implement a pipeline 400 as follows: 1) Instruction fetch 438 performs a fetch and length decoding stage 402 and 404; 2) The decode unit 440 performs a decode stage 406; 3) The rename / allocator unit 452 performs an allocation stage 408 and a rename stage 410; 4) The scheduler unit 456 performs a schedule stage 412; 5) The physical register file unit 458 and the memory unit 470 perform a register read / memory read stage 414; The execution cluster 460 performs an execution stage 416; 6) The memory unit 470 and the physical register file unit 458 perform a writeback / memory write stage 418; 7) Various units may be involved in an exception handling stage 422; and 8) The retirement unit 454 and the physical register file unit 458 perform a commit stage 424.

[0094] The core 490 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added with more recent versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, CA; the ARM instruction set of ARM Holdings of Sunnyvale, CA (with optional additional extensions such as NEON)), including the instructions described herein. In one embodiment, the core 490 includes logic for supporting packed data instruction set extensions (e.g., AVX1, AVX2), thus allowing operations used by many multimedia applications to be performed using packed data.

[0095] It should be understood that the core may support multithreading (two or more parallel sets of operations or threads), and may do so in a variety of ways, including time-sliced multithreading, simultaneous multithreading (where in the case where a single physical core provides a logical core for each of the threads, that physical core is performing simultaneous multithreading), or a combination thereof (e.g., time-sliced fetching and decoding followed by simultaneous multithreading such as in Intel® Hyper-Threading Technology).

[0096] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated embodiments of the processor also include separate instruction and data cache units 434 / 474 and a shared L2 cache unit 476, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a level 1 (L1) internal cache, or multiple levels of internal caches. In some embodiments, the system may include a combination of an internal cache and an external cache external to the core and / or the processor. Alternatively, all caches may be external to the core and / or the processor.

[0097] Specific Exemplary In - Order Core Architecture

[0098] Figure 5A -Block B shows a more specific exemplary in-order core architecture in which the core would be one of several logic blocks in a chip (including other cores of the same type and / or different types). The logic blocks communicate, depending on the application, via a high-bandwidth interconnect network (e.g., a ring network) with some fixed functional logic, a memory I / O interface, and other necessary I / O logic.

[0099] Figure 5A is a block diagram of a single processor core according to an embodiment of the present invention, along with its connection to the on-die interconnect network 502 and its local subset of the level 2 (L2) cache 504. In one embodiment, the instruction decoder 500 supports the x86 instruction set with packed data instruction set extensions. The L1 cache 506 allows low-latency access to cache memory into the scalar and vector units. Although in one embodiment (for simplicity of design), the scalar unit 508 and the vector unit 510 use separate register sets (correspondingly, scalar registers 512 and vector registers 514), and the data transferred between them is written to memory and then read back from the level 1 (L1) cache 506, alternative embodiments of the present invention may use different means (e.g., using a single register set or including a communication path that allows data to be transferred between the two register banks without being written and read back).

[0100] The local subset of the L2 cache 504 is part of the global L2 cache, which is partitioned into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache 504. Data read by a processor core is stored in its L2 cache subset 504 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 504 and flushed from other subsets if necessary. The ring network ensures consistency of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. In some embodiments, each ring data-path is 1024-bits wide in each direction.

[0101] Figure 5B is part of a processor core according to an embodiment of the present invention Figure 5A expanded view. Figure 5B includes part of the L1 data cache 506A including the L1 cache 504, and more details regarding the vector unit 510 and vector registers 514. Specifically, the vector unit 510 is a 6-wide vector processing unit (VPU) (see 16-wide ALU 528) that executes one or more of integer, single-precision floating, and double-precision floating instructions. The VPU supports shuffling register inputs via a shuffle unit 520 on memory inputs, numerical conversion via numerical conversion units 522A-B, and replication via a replication unit 524.

[0102] Processor with integrated memory controller and graphics

[0103] Figure 6 is a block diagram of a processor 600 according to an embodiment of the present invention that may have more than one core, may have an integrated memory controller, and may have integrated graphics. Figure 6 The solid-line boxes in show the processor 600 with a set including a single core 602A, a system agent 610, and a set of one or more bus controller units 616, while the optional additional dashed-line boxes show an alternative processor 600 with a set including multiple cores 602A-N, one or more integrated memory controller units 614 in the system agent unit 610, and dedicated logic 608.

[0104] Thus, different implementations of the processor 600 may include: 1) a CPU with dedicated logic 608 that is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and cores 602A-N that are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, a combination of the two); 2) a coprocessor with cores 602A-N that are a large number of dedicated cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor with cores 602A-N that are a large number of general-purpose in-order cores. Thus, the processor 600 can be a general-purpose processor, a coprocessor, or a special-purpose processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, and so on. The processor can be implemented on one or more chips. Using any of a number of processing technologies (such as, for example, BiCMOS, CMOS, or NMOS), the processor 600 can be implemented on one or more substrates and / or as portions thereof.

[0105] The memory hierarchy includes one or more levels of caches within the cores 604A-N, a set or sets of shared cache units 606, and external memory (not shown) coupled to a set of integrated memory controller units 614. The set of shared cache units 606 can include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, last-level cache (LLC), and / or combinations thereof. Although in one embodiment, a ring-based interconnect unit 612 interconnects the integrated graphics logic 608, the set of shared cache units 606, and the system agent unit 610 / integrated memory controller unit 614, alternative embodiments can use any number of well-known techniques for interconnecting such units. In one embodiment, coherence is maintained between one or more cache units 606 and the cores 602-A-N.

[0106] In some embodiments, one or more of the cores 602A-N have multi-threading capabilities. The system agent 610 includes those components that coordinate and operate the cores 602A-N. The system agent unit 610 can include, for example, a power control unit (PCU) and a display unit. The PCU can be or include the logic and components needed to regulate the power states of the integrated graphics logic 608 and the cores 602A-N. The display unit is used to drive one or more externally connected displays.

[0107] The core 602A-N can be homogeneous or heterogeneous with respect to the architecture instruction set; that is, two or more cores of the core 602A-N can have the ability to execute the same instruction set, while other cores can have the ability to execute different instruction sets or only subsets of that instruction set.

[0108] Exemplary computer architecture

[0109] Figures 7 - 10 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptop computers, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular telephones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices capable of incorporating the processors and / or other execution logic disclosed herein are generally suitable.

[0110] Now refer to Figure 7 , shown is a block diagram of a system 700 according to one embodiment of the present invention. The system 700 may include one or more processors 710, 715 coupled to a controller hub 720. In one embodiment, the controller hub 720 includes a Graphics Memory Controller Hub (GMCH) 790 and an Input / Output Hub (IOH) 750 (which may be on separate chips); the GMCH 790 includes a memory and a graphics controller to which a memory 740 and a coprocessor 745 are coupled; the IOH 750 couples input / output (I / O) devices 760 to the GMCH 790. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), and the memory 740 and the coprocessor 745 are directly coupled to the processors 710, and the controller hub 720 in a single chip with the IOH 750.

[0111] The optional nature of the additional processor 715 is denoted by a broken line in Figure 7 . Each processor 710, 715 may include one or more of the processing cores described herein and may be a version of the processor 600.

[0112] The memory 740 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two memories. For at least one embodiment, the controller hub 720 communicates with the processors 710, 715 via a multi-drop bus such as a front-side bus (FSB), a point-to-point interface, or a similar connection 795.

[0113] In one embodiment, the coprocessor 745 is a special-purpose processor such as, for example, a high-throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and the like. In one embodiment, the controller hub 720 may include an integrated graphics accelerator.

[0114] There can be a wide variety of differences between the physical resources 710, 7155 in terms of a spectrum of specifications including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

[0115] In one embodiment, the processor 710 executes instructions that control general types of data processing operations. Coprocessor instructions may be embedded within the instructions. The processor 710 identifies these coprocessor instructions as being of a type to be executed by an attached coprocessor 745. Accordingly, the processor 710 issues these coprocessor instructions (or control signals representative of the coprocessor instructions) on a coprocessor bus or other interconnect to the coprocessor 745. One or more coprocessors 745 receive and execute the received coprocessor instructions.

[0116] Now referring Figure 8 , shown is a block diagram of a first more specific exemplary system 800 in accordance with an embodiment of the present invention. As Figure 8 shown, the multi-processor system 800 is a point-to-point interconnect system and includes a first processor 870 and a second processor 880 coupled via a point-to-point interconnect 850. Each of processors 870 and 880 may be some version of processor 600. In one embodiment of the present invention, processors 870 and 880 are respectively processor 710 and 715, and the coprocessor 838 is coprocessor 745. In another embodiment, processors 870 and 880 are respectively processor 710, coprocessor 745.

[0117] Processors 870 and 880 are shown respectively including integrated memory controller (IMC) units 872 and 882. Processor 870 also includes point-to-point (P-P) interfaces 876 and 878 as part of its bus controller unit; similarly, second processor 880 includes P-P interfaces 886 and 888. Using P-P interface circuits 878, 888, processors 870, 880 may exchange information via a point-to-point (P-P) interface 850. As Figure 8 shown, the IMCs 872 and 882 couple the processors to respective memories (i.e., memory 832 and memory 834), which may be portions of main memories locally attached to the respective processors.

[0118] Using point-to-point interface circuits 876, 894, 886, 898, processors 870, 880 can each exchange information with chipset 890 via respective P-P interfaces 852, 854. Chipset 890 can optionally exchange information with coprocessor 838 via high performance interface 892. In one embodiment, coprocessor 838 is a dedicated processor such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and the like.

[0119] A shared cache (not shown) can be included either in any of the processors or outside of both processors and connected to the processors via a P-P interconnect such that if a processor is placed in a low power mode, local cache information of either or both processors can be stored in the shared cache.

[0120] Chipset 890 can be coupled to first bus 816 via interface 896. In one embodiment, first bus 816 can be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another I / O interconnect bus, although the scope of the present invention is not so limited.

[0121] As Figure 8 shown, various I / O devices 814 can be coupled to first bus 816 along with bus bridge 818 which couples first bus 816 to second bus 820. In one embodiment, one or more additional processors 815 such as a coprocessor, a high throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or a Digital Signal Processing (DSP) unit), a Field Programmable Gate Array, or any other processor are coupled to first bus 816. In one embodiment, second bus 820 can be a Low Pin Count (LPC) bus. Various devices can be coupled to second bus 820 including, for example, a keyboard and / or mouse 822, a communication device 827, and a storage unit 828 such as a hard disk drive or other mass storage device which can include instructions / code and data 830 (in one embodiment). Further, audio I / O 824 can be coupled to second bus 816. Note that other architectures are possible. For example, instead of Figure 8 the point-to-point architecture, the system can implement a multi-drop bus or another such architecture.

[0122] Now referring Figure 9 , shown is a block diagram of a second more specific exemplary system 900 in accordance with an embodiment of the present invention. Figure 8 and 9 Like elements in Figure 8 are labeled with like reference numerals and Figure 9 certain aspects ofFigure 9 Other aspects are difficult to understand.

[0123] Figure 9 Illustrated is that processors 870, 880 may respectively include integrated memories and I / O control logics (“CL”) 972 and 982. Accordingly, CL 972, 982 include integrated memory controller units and include I / O control logics. Figure 9 Illustrated is that not only memories 832, 834 are coupled to CL 872, 882, but also I / O device 914 is coupled to control logics 872, 882. Legacy I / O device 915 is coupled to chipset 890.

[0124] Now refer to Figure 10 , shown is a block diagram of SoC 1000 according to an embodiment of the present invention. Figure 6 Similar elements in Figure 10 are labeled with like reference numerals. Also, the dashed boxes are optional features on more advanced SoCs. In

[0125] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation means. Embodiments of the present invention may be implemented as program code or a computer program executed on a programmable system including at least one processor, a storage system (including volatile and non-volatile memories and / or storage elements), at least one input device, and at least one output device.

[0126] Such as Figure 8The program code of code 830 shown may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor (such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor).

[0127] The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with the processing system. If desired, the program code may also be implemented in assembly or machine language. In fact, the mechanisms described herein are not limited to any specific programming language. In any case, the language may be a compiled or interpreted language.

[0128] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium, the representative instructions representing various logic within a processor, which when read by a machine cause the machine to fabricate logic for performing the techniques described herein. Such representations (known as "IP cores") may be stored on a tangible, machine-readable medium and supplied to various customers or manufacturing facilities to be loaded into the manufacturing machines that actually make the logic or processor.

[0129] Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media (such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memory (CD-ROM), rewritable compact disk (CD-RW), and magneto-optical disks), semiconductor devices (such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM), magnetic or optical cards, or any other type of medium suitable for storing electronic instructions).

[0130] Accordingly, embodiments of the present invention also include non-transitory, tangible machine-readable media that contain instructions or contain design data, such as a hardware description language (HDL), that define the structures, circuits, devices, processors, and / or system features described herein. Such embodiments may also be referred to as program products.

[0131] Emulation (including binary translation, code morphing, etc.)

[0132] In some cases, an instruction converter may be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert the instructions into one or more other instructions to be processed by a core. The instruction converter is implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on the processor, off the processor, or partly on and partly off the processor.

[0133] Figure 11 is a block diagram that illustrates the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 11 shows that using a first compiler 1104, a program in a high-level language 1102 can be compiled to generate first binary code (e.g., x86) 1106, which can be natively executed by a processor 1116 with at least one first instruction set core. In some embodiments, the processor 1116 with at least one first instruction set core represents any processor that can generally perform the same functions as an Intel processor with at least one x86 instruction set core, either by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core, or (2) an object code version of an application or other software targeted to run on an Intel processor with at least one x86 instruction set core, so as to obtain generally the same results as an Intel processor with at least one x86 instruction set core. The first compiler 1104 represents a compiler operable to generate binary code 1106 (e.g., object code) of a first instruction set, and the binary code 1106 of the first instruction set can be executed on the processor 1116 with at least one first instruction set core with or without additional linking processing. Similarly, Figure 11FIG. 0 shows that with an alternative instruction set compiler 1108, a program in a high-level language 1102 can be compiled to generate alternative instruction set binary code 1110, which can be natively executed by a processor 1114 without at least one first instruction set core (e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and / or the ARM instruction set of ARM Holdings of Sunnyvale, CA). An instruction converter 1112 is used to convert the first binary code 1106 into code that can be natively executed by the processor 1114 without the first instruction set core. This converted code is unlikely to be the same as the alternative instruction set binary code 1110 because it is difficult to make an instruction converter that can do so; however, the converted code will perform the general operations and be composed of instructions from the alternative instruction set. Thus, the instruction converter 1112 represents software, firmware, hardware, or a combination thereof that allows a processor or another electronic device without a first instruction set processor or core to execute the first binary code 1106 through emulation, simulation, or any other process.

[0134] Apparatus and method for digital signal processing instructions

[0135] Digital signal processing (DSP) instructions are described below. In one embodiment, the circuitry and logic for performing DSP operations are integrated within the execution engine unit 450 shown in Figure 4B , within the various cores (see, e.g., Figure 6 and 10 the cores 602A-N in Figure 5A ), and / or within the vector unit 510 shown in Figure 4B . For example, the various source and destination registers can be SIMD registers within one or more physical register file units 458 in Figure 3 and / or the vector registers 310 in Figure 4B . The multiplication circuitry, adder circuitry, accumulator circuitry, and other circuitry described below can be integrated within the execution components of the above architectures, including, by way of example and not limitation, Figure 4B one or more execution units 462 in

[0136] One embodiment of the present invention includes circuitry and / or logic for processing Digital Signal Processing (DSP) instructions. Specifically, one embodiment includes a multiply-accumulate (MAC) architecture having eight 16×16 bit multipliers and two 64 bit accumulators. The Instruction Set Architecture (ISA) described below can process various multiply and MAC operations on 128-bit packed (8-bit, 16-bit, or 32-bit data elements) integer, fixed-point, and complex data types. In addition, certain instructions have direct support for efficient Fast Fourier Transform (FFT) and Finite Impulse Response (FIR) filtering of accumulated data through shift, round, and saturate operations, as well as post-processing.

[0137] One embodiment of the new DSP instructions uses opcode encoding based on the VEX.128 prefix, and several SSE / SSE2 / AVX instructions for post-processing of data are used with the DSP ISA. VEX-encoded 128-bit DSP instructions with memory operands can have relaxed memory alignment requirements.

[0138] In one embodiment, the instructions also support various integer and fixed-point data types, including:

[0139] 1) Q31 data type for signals requiring analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC) with a modulus greater than 16 bits;

[0140] 2) Q15 data type common in DSP algorithms;

[0141] 3) Complex 16-bit data type; and

[0142] 4) Complex 32-bit data type.

[0143] The Instruction Set Architecture described herein targets a wide range of standard DSP (e.g., FFT, filtering, pattern matching, correlation, polynomial evaluation, etc.) and statistical operations (e.g., mean, moving average, variance, etc.).

[0144] Target applications of embodiments of the present invention include sensors, audio, classification tasks in computer vision, and speech recognition. The DSP ISA described herein includes various instructions applicable to deep neural networks (DNNs), automatic speech recognition (ASR), sensor fusion with Kalman filtering, and other major DSP applications. Given a weight sequence {w 1 ,w 2 ,... w k} and an input sequence {x 1 ,x 2 ,x 3 ,... x n}, many image processing and machine learning tasks require computing by y i= w 1 x i + w 2 x i+1 +... +w k x i+k-1 Define the resulting sequence {y 1 , y 2 , y 3 ,... y n + 1-K}.

[0145] Figure 12 FIG. shows an exemplary processor 1255 on which embodiments of the present invention may be implemented, which includes a plurality of cores 0-N for simultaneously executing multiple instruction threads. The illustrated embodiment includes DSP instruction decoding circuitry / logic 1231 within decoder 1230 and DSP instruction execution circuitry / logic 1341 within execution unit 1240. These pipeline components may perform the operations described herein in response to the decoding and execution of DSP instructions. Although Figure 12 only the details of a single core (core 0) are shown, it should be understood that each of the other cores of processor 1255 may include similar components.

[0146] Before describing the specific details of embodiments of the present invention, a description of the various components of exemplary processor 1255 is provided directly below. Each of the plurality of cores 0-N may include a memory management unit 1290 for performing memory operations (such as load / store operations), a set of general-purpose registers (GPRs) 1205, a set of vector registers 1206, and a set of mask registers 1207. In one embodiment, multiple vector data elements are packed into each vector register 1206, and the vector register may have a 512-bit width for storing two 256-bit values, four 128-bit values, eight 64-bit values, sixteen 32-bit values, etc. However, the underlying principles of the present invention are not limited to any specific size / type of vector data. In one embodiment, mask register 1207 includes eight 64-bit operand mask registers for performing bit masking operations on the values stored in vector register 1206 (e.g., implemented as mask registers k0-k7 described herein). However, the underlying principles of the present invention are not limited to any specific mask register size / type.

[0147] Each core 0 - N may include dedicated level 1 (L1) cache 1212 and level 2 (L2) cache 1211 for caching instructions and data according to a specified cache management policy. The L1 cache 1212 includes a separate instruction cache 1220 for storing instructions and a separate data cache 1221 for storing data. Instructions and data stored within the various processor caches are managed at the granularity of cache lines, which may be of a fixed size (e.g., length 64, 128, 512 bytes). Each core of this exemplary embodiment has an instruction fetch unit 1210 for fetching instructions from main memory 1200 and / or shared level 3 (L3) cache 1216. The instruction fetch unit 1210 includes well - known components, including a next instruction pointer 1203 for storing the address of the next instruction to be fetched from memory 1200 (or one of the caches), an instruction translation lookaside buffer (ITLB) 1204 for storing mappings of recently used virtual - to - physical instruction addresses to improve the speed of address translation, a branch prediction unit 1202 for speculatively predicting instruction branch addresses, and a branch target buffer (BTB) 1201 for storing branch addresses and target addresses.

[0148] As described above, the decode unit 1230 includes DSP instruction decoding circuitry / logic 1231 for decoding the DSP instructions described herein into micro - operations or "uops" and the execution unit 1240 includes DSP instruction execution circuitry / logic 1241 for executing the DSP instructions. The write - back / retire unit 1250 retires the executed instructions and writes back the results.

[0149] Vector - packed double - complex multiply - add and accumulate real - part portion

[0150] One embodiment of the present invention includes a set of vector - packed instructions that multiply the real - part and the imaginary - part components of complex numbers stored in the packed data - element positions of source registers. The described embodiment operates on signed words in 128 - bit packed data registers (e.g., such as xmm1, xmm2, and xmm3 / m128). However, it should be noted that the basic principles of the present invention are not so limited.

[0151] In one embodiment, a first accumulator performs the operation Re((16 + 16i) x (16 + 16i)) + Re((16 + 16i) x (16 + 16i)) + 64 = 64 to calculate and accumulate a first real part portion, and a second accumulator performs the operation Re((16 + 16i) x (16 + 16i)) + Re((16 + 16i) x (16 + 16i)) + 64 = 64 to calculate and accumulate a second real part portion. In the foregoing notation, the numbers represent the number of bits used to represent each number (e.g., 16 + 16i represents a complex number represented by a 16-bit real component and a 16-bit imaginary component).

[0152] One specific embodiment decodes and executes a single instruction (sometimes distinguishable by the mnemonic VPCDPWQRE) to perform vector-packing of double complex multiply-addition and accumulation of real components. The following code details the individual operations performed in one embodiment, where TEMP0 and TEMP1 are registers or memory locations for storing intermediate values, and DEST is the destination register:

[0153] TEMP0[33:0] ← (((SRC2[47:32] * SRC3[47:32]) - (SRC2[63:48] * SRC3[63:48])) + ((SRC2[15:0] * SRC3[15:0]) - (SRC2[31:16] * SRC3[31:16])));

[0154] TEMP1[33:0] ← (((SRC2[111:96] * SRC3[111:96]) - (SRC2[127:112] *SRC3[127:112])) + ((SRC2[79:64] * SRC3[79:64]) - (SRC2[95:80] * SRC3[95:80])));

[0155] DEST[63:0] ← AddToQuadword({{30{TEMP0

[33] }}, TEMP0[33:0]}, DEST[63:0]);

[0156] DEST[127:64] ← AddToQuadword({{30{TEMP1

[33] }}, TEMP1[33:0]}, DEST[127:64]);

[0157] Figure 13Shows the bit distribution in exemplary source registers (SRCx) that will be used herein. In one embodiment, where the real and imaginary components of each complex number are stored in adjacent data element positions, the real component may be stored as, for example, data element A, and the corresponding imaginary component may be stored as data element B. In this arrangement, data elements C, E, and G store additional real components respectively, and data elements D, F, and H store the additional corresponding imaginary components respectively. In other embodiments, reverse the real and imaginary components in the above description (i.e., data element A includes the imaginary component and data element B includes the real component). However, the remaining description will assume an arrangement where data elements A, C, E, and G are real parts and data elements B, D, F, and H are imaginary parts.

[0158] Returning to the code above, TEMP0 stores the result of multiplication and addition / subtraction using the lower half (i.e., bits 63:0) of the data elements from SRC2 and SRC3, and TEMP1 stores the result of multiplication and addition / subtraction using the upper half (i.e., bits 127:64) of the data elements from SRC2 and SRC3. Real numbers are produced by these operations because an imaginary number times an imaginary number and a real number times a real number.

[0159] Then, the result in TEMP0 is accumulated with the existing quadword in the lower 64 bits (i.e., 63:0) of DEST, and the result in TEMP1 is accumulated with the existing quadword in the upper 64 bits (i.e., 127:64) of DEST. In one embodiment, the results are sign-extended before accumulating DEST[63:0] and DEST[127:64] with the results in TEMP0 and TEMP1 respectively. For example, 30{TEMP0

[33] } and 30{TEMP0

[33] } indicate that bit 33 (the most significant bit) of the result is copied to the adjacent 30-bit positions to produce a 64-bit value. Then, these two 64-bit values are accumulated with the two 64-bit values in the destination register. The final result includes the accumulation of the real number components.

[0160] Figure 14Shows an exemplary architecture for implementing the above operations, including a first source register SRC2 1401 that stores data elements S2A - S2H and a second source register SRC3 1402 that stores data elements S3A - S3H (where S2 is used as an abbreviation for SRC2 and S3 is used as an abbreviation for SRC3). In one embodiment, elements A, C, E, and G are real parts, and data elements B, D, F, and H are imaginary parts. Eight multipliers 1405 multiply the data elements in S2 with the corresponding data elements in S3 to generate 8 products (e.g., S3A * S2A, S3B * S2B, S3C * S2C, etc.). The first and second sets of adder networks 1410 - 1411 add and subtract the various products according to the above code. For example, adder network 1410 performs the following operations:

[0161] ((S2C * S3C) - (S2D * S3D)) + ((S2A * S3A) - (S2B * S3B));

[0162] And adder network 1411 performs the following operations:

[0163] ((S2G * S3G) - (S2H * S3H)) + ((S2E * S3E) - (S2F * S3F)).

[0164] The first and second accumulators, which include a first and a second adder 1420 - 1421 respectively, add the above results to the previously accumulated results (if any) stored in the SRC1 / DEST register 1460. Specifically, the outputs of adder network 1410, AN0_A to AN0_D, are added to the accumulated data in the lower 64 bits of the SRC1 / DEST register 1460. The result is saturated by the saturation circuit 1440 (i.e., if one or more values are greater than the maximum supported value, the maximum value is the output) and (potentially) the saturated result is stored back into the lower 64 bits of SRC1 / DEST 1460. Similarly, the outputs of adder network 1411, AN1_A to AN1_D, are added to the accumulated data in the upper 64 bits of the SRC1 / DEST register 1460. The result is saturated by the saturation circuit 1441 and output back into the upper 64 bits of SRC1 / DEST 1460.

[0165] Figure 15 Shows a method according to one embodiment. The method can be implemented in the processor architecture described in the context, but is not limited to any specific processor architecture.

[0166] At 1501, a first instruction is fetched, the first instruction having fields for an opcode and first and second packed data source operands representing complex numbers having real and imaginary part values, and a packed data destination operand. At 1502, the first instruction is decoded. At 1503, the real and imaginary part values associated with the first and second source operands are stored as packed data elements in first and second source registers, and the first instruction is scheduled for execution. As described above, in one embodiment, the first and second source operands are stored in a 128-bit packed data register that stores 16-bit packed data elements, each packed data element including a real or imaginary part value.

[0167] At 1504, the first decoded instruction is executed to multiply selected packed real part data elements from the first source register with corresponding packed real part data elements from the second source register to generate a first real part product. Additionally, selected packed imaginary part data elements from the first source register are multiplied with corresponding packed imaginary part data elements from the second source register to generate a second real part product.

[0168] At 1505, selected combinations of the first and second real part products are added / subtracted to respectively generate first and second sets of temporary results. As described above, in one embodiment, this includes the operations: ((S2C * S3C) - (S2D * S3D)) + ((S2A * S3A) - (S2B * S3B)) to produce a first temporary result and ((S2G) * S3G) - (S2H * S3H)) + ((S2E * S3E) - (S2F * S3F)) to produce a second temporary result, where S2C * S3C, S2D * S3D, S2A * S3A, and S2B * S3B are the first set of real part products and S2G * S3G, S2H * S3H, S2E * S3E, and S2F * S3F are the second set of real part products. In one embodiment, the first temporary result is combined with the lower 64 bits of the destination register, and the accumulated result is stored back into the lower 64 bits of the destination register. Similarly, the second temporary result is combined with the upper 64 bits of the destination register, and the accumulated result is stored back into the upper 64 bits of the destination register. In one embodiment, if necessary, the accumulated result is saturated before being stored back into the destination register.

[0169] At 1506, the result of the first instruction is committed to memory (e.g., and made globally visible).

[0170] Although the lengths of the real and imaginary part values described above are 16 bits, the basic principles of the present invention can be implemented using data elements of any size. For example, the real and imaginary components can be 8 bits, 32 bits, or 64 bits and still conform to the basic principles of the present invention.

[0171] Vector Packed Double Complex Multiply-Add and Accumulate Imaginary Part Portion

[0172] One embodiment of the present invention uses Figure 14 the architecture shown in to perform a set of packed double complex multiply-adds and accumulation of the imaginary components of a set of complex numbers. The described embodiment performs operations on signed words in a 128-bit packed data register (e.g., such as xmm1, xmm2, and xmm3 / m128). However, it should be noted that the basic principles of the present invention are not so limited.

[0173] In one embodiment, the first accumulator performs the following operation: Im((16 + 16i) × (16 + 16i)) + Im((16 + 16i) × (16 + 16i)) + 64i = 64i to calculate and accumulate the first imaginary component and the second accumulator performs the operation: Im((16 + 16i) x (16 + 16i)) + Im((16 + 16i) x (16 + 16i)) + 64i = 64i to calculate and accumulate the second imaginary component. As mentioned, in the foregoing notation, the numbers represent the number of bits used to represent each number (e.g., 16 + 16i represents a complex number represented by a 16-bit real component and a 16-bit imaginary component).

[0174] A specific embodiment decodes and executes a single instruction to perform vector packed double complex multiply-addition and accumulation of the real part portion, distinguished herein by the mnemonic VPCDPWQIMM. The following code details the individual operations performed in one embodiment, where TEMP0 and TEMP1 are registers or memory locations for storing intermediate values, and DEST is the destination register:

[0175] TEMP0[33:0] ← (((SRC2[47:32] * SRC3[63:48]) + (SRC2[63:48] * SRC3[47:32])) + ((SRC2[15:0] * SRC3[31:16]) + (SRC2[31:16] * SRC3[15:0])));

[0176] TEMP1[33:0] ← (((SRC2[111:96] * SRC3[127:112]) + (SRC2[127:112] *SRC3[111:96])) + ((SRC2[79:64] * SRC3[95:80]) + (SRC2[95:80] * SRC3[79:64])));

[0177] DEST[63:0] ← AddToQuadword({{30{TEMP0

[33] }}, TEMP0[33:0]}, DEST[63:0]);

[0178] DEST[127:64] ← AddToQuadword(({30{TEMP1

[33] }}, TEMP1[33:0]}, DEST[127:64]);

[0179] TEMP0 stores the result of multiplication and addition using the lower half data elements (i.e., bits 63:0) from SRC2 and SRC3, and TEMP1 stores the result of multiplication and addition using the upper half data elements (i.e., bits 127:64) from SRC2 and SRC3. Imaginary numbers are generated by these operations because each product includes an imaginary number multiplied by a real number.

[0180] Then, the result in TEMP0 is accumulated with the existing quadword in the lower 64 bits (i.e., 63:0) of the destination DEST, and the result in TEMP1 is accumulated with the existing quadword in the upper 64 bits (i.e., 127:64) of the destination DEST. Thus, the final result includes multiple accumulated imaginary number components.

[0181] Return to Figure 14 , the first source register SRC2 1401 stores data elements S2A - S2H, and the second source register SRC3 1402 stores data elements S3A - S3H. In one embodiment, elements A, C, E, and G are real parts, and data elements B, D, F, and H are imaginary parts. Eight multipliers 1405 multiply the real / imaginary data elements in SRC2 with the imaginary / real data elements in SRC3 to generate 8 imaginary products. In this case, the products added and stored in TEMP0 are S2C*S3D + S2D*S3C + S2A*S3B + S2B * S3A, and the products added and stored in TEMP1 are S2G*S3H + S2H*S3G + S2E*S3F + S2F*S3E. The first and second sets of adder networks 1410 - 1411 add the various imaginary products according to the above code. For example, adder network 1410 performs the following addition operation:

[0182] S2C*S3D + S2D*S3C + S2A*S3B + S2B * S3A;

[0183] And adder network 1411 performs the following addition operation:

[0184] S2G * S3H + S2H * S3G + S2E * S3F + S2F * S3E。

[0185] The accumulation circuit including adders 1420 - 1421 adds the above result to the previous accumulation result (if any) stored in the SRC1 / DEST register 1460. Specifically, the outputs of the adder network 1410, AN0_A to AN0_D, are added to the accumulated data at the element positions A - D in the SRC1 / DEST register 1460. The imaginary part result is saturated by the saturation circuit 1440 (i.e., if one or more values are greater than the maximum supported value, the maximum value is output). Then the result is stored back at the destination at the data element positions A - D. Similarly, the outputs of the adder network 1411, AN1_A to AN1_D, are added to the accumulated data at the element positions E - H in the SRC1 / DEST register 1460. The result is saturated by the saturation circuit 1441 and output back to the destination at the data element positions E - H.

[0186] Figure 16 A method according to one embodiment is shown. The method can be implemented within the context of the processor architectures described herein, but is not limited to any specific processor architecture.

[0187] At 1601, a first instruction is fetched, the first instruction having fields for an opcode and first and second packed data source operands and a packed data destination operand representing complex numbers having real and imaginary part values. At 1602, the first instruction is decoded. At 1603, the real and imaginary part values associated with the first and second source operands are stored as packed data elements in the first and second source registers, and the first instruction is scheduled for execution. As described above, in one embodiment, the first and second source operands are stored in a 128 - bit packed data register storing 16 - bit packed data elements, each packed data element including a real or imaginary part value.

[0188] At 1604, the first decoded instruction is executed to multiply a selected real part value from the first operand with a selected imaginary part value from the second operand to generate a first imaginary part product, and to multiply a selected imaginary part value from the first operand with a selected real part value from the second operand to generate a second imaginary part product.

[0189] In 1605, selected combinations of the first and second imaginary part products are added together to respectively generate first and second sets of temporary results. As described above, in one embodiment, this includes the following operations: S2C*S3D + S2D*S3C + S2A*S3B + S2B *S3A and S2G*S3H + S2H*S3G + S2E*S3F + S2F*S3E, where S2C*S3D, S2D*S3C, S2A*S3B, and S2B* S3A are the first set of imaginary part products, and S2G*S3H, S2H*S3G, S2E*S3F, and S2F*S3E are the second set of imaginary part products.

[0190] Additionally, in 1605, the first temporary result is combined with the data in the lower 64 bits of the destination register, and the accumulated result is stored back into the lower 64 bits of the destination register. Similarly, the second temporary result is combined with the upper 64 bits of the destination register, and the accumulated result is stored back into the upper 64 bits of the destination register. In one embodiment, if necessary, the accumulated result is saturated before being stored back into the destination register.

[0191] In 1606, the result of the first instruction is committed to the memory (e.g., and made globally visible).

[0192] Although the lengths of the above real part values and imaginary part values are 16 bits, the basic principles of the present invention can be implemented using data elements of any size. For example, the real part and imaginary part components can be 8 bits, 32 bits, or 64 bits and still comply with the basic principles of the present invention.

[0193] Although the lengths of the above real part values and imaginary part values are 16 bits, the basic principles of the present invention can be implemented using data elements of any size. For example, the real part and imaginary part components can be 8 bits, 32 bits, or 64 bits and still comply with the basic principles of the present invention.

[0194] The present invention also provides the following technical solutions:

[0195] 1. A processor, comprising:

[0196] A decoder for decoding a first instruction to generate a decoded instruction;

[0197] A first source register for storing a first plurality of packed real and imaginary data elements;

[0198] A second source register for storing a second plurality of packed real and imaginary data elements;

[0199] An execution circuit for executing the decoded instruction, the execution circuit comprising:

[0200] A multiplier circuit for selecting real and imaginary data elements in the first source register and the second source register for multiplication, the multiplier circuit for multiplying each selected imaginary data element in the first source register with the selected real data element in the second source register, and the multiplier circuit for multiplying each selected real data element in the first source register with the selected imaginary data element in the second source register to generate a plurality of imaginary products.

[0201] An adder circuit for adding a first subset of the plurality of imaginary products to generate a first temporary result, and for adding a second subset of the plurality of imaginary products to generate a second temporary result;

[0202] An accumulation circuit for combining the first temporary result with a first data from a destination register to generate a first final result, and for combining the second temporary result with a second data from the destination register to generate a second final result, and for storing the first final result and the second final result back into the destination register.

[0203] 2. The processor according to claim 1, wherein the real and imaginary values are stored as 16-bit data elements in the first and second source registers, each imaginary value being stored in a data element position contiguous to the data element position of the corresponding real value, and each combination of real and imaginary values representing a complex number.

[0204] 3. The processor according to claim 2, wherein the first and second source registers comprise 128-bit packed data registers configurable with data element positions A, B, C, D, E, F, G, and H for storing data elements A, B, C, D, E, F, G, and H respectively, and wherein data elements A, C, E, and G are real data elements, and data elements B, D, F, and H are corresponding imaginary data elements.

[0205] 4. The processor according to claim 3, wherein to execute the decoded instruction, the multiplier circuit is to perform multiplications S1C*S2D, S1D*S2C, S1A*S2B, S1B*S2A, S1G*S2H, S1H*S2G, S1E*S2F, S1F*S2E to generate the plurality of imaginary products, where S1 identifies the first source register, S2 identifies the second source register, and A - H respectively identify the packed data elements in data element positions A - H in the first and second source registers.

[0206] 5. The processor according to claim 4, wherein the addition of the first subset of the plurality of imaginary part products includes S1C*S2D + S1D*S2C + S1A*S2B + S1B*S2A, and the addition of the second subset of the plurality of imaginary part products includes S1G*S2H + S1H*S2G + S1E*S2F + S1F*S2E, to respectively generate the first temporary result and the second temporary result.

[0207] 6. The processor according to claim 5, wherein the first temporary result and the second temporary result are each to be extended to 64-bit values before being respectively accumulated with the first and second data from the destination register.

[0208] 7. The processor according to claim 6, wherein the first data includes a 64-bit data element packed in the lower half of the destination register and the second data includes a 64-bit data element packed in the upper half of the destination register.

[0209] 8. The processor according to claim 6, wherein the first temporary result and the second temporary result are sign-extended.

[0210] 9. The processor according to claim 8, wherein the values in the most significant bit positions of the first temporary result and the second temporary result are repeated a plurality of times to convert the first temporary result and the second temporary result into 64-bit values.

[0211] 10. A method, comprising:

[0212] decoding a first instruction to generate a decoded instruction;

[0213] storing a first plurality of packed real and imaginary data elements in a first source register;

[0214] storing a second plurality of packed real and imaginary data elements in a second source register;

[0215] selecting real and imaginary data elements in the first source register and the second source register for multiplication,

[0216] multiplying each selected imaginary data element in the first source register by a selected real data element in the second source register, and multiplying each selected real data element in the first source register by a selected imaginary data element in the second source register, to generate a plurality of imaginary part products,

[0217] Sum the first subset of the plurality of imaginary part products to generate a first temporary result, and sum the second subset of the plurality of imaginary part products to generate a second temporary result;

[0218] Accumulate the first temporary result with the first data from the destination register to generate a first final result, and accumulate the second temporary result with the second data from the destination register to generate a second final result; and

[0219] Store the first final result and the second final result back into the destination register.

[0220] 11. The method according to claim 10, wherein the real and imaginary part values are stored as 16-bit data elements in the first and second source registers, and each imaginary part value is stored in a data element position contiguous to the data element position of the corresponding real part value, and each combination of real and imaginary part values represents a complex number.

[0221] 12. The method according to claim 10, wherein the first and second source registers include 128-bit packed data registers, and the 128-bit packed data registers can be configured with data element positions A, B, C, D, E, F, G, and H for storing data elements A, B, C, D, E, F, G, and H respectively, and wherein data elements A, C, E, and G are real part data elements, and data elements B, D, F, and H are corresponding imaginary part data elements.

[0222] 13. The method according to claim 12, wherein in order to execute the decoded instruction, the multiplier circuit is to perform multiplications S1C*S2D, S1D*S2C, S1A*S2B, S1B*S2A, S1G*S2H, S1H*S2G, S1E*S2F, S1F*S2E to generate the plurality of imaginary part products, where S1 identifies the first source register, S2 identifies the second source register, and A-H respectively identify the packed data elements in data element positions A-H in the first and second source registers.

[0223] 14. The method according to claim 13, wherein the summing of the first subset of the plurality of imaginary part products includes S1C*S2D + S1D*S2C + S1A*S2B + S1B*S2A, and the summing of the second subset of the plurality of imaginary part products includes S1G*S2H + S1H*S2G + S1E*S2F + S1F*S2E to generate the first temporary result and the second temporary result respectively.

[0224] 15. The method according to claim 14, wherein the first temporary result and the second temporary result are each to be extended to a 64-bit value before being respectively accumulated with the first and second data from the destination register.

[0225] 16. The method according to claim 15, wherein the first data includes a 64-bit data element packed in the lower half of the destination register and the second data includes a 64-bit data element packed in the upper half of the destination register.

[0226] 17. The method according to claim 15, wherein the first temporary result and the second temporary result are sign-extended.

[0227] 18. The method according to claim 17, wherein the value in the most significant bit position of the first temporary result and the second temporary result is repeated a plurality of times to convert the first temporary result and the second temporary result into 64-bit values.

[0228] 19. A machine-readable medium having program code stored thereon, which when executed by a machine, causes the machine to perform the following operations:

[0229] Decode a first instruction to generate a decoded instruction;

[0230] Store a first plurality of packed real and imaginary data elements in a first source register;

[0231] Store a second plurality of packed real and imaginary data elements in a second source register;

[0232] Select real and imaginary data elements in the first source register and the second source register for multiplication;

[0233] Multiply each selected imaginary data element in the first source register by a selected real data element in the second source register, and multiply each selected real data element in the first source register by a selected imaginary data element in the second source register to generate a plurality of imaginary products,

[0234] Add a first subset of the plurality of imaginary products to generate a first temporary result, and add a second subset of the plurality of imaginary products to generate a second temporary result;

[0235] Accumulate the first temporary result with first data from a destination register to generate a first final result, and accumulate the second temporary result with second data from the destination register to generate a second final result; and

[0236] Store the first final result and the second final result back into the destination register.

[0237] 20. The machine-readable medium according to claim 19, wherein the real and imaginary part values are stored as 16-bit data elements in the first and second source registers, each imaginary part value being stored in a data element position contiguous to the data element position of the corresponding real part value, and each combination of real and imaginary part values representing a complex number.

[0238] 21. The machine-readable medium according to claim 19, wherein the first and second source registers comprise 128-bit packed data registers, the 128-bit packed data registers being configurable with data element positions A, B, C, D, E, F, G, and H for storing data elements A, B, C, D, E, F, G, and H respectively, and wherein data elements A, C, E, and G are real part data elements, and data elements B, D, F, and H are corresponding imaginary part data elements.

[0239] 22. The machine-readable medium according to claim 21, wherein, in order to execute the decoded instruction, the multiplier circuit is to perform multiplications S1C*S2D, S1D*S2C, S1A*S2B, S1B*S2A, S1G*S2H, S1H*S2G, S1E*S2F, S1F*S2E to generate the plurality of imaginary part products, where S1 identifies the first source register, S2 identifies the second source register, and A-H respectively identify the packed data elements in data element positions A-H in the first and second source registers.

[0240] 23. The machine-readable medium according to claim 13, wherein the addition of the first subset of the plurality of imaginary part products comprises S1C*S2D+S1D*S2C+S1A*S2B+S1B*S2A, and the addition of the second subset of the plurality of imaginary part products comprises S1G*S2H+S1H*S2G+S1E*S2F+S1F*S2E, to generate the first temporary result and the second temporary result respectively.

[0241] 24. The machine-readable medium according to claim 24, wherein the first temporary result and the second temporary result are each to be extended to 64-bit values before being respectively accumulated with the first and second data from the destination register.

[0242] 25. The machine-readable medium according to claim 25, wherein the first data comprises 64-bit data elements packed in the lower half of the destination register and the second data comprises 64-bit data elements packed in the upper half of the destination register.

[0243] 26. The machine-readable medium according to claim 25, wherein the first temporary result and the second temporary result are sign-extended.

[0244] 27. The machine-readable medium according to claim 26, wherein the value at the most significant bit position of the first temporary result and the second temporary result is repeated a plurality of times to convert the first temporary result and the second temporary result into 64-bit values.

[0245] In the foregoing specification, embodiments of the invention have been described with reference to specific exemplary embodiments. However, it will be apparent that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0246] Embodiments of the invention may include the various steps described above. These steps may be implemented in machine-executable instructions that may be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, these steps may be performed by specific hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

[0247] As described herein, an instruction may relate to a particular configuration of hardware, such as an application specific integrated circuit (ASIC) configured to perform certain operations or having pre-determined functionality or software instructions stored in a memory implemented in a non-transitory computer-readable medium. Thus, the techniques shown in the figures can be implemented using code and / or data stored and executed on one or more electronic devices (e.g., terminal stations, network elements, etc.). Such electronic devices use computer machine-readable media, such as non-transitory computer machine-readable storage media (e.g., magnetic disks, optical disks, random access memory, read-only memory, flash memory devices, phase change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustic, or other forms of propagated signals - such as carrier waves, infrared signals, digital signals, etc.), to store and transfer (internally and / or over a network with other electronic devices) code and data. Additionally, such electronic devices generally include a collection of one or more processors coupled to one or more other components such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touchscreens, and / or displays), and network connections. The coupling of the collection of processors to the other components is generally through one or more buses and bridges (also known as bus controllers). Signals carrying network traffic and storage devices represent one or more machine-readable communication media and machine-readable storage media, respectively. Thus, the storage device of a given electronic device generally stores code and / or data for execution on one or more of the processors in the collection of processors of the electronic device. Of course, different combinations of software, firmware, and / or hardware can be used to implement one or more portions of embodiments of the present invention. Throughout this detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, those skilled in the art will understand that the present invention can be practiced without some of these specific details. In some instances, well-known structures and functions are not described in detail in order to avoid obscuring the subject matter of the present invention. Accordingly, the scope and spirit of the present invention should be judged based on the following claims.

Claims

1. A processor, comprising: a decoder for decoding a first instruction to generate a decoded instruction; a first source register for storing a first plurality of packed real and imaginary data elements; a second source register for storing a second plurality of packed real and imaginary data elements; an execution circuit for executing the decoded instruction, the execution circuit comprising: a multiplier circuit for selecting real and imaginary data elements in the first and second source registers for multiplication, the multiplier circuit for multiplying each selected imaginary data element in the first source register by a selected real data element in the second source register, and the multiplier circuit for multiplying each selected real data element in the first source register by a selected imaginary data element in the second source register to generate a plurality of imaginary products; an adder circuit for adding a first subset of the plurality of imaginary products to generate a first temporary result and for adding a second subset of the plurality of imaginary products to generate a second temporary result; an accumulation circuit for combining the first temporary result with a first data from a destination register to generate a first final result, and for combining the second temporary result with a second data from the destination register to generate a second final result, and for storing the first final result and the second final result back into the destination register.

2. The processor according to claim 1, wherein the real and imaginary values are stored as 16-bit data elements in the first and second source registers, each imaginary value being stored in a data element position contiguous to the data element position of the corresponding real value, and each combination of real and imaginary values representing a complex number.

3. The processor according to claim 1 or 2, wherein the first and second source registers comprise 128-bit packed data registers configurable with data element positions A, B, C, D, E, F, G, and H for storing data elements A, B, C, D, E, F, G, and H respectively, and wherein data elements A, C, E, and G are real data elements and data elements B, D, F, and H are corresponding imaginary data elements.

4. The processor according to claim 3, wherein to execute the decoded instruction, the multiplier circuit is to perform multiplications S1C*S2D, S1D*S2C, S1A*S2B, S1B*S2A, S1G*S2H, S1H*S2G, S1E*S2F, S1F*S2E to generate the plurality of imaginary products, where S1 identifies the first source register, S2 identifies the second source register, and A-H respectively identify the packed data elements in data element positions A-H in the first and second source registers.

5. The processor according to claim 4, wherein the addition of the first subset of the plurality of imaginary part products includes S1C*S2D + S1D*S2C + S1A*S2B + S1B*S2A, and the addition of the second subset of the plurality of imaginary part products includes S1G*S2H + S1H*S2G + S1E*S2F + S1F*S2E, to generate the first temporary result and the second temporary result respectively.

6. The processor according to claim 1 or 5, wherein the first temporary result and the second temporary result are each to be extended to 64-bit values before being respectively accumulated with the first and second data from the destination register.

7. The processor according to claim 1 or 5, wherein the first data includes a 64-bit data element packed in the lower half of the destination register and the second data includes a 64-bit data element packed in the upper half of the destination register.

8. The processor according to claim 1 or 5, wherein the first temporary result and the second temporary result are sign-extended.

9. The processor according to claim 1 or 5, wherein the values in the most significant bit positions of the first temporary result and the second temporary result are repeated a number of times to convert the first temporary result and the second temporary result into 64-bit values.

10. A data processing method, comprising: decoding a first instruction to generate a decoded instruction; storing a first plurality of packed real and imaginary data elements in a first source register; storing a second plurality of packed real and imaginary data elements in a second source register; selecting real and imaginary data elements in the first source register and the second source register for multiplication; multiplying each selected imaginary data element in the first source register by a selected real data element in the second source register, and multiplying each selected real data element in the first source register by a selected imaginary data element in the second source register, to generate a plurality of imaginary part products; adding a first subset of the plurality of imaginary part products to generate a first temporary result, and adding a second subset of the plurality of imaginary part products to generate a second temporary result; accumulating the first temporary result with first data from a destination register to generate a first final result, and accumulating the second temporary result with second data from the destination register to generate a second final result; and storing the first final result and the second final result back in the destination register.

11. The data processing method according to claim 10, wherein the real and imaginary values are stored as 16-bit data elements in the first and second source registers, each imaginary value is stored in a data element position contiguous to the data element position of the corresponding real value, and each combination of a real and an imaginary value represents a complex number.

12. The data processing method according to claim 10 or 11, wherein the first and second source registers comprise 128-bit packed data registers, the 128-bit packed data registers being configurable with data element positions A, B, C, D, E, F, G, and H for storing data elements A, B, C, D, E, F, G, and H respectively, and wherein data elements A, C, E, and G are real part data elements, and data elements B, D, F, and H are corresponding imaginary part data elements.

13. The data processing method according to claim 12, wherein, in order to execute the decoded instruction, the multiplier circuit is to perform multiplications S1C*S2D, S1D*S2C, S1A*S2B, S1B*S2A, S1G*S2H, S1H*S2G, S1E*S2F, S1F*S2E to generate the plurality of imaginary part products, where S1 identifies the first source register, S2 identifies the second source register, and A-H respectively identify the packed data elements in data element positions A-H in the first and second source registers.

14. The data processing method according to claim 13, wherein the addition of the first subset of the plurality of imaginary part products comprises S1C*S2D + S1D*S2C + S1A*S2B + S1B*S2A, and the addition of the second subset of the plurality of imaginary part products comprises S1G*S2H + S1H*S2G + S1E*S2F + S1F*S2E, to generate the first temporary result and the second temporary result respectively.

15. The data processing method according to claim 10 or 14, wherein the first temporary result and the second temporary result are each to be extended to 64-bit values respectively before being added to the first and second data from the destination register.

16. The method according to claim 10 or 14, wherein the first data comprises 64-bit data elements packed in the lower half of the destination register and the second data comprises 64-bit data elements packed in the upper half of the destination register.

17. The data processing method according to claim 10 or 14, wherein the first temporary result and the second temporary result are sign-extended.

18. The data processing method according to claim 10 or 14, wherein the value in the most significant bit position of the first temporary result and the second temporary result is repeated a plurality of times to convert the first temporary result and the second temporary result into 64-bit values.

19. A machine-readable medium having program code stored thereon, the program code when executed by a machine causing the machine to perform the following operations: Decode a first instruction to generate a decoded instruction; Store a first plurality of packed real and imaginary part data elements in a first source register; Store a second plurality of packed real and imaginary part data elements in a second source register; Select real and imaginary part data elements in the first source register and the second source register for multiplication; Multiply each selected imaginary data element in the first source register by a selected real data element in the second source register, and multiply each selected real data element in the first source register by a selected imaginary data element in the second source register to generate a plurality of imaginary products. Add a first subset of the plurality of imaginary products to generate a first temporary result, and add a second subset of the plurality of imaginary products to generate a second temporary result. Accumulate the first temporary result with a first data from the destination register to generate a first final result, and accumulate the second temporary result with a second data from the destination register to generate a second final result. And Store the first final result and the second final result back into the destination register.

20. The machine-readable medium according to claim 19, wherein the real and imaginary values are stored as 16-bit data elements in the first and second source registers, and each imaginary value is stored in a data element position contiguous to the data element position of the corresponding real value, and each combination of a real and an imaginary value represents a complex number.

21. The machine-readable medium according to claim 19 or 20, wherein the first and second source registers include 128-bit packed data registers, the 128-bit packed data registers configurable with data element positions A, B, C, D, E, F, G, and H for storing data elements A, B, C, D, E, F, G, and H respectively, and wherein data elements A, C, E, and G are real data elements, and data elements B, D, F, and H are corresponding imaginary data elements.

22. The machine-readable medium according to claim 21, wherein to execute the decoded instruction, a multiplier circuit is to perform multiplications S1C*S2D, S1D*S2C, S1A*S2B, S1B*S2A, S1G*S2H, S1H*S2G, S1E*S2F, S1F*S2E to generate the plurality of imaginary products, where S1 identifies the first source register, S2 identifies the second source register, and A-H respectively identify the packed data elements in data element positions A-H in the first and second source registers.

23. The machine-readable medium according to claim 22, wherein the addition of the first subset of the plurality of imaginary products includes S1C*S2D + S1D*S2C + S1A*S2B + S1B*S2A, and the addition of the second subset of the plurality of imaginary products includes S1G*S2H + S1H*S2G + S1E*S2F + S1F*S2E to generate the first temporary result and the second temporary result respectively.

24. The machine-readable medium according to claim 19 or 23, wherein the first temporary result and the second temporary result are each to be extended to 64-bit values before being accumulated with the first and second data from the destination register respectively.

25. The machine-readable medium according to claim 19 or 23, wherein the first data comprises a 64-bit data element packed in the lower half of the destination register and the second data comprises a 64-bit data element packed in the upper half of the destination register.

26. A data processing apparatus, comprising: means for decoding a first instruction to generate a decoded instruction; means for storing a first plurality of packed real and imaginary data elements in a first source register; means for storing a second plurality of packed real and imaginary data elements in a second source register; means for selecting real and imaginary data elements in the first and second source registers for multiplication; means for performing the following operations: multiplying each selected imaginary data element in the first source register by a selected real data element in the second source register, and multiplying each selected real data element in the first source register by a selected imaginary data element in the second source register to generate a plurality of imaginary products; means for performing the following operations: adding a first subset of the plurality of imaginary products to generate a first temporary result, and adding a second subset of the plurality of imaginary products to generate a second temporary result; means for performing the following operations: accumulating the first temporary result with first data from a destination register to generate a first final result, and accumulating the second temporary result with second data from the destination register to generate a second final result; and means for storing the first final result and the second final result back in the destination register.

27. The apparatus according to claim 26, wherein the real and imaginary values are stored as 16-bit data elements in the first and second source registers, each imaginary value being stored in a data element position contiguous to the data element position of the corresponding real value, and each combination of a real and an imaginary value representing a complex number.

28. The apparatus according to claim 26 or 27, wherein the first and second source registers comprise 128-bit packed data registers, the 128-bit packed data registers being configurable with data element positions A, B, C, D, E, F, G, and H for storing data elements A, B, C, D, E, F, G, and H respectively, and wherein data elements A, C, E, and G are real data elements and data elements B, D, F, and H are corresponding imaginary data elements.

29. The apparatus according to claim 28, wherein, in order to execute the decoded instruction, the multiplier circuit is to perform multiplications S1C*S2D, S1D*S2C, S1A*S2B, S1B*S2A, S1G*S2H, S1H*S2G, S1E*S2F, S1F*S2E to generate the plurality of imaginary part products, where S1 identifies the first source register, S2 identifies the second source register, and A-H respectively identify the packed data elements in data element positions A-H in the first and second source registers.

30. The apparatus according to claim 29, wherein the addition of the first subset of the plurality of imaginary part products includes S1C*S2D + S1D*S2C + S1A*S2B + S1B*S2A, and the addition of the second subset of the plurality of imaginary part products includes S1G*S2H + S1H*S2G + S1E*S2F + S1F*S2E, to generate the first temporary result and the second temporary result respectively.

31. The apparatus according to claim 26 or 30, wherein the first temporary result and the second temporary result are each to be extended to 64-bit values respectively before the first and second data accumulations from the destination register.

32. The apparatus according to claim 26 or 30, wherein the first data includes 64-bit data elements packed in the lower half of the destination register and the second data includes 64-bit data elements packed in the upper half of the destination register.

33. The apparatus according to claim 26 or 30, wherein the first temporary result and the second temporary result are sign-extended.

34. The apparatus according to claim 26 or 30, wherein the values in the most significant bit positions of the first temporary result and the second temporary result are repeated a number of times to convert the first temporary result and the second temporary result into 64-bit values.

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