Clock Control in Semiconductor Systems

Abstract

Clock generation and control in a semiconductor system with process, voltage and temperature (PVT) variations. A semiconductor device may include at least a first ring oscillator and a second ring oscillator, each of which is respectively disposed at a position closest to a first logic circuit and a second logic circuit of an operation circuit, and generates a first oscillation signal and a second oscillation signal. A detection circuit is configured to perform a predetermined logic operation on the first oscillation signal and the second oscillation signal to generate a first clock signal. A calibration circuit is configured to receive the first clock signal from the detection circuit and perform delay control on each of the first ring oscillator and the second ring oscillator to generate a second clock signal for operating the operation circuit.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2017-0133562 filed on October 13, 2017, and Korean Patent Application No. 10-2017-0152061 filed on November 15, 2017, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0002] The present disclosure relates to clock generation and control in integrated circuits, and particularly takes into account process, voltage, and temperature (PVT) variations. Background Art

[0003] Semiconductor circuits such as integrated circuits (ICs) include multiple logic circuits (or logic cells) including transistors and other circuit elements. The performance and characteristics of the logic circuits may vary depending on PVT variations, where such variations may be global (occurring throughout the IC) and / or local (location-specific) variations.

[0004] Global changes in semiconductor circuits may occur due to changing production process parameters, supply voltage, and ambient temperature. For example, when the voltage supplied to a semiconductor logic circuit is at the high end of a specified range, the operating frequency of the semiconductor circuit (e.g., reflected as processing speed) is typically also at the high end of the range. In a similar manner, when the ambient temperature surrounding the IC increases, the operating frequency typically decreases. Changes in the performance and characteristics of semiconductor circuits are strongly affected by PVT variations.

[0005] Local variations refer to variations that depend on location in a semiconductor circuit, even if the semiconductor circuit is manufactured under uniform process conditions. For example, local temperatures throughout a semiconductor circuit may vary due to the presence or absence of resistive elements that generate heat at various locations (via "instant" voltage drops). The voltage supplied to the logic circuit may also vary in amplitude depending on the location within the chip. Therefore, a first logic circuit located at a first point that is different in temperature from a second point may have an operating frequency and other characteristics that are different from a second logic circuit of the same design located at the second point. Similarly, a logic circuit located at a point where the power supply voltage is close to the low end of a specified range may operate slower than a logic circuit located at another point where the power supply voltage is higher.

[0006] The clock signal is an oscillating electronic signal required to operate the logic circuit of the semiconductor circuit. The logic circuit can operate as desired when the frequency of the clock signal is within a certain range. However, if the clock signal frequency is too high when significant global / local PVT changes constrain the performance of the logic circuit, the logic circuit may show timing errors. Therefore, in order to generate a clock signal at an appropriate clock frequency within the range of expected global and local changes, there is a method to provide sufficient clock signal margin for the case where the maximum change occurs, that is, the worst case.

[0007] However, setting the clock signal margin based on the worst case is a scheme that applies a uniform standard to the entire semiconductor circuit, and typically does not result in optimized performance and power consumption of the semiconductor circuit. In addition, the worst case setting scheme does not flexibly respond to changes in the operating environment. Summary of the invention

[0008] Aspects of the inventive concept provide semiconductor devices and systems having clock generation and control techniques capable of improving performance and reducing power consumption of integrated circuits by overcoming local and global variations corresponding to PVT while reducing the margin required for clock signals used to operate the integrated circuits.

[0009] Aspects of the inventive concept also provide semiconductor devices and systems capable of monitoring performance of an integrated circuit in consideration of local and global changes corresponding to PVT.

[0010] According to aspects of the inventive concept, a semiconductor device may include a first ring oscillator disposed at a first position and configured to generate a first oscillation signal. A second ring oscillator is disposed at a second position and configured to generate a second oscillation signal, wherein the first position is closer to a first logic circuit of an operation circuit than the second position, and the second position is closer to a second logic circuit of the operation circuit than the first position. A detection circuit may be configured to generate a first clock signal by performing a predetermined logic operation on the first oscillation signal and the second oscillation signal. A calibration circuit may be configured to generate a second clock signal for operating the operation circuit by receiving the first clock signal from the detection circuit and performing delay control on each of the first ring oscillator and the second ring oscillator.

[0011] According to another aspect of the inventive concept, a semiconductor device may include the above-mentioned first ring oscillator and the second ring oscillator arranged relative to the first logic circuit and the second logic circuit in the above-mentioned manner. The detection circuit may be configured to generate a first clock signal reflecting a local change of the operation circuit based on the first oscillation signal and the second oscillation signal. The calibration circuit is configured to receive the first clock signal from the detection circuit and reflect the global change corresponding to the production process parameter, power supply voltage and temperature (PVT) in the first clock signal to generate a second clock signal for operating the operation circuit.

[0012] According to another aspect of the inventive concept, a semiconductor device may include the first ring oscillator and the second ring oscillator arranged relative to the first logic circuit and the second logic circuit in the above manner. A phase-locked loop (PLL) is arranged at a third position in the operation circuit and is configured to generate a PLL clock signal. The detection circuit is configured to perform a predetermined logic operation on the first oscillation signal, the second oscillation signal and the PLL clock signal to generate a clock signal for operating the operation circuit.

[0013] According to another aspect of the inventive concept, a semiconductor system is provided, comprising: a first critical path replica, configured to generate a first oscillation signal by reflecting a first condition associated with a first logic circuit in an operation circuit; a second critical path replica, configured to generate a second oscillation signal by reflecting a second condition associated with a second logic circuit in the operation circuit; a monitoring control circuit, configured to generate a first critical path replica selection signal for selecting the first critical path replica, provide the generated first critical path replica selection signal to the first critical path replica, generate a second critical path replica selection signal for selecting the second critical path replica, and provide the generated second critical path replica selection signal to the second critical path replica; and a detection circuit, configured to receive the first critical path replica selection signal and the second critical path replica selection signal from the monitoring control circuit, and perform a predetermined logic operation on the first oscillation signal, the second oscillation signal, the first critical path replica selection signal, and the second critical path replica selection signal to generate a monitoring signal for monitoring the operation circuit.

[0014] In yet another aspect of the inventive concept, a method for controlling a clock in an integrated circuit may involve generating N oscillation signals using N ring oscillators, respectively, wherein the N ring oscillators are respectively disposed proximate to a different one of N logic circuits of the integrated circuit. A clock signal having a frequency that initially matches the slowest oscillation frequency of the N oscillation signals may be generated. The frequency of the clock signal may be adjusted in response to a signal timing test using a critical path replica circuit. The clock signal having the adjusted frequency may be used to control the N logic circuits of the integrated circuit.

[0015] It should be noted that aspects of the inventive concept are not limited to the aspects of this summary of the invention. Other aspects of the inventive concept will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects and features of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which like reference numerals represent like components or functions, and in which:

[0017] Figure 1 is a schematic diagram illustrating a semiconductor system according to an embodiment of the inventive concept;

[0018] Figure 2 is a schematic diagram illustrating a semiconductor device according to an embodiment of the inventive concept;

[0019] Figure 3 is a schematic diagram illustrating an example ring oscillator according to an embodiment of the inventive concept;

[0020] Figure 4 is a schematic diagram illustrating a detection circuit according to an embodiment of the inventive concept;

[0021] Figure 5 is a schematic diagram illustrating a semiconductor device according to an embodiment of the inventive concept;

[0022] Figure 6 is a schematic diagram illustrating a critical path replication circuit according to an embodiment of the inventive concept;

[0023] Figure 7 is a flowchart illustrating a method of generating and controlling a clock in a semiconductor device according to an embodiment of the inventive concept;

[0024] Figure 8 is a schematic diagram illustrating a semiconductor system according to an embodiment of the inventive concept;

[0025] Fig.9A is a schematic diagram illustrating a semiconductor device according to an embodiment of the inventive concept;

[0026] Fig. 9B It shows that it can be Fig.9A Example configuration of a detection circuit used in a semiconductor device;

[0027] Fig.10 is a schematic diagram illustrating a semiconductor system according to an embodiment of the inventive concept;

[0028] Fig.11 is a schematic diagram illustrating a monitoring circuit according to an embodiment of the inventive concept; and

[0029] Fig.12 is a schematic diagram illustrating a detection circuit of a monitoring circuit according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0030] In the following, reference will be made to Figures 1 to 12 Semiconductor devices according to some example embodiments of the inventive concept are described.

[0031] Figure 11 is a schematic diagram illustrating a semiconductor system 1 according to an embodiment of the inventive concept. The semiconductor system 1 includes a plurality of logic circuits 20a, 20b, 20c, and 20d and a clock generation circuit 10. Hereinafter, the semiconductor system 1 may be interchangeably referred to as an operation circuit 1 or an integrated circuit (IC) 1.

[0032] The plurality of logic circuits 20a to 20d may include logic elements or logic cells for performing any functions or tasks required by the operation circuit 1. For example, the plurality of logic circuits 20a to 20d may include logic devices each consisting of a plurality of transistors and optional other circuit elements (e.g., capacitors, resistors, etc.).

[0033] In this embodiment, the plurality of logic circuits 20a to 20d may be provided at different locations in the arithmetic circuit 1. Figure 1 1 is a plan view of the operation circuit 1, the clock generation circuit 10 is arranged in the central area and the logic circuits 20a-20d are arranged outside the central area. For example, the logic circuits 20a and 20c are arranged in the area on the left side of the operation circuit 1, and the logic circuits 20b and 20d may be arranged in the area on the right side of the operation circuit 1. In another example layout, the logic circuits 20a and 20b may be arranged in the area located above the clock generation circuit 10 or the operation circuit 1, and the logic circuits 20c and 20d may be arranged in the area located below the clock generation circuit 10 or the operation circuit 1. In other layouts, the clock generation circuit is not in the center, and / or more or less logic circuits 20 are located close to the clock generation circuit 10.

[0034] The clock generation circuit 10 generates a clock signal CLK for operating the operation circuit 1. In the embodiment, the clock generation circuit 10 includes a plurality of ring oscillators (RO) 110a, 110b, 110c, and 110d and a clock control circuit 100.

[0035] The plurality of ring oscillators 110a to 110d generate oscillation signals and provide the generated oscillation signals to the clock control circuit 100. For example, the plurality of ring oscillators 110a to 110d may include an odd number of inverting gates and may generate oscillation signals by means of inverting gates. Feedback from the output to the input creates oscillation. This will be referred to below. Figure 3 A specific structure for one example configuration of the ring oscillators 110 a to 110 d is described.

[0036] According to the inventive concept, the ring oscillators 110a to 110d may be disposed at different locations in the operational circuit 1, and each may be adjacent to a different logic circuit 20. That is, each of the ROs 110a-110d is disposed closest to a different one of the logic circuits 20a-20d. In this manner, the oscillation frequency of the signal output by each RO reflects the local environment (in terms of PVT) of the nearest (e.g., adjacent) logic circuit. For example, the ring oscillator 110a may be disposed at a point (i.e., position) adjacent to the logic circuit 20a, and the ring oscillator 110b may be disposed at a point adjacent to the logic circuit 20b. In addition, the ring oscillator 110c may be disposed at a point adjacent to the logic circuit 20c, and the ring oscillator 110d may be disposed at a point adjacent to the logic circuit 20d. For example, if ROs 110a and 110b are of the same design and have internal delays set in the same manner, then ROs 110a and 110b will output oscillating signals having the same frequency when operated at the same ambient temperature and supply voltage (assuming minimal process variation between ROs). However, if the local temperature around RO 110a is higher than the local temperature around RO 110b due to logic circuit 20a dissipating more power than logic circuit 20b, the frequency of the signal output by RO 110a may be lower than that of RO 110b. Similar effects of different RO output frequencies may occur if the ring oscillators (and logic circuits) receive different supply voltages from each other. Note that the effects of process variation may typically be more global rather than local, and may not result in large differences in signal frequency output among ROs 110a-110d.

[0037] The clock control circuit 100 receives oscillation signals from a plurality of ring oscillators 110a to 110d disposed at different locations. In addition, the clock control circuit 100 performs a predetermined logic operation (an example of which is described below) on the oscillation signal to generate a clock signal CLK that reflects global changes and local changes of the operation circuit 1. The clock signal CLK generated by the clock control circuit 100 can operate a plurality of logic circuits 20a to 20d. Briefly explained, given the current PVT state of the operation circuit 1, the clock signal CLK can be generated at a frequency that is determined to be appropriate for the highest processing speed (for example, to avoid timing errors in the logic circuit) and / or optimal. Reference Figure 2 The operation of the example clock control circuit 100 is described.

[0038] Figure 21 is a schematic diagram illustrating an example clock generation circuit 10 according to an embodiment of the inventive concept. (The clock generation circuit 10 is also an example of a semiconductor device according to the inventive concept.) The clock generation circuit 10 includes at least the above-mentioned ring oscillators 110a and 110b and the clock control circuit 100. For clarity of explanation, the operation using at least two ring oscillators 110a and 110b (wherein additional ROs such as ROs 110c and 110d are optionally included) is explained below. Figure 2 In general, the clock generation circuit 10 includes at least two ROs, but the number of ROs can be set by the designer and can depend on how many logic circuit areas within the operation circuit 1 the designer wants to monitor and reflect using the ROs. The following description is equally applicable to the use of only a single RO or at least three ROs within the clock generation circuit 10.

[0039] As reference Figure 1 As described above, the ring oscillators 110a to 110d are provided at different points in the operation circuit 1. Referring collectively to Figure 1 and Figure 2 The first ring oscillator 110a is disposed at a first point adjacent to the first logic circuit 20a of the operation circuit 1 and is configured to generate a first oscillation signal RO_OUT1. The second ring oscillator 110b is disposed at a second point adjacent to the second logic circuit 20b in the operation circuit 1 and different from the first point and is configured to generate a second oscillation signal RO_OUT2.

[0040] The clock control circuit 100 may include a detection circuit 120 , a calibration circuit 130 , and a critical path replica (CPR) circuit 140 .

[0041] The detection circuit 120 generates a first clock signal CLK0 reflecting the local variation based on the first oscillation signal RO_OUT1 output from the first ring oscillator 110a and the second oscillation signal RO_OUT2 output from the second ring oscillator 110b. (If RO 110c and 110d are included in Figure 210, they can output the third oscillation signal RO_OUT3 and the fourth oscillation signal RO_OUT4 to the detection circuit 120, which in turn generates the first clock signal CLK0 based on these signals.) For example, the detection circuit 120 can provide the first clock signal CLK0 at a clock frequency that matches the lowest oscillation frequency among the first oscillation signal RO_OUT1 and the second oscillation signal RO_OUT2. Assume, for example, that the temperature is locally high near the RO 110a so that the logic circuit 20a adjacent to the RO 110a may operate best at a relatively low clock frequency to ensure minimum timing error. In this case, the oscillation frequency of the RO 110a is relatively low, reflecting the local environment of the logic circuit 20a (because the RO 110a inherently outputs an oscillation signal with a frequency that is positively correlated with the operating temperature of the RO 110a). The clock control circuit 100 (via the detection circuit 120, the calibration circuit 130 and the CPR circuit 140 explained below) can then provide the output clock signal CLK at a relatively low frequency to ensure error-free operation of the logic circuit 20a. On the other hand, if there is no RO reflecting the locally high temperature, the clock control circuit 100 can output the clock signal CLK at a relatively high clock frequency and thereby optimize the performance of the operation circuit 1 (e.g., faster processing speed with higher clock speed).

[0042] Here, local variation refers to, for example, variation depending on the location in the semiconductor circuit, even if the semiconductor circuit is manufactured under uniform process conditions. (With uniform process conditions, process variation between different logic circuits of the operation circuit 1 can be minimized and may not be the cause of excessive performance variation between logic circuits.) For example, when the temperature at a first point in the semiconductor circuit is significantly different from the temperature at a second point in the semiconductor circuit, the logic circuit located at the first point and the logic circuit located at the second point may have different performance and characteristics. As another example, a logic circuit located at a point in the semiconductor circuit where a voltage drop occurs instantaneously may have different performance and characteristics from a logic circuit located at another point.

[0043] The detection circuit 120 may generate the first clock signal CLK0 by performing a predetermined logic operation on the first oscillation signal RO_OUT1 and the second oscillation signal RO_OUT2. For example, in the first operation mode, the detection circuit 120 may track the slowest oscillation from among the first oscillation signal RO_OUT1 and the second oscillation signal RO_OUT2 (or track the slowest transition in the first oscillation signal RO_OUT1 and the second oscillation signal RO_OUT2). For example, in the second operation mode, the detection circuit 120 may output a clock signal at a frequency that matches only the slowest one of the first oscillation signal RO_OUT1 and the second oscillation signal RO_OUT2 (or may output only the transition of one of the first oscillation signal RO_OUT1 and the second oscillation signal RO_OUT2).

[0044] The calibration circuit 130 receives the first clock signal CLK0 from the detection circuit 120 and receives the result signal RES from the CPR circuit 140. Based on the RES signal, the calibration circuit 130 reflects the global changes corresponding to the production process parameters, power supply voltage and temperature (PVT) in the first clock signal CLK0 to generate a second clock signal CLK for operating the operation circuit 1. For example, as described later with respect to Figure 7 As explained, based on the RES signal, the frequency of the second clock signal CLK can be reduced below the initial frequency of the first clock signal CLK0. Such a clock frequency reduction can be warranted if global analog testing within the CPR circuit 140 indicates that timing errors in the critical path will occur if the clock speed is not reduced below the initial frequency of the first clock signal CLK0.

[0045] Here, global variation refers to the variation that occurs in semiconductor circuits according to production process parameters, power supply voltage, and temperature. For example, when the voltage supplied to a semiconductor circuit increases, the operating frequency of the semiconductor circuit generally also increases. Changes in the performance and characteristics of semiconductor circuits are strongly affected by PVT.

[0046] Further specifically, by performing delay control on the first ring oscillator 110a and the second ring oscillator 110b, the calibration circuit 130 can generate a second clock signal CLK for operating the operation circuit 1. Here, delay control refers to the task of matching the delay of the first clock signal CLK0 reflecting the local variation to the environment of the operation circuit 1. To this end, the calibration circuit 130 can provide a delay control signal DC to the first ring oscillator 110a and the second ring oscillator 110b. The delay control signal DC controls the internal delay of the first ring oscillator 110a, and thereby controls the frequency of the oscillation output signal, wherein a higher delay results in a slower oscillation frequency.

[0047] In addition, the calibration circuit 130 may provide an enable signal EN for enabling only one of the first ring oscillator 110a and the second ring oscillator 110b to the first ring oscillator 110a and the second ring oscillator 110b. Figure 2 Different enable signals EN1 and EN2 are shown applied to RO 110a and RO 110b, respectively.

[0048] In addition, the calibration circuit 130 may provide the ring oscillator selection signal RO_SEL to the detection circuit 120 , and may receive the output of the ring oscillator enabled by the enable signal EN from the detection circuit 120 operating in the second operation mode.

[0049] The critical path replica circuit 140 receives the first clock signal CLK0 from the detection circuit 120 and verifies whether the first clock signal CLK0 generates timing errors in a plurality of predetermined critical paths.

[0050] The critical path replication circuit 140 determines whether the first clock signal CLK0 has a timing error by means of a plurality of predetermined critical path replications (CPRs), and each critical path replication (CPR) corresponds to a replication circuit utilizing a critical path corresponding to the PVT condition of the operational circuit 1 in its current state. For example, the CPR may be a replication of a specific logic circuit within the operational circuit 1 so that a performance simulation of the logic circuit may be performed via a test CPR. It may be assumed that the CPR and the actual logic circuit within the operational circuit 1 have minimal process variation therebetween because they are manufactured together (even if process effects vary chip by chip and batch by batch, etc.). The CPR experiences substantially the same ambient global temperature as the actual logic circuit, and operates at substantially the same voltage as the actual logic circuit (both of which may vary over time and circumstances). Therefore, a performance simulation with a CPR may reflect the global PVT condition of the logic circuit.

[0051] Based on the control signal (CTL) received from the calibration circuit 130, the critical path replication circuit 140 applies a test pulse to multiple critical path replications to determine whether the first clock signal CLK0 has a timing error (or will cause a timing error within the CPR due to the clock speed being too high), and then transmits the determination result signal TES_OUT to the calibration circuit 130.

[0052] Figure 31 is a schematic diagram illustrating an example of a ring oscillator 110 that can be used for any of the ring oscillators described herein. The ring oscillator 110 may include a default oscillation period adjustment circuit 112, a first oscillation period adjustment circuit 114, and a second oscillation period adjustment circuit 116. For the ring oscillator 110, the delay between the serially connected elements can be adjusted in response to an externally applied delay control signal DC. The delay control signal DC indicating a relatively long delay is used to generate a relatively low frequency of oscillation of the RO output signal RO_OUT. Note that the ring oscillator 110 is different from many conventional ring oscillators that use direct feedback from the output port back to the input for generating oscillations.

[0053] The default oscillation period adjustment circuit 112 may include a plurality of inversion gates 123 . The default oscillation period adjustment circuit 112 generates an oscillation signal from the input signal RO_IN by means of the plurality of inversion gates 123 , and then transmits the generated oscillation signal to the first oscillation period adjustment circuit 114 .

[0054] In this embodiment, the input signal RO_IN of the ring oscillator 110 may be a feedback signal of the first clock signal CLK0 generated by the detection circuit 120. Returning temporarily to Figure 2 and Figure 3 In the first operation mode, the detection circuit 120 can enable the first clock signal CLK0 to reflect local changes by tracking the slowest oscillation frequency among the first oscillation signal RO_OUT1 and the second oscillation signal RO_OUT2, and then feed the generated first clock signal CLK0 (having a clock frequency substantially equal to the tracked slowest oscillation frequency) back to the ring oscillators 110a and 110b.

[0055] The first oscillation period adjustment circuit 114 may include a plurality of inverting gates 1142 and a multiplexer (MUX) 1144. The first oscillation period adjustment circuit 114 may adjust the oscillation period of the oscillation signal received from the default oscillation period adjustment circuit 112 to a first unit period. That is, the first oscillation period adjustment circuit 114 may adjust the delay of the oscillation signal received from the default oscillation period adjustment circuit 112 to the first unit period.

[0056] To this end, the first oscillation period adjustment circuit 114 may receive a delay control signal DC from the calibration circuit 130. The delay control signal DC may control the first oscillation period adjustment circuit 114 through the multiplexer 1144 to adjust the oscillation period to the first unit period.

[0057] Subsequently, the first oscillation period adjustment circuit 114 transmits the oscillation signal having the oscillation period adjusted to the first unit period to the second oscillation period adjustment circuit 116 .

[0058] The second oscillation period adjustment circuit 116 may include a plurality of inversion gates 1162 and a multiplexer (MUX) 1164 .

[0059] The second oscillation period adjustment circuit 116 can adjust the oscillation period of the oscillation signal received from the first oscillation period adjustment circuit 114 to a second unit period that is smaller than the first unit period. That is, the second oscillation period adjustment circuit 116 can adjust the delay of the oscillation signal received from the first oscillation period adjustment circuit 114 to the second unit period.

[0060] To this end, the second oscillation period adjustment circuit 116 may receive a delay control signal DC from the calibration circuit 130. The delay control signal DC may control the second oscillation period adjustment circuit 116 through the multiplexer 1164 to adjust the oscillation period to the second unit period.

[0061] Then, the second oscillation period adjustment circuit 116 transmits the oscillation signal having the oscillation period adjusted to the second unit period to the enable setting circuit 118 .

[0062] According to the enable signal EN received from the calibration circuit 130 , the enable setting circuit 118 may enable or disable the output of the oscillation signal that has passed through the default oscillation period adjustment circuit 112 , the first oscillation period adjustment circuit 114 , and the second oscillation period adjustment circuit 116 .

[0063] Subsequently, the output signal RO_OUT output by the enable setting circuit 118 may be transmitted to the detection circuit 120 .

[0064] As described above, the ring oscillator 110 may be implemented as an adjustable ring oscillator capable of adjusting the oscillation period, thereby adjusting the frequency of the output oscillation signal RO_OUT.

[0065] As discussed earlier, according to the present inventive concept, a plurality of ring oscillators 110a to 110d (see Figure 1 ) can be set at several points of the operation circuit 1 to generate a clock signal reflecting the local changes of the operation circuit 1. The period of the clock signal for operating the logic circuits 20a to 20d may be different for each point. To take this into account, the plurality of ring oscillators 110a to 110d may be implemented as adjustable ring oscillators to perform delay control suitable for each point. However, in Figure 1 In the example of FIG. 1 , the same clock signal CLK is applied to each logic circuit 20 a - 20 d and thus all logic circuits 20 a - 20 d can operate at the same clock speed. Figure 7As explained, as a result of the simulation test, it may be necessary to further reduce the clock speed. In this case, the selected one of the ring oscillators can be delayed by the delay control signal DC to produce a slower RO oscillation output signal, which can then be propagated through the detection circuit 120 and the calibration circuit 130 to generate the final slower output clock signal CLK. In other embodiments, multiple clock signals can be generated at different clock speeds, and each is applied to a different one of the logic circuits 20a-20d. Each of these clock signals can originate from a different one of the ring oscillators 110a-110d controlled by the corresponding delay control signal DC to oscillate at a unique frequency.

[0066] In some embodiments of the inventive concept, the plurality of inversion gates 1142 of the first oscillation period adjustment circuit 114 of the ring oscillator 110 may be implemented using the same type of logic gates as the plurality of inversion gates 1162 of the second oscillation period adjustment circuit 116 .

[0067] For example, the multiple inverting gates 1142 of the first oscillation period adjustment circuit 114 of the ring oscillator 110 can be implemented using a first type of logic gate, for example, a NAND logic gate 123 (where each input line shown is divided into two lines to provide a first and a second input of the same logic level, the NAND gate 123 thereby forming a NOT gate), and the multiple inverting gates 1162 of the second oscillation period adjustment circuit 116 of the ring oscillator 110 can be implemented using a second type of logic gate, for example, an inverter.

[0068] Other suitable configurations are contemplated for ring oscillator 110. Any configuration capable of providing an output oscillation signal RO_OUT based on feedback signal RO_IN, having an adjustable oscillation frequency responsive to input delay control signal DC, and enabled by signal EN may be sufficient.

[0069] In some embodiments of the inventive concept, the plurality of ring oscillators 110 a to 110 d may be implemented using the same type of logic cells or different types of logic cells.

[0070] Figure 4 1 is a schematic diagram illustrating an example of a detection circuit 120 according to an embodiment of the inventive concept. The detection circuit 120 may include a first logic gate 121, a second logic gate 122, a third logic gate 124, and a fourth logic gate 125. In the configuration shown, the detection circuit 120 has a "C-element" design for processing asynchronous inputs, which maintains a previous output state when two asynchronous inputs meet a certain standard. The C-element configuration of the detection circuit 120 shown is sufficient to output a first clock frequency signal CLK0 at a frequency that matches the slowest oscillation frequency of a plurality of asynchronous input signals.

[0071] The first logic gate 121 may be a multi-input AND logic gate for performing a first logic operation, such as an AND logic operation, on a plurality of input signals. The first logic gate 121 performs a first logic operation on the first oscillation signal RO_OUT1 and the second oscillation signal RO_OUT2 and transmits the result signal to the third logic gate 124 .

[0072] The second logic gate 122 may be a multi-input OR logic gate for performing a second logic operation, for example, an OR logic operation, on a plurality of input signals. The second logic gate 122 performs a second logic operation on the first oscillation signal RO_OUT1 and the second oscillation signal RO_OUT2 and transmits the result signal to the fourth logic gate 125 .

[0073] The third logic gate 124 may be an OR logic gate for performing a third logic operation, for example, an OR logic operation, on two input signals. The third logic gate 124 performs a third logic operation on the output signal of the first logic gate 121 and the output signal of the fourth logic gate 125 and transmits the result signal as the first clock signal CLK0.

[0074] The fourth logic gate 125 may be a multi-input AND logic gate for performing a fourth logic operation on a plurality of input signals, for example, an AND logic operation. The fourth logic gate 125 performs a fourth logic operation on the output signal of the second logic gate 122, the inverted signal of the ring oscillator selection signal RO_SEL, and the output signal of the third logic gate 124, and transmits the result signal to the third logic gate 124.

[0075] Here, the ring oscillator selection signal RO_SEL refers to a signal that the calibration circuit 130 provides to the detection circuit 120 to receive the output of the ring oscillator enabled by the enable signal EN from the detection circuit 120 .

[0076] Common reference Figure 2 and Figure 4 When the selection signal RO_SEL is a first value, for example, "0", the detection circuit 120 can track the slowest oscillation frequency among the first oscillation signal RO_OUT1 and the second oscillation signal RO_OUT2 in the first operating mode, and can output the resulting signal as the first clock signal CLK0 (to match the clock frequency of the slowest oscillation frequency).

[0077] Therefore, the first clock signal CLK0 can reflect local changes of the operation circuit 1. More specifically, the first clock signal CLK0 can reflect the first operating environment of the first logic circuit 20a by using the first oscillation signal RO_OUT1, and can reflect the operating environment of the second logic circuit 20b by using the second oscillation signal RO_OUT2.

[0078] When the selection signal RO_SEL is a second value, for example, "1", the detection circuit 120 may propagate only the oscillation signal (i.e., one of the first oscillation signal RO_OUT1 and the second oscillation signal RO_OUT2) output from the ring oscillator enabled by the enable signal EN in the second operation mode. In other words, in the second operation mode, the first clock signal CLK0 may have a clock frequency matching the frequency of the oscillation signal RO_OUT1 or RO_OUT2 selected by the enable signal.

[0079] In particular, the calibration circuit 130 may enable the first ring oscillator 110a and disable the second ring oscillator 110b, and vice versa, by using the enable signal EN. In addition, the calibration circuit 130 may perform delay control on the enabled first ring oscillator 110a by using the delay control signal DC.

[0080] The detection circuit 120 operating in the second operation mode may output, as the first clock signal CLK0 , a propagation signal of the first ring oscillator 110 a which is enabled and on which delay control is performed.

[0081] Subsequently, the calibration circuit 130 may enable the second ring oscillator 110b and disable the first ring oscillator 110a by using the enable signal EN. In addition, the calibration circuit 130 may perform delay control on the enabled second ring oscillator 110b by using the delay control signal DC.

[0082] The detection circuit 120 operating in the second operation mode may output, as the first clock signal CLK0 , a propagation signal of the second ring oscillator 110 b which is enabled and on which delay control is performed.

[0083] Therefore, the first clock signal CLK0 can reflect the global change corresponding to the PVT of the operation circuit 1 .

[0084] In some embodiments of the inventive concept, the calibration circuit 130 may match the delay of the first clock signal CLK0 reflecting local variations with the environment of the operation circuit 1 through delay control, and then additionally set a margin for the first clock signal CLK0 .

[0085] Figure 5 is a schematic diagram for illustrating a clock generation circuit according to an embodiment of the inventive concept. In this example, the clock generation circuit 10 ′, which is a semiconductor device according to an embodiment of the inventive concept, may be different from the clock generation circuit 10 by further including a lookup table (LUT) 150 .

[0086] The lookup table 150 may be accessed by the calibration circuit 130 to obtain data. Specifically, the lookup table 150 may pre-store data on delay settings corresponding to one or more PVT conditions.

[0087] The calibration circuit 130 may receive pre-stored data from the lookup table 150 , and may perform delay control on the first ring oscillator 110 a and the second ring oscillator 110 b based on the received data.

[0088] In the present embodiment, the lookup table 150 may be implemented in a volatile memory including a dynamic random access memory (DRAM), or may be implemented in a non-volatile memory including a flash memory.

[0089] Figure 6 1 is a schematic diagram illustrating an example critical path replication circuit 140 according to an embodiment of the inventive concept. The critical path replication (CPR) circuit 140 may include a test pulse launch (TPL) circuit 144, a critical path replication circuit unit 142, and a timing error statistics (TES) circuit 146. The CPR circuit 140 may further include a first latch unit 148a and a second latch unit 148b that control the progress of the test pulse according to the first clock signal CLK0 received by the detection circuit 120.

[0090] The TPL circuit 144 generates a test pulse for checking whether the first clock signal CLK0 has a timing error. For example, if one of the multiple different critical path replicas within the CPR circuit 140 fails the timing error test based on the current clock frequency of the first clock signal CLK0, the first clock signal CLK0 can be considered to have a timing error.

[0091] Specifically, the TPL circuit 144 generates a test pulse according to the control signal CTL received from the calibration circuit 130 and transmits the generated test pulse to the first latch unit 148a. The test pulse is applied to the CPR circuit unit 142 through the first latch unit 148a synchronized according to the first clock signal CLK0.

[0092] The critical path replica circuit unit 142 includes a plurality of critical path replicas 142a to 142c. Here, each of the critical path replicas 142a to 142c corresponds to a replica circuit using a critical path corresponding to the PVT condition of the operation circuit 1 in its current state.

[0093] Specifically, the first critical path replica 142a may reflect a first predetermined condition, i.e., a first PVT condition. For example, the first critical path replica 142a may be a replica circuit that "borrows" a critical path extracted from a first corner. Here, a corner may refer to a process corner or a certain area of ​​the IC 1. In the latter case, the critical path may be "borrowed" by providing a circuit that substantially replicates the critical path circuit present in the area.

[0094] The second critical path replica 142b may reflect the second predetermined condition, ie, the second PVT condition. For example, the second critical path replica 142b may be a replica circuit that borrows the critical paths extracted from the second corner and the third corner.

[0095] In some embodiments of the inventive concept, the number of critical path copies 142a to 142c can be optimized to be less than the number of critical paths extracted from all corners. For example, multiple critical path copies 142a to 142c can only include the results obtained from additionally filtering the paths that can meet the timing signoff condition among the critical paths extracted from the corners.

[0096] The critical path replica circuit unit 142 applies a test pulse to the plurality of critical path replicas 142 a to 142 c and then transmits a resultant signal to the timing error statistics circuit 146 through the second latch unit 148 b synchronized according to the first clock signal CLK0 .

[0097] Based on the result signal received through the second latch unit 148 b , the timing error statistics circuit 146 determines whether the first clock signal CLK0 generates timing errors in several critical paths in the operation circuit 1 , and then transmits a determination result signal TES_OUT to the calibration circuit 130 .

[0098] For example, to determine the timing error of TPL circuit 144, critical path replica circuit 140 generates a test pulse, such as a transition from "0" to "1", checks whether the value captured by timing error statistics circuit 146 is "0", and determines that a timing error has occurred when the value is not "0". An alternative timing error test may use the falling edge of the pulse.

[0099] Figure 7 1 is a flow chart illustrating a method of generating and controlling a clock in a semiconductor device according to an embodiment of the inventive concept. The method may be performed by a clock generation circuit 10, which may output a first clock signal CLK0 initially having a frequency matching the slowest oscillation frequency among the first oscillation signal RO_OUT1 and the second oscillation signal RO_OUT2 as part of a reset operation (S701). Alternatively, the first clock signal CLK0 tracks the slowest transition among the oscillation signals RO_OUT1 and RO_OUT2.

[0100] Subsequently, the calibration circuit 130 may select one of the plurality of ring oscillators 110a to 110d by using the enable signal EN (S703). The detection circuit 120 may then generate the first clock signal CLK0 by means of the selected ring oscillator (S705).

[0101] Next, the calibration circuit 130 determines whether a timing error of the first clock signal CLK0 occurs by using the critical path replicas 142 a to 142 c of the critical path replica circuit 140 ( S707 ).

[0102] In addition, when it is determined that the timing error of the first clock signal CLK0 has occurred (Y in S707), the calibration circuit 130 controls the delay of the selected ring oscillator by using the delay control signal DC (S709) and then performs step S705 again. In the illustrated example, the delay is increased in operation S709 to thereby reduce the frequency of the oscillation signal output by the selected RO chain and reduce the clock frequency of the first clock signal CLK0. However, the delay control can reduce or increase the frequency of the oscillation of the oscillation signal output by the selected RO chain to thereby change the clock frequency of the first clock signal CLK0 accordingly.

[0103] When it is determined that the timing error of the first clock signal has not occurred (N in S707 ), the calibration circuit 130 determines whether all delay control tasks for other ring oscillators have been completed ( S711 ).

[0104] When all tasks have been completed (Y in S711 ), the calibration circuit 130 generates a second (output) clock signal CLK by means of a plurality of ring oscillators 110 a to 110 d .

[0105] When at least one task (N in S711) remains, the calibration circuit 130 increases the index to select another ring oscillator and performs step S703. Then, the calibration circuit 130 selects another one of the plurality of ring oscillators 110a to 110d by using the enable signal EN and proceeds to the subsequent steps.

[0106] Figure 8 1 is a schematic diagram illustrating a semiconductor system (operation circuit) 2 according to an embodiment of the inventive concept. The operation circuit 2 includes a plurality of logic circuits 20a to 20d, and a phase-locked loop (PLL) 30 that is different from the conventional semiconductor system. Figure 1 The clock generation circuit 10 of the clock generation circuit 10 is a clock generation circuit 10". Other aspects of the logic circuits 20a-20d and the clock generation circuit 10" can be the same as those of the reference Figure 1 Therefore, the logic circuits 20 a to 20 d may be disposed at different locations in the operation circuit 2 , and the plurality of ring oscillators 110 a to 110 d may also be disposed at different corresponding locations in the operation circuit 2 .

[0107] The PLL 30 may provide a PLL clock signal PLL_CLK to a clock control circuit 102 of a clock generation circuit 10 ″. The clock control circuit 102 may also receive oscillation signals from a plurality of ring oscillators 110 a to 110 d .

[0108] The clock control circuit 102 may appropriately switch the oscillation signals received from the plurality of ring oscillators 110 a to 110 d and the PLL clock signal PLL_CLK received from the PLL 30 according to the operating environment of the operation circuit 2 to generate the clock signal CLK for operating the operation circuit 2 .

[0109] Below, we will refer to Fig.9A and Fig. 9B The operation of the clock control circuit 102 will be described in detail.

[0110] Fig.9A 1 is a schematic diagram illustrating an example clock generation circuit 10″ according to an embodiment of the inventive concept. The clock generation circuit 10″ (which is another example of a semiconductor device according to the inventive concept) includes at least two ring oscillators 110a and 110b, a PLL 30, and a clock control circuit 102. For clarity of explanation, two ring oscillators 110a and 110b will be discussed in the present embodiment, but in other variations of the embodiment, more or less than two ring oscillators may be utilized. The clock control circuit 102 differs from the above-described clock control circuit 100 via a modified detection circuit 120′ and by omitting a CPR circuit and a calibration circuit. An example configuration of the detection circuit 120′ is as follows: Fig. 9B shown.

[0111] As reference Figure 8 As described above, the plurality of ring oscillators 110a to 110d are provided at different points in the operation circuit 2. Referring collectively to Figure 8 , Fig.9A and Fig. 9B , the first ring oscillator 110a is disposed at a first point adjacent to the first logic circuit 20a in the operation circuit 2, and is configured to generate a first oscillation signal RO_OUT1. In addition, the second ring oscillator 110b is disposed at a second point adjacent to the second logic circuit 20b in the operation circuit 2 and different from the first point, and is configured to generate a second oscillation signal RO_OUT2. Therefore, the first oscillation signal RO_OUT1 reflects the first operating environment of the first logic circuit 20a, and the second oscillation signal RO_OUT2 reflects the operating environment of the second logic circuit 20b.

[0112] Independently of the position where the PLL 30 is provided in the arithmetic circuit 2 , the PLL 30 generates a PLL clock signal PLL_CLK which is an oscillation signal of a predetermined frequency.

[0113] The detection circuit 120 ′ may generate a clock signal CLK reflecting local variations based on the first oscillation signal RO_OUT1 outputted from the first ring oscillator 110 a and the second oscillation signal RO_OUT2 outputted from the second ring oscillator 110 b , and may generate a clock signal CLK irrelevant to local variations based on the PLL clock signal PLL_CLK.

[0114] For example, when a voltage drop occurs in the first logic circuit 20a based on the PLL clock signal PLL_CLK while the operation circuit 2 is operated by the clock signal, the detection circuit 120' can generate the clock signal CLK based on the first oscillation signal RO_OUT1 output from the first ring oscillator 110a to take into account the local variation. That is, the voltage drop causes local heat dissipation that is closest to the first ring oscillator 110a and not as much at the second ring oscillator 110b. The higher temperature at the first ring oscillator 110a causes the first oscillation signal RO_OUT1 to oscillate at a lower frequency than the second oscillation signal RO_OUT2 and the PLL clock signal PLL_CLK.

[0115] To this end, the detection circuit 120 ′ may track the slowest transition or oscillation among the first oscillation signal RO_OUT1 , the second oscillation signal RO_OUT2 , and the PLL clock signal PLL_CLK.

[0116] In this embodiment, the clock signal CLK generated by the detection circuit 120 ′ may be fed back to the first ring oscillator 110 a and the second ring oscillator 110 b .

[0117] In some embodiments of the inventive concept, the detection circuit 120 may perform a predetermined logic operation on the first oscillation signal RO_OUT1 , the second oscillation signal RO_OUT2 , and the PLL clock signal PLL_CLK to generate the clock signal CLK.

[0118] For example, Fig. 9B As shown, the detection circuit 120' may include a first logic gate 121, a second logic gate 122, a third logic gate 124, and a fourth logic gate 125. As in the case of the detection circuit 120 described earlier, the detection circuit 120' is shown as having a C-cell design for processing asynchronous inputs, which maintains a previous output state when two inputs meet a certain criterion. Specifically, the detection circuit 120' is configured to output a clock signal CLK at a frequency that substantially matches the lowest oscillation frequency among the three asynchronous input signals RO_OUT1, RO_OUT2, and PLL_CLK.

[0119] In particular, the first logic gate 121 may be a multi-input AND logic gate for performing a first logic operation, for example, an AND logic operation, on a plurality of input signals. The first logic gate 121 performs a first logic operation on the first oscillation signal RO_OUT1, the second oscillation signal RO_OUT2, and the PLL clock signal PLL_CLK, and transmits the result signal to the third logic gate 124.

[0120] The second logic gate 122 may be a multi-input OR logic gate for performing a second logic operation, for example, an OR logic operation, on a plurality of input signals. The second logic gate 122 performs a second logic operation on the first oscillation signal RO_OUT1 , the second oscillation signal RO_OUT2 , and the PLL clock signal PLL_CLK, and transmits the result signal to the fourth logic gate 125 .

[0121] The third logic gate 124 may be an OR logic gate for performing a third logic operation, for example, an OR logic operation, on two input signals. The third logic gate 124 performs a third logic operation on the output signal of the first logic gate 121 and the output signal of the fourth logic gate 125 and transmits the result signal as a clock signal CLK.

[0122] The fourth logic gate 125 may be an AND logic gate for performing a fourth logic operation, for example, an AND logic operation, on two input signals. The fourth logic gate 125 performs a fourth logic operation on the output signal of the second logic gate 122 and the output signal of the third logic gate 124 and transmits the result signal to the third logic gate 124.

[0123] Fig.10 is a schematic diagram for illustrating a semiconductor system (arithmetic circuit) 3 according to an embodiment of the inventive concept. The arithmetic circuit 3 includes logic circuits 20 a to 20 d , a clock generation circuit 10 ′″, and a monitoring circuit 40 .

[0124] The monitoring circuit 40 is a circuit for monitoring the actual performance of the operation circuit 3 according to the global change and the local change corresponding to the PVT. By monitoring the operation circuit 3 by means of the monitoring circuit 40, it is possible to track the minimum conditions for operating the operation circuit 3 under various conditions and further facilitate the adjustment of the power supply voltage or frequency of the clock signal provided to the operation circuit 3.

[0125] Fig.11 is a diagram illustrating an example configuration for a monitoring circuit 40 according to an embodiment of the inventive concept. The monitoring circuit 40, which is another semiconductor device according to an embodiment of the inventive concept, may include a monitoring control circuit 400, a detection circuit 410, and a counter 420.

[0126] The monitoring circuit 40 can use the reference Figure 6Here, the critical path replicas 142a to 142c correspond to replica circuits that utilize the critical path corresponding to the PVT condition of the operation circuit 3 as it is. For clarity of explanation, two critical path replicas 142a and 142b are provided in the present embodiment, but the inventive concept is not limited thereto.

[0127] Still Figure 6 As shown, the first critical path replica 142a may reflect the first predetermined condition, ie, the first PVT condition. For example, the first critical path replica 142a may be a replica circuit using the critical path extracted from the first corner.

[0128] The second critical path replica 142b may reflect the second predetermined condition, ie, the second PVT condition. For example, the second critical path replica 142b may be a replica circuit using critical paths extracted from the second corner and the third corner.

[0129] In some embodiments of the inventive concept, the number of critical path copies 142a to 142c can be optimized to be lower than the number of critical paths extracted from all corners. For example, multiple critical path copies 142a to 142c can only include the results obtained from additionally filtering the paths that can meet the timing end condition among the critical paths extracted from the corners.

[0130] The monitoring control circuit 400 generates a first critical path replica selection signal CPR_SEL1 for selecting the first critical path replica 142a, and transmits the generated first critical path replica selection signal CPR_SEL1 to the first critical path replica 142a. In addition, the monitoring control circuit 400 generates a second critical path replica selection signal CPR_SEL2 for selecting the second critical path replica 142b, and transmits the generated second critical path replica selection signal CPR_SEL2 to the second critical path replica 142b.

[0131] The monitoring control circuit 400 further transmits the first CPR selection signal CPR_SEL1 and the second CPR selection signal CPR_SEL2 to the detection circuit 410 .

[0132] The detection circuit 410 receives the first critical path copy selection signal CPR_SEL1 and the second critical path copy selection signal CPR_SEL2 from the monitoring control circuit 400, and performs a predetermined logic operation on the first oscillation signal CPR_OUT1, the second oscillation signal CPR_OUT2, the first critical path copy selection signal CPR_SEL1 and the second critical path copy selection signal CPR_SEL2 to generate a monitoring signal MON_OUT for the monitoring operation circuit 3.

[0133] In this embodiment, the output signal CLK1 generated by the detection circuit 410 can be fed back to the first critical path copy 142a and the second critical path copy 142b. The counter 420 is any kind of statistical logic. For example, the counter 420 can count the output signal CLK1, and the output of the counter 420 will be used to generate the monitoring signal MON_OUT. The implementation of the monitoring signal MON_OUT is not limited to a specific form.

[0134] Fig.12 Detection circuit 410 may include first logic gate 411, second logic gate 412, third logic gate 414, and fourth logic gate 415.

[0135] The first logic gate 411 may be a multi-input AND logic gate for performing a first logic operation, for example, an AND logic operation, on the plurality of first signals. The first logic gate 411 performs the first logic operation on the plurality of first signals and transmits the result signal to the third logic gate 414 .

[0136] The second logic gate 412 may be a multi-input OR logic gate for performing a second logic operation, for example, an OR logic operation, on the plurality of second signals. The second logic gate 412 performs a second logic operation on the plurality of second signals and transmits a result signal to the fourth logic gate 415 .

[0137] The third logic gate 414 may be an OR logic gate for performing a third logic operation, for example, an OR logic operation, on two input signals. The third logic gate 414 performs a third logic operation on the output signal of the first logic gate 411 and the output signal of the fourth logic gate 415 and transmits the result signal as a clock signal CLK.

[0138] The fourth logic gate 415 may be a multi-input AND logic gate for performing a fourth logic operation, for example, an AND logic operation, on two input signals. The fourth logic gate 415 performs a fourth logic operation on the output signal of the second logic gate 412 and the output signal of the third logic gate 414 and transmits the result signal to the third logic gate 414.

[0139] Here, the plurality of first signals include an output signal obtained by performing a fifth logic operation, for example, an OR logic operation, on the first oscillation signal CPR_OUT1 and the inverted signal of the first critical path copy selection signal CPR_SEL1, and include an output signal obtained by performing a fifth logic operation on the second oscillation signal CPR_OUT2 and the inverted signal of the second critical path copy selection signal CPR_SEL2.

[0140] The plurality of second signals include an output signal obtained by performing a sixth logic operation, for example, an AND logic operation, on the first oscillation signal CPR_OUT1 and the first critical path copy selection signal CPR_SEL1, and include an output signal obtained by performing a sixth logic operation on the second oscillation signal CPR_OUT2 and the second critical path copy selection signal CPR_SEL2.

[0141] According to the above-described various embodiments of the inventive concept, global and local variations corresponding to PVT can be overcome while reducing a margin required for a clock signal for operating a semiconductor circuit, thereby improving performance of the semiconductor circuit and reducing power consumption thereof.

[0142] While the inventive concepts described herein have been particularly shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the claimed subject matter as defined in the following claims and their equivalents.

Claims

1. A semiconductor device, include: a first ring oscillator disposed at a first location and configured to generate a first oscillation signal; a second ring oscillator disposed at a second position and configured to generate a second oscillation signal, the first position being closer to the first logic circuit of the operation circuit than the second position, and the second position being closer to the second logic circuit of the operation circuit than the first position; a detection circuit configured to generate a first clock signal by performing a predetermined logic operation on the first oscillation signal and the second oscillation signal; as well as a calibration circuit configured to generate a second clock signal for operating the operation circuit by receiving the first clock signal from the detection circuit and performing delay control on each of the first ring oscillator and the second ring oscillator, The first clock signal reflects a first operating environment of the first logic circuit based on the frequency of the first oscillation signal, and the second clock signal reflects a second operating environment of the second logic circuit based on the frequency of the second oscillation signal.

2. The semiconductor device according to claim 1, in, The first clock signal generated by the detection circuit is fed back to the first ring oscillator and the second ring oscillator to cause each of the first ring oscillator and the second ring oscillator to oscillate.

3. The semiconductor device according to claim 1, in, The calibration circuit supplies a delay control signal for performing delay control on each of the first ring oscillator and the second ring oscillator to the first ring oscillator and the second ring oscillator.

4. The semiconductor device according to claim 3, in, The first ring oscillator and the second ring oscillator each include a first oscillation period adjustment circuit configured to adjust the oscillation period to a first unit period and a second oscillation period adjustment circuit configured to adjust the oscillation period to a second unit period smaller than the first unit period, and The delay control signal controls the first oscillation period adjustment circuit and the second oscillation period adjustment circuit.

5. The semiconductor device according to claim 1, in, The first oscillation signal and the second oscillation signal are asynchronous signals, and the detection circuit is a C-cell type circuit configured to output a first clock signal at a frequency matching the slowest oscillation frequency among the first oscillation signal and the second oscillation signal.

6. The semiconductor device according to claim 1, in, The calibration circuit provides an enable signal to the first ring oscillator and the second ring oscillator for enabling only one of the first ring oscillator and the second ring oscillator to output the first oscillation signal or the second oscillation signal to the detection circuit.

7. The semiconductor device according to claim 6, in, The calibration circuit provides a ring oscillator selection signal to the detection circuit, and receives from the detection circuit a first clock signal having a clock frequency matching a first oscillation signal or a second oscillation signal output from the ring oscillator enabled by the enable signal.

8. The semiconductor device according to claim 7, in, The detection circuit includes a first logic gate, a second logic gate, a third logic gate and a fourth logic gate. The first logic gate and the second logic gate perform a first logic operation and a second logic operation on the first oscillation signal and the second oscillation signal respectively. wherein the third logic gate performs a third logic operation on an output signal of the first logic gate and an output signal of the fourth logic gate, and The fourth logic gate performs a fourth logic operation on the output signal of the second logic gate, the inverted signal of the ring oscillator selection signal, and the output signal of the third logic gate. 9 . The semiconductor device of claim 1 , further comprising a critical path replica circuit configured to receive the first clock signal from the detection circuit and check whether a timing error has occurred in the first clock signal in a plurality of critical paths.

10. The semiconductor device according to claim 9, in, The critical path replication circuit includes a first critical path replication reflecting a first predetermined condition, and a second critical path replication reflecting a second predetermined condition.

11. The semiconductor device of claim 1 , further comprising a look-up table (LUT) accessed by the calibration circuit, and in, The calibration circuit is configured to receive pre-stored data from a lookup table and perform delay control on each of the first ring oscillator and the second ring oscillator based at least in part on the pre-stored data.

12. A semiconductor device, include: a first ring oscillator disposed at a first location and configured to generate a first oscillation signal; a second ring oscillator disposed at a second position and configured to generate a second oscillation signal, the first position being closer to the first logic circuit of the operation circuit than the second position, and the second position being closer to the second logic circuit of the operation circuit than the first position; a phase-locked loop (PLL) disposed at a third location and configured to generate a PLL clock signal; as well as a detection circuit configured to perform a predetermined logic operation on the first oscillation signal, the second oscillation signal and the PLL clock signal to generate a clock signal for operating the operation circuit, The first oscillation signal reflects a first operating environment of the first logic circuit, and the second oscillation signal reflects a second operating environment of the second logic circuit.

13. The semiconductor device according to claim 12, in, The clock signal generated by the detection circuit is fed back to the first ring oscillator and the second ring oscillator.

14. The semiconductor device according to claim 12, in, The detection circuit includes a first logic gate, a second logic gate, a third logic gate and a fourth logic gate. The first logic gate and the second logic gate respectively perform a first logic operation and a second logic operation on the first oscillation signal, the second oscillation signal and the PLL clock signal. wherein the third logic gate performs a third logic operation on an output signal of the first logic gate and an output signal of the fourth logic gate, and The fourth logic gate performs a fourth logic operation on the output signal of the second logic gate and the output signal of the third logic gate.

15. A semiconductor device, include: a first critical path replica configured to generate a first oscillating signal by reflecting a first condition associated with a first logic circuit in the operational circuit; a second critical path replica configured to generate a second oscillating signal by reflecting a second condition associated with a second logic circuit in the operational circuit; a monitoring control circuit configured to generate a first critical path replica selection signal for selecting a first critical path replica, provide the generated first critical path replica selection signal to the first critical path replica, generate a second critical path replica selection signal for selecting a second critical path replica, and provide the generated second critical path replica selection signal to the second critical path replica; as well as The detection circuit is configured to receive the first critical path copy selection signal and the second critical path copy selection signal from the monitoring control circuit, and perform a predetermined logic operation on the first oscillation signal, the second oscillation signal, the first critical path copy selection signal, and the second critical path copy selection signal to generate a monitoring signal for the monitoring operation circuit.

16. The semiconductor device according to claim 15, in, The output signal generated by the detection circuit is fed back to the first critical path replica and the second critical path replica.

17. The semiconductor device according to claim 15, in, The detection circuit includes a first logic gate, a second logic gate, a third logic gate and a fourth logic gate. wherein the first logic gate performs a first logic operation on a plurality of first signals, wherein the second logic gate performs a second logic operation on a plurality of second signals, wherein the third logic gate performs a third logic operation on an output signal of the first logic gate and an output signal of the fourth logic gate, and The fourth logic gate performs a fourth logic operation on the output signal of the second logic gate and the output signal of the third logic gate. wherein the plurality of first signals include an output signal obtained by performing a fifth logic operation on the first oscillation signal and an inverted signal of the first critical path copy selection signal, and include an output signal obtained by performing a fifth logic operation on the second oscillation signal and an inverted signal of the second critical path copy selection signal, and The plurality of second signals include an output signal obtained by performing a sixth logic operation on the first oscillation signal and the first CPR selection signal, and include an output signal obtained by performing a sixth logic operation on the second oscillation signal and the second CPR selection signal.

18. The semiconductor device according to claim 15, in, The first oscillating signal reflects a first operating environment of a first logic circuit, and the second oscillating signal reflects a second operating environment of a second logic circuit.

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