Switched capacitor circuit to smooth the change of reference voltage

Abstract

The present disclosure provides a switching capacitor circuit that makes the change of the reference voltage smooth. A switching capacitor circuit includes a first main sampler circuit, a second main sampler circuit, a first replica sampler circuit, and a second replica sampler circuit. The first main sampler circuit samples a first input of a differential input, and generates a first output corresponding to the sampled first input based on a first reference voltage. The second main sampler circuit samples a second input of a differential input, and generates a second output corresponding to the sampled second input based on a second reference voltage. The first replica sampler circuit receives a first input and maintains the received first input based on a second reference voltage. The second replica sampler circuit receives a second input and maintains the received second input based on the first reference voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2017-0164439 filed on December 1, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an electronic device, and more particularly, to the construction and operation of a switched capacitor circuit for processing a signal. Background Art

[0004] In recent years, various electronic devices are being used. The electronic device provides its own functions according to the operation of the electronic circuit contained in the electronic device. Some electronic circuits can process signals sent / received outside / inside the electronic device, and thus can generate signals / data / information suitable for operating the electronic device.

[0005] A switched capacitor circuit is an example of an electronic circuit for processing discrete time signals. A switched capacitor circuit can discretely sample a signal that is continuous in the time domain and can generate an output corresponding to the sampled result. A switched capacitor circuit can be used for various purposes, such as a data sampler, a signal integrator, a voltage converter, a filter, etc.

[0006] At the same time, in electronic circuits, signal flow can affect electrical states (e.g., voltage, current, etc.). For example, when current flows, the level of the voltage used to drive the current may temporarily fluctuate. Such fluctuations in electrical states may affect the overall operation of the electronic circuit. Therefore, accurately controlling the operation of the electronic circuit so that the electrical state varies within a predictable range can be an important issue in terms of the accuracy and stability of the operation of the electronic circuit. Summary of the invention

[0007] Example embodiments of the present disclosure may provide a structure and operation so that the amount of change in the reference voltage level for operation of the switched capacitor circuit is smooth regardless of the input level of the differential input. Some example embodiments may provide a structure and operation capable of supplying a charge for providing the reference voltage.

[0008] In some example embodiments, a switched capacitor circuit may include a first main sampler circuit, a second main sampler circuit, a first replica sampler circuit, and a second replica sampler circuit. The first main sampler circuit may sample a first input of a differential input, and may generate a first output corresponding to the sampled first input based on a first reference voltage. The second main sampler circuit may sample a second input of a differential input, and may generate a second output corresponding to the sampled second input based on a second reference voltage. The first replica sampler circuit may receive a first input, and may maintain the received first input based on a second reference voltage. The second replica sampler circuit may receive a second input, and may maintain the received second input based on the first reference voltage.

[0009] In some example embodiments, a switched capacitor circuit may include a main sampler circuit, a replica sampler circuit, and an amplifier. The main sampler circuit may include: a first capacitive element that stores a charge corresponding to one input of a differential input; a first sampling switch element that passes the one input to the first capacitive element; and a first holding switch element that provides a first reference voltage to the first capacitive element. The replica sampler circuit may include: a second capacitive element that stores a charge corresponding to the one input; a second sampling switch element that passes the one input to a second capacitive element; and a second holding switch element that provides a second reference voltage different from the first reference voltage to the second capacitive element. The amplifier may generate an output based on the charge stored in the first capacitive element.

[0010] In some example embodiments, a switched capacitor circuit may include a main sampler circuit and a replica sampler circuit. The main sampler circuit may include a first capacitive element storing a charge corresponding to a first input of a differential input, and may generate an output corresponding to the charge stored in the first capacitive element based on a reference voltage. The replica sampler circuit may include a second capacitive element storing a charge corresponding to a second input of the differential input, and may maintain the charge stored in the second capacitive element based on a reference voltage. Regardless of the levels of the first input and the second input, the amount of charge supplied to the main sampler circuit and the replica sampler circuit based on the reference voltage may remain stable.

[0011] In some example embodiments, a switched capacitor circuit includes: a differential amplifier having a first differential input terminal and a second differential input terminal; a first sampling circuit including a first capacitor; a second sampling circuit including a second capacitor; a third sampling circuit including a third capacitor; and a fourth sampling circuit including a fourth capacitor. During a first time period: (1) the first sampling circuit charges the first capacitor with a first voltage generated between a first differential input signal and a common mode voltage, (2) the second sampling circuit charges the second capacitor with a second voltage generated between the first differential input signal and the common mode voltage, (3) the third sampling circuit charges the third capacitor with a third voltage generated between the second differential input signal and the common mode voltage, and (4) the fourth sampling circuit charges the fourth capacitor with a fourth voltage generated between the second differential input signal and the common mode voltage. During a second time period following the first time period and not overlapping with the first time period: (5) the fourth sampling circuit charges the fourth capacitor using a fifth voltage generated between the first reference voltage and the common mode voltage, (6) the first sampling circuit charges the first capacitor using a sixth voltage generated between the second reference voltage and the common mode voltage, (7) the second sampling circuit provides the first charge stored in the second capacitor during the first time period to the first differential input terminal of the differential amplifier and provides the first reference voltage to the second capacitor so as to maintain the first charge in the second capacitor, and (8) the third sampling circuit provides the second charge stored in the third capacitor in the first time period to the second differential input terminal of the differential amplifier and provides the second reference voltage to the third capacitor so as to maintain the second charge in the third capacitor.

[0012] In some example embodiments, since the level variation of the reference voltage used in the operation of the switched capacitor circuit is predictable, the linearity and accuracy of the operation of the switched capacitor circuit can be improved. In some example embodiments, since a configuration for supplying charge to the reference voltage is adopted, the operation speed of the switched capacitor circuit can be faster and its power consumption can be reduced. These example embodiments can be implemented at a low cost on a small circuit area. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects and features of the present disclosure will become apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0014] Figure 1 is a circuit diagram illustrating an example configuration of a switched capacitor circuit according to some example embodiments.

[0015] Figure 2 Is used to describe Figure 1 Graph of an example differential input and an example reference voltage in .

[0016] Figure 3 It is used to describe control Figure 1 A graph of example signals for the switches in FIG.

[0017] Figures 4 to 6 is used to describe the Figure 1 Conceptual diagram of example voltages of capacitor elements in FIG.

[0018] Figure 7 and Figure 8 is used to describe the level of the reference voltage as Figure 1 A graph showing the variation of the input level of the switched capacitor circuit.

[0019] Fig. 9 is a block diagram illustrating an example configuration of a switched capacitor circuit according to some example embodiments.

[0020] Fig.10 and Fig.11 It is shown Fig. 9 A circuit diagram of an example configuration of a switched capacitor circuit.

[0021] Figure 12 to Figure 14 Is used to describe Figure 2 and Figure 3 The curve diagram in Fig.10 and Fig.11 Conceptual diagram of example voltages of capacitor elements in FIG.

[0022] Fig.15 It is shown in Fig. 9 Block diagram of an example configuration for supplying charge based on a reference voltage in a switched capacitor circuit in FIG.

[0023] Fig.16 shows the reference voltage level used to describe the Fig.15 A graph of example changes in a switched capacitor circuit.

[0024] Fig.17 It is shown in Fig. 9 Block diagram of an example configuration for supplying charge based on a reference voltage in a switched capacitor circuit in FIG.

[0025] Fig.18 shows the reference voltage level used to describe the Fig.17 A graph of example changes in a switched capacitor circuit.

[0026] Fig.19 is a block diagram illustrating an example configuration of a switched capacitor circuit according to some example embodiments.

[0027] Fig. 20 It is shown Fig.19A circuit diagram of an example configuration of a switched capacitor circuit.

[0028] Fig.21 It is used to describe the control Fig. 20 A graph of example signals for the switches in FIG.

[0029] Figure 22 to Figure 24 Is used to describe Fig. 20 The charge supply circuit in Fig.21 A conceptual diagram of the operations of example signals.

[0030] Fig.25 and Fig.26 It is used to describe the Fig. 20 A conceptual diagram of an example method of determining a capacitance value or a charge supply voltage level of a capacitive element in FIG.

[0031] Fig. 27 It is shown Fig.19 A circuit diagram of an example configuration of a switched capacitor circuit. DETAILED DESCRIPTION

[0032] Hereinafter, some example embodiments will be described in detail and clearly with reference to the accompanying drawings so that those skilled in the art can easily implement the example embodiments.

[0033] Figure 1 is a circuit diagram illustrating an example configuration of a switched capacitor circuit 1000 according to some example embodiments.

[0034] The switched capacitor circuit 1000 may include reference buffers 1110 and 1120 , primary sampler circuits 1200 and 1400 , a switching element 1305 , an amplifier 1510 , and capacitive elements 1512 and 1514 .

[0035] The switched capacitor circuit 1000 may be an electronic circuit including at least a capacitive element and a switching element. For example, the capacitive element may include an element for storing charge (eg, a capacitor), and the switching element may include an element for passing and blocking an electrical signal (eg, a transistor).

[0036] For example, the main sampler circuit 1200 of the switched capacitor circuit 1000 may include switch elements 1205, 1210, 1220, and 1230 and a capacitive element 1240, and the main sampler circuit 1400 of the switched capacitor circuit 1000 may include switch elements 1405, 1410, 1420, and 1430 and a capacitive element 1440. Each of the capacitive elements 1240 and 1440 may have a capacitance value Cs.

[0037] The switched capacitor circuit 1000 may be used for signal processing. For example, the switched capacitor circuit 1000 may receive a differential input (eg, inputs VINP and VINN). For example, the switched capacitor circuit 1000 may process the inputs VINP and VINN to generate a differential output (eg, outputs VOUTP and VOUTN).

[0038] Figure 1 An example is shown where the switched capacitor circuit 1000 is a fully differential circuit, but this is provided to facilitate better understanding and is not intended to limit the present disclosure. In some example embodiments, the switched capacitor circuit 1000 may be changed and modified to produce a single-ended type of output.

[0039] For example, the switched capacitor circuit 1000 may be used for various purposes such as a data sampler, a signal integrator, a voltage converter, a filter, etc. For example, the switched capacitor circuit 1000 may be employed in various functional circuits such as a modulator (e.g., a delta-sigma modulator, etc.), an analog-to-digital converter (ADC), a digital-to-analog converter, etc., and may be included in various devices such as a modulator / demodulator (MODEM), a sensor (e.g., an image sensor, a biosensor, a touch sensor, etc.), an audio processor, a power management integrated circuit (PMIC), etc.

[0040] The switched capacitor circuit 1000 may receive the main reference voltages REFT and REFB and the common mode voltage CML. For example, the main reference voltages REFT and REFB and the common mode voltage CML may be received from a voltage source, such as a bandgap reference circuit, a PMIC, a voltage regulator, etc. Figure 2 1 and 2 , and the inputs VINP and VINN, the main reference voltages REFT and REFB, and the common mode voltage CML are further described.

[0041] The reference buffer 1110 may buffer the main reference voltage REFT to output a buffered reference voltage. The reference buffer 1120 may buffer the main reference voltage REFB to output a buffered reference voltage. In some example embodiments, the buffered reference voltages output from the reference buffers 1110 and 1120 may be provided as reference voltages REF1 and REF2. The reference voltage REF1 may be different from the reference voltage REF2. Figure 7 and Figure 8 The reference voltages REF1 and REF2 are further described.

[0042] The sampling switch element 1205 can transfer the input VINP of the differential input to the capacitive element 1240 in response to the sampling signal Psam. Therefore, the capacitive element 1240 can store the charge corresponding to the input VINP. As a result, the main sampler circuit 1200 can sample the input VINP in response to the sampling signal Psam.

[0043] The selection switch element 1210 can provide the reference voltage REF1 to the capacitor element 1240 in response to the selection signal RD, and the selection switch element 1220 can provide the reference voltage REF2 to the capacitor element 1240 in response to the selection signal RDB. The selection signal RD can be complementary to the selection signal RDB. Therefore, the main sampler circuit 1200 can selectively provide the reference voltage REF1 or the reference voltage REF2 to the capacitor element 1240 in response to the selection signals RD and RDB.

[0044] The main sampler circuit 1200 may receive one selected from the reference voltages REF1 and REF2 in response to the hold signal Phold. The hold switch element 1230 may provide the capacitor element 1240 with one selected from the reference voltages REF1 and REF2 in response to the hold signal Phold. The hold signal Phold may be received after the capacitor element 1240 stores the charge in response to the sampling signal Psam. The hold signal Phold may be complementary to the sampling signal Psam.

[0045] For example, the signals Psam, Phold, RD, and RDB may be received from a separate clock generation circuit or a separate control circuit. Each of the signals Psam, Phold, RD, and RDB may have a level or value for connecting or disconnecting a corresponding switching element. Figure 3 The signals Psam, Phold, RD and RDB are further described below.

[0046] When receiving the hold signal Phold, the master sampler circuit 1200 may generate an output corresponding to the charge stored in the capacitive element 1240 based on one selected from the reference voltages REF1 and REF2. As a result, the master sampler circuit 1200 may generate an output corresponding to the sampled input VINP based on the selected reference voltage.

[0047] The sampling switch element 1405 can transfer the differential input input VINN to the capacitive element 1440 in response to the sampling signal Psam. Therefore, the capacitive element 1440 can store the charge corresponding to the input VINN. As a result, the main sampler circuit 1400 can sample the input VINN in response to the sampling signal Psam.

[0048] The selection switch element 1410 may provide the reference voltage REF1 to the capacitance element 1440 in response to the selection signal RDB, and the selection switch element 1420 may provide the reference voltage REF2 to the capacitance element 1440 in response to the selection signal RD. The main sampler circuit 1400 may selectively provide the reference voltage REF1 or the reference voltage REF2 to the capacitance element 1440 in response to the selection signals RDB and RD.

[0049] According to the selection signals RD and RDB, the reference voltage of the reference voltages REF1 and REF2 to be provided to the main sampler circuit 1200 may be different from the reference voltage of the reference voltages REF1 and REF2 to be provided to the main sampler circuit 1400. For example, when the main sampler circuit 1200 receives the reference voltage REF1 in response to the selection signal RD, the main sampler circuit 1400 may receive the reference voltage REF2 in response to the selection signal RD. On the other hand, when the main sampler circuit 1200 receives the reference voltage REF2 in response to the selection signal RDB, the main sampler circuit 1400 may receive the reference voltage REF1 in response to the selection signal RDB.

[0050] For example, which selection signal of the selection signals RD and RDB is to be received may be determined according to the operation strategy or operation state of the functional circuit or device including the switched capacitor circuit 1000. For example, a separate control circuit may provide the switched capacitor circuit 1000 with a selection signal determined according to the operation strategy or operation state of the functional circuit or device including the switched capacitor circuit 1000.

[0051] The master sampler circuit 1400 may receive one selected from the reference voltages REF1 and REF2 in response to the hold signal Phold. The hold switch element 1430 may provide the capacitor element 1440 with one selected from the reference voltages REF1 and REF2 in response to the hold signal Phold.

[0052] When receiving the hold signal Phold, the master sampler circuit 1400 may generate an output corresponding to the charge stored in the capacitive element 1440 based on one selected from the reference voltages REF1 and REF2. As a result, the master sampler circuit 1400 may generate an output corresponding to the sampled input VINN based on the selected reference voltage.

[0053] The switch element 1305 can provide the common mode voltage CML to the main sampler circuits 1200 and 1400 in response to the sampling signal Psam. The common mode voltage CML can be provided to the capacitive elements 1240 and 1440. Figures 4 to 6 The voltages provided to capacitor elements 1240 and 1440 are further described.

[0054] The main sampler circuits 1200 and 1400 may generate outputs based on the charges stored in the capacitive elements 1240 and 1440. The amplifier 1510 may generate differential outputs (e.g., outputs VOUTP and VOUTN) based on the outputs of the main sampler circuits 1200 and 1400. That is, the outputs VOUTP and VOUTN may be generated based on the charges stored in the capacitive elements 1240 and 1440.

[0055] Capacitive elements 1512 and 1514 may be connected between an input terminal and an output terminal of amplifier 1510. Capacitive elements 1512 and 1514 may affect an amplification ratio of amplifier 1510. The amplification ratio of amplifier 1510 may correspond to a level ratio between an input of amplifier 1510 and an output of amplifier 1510. For example, a capacitance ratio of capacitor elements 1240 and 1512 and a capacitance ratio of capacitor elements 1440 and 1514 may determine an amplification ratio of amplifier 1510.

[0056] Figure 2 Is used to describe Figure 1 Graph of example differential inputs VINP and VINN and example reference voltages REFT and REFB in FIG.

[0057] The levels of inputs VINP and VINN may be symmetrical with respect to the common mode voltage CML. The common mode voltage CML may provide a reference for the differential inputs VINP and VINN. The maximum difference between the levels of inputs VINP and VINN may be "VIN". Therefore, the levels of inputs VINP and VINN may vary between "CML+VIN / 2" and "CML-VIN / 2".

[0058] For example, the level of the main reference voltage REFT may be higher than "CML+VIN / 2", and the level of the main reference voltage REFB may be lower than "CML-VIN / 2". The levels of the main reference voltages REFT and REFB may provide the levels that the reference voltages REF1 and REF2 are intended to have. The reference voltages REF1 and REF2 may be used to generate an output based on the charges stored in the capacitive elements 1240 and 1440.

[0059] For example, when the level of input VINP is higher than the level of input VINN (e.g., between time t0 and t2), differential inputs VINP and VINN may be intended to indicate a data value of logic "1". On the other hand, when the level of input VINP is lower than the level of input VINN (e.g., between time t2 and t4), differential inputs VINP and VINN may be intended to indicate a data value of logic "0". However, this example is provided to facilitate better understanding, and the data values ​​intended for the differential inputs VINP and VINN may be changed or modified to be different from this example.

[0060] Figure 3 It is used to describe the control Figure 1 Graphs of example signals Psam, Phold, RD and RDB for switches in FIG.

[0061] Each of the signals Psam and Phold may have a level or value for connecting or disconnecting the switching elements 1205, 1230, 1305, 1405, and 1430. The sampling signal Psam may be complementary to the holding signal Phold.

[0062] For example, in the sampling period (e.g., between time t0 and t1, and between time t2 and t3), the sampling signal Psam may have a level of logic "1", and the holding signal Phold may have a level of logic "0". For example, in the holding period (e.g., between time t1 and t2, and between time t3 and t4), the sampling signal Psam may have a level of logic "0", and the holding signal Phold may have a level of logic "1".

[0063] Refer to Figure 1 In the sampling period, the switch elements 1205, 1305, and 1405 may be connected (e.g., closed or turned on to form a current) in response to the sampling signal Psam, and the switch elements 1230 and 1430 may be disconnected (e.g., opened or turned off to block the current) in response to the holding signal Phold. Therefore, the capacitive elements 1240 and 1440 may store charges corresponding to the inputs VINP and VINN based on the common mode voltage CML.

[0064] Meanwhile, in the hold period, the switch elements 1205, 1305, and 1405 may be disconnected in response to the sampling signal Psam, and the switch elements 1230 and 1430 may be connected in response to the hold signal Phold. Therefore, the charges stored in the capacitors 1240 and 1440 may be output to the amplifier 1510 and the capacitors 1512 and 1514 based on the reference voltages REF1 and REF2. In the hold period, as the switch element 1305 is disconnected, the input terminals of the amplifier 1510 may have the same level due to the characteristics of the amplifier 1510 (e.g., this is also referred to as a "virtual ground" state).

[0065] return Figure 3 For example, the level of logic "1" of the sampling signal Psam and the holding signal Phold can be understood as the sampling signal Psam and the holding signal Phold being received. On the other hand, the level of logic "0" of the sampling signal Psam and the holding signal Phold can be understood as the sampling signal Psam and the holding signal Phold not being received. In this regard, it can be understood that the sampling signal Psam and the holding signal Phold are continuously and alternately received.

[0066] Each of the signals RD and RDB may have a level or value for connecting or disconnecting the corresponding switch elements 1210, 1220, 1410, and 1420. The selection signal RD may be complementary to the selection signal RDB. For example, the selection signal RD may have a level of logic "1", and the selection signal RDB may have a level of logic "0". In this example, referring to Figure 1 , the master sampler circuit 1200 may receive a reference voltage REF1, and the master sampler circuit 1400 may receive a reference voltage REF2.

[0067] It will be described below that, in response to the selection signal RD, the master sampler circuit 1200 receives the reference voltage REF1 and the master sampler circuit 1400 receives the reference voltage REF2. However, this is provided to facilitate better understanding and is not intended to limit the present disclosure. As described above, the reference voltages to be provided to the master sampler circuits 1200 and 1400 may be interchanged according to the operation strategy or operation state of the functional circuit or device including the switch capacitor circuit 1000.

[0068] Figures 4 to 6 is used to describe the Figure 1 Conceptual diagram of example voltages of capacitor elements 1240 and 1440 in FIG.

[0069] Figure 4 1 shows the voltages provided to the capacitive elements 1240 and 1440 during the sampling period between time t0 and t1. Figures 1 to 3 , in the sampling period between time t0 and t1, the input VINP of the level of "CML+VIN / 2" and the common mode voltage CML may be provided to the opposite ends of the capacitive element 1240. In addition, the input VINN of the level of "CML-VIN / 2" and the common mode voltage CML may be provided to the opposite ends of the capacitive element 1440. Therefore, the capacitive elements 1240 and 1440 may store charges in response to the levels of "CML+VIN / 2" and "CML-VIN / 2".

[0070] Figure 5 1 and 2 show the voltages supplied to the capacitor elements 1240 and 1440 during the holding period between time t1 and t2 and between time t3 and t4. Figures 1 to 3 , in the hold period, the reference voltages REF1 and REF2 may be provided to the first terminals of the capacitors 1240 and 1440, respectively. Therefore, the charges stored in the capacitors 1240 and 1440 may be output to the amplifier 1510 and the capacitors 1512 and 1514 based on the reference voltages REF1 and REF2. Meanwhile, as the input terminal of the amplifier 1510 is in a virtual ground state, the levels of the second terminals of the capacitors 1240 and 1440 may be substantially maintained at the level of the common mode voltage CML.

[0071] Figure 6 1 shows the voltages provided to the capacitive elements 1240 and 1440 during the sampling period between time t2 and time t3. Figures 1 to 3 , in the sampling period between time t2 and time t3, the input VINP of the level of "CML-VIN / 2" and the common mode voltage CML may be provided to the opposite ends of the capacitive element 1240. In addition, the input VINN of the level of "CML+VIN / 2" and the common mode voltage CML may be provided to the opposite ends of the capacitive element 1440. Therefore, the capacitive elements 1240 and 1440 may store charges in response to the levels of "CML-VIN / 2" and "CML+VIN / 2".

[0072] Figure 7 shows a diagram for describing the level of the reference voltage REF1 as the Figure 1 FIG. 1 is a graph showing changes in the level of the input VINP of the switched capacitor circuit 1000. FIG.

[0073] For example, after the input VINP of the level of "CML+VIN / 2" is provided to the capacitor 1240 in the sampling period between time t0 and t1, as the reference voltage REF1 is provided to the capacitor 1240 in the holding period between time t1 and t2, the capacitor 1240 may need as much additional charge as the charge amount "Cs×VT11" corresponding to the voltage difference "VT11 (=REFT-(CML+VIN / 2))". The additional charge can be supplied based on the reference voltage REF1.

[0074] In the sampling period between time t0 and t1, the level of reference voltage REF1 can be maintained at the level of main reference voltage REFT. However, in the holding period between time t1 and t2, since capacitor element 1240 requires additional charge, the level of reference voltage REF1 can change by a change amount VT21 compared to the level of main reference voltage REFT, and then can be restored to the level of main reference voltage REFT.

[0075] Similarly, after the input VINP of the level of "CML-VIN / 2" is provided to the capacitor 1240 in the sampling period between time t2 and t3, since the reference voltage REF1 is provided to the capacitor 1240 in the holding period between time t3 and t4, the capacitor 1240 may require as much additional charge as the charge amount "Cs×VT12" corresponding to the voltage difference "VT12 (=REFT-(CML-VIN / 2))". Therefore, in the sampling period between time t2 and t3, after the level of the reference voltage REF1 is maintained at the level of the main reference voltage REFT, in the holding period between time t3 and t4, the level of the reference voltage REF1 may change by the change amount VT22 compared to the level of the main reference voltage REFT, and may then be restored to the level of the main reference voltage REFT.

[0076] Figure 8 shows a diagram for describing the level of the reference voltage REF2 as the Figure 1 FIG. 1 is a graph showing changes in the level of the input VINP of the switched capacitor circuit 1000. FIG.

[0077] For example, after the input VINN of the level of "CML-VIN / 2" is provided to the capacitor 1440 in the sampling period between time t0 and t1, the capacitor 1440 may need additional charges as much as the charge amount "Cs×VB11" corresponding to the voltage difference "VB11 (=REFB-(CML-VIN / 2))" because the reference voltage REF2 is provided to the capacitor 1440 in the holding period between time t1 and t2. The additional charges may be supplied based on the reference voltage REF2.

[0078] In the sampling period between time t0 and t1, the level of reference voltage REF2 can be maintained at the level of main reference voltage REFB. However, in the holding period between time t1 and t2, since capacitor element 1440 requires additional charge, the level of reference voltage REF2 can change by a change amount VB21 compared to the level of main reference voltage REFB, and then can be restored to the level of main reference voltage REFB.

[0079] Similarly, after the input VINN of the level of "CML+VIN / 2" is provided to the capacitor 1440 in the sampling period between time t2 and t3, since the reference voltage REF2 is provided to the capacitor 1440 in the holding period between time t3 and t4, the capacitor 1440 may require as much additional charge as the charge amount "Cs×VB12" corresponding to the voltage difference "VB12 (=REFB-(CML+VIN / 2))". Therefore, in the sampling period between time t2 and t3, after the level of the reference voltage REF2 is maintained at the level of the main reference voltage REFB, in the holding period between time t3 and t4, the level of the reference voltage REF2 may change by the change amount VB22 compared to the level of the main reference voltage REFB, and may then be restored to the level of the main reference voltage REFB.

[0080] Reference Figure 7 and Figure 8 It can be understood that the reference voltages REF1 and REF2 vary with the inputs VINP and VINN, respectively. For example, with respect to the reference voltage REF1, Figure 7 , the change amount VT21 in the holding period between time t1 and t2 may be different from the change amount VT22 in the holding period between time t3 and t4. In addition, regarding the reference voltage REF2, the reference voltage Figure 8 , the change amount VB21 in the holding period between time t1 and t2 may be different from the change amount VB22 in the holding period between time t3 and t4.

[0081] That is, it is understood that the amount of change in the level of the reference voltages REF1 and REF2 varies according to the level of the inputs VINP and VINN (e.g., according to the data value to which the differential inputs VINP and VINN are intended). In this case, the amount of change in the level of the reference voltages REF1 and REF2 may not be accurately predicted, and the linearity of the operation of the switched capacitor circuit 1000 may be reduced. Therefore, it may be difficult to accurately control the operation of the switched capacitor circuit 1000.

[0082] Fig. 9 is a block diagram illustrating an example configuration of a switched capacitor circuit 2000 according to some example embodiments.

[0083] The switched capacitor circuit 2000 may include reference buffers 1110 and 1120, master sampler circuits 1200 and 1400, replica sampler circuits 2200 and 2400, a switch element 1305, an amplifier 1510, and capacitive elements 1512 and 1514. The switched capacitor circuit 2000 may be employed for the same or similar purpose or function as the switched capacitor circuit 1000.

[0084] Reference buffers 1110 and 1120, main sampler circuits 1200 and 1400, switch element 1305, amplifier 1510, and capacitor elements 1512 and 1514 may be constructed and may be connected to a reference Figures 1 to 8 For the sake of simplicity, repeated descriptions related to these components will be omitted below.

[0085] The replica sampler circuits 2200 and 2400 may be provided by replicating the construction of the master sampler circuits 1200 and 1400. However, as will be seen in reference Fig.10 and Fig.11 As described above, some constructions and operations of the replica sampler circuits 2200 and 2400 may differ from those of the main sampler circuits 1200 and 1400 .

[0086] Fig.10 It is shown Fig. 9 2000 is a circuit diagram of an example configuration of a switched capacitor circuit. For example, Fig.10 The configuration associated with the differential input VINP and the positive side input VINP of VINN is shown.

[0087] The replica sampler circuit 2200 of the switched capacitor circuit 2000 may include switch elements 2205, 2210, 2220, and 2230 and a capacitive element 2240. The capacitive element 2240 may have a capacitance value Cs. The capacitive element 2240 may receive a common mode voltage CML.

[0088] The replica sampler circuit 2200 may receive the input VINP in response to the sampling signal Psam. The sampling switch element 2205 may transfer the input VINP to the capacitive element 2240 in response to the sampling signal Psam. Therefore, the capacitive element 2240 may store the charge corresponding to the input VINP.

[0089] The selection switch element 2210 may provide the reference voltage REF1 to the capacitor element 2240 in response to the selection signal RDB, and the selection switch element 2220 may provide the reference voltage REF2 to the capacitor element 2240 in response to the selection signal RD. The replica sampler circuit 2200 may selectively provide the reference voltage REF1 or the reference voltage REF2 to the capacitor element 2240 in response to the complementary selection signals RDB and RD.

[0090] The replica sampler circuit 2200 may receive one selected from the reference voltages REF1 and REF2 in response to the hold signal Phold. The hold switch element 2230 may provide the capacitor element 2240 with one selected from the reference voltages REF1 and REF2 in response to the hold signal Phold.

[0091] When the hold signal Phold is received, the replica sampler circuit 2200 can hold the charge stored in the capacitive element 2240 based on one selected from the reference voltages REF1 and REF2. It can be understood that the replica sampler circuit 2200 holds the received input VINP based on the selected reference voltage. Here, holding the charge or input VINP can mean storing at least a portion of the charge supplied based on the input VINP in the capacitive element 2240.

[0092] The main sampler circuit 1200 and the replica sampler circuit 2200 may share the input VINP. The connection between the switch elements 2205, 2210, 2220, and 2230 and the capacitive element 2240 may be the same as the connection between the switch elements 1205, 1210, 1220, and 1230 and the capacitive element 1240. It appears as if the replica sampler circuit 2200 is provided by replicating the construction of the main sampler circuit 1200.

[0093] However, when the main sampler circuit 1200 receives the reference voltage REF1 in response to the selection signal RD, the replica sampler circuit 2200 may receive the reference voltage REF2 in response to the selection signal RD. On the other hand, when the main sampler circuit 1200 receives the reference voltage REF2 in response to the selection signal RDB, the replica sampler circuit 2200 may receive the reference voltage REF1 in response to the selection signal RDB.

[0094] According to the selection signals RD and RDB, a reference voltage of the reference voltages REF1 and REF2 provided to the main sampler circuit 1200 may be different from a reference voltage of the reference voltages REF1 and REF2 provided to the replica sampler circuit 2200. Therefore, a reference voltage received in the main sampler circuit 1200 in response to the hold signal Phold may be different from a reference voltage received in the replica sampler circuit 2200 in response to the hold signal Phold.

[0095] Meanwhile, replica sampler circuit 2200 may not be directly connected to amplifier 1510. Amplifier 1510 may use the charges stored in capacitive elements 1240 and 1440 to generate outputs VOUTP and VOUTN. However, amplifier 1510 may not use the output from replica sampler circuit 2200 (e.g., may not use the charges stored in capacitive element 2240).

[0096] Fig.11 It is shown Fig. 9 2000 is a circuit diagram of an example configuration of a switched capacitor circuit. For example, Fig.11 The configuration associated with differential inputs VINP and a negative side input VINN of VINN is shown.

[0097] The replica sampler circuit 2400 of the switched capacitor circuit 2000 may include switch elements 2405, 2410, 2420, and 2430 and a capacitive element 2440. The capacitive element 2440 may have a capacitance value Cs. The capacitive element 2440 may receive a common mode voltage CML.

[0098] The replica sampler circuit 2400 may receive the input VINN in response to the sampling signal Psam. The sampling switch element 2405 may transfer the input VINN to the capacitive element 2440 in response to the sampling signal Psam. Therefore, the capacitive element 2440 may store a charge corresponding to the input VINN.

[0099] The selection switch element 2420 may provide the reference voltage REF1 to the capacitor element 2440 in response to the selection signal RD, and the selection switch element 2410 may provide the reference voltage REF2 to the capacitor element 2440 in response to the selection signal RDB. The replica sampler circuit 2400 may selectively provide the reference voltage REF1 or the reference voltage REF2 to the capacitor element 2440 in response to the complementary selection signals RD and RDB.

[0100] The replica sampler circuit 2400 may receive one selected from the reference voltages REF1 and REF2 in response to the hold signal Phold. The hold switch element 2430 may provide the capacitor element 2440 with one selected from the reference voltages REF1 and REF2 in response to the hold signal Phold. When the hold signal Phold is received, the replica sampler circuit 2400 may hold the charge stored in the capacitor element 2440 based on one selected from the reference voltages REF1 and REF2. It is understood that the replica sampler circuit 2400 holds the received input VINN based on the selected reference voltage.

[0101] The main sampler circuit 1400 and the replica sampler circuit 2400 may share the input VINN. The connection between the switch elements 2405, 2410, 2420, and 2430 and the capacitive element 2440 may be the same as the connection between the switch elements 1405, 1410, 1420, and 1430 and the capacitive element 1440. It appears as if the replica sampler circuit 2400 is provided by replicating the construction of the main sampler circuit 1400.

[0102] However, according to the selection signals RD and RDB, the reference voltage of the reference voltages REF1 and REF2 provided to the main sampler circuit 1400 may be different from the reference voltage of the reference voltages REF1 and REF2 provided to the replica sampler circuit 2400. Therefore, the reference voltage received in the main sampler circuit 1400 in response to the hold signal Phold may be different from the reference voltage received in the replica sampler circuit 2400 in response to the hold signal Phold.

[0103] Meanwhile, the replica sampler circuit 2400 may not be directly connected to the amplifier 1510. The amplifier 1510 may not use the output from the replica sampler circuit 2400 (eg, may not use the charge stored in the capacitive element 2440).

[0104] Figure 12 to Figure 14 Is used to describe Figure 2 and Figure 3 The curve diagram in Fig.10 and Fig.11 1440, 2240, and 2240. The voltages provided to the capacitors 1240 and 1440 are referenced to Figures 4 to 6 To be described, and therefore, for the sake of simplicity, the description related to the capacitor elements 1240 and 1440 will be omitted below.

[0105] Fig.12The voltages provided to the capacitive elements 1240, 1440, 2240, and 2440 during the sampling period between time t0 and t1 are shown. Figure 2 , Figure 3 , Fig.10 and Fig.11 , in the sampling period between time t0 and t1, the input VINP of the level of "CML+VIN / 2" and the common mode voltage CML may be provided to the opposite ends of the capacitive element 2240. In addition, the input VINN of the level of "CML-VIN / 2" and the common mode voltage CML may be provided to the opposite ends of the capacitive element 2440. Therefore, the capacitive elements 2240 and 2440 may store charges in response to the levels of "CML+VIN / 2" and "CML-VIN / 2".

[0106] Fig.13 The voltages provided to the capacitor elements 1240, 1440, 2240, and 2440 during the holding period between time t1 and t2 and between time t3 and t4 are shown. Figure 2 , Figure 3 , Fig.10 and Fig.11 In the holding period, the reference voltages REF2 and REF1 may be respectively provided to the first terminals of the capacitors 2240 and 2440. Therefore, the charges stored in the capacitors 2240 and 2440 may be held in the capacitors 2240 and 2440 based on the reference voltages REF2 and REF1.

[0107] Reference Fig.13 , it can be understood that the voltage provided to the opposite end of capacitor element 1240 is equivalent to the voltage provided to the opposite end of capacitor element 2240. In addition, it can be understood that the voltage provided to the opposite end of capacitor element 1440 is equivalent to the voltage provided to the opposite end of capacitor element 2240. Here, "equivalent to" can mean that the two values ​​are the same or similar within an acceptable error range without being greatly different.

[0108] Fig.14 2 shows the voltages provided to the capacitive elements 1240, 1440, 2240, and 2440 during the sampling period between time t2 and t3. Figure 2 , Figure 3 , Fig.10 and Fig.11, in the sampling period between time t2 and t3, the input VINP of the level of "CML-VIN / 2" and the common mode voltage CML may be provided to the opposite ends of the capacitive element 2240. In addition, the input VINN of the level of "CML+VIN / 2" and the common mode voltage CML may be provided to the opposite ends of the capacitive element 2240. Therefore, the capacitive elements 2240 and 2440 may store charges in response to the levels of "CML-VIN / 2" and "CML+VIN / 2".

[0109] Fig.15 It is shown that the Fig. 9 2 is a block diagram of an example configuration for supplying charge using a reference voltage REF1 in a switched capacitor circuit 2000.

[0110] The master sampler circuit 1200 and the replica sampler circuit 2400 may receive different inputs VINP and VINN. In response to the sampling signal Psam, the inputs VINP and VINN may be delivered to the capacitive elements 1240 and 2440, respectively.

[0111] At the same time, the main sampler circuit 1200 and the replica sampler circuit 2400 can share the same reference voltage. For example, when receiving the selection signal RD, the main sampler circuit 1200 and the replica sampler circuit 2400 can share the reference voltage REF1. In response to the hold signal Phold, the reference voltage REF1 can be provided to each of the capacitive elements 1240 and 2440.

[0112] Fig.16 Shown is a diagram for describing Fig.15 FIG. 2 is a graph of an example change in the level of the reference voltage REF1 of the switched capacitor circuit 2000 in FIG.

[0113] For example, in the sampling period between time t0 and t1, an input VINP of a level of "CML+VIN / 2" may be provided to the capacitor element 1240, and an input VINN of a level of "CML-VIN / 2" may be provided to the capacitor element 2440. Then, in the holding period between time t1 and t2, the reference voltage REF1 may be provided to the capacitor elements 1240 and 2440.

[0114] In the holding period between time t1 and t2, the capacitor 1240 may require as much additional charge as the charge amount "Cs×VT11P" corresponding to the voltage difference "VT11P (=REFT-(CML+VIN / 2))", and the capacitor 2440 may require as much additional charge as the charge amount "Cs×VT11N" corresponding to the voltage difference "VT11N (=REFT-(CML-VIN / 2))". These additional charges may be supplied based on the reference voltage REF1. The total amount of additional charge to be supplied based on the reference voltage REF1 may be "Cs×(VT11P+VT11N)", i.e., "2×Cs×(REFT-CML)".

[0115] Meanwhile, in the sampling period between time t2 and t3, an input VINP of a level of "CML-VIN / 2" may be provided to the capacitor element 1240, and an input VINN of a level of "CML+VIN / 2" may be provided to the capacitor element 2440. Then, in the holding period between time t3 and t4, the reference voltage REF1 may be provided to the capacitor elements 1240 and 2440.

[0116] In the holding period between time t3 and t4, capacitor 1240 may require as much additional charge as the charge amount "Cs×VT12P" corresponding to voltage difference "VT12P (=REFT-(CML-VIN / 2))", and capacitor 2440 may require as much additional charge as the charge amount "Cs×VT12N" corresponding to voltage difference "VT12N (=REFT-(CML+VIN / 2))". These additional charges may be supplied based on reference voltage REF1. The total amount of additional charge to be supplied based on reference voltage REF1 may be "Cs×(VT12P+VT12N)", i.e., "2×Cs×(REFT-CML)".

[0117] and Figure 7 Unlike the example Fig.16 In the example of , the amount of additional charge required in the hold period between time t1 and t2 may be equal to the amount of additional charge required in the hold period between time t3 and t4. Therefore, the level of reference voltage REF1 may change by the same amount in the hold periods between time t1 and t2 and between time t3 and t4. For example, the level of reference voltage REF1 may change by a change amount VT20 compared to the level of main reference voltage REFT, and may then return to the level of main reference voltage REFT.

[0118] Fig.17 It is shown in Fig. 9 2000 is a block diagram of an example configuration for supplying charge based on a reference voltage REF2 in a switched capacitor circuit 2000 in FIG.

[0119] The master sampler circuit 1400 and the replica sampler circuit 2200 may receive different inputs VINN and VINP. In response to the sampling signal Psam, the inputs VINN and VINP may be delivered to the capacitive elements 1440 and 2240, respectively.

[0120] At the same time, the main sampler circuit 1400 and the replica sampler circuit 2200 can share the same reference voltage. For example, when receiving the selection signal RD, the main sampler circuit 1400 and the replica sampler circuit 2200 can share the reference voltage REF2. In response to the hold signal Phold, the reference voltage REF2 can be provided to each of the capacitive elements 1440 and 2240.

[0121] Fig.18 Shown is a diagram for describing Fig.17 FIG. 2 is a graph of an example change in the level of the reference voltage REF2 of the switched capacitor circuit 2000 in FIG.

[0122] For example, in the sampling period between time t0 and t1, an input VINN of a level of "CML-VIN / 2" may be provided to the capacitor 1440, and an input VINP of a level of "CML+VIN / 2" may be provided to the capacitor 2240. Then, in the holding period between time t1 and t2, the reference voltage REF2 may be provided to the capacitors 1440 and 2240.

[0123] In the holding period between time t1 and t2, capacitor 1440 may require as much additional charge as the charge amount "Cs×VB11N" corresponding to voltage difference "VB11N (=(CML-VIN / 2)-REFB)", and capacitor 2240 may require as much additional charge as the charge amount "Cs×VB11P" corresponding to voltage difference "VB11P (=(CML+VIN / 2)-REFB)". These additional charges may be supplied based on reference voltage REF2. The total amount of additional charge to be supplied based on reference voltage REF2 may be "Cs×(VB11P+VB11N)", i.e., "2×Cs×(CML-REFB)".

[0124] Meanwhile, in the sampling period between time t2 and t3, an input VINN of a level of "CML+VIN / 2" may be provided to the capacitor element 1440, and an input VINP of a level of "CML-VIN / 2" may be provided to the capacitor element 2240. Then, in the holding period between time t3 and t4, a reference voltage REF2 may be provided to the capacitor elements 1440 and 2240.

[0125] In the holding period between time t3 and t4, capacitor 1440 may require as much additional charge as the charge amount "Cs×VB12N" corresponding to voltage difference "VB12N (=(CML+VIN / 2)-REFB)", and capacitor 2240 may require as much additional charge as the charge amount "Cs×VB12P" corresponding to voltage difference "VB12P (=(CML-VIN / 2)-REFB)". These additional charges may be supplied based on reference voltage REF2. The total amount of additional charge to be supplied based on reference voltage REF2 may be "Cs×(VB12P+VB12N)", i.e., "2×Cs×(CML-REFB)".

[0126] and Figure 8 Unlike the example Fig.18 In the example of , the amount of additional charge required in the hold period between time t1 and t2 may be equal to the amount of additional charge required in the hold period between time t3 and t4. Therefore, the level of reference voltage REF2 may change by the same amount in the hold periods between time t1 and t2 and between time t3 and t4. For example, the level of reference voltage REF2 may change by a change amount VB20 compared to the level of main reference voltage REFB, and may then return to the level of main reference voltage REFB.

[0127] Reference Fig.16 and Fig.18 , the sum of the voltage differences “VT11P” and “VT11N” may be substantially equal to the sum of the voltage differences “VB11P” and “VB11N”. In addition, the sum of the voltage differences “VT12P” and “VT12N” may be substantially equal to the sum of the voltage differences “VB12P” and “VB12N”. In this regard, the amount of charge supplied to the main sampler circuit 1200 and the replica sampler circuit 2400 based on the reference voltage REF1 may be equivalent to the amount of charge supplied to the main sampler circuit 1400 and the replica sampler circuit 2200 based on the reference voltage REF2.

[0128] Reference Fig.16 , the sum of the voltage differences "VT11P" and "VT11N" can be substantially equal to the sum of the voltage differences "VT12P" and "VT12N". In this regard, regardless of the levels of the inputs VINP and VINN (e.g., regardless of the data values ​​to which the differential inputs VINP and VINN are intended), the amount of charge supplied to the main sampler circuit 1200 and the replica sampler circuit 2400 based on the reference voltage REF1 can remain stable. Herein, "stable" can mean that the value remains approximately at the same level without large changes within an acceptable error range.

[0129] Reference Fig.18, the sum of the voltage differences "VB11P" and "VB11N" may be substantially equal to the sum of the voltage differences "VB12P" and "VB12N". In this regard, the amount of charge supplied to the main sampler circuit 1400 and the replica sampler circuit 2200 based on the reference voltage REF2 may remain stable regardless of the levels of the inputs VINP and VINN.

[0130] Reference Fig.16 and Fig.18 , the sum of the voltage differences “VT11P” and “VB11P” may be substantially equal to the sum of the voltage differences “VB11N” and “VT11N”. In addition, the sum of the voltage differences “VT12P” and “VB12P” may be substantially equal to the sum of the voltage differences “VB12N” and “VT12N”. In this regard, the amount of charge supplied to the main sampler circuit 1200 based on the reference voltage REF1 and to the replica sampler circuit 2200 based on the reference voltage REF2 may be equivalent to the amount of charge supplied to the main sampler circuit 1400 based on the reference voltage REF2 and to the replica sampler circuit 2400 based on the reference voltage REF1.

[0131] Reference Fig.16 and Fig.18 , the sum of the voltage differences "VT11P" and "VB11P" may be substantially equal to the sum of the voltage differences "VT12P" and "VB12P". In this regard, the amount of charge supplied to the main sampler circuit 1200 based on the reference voltage REF1 and to the replica sampler circuit 2200 based on the reference voltage REF2 may remain stable regardless of the levels of the inputs VINP and VINN.

[0132] Reference Fig.16 and Fig.18 , the sum of the voltage differences "VB11N" and "VT11N" may be substantially equal to the sum of the voltage differences "VB12N" and "VT12N". In this regard, the amount of charge supplied to the main sampler circuit 1400 based on the reference voltage REF2 and to the replica sampler circuit 2400 based on the reference voltage REF1 may remain stable regardless of the levels of the inputs VINP and VINN.

[0133] Reference Fig.16 , while the reference voltage REF1 is supplied to the main sampler circuit 1200 and the replica sampler circuit 2400, the level of the reference voltage REF1 may be changed from the level of the main reference voltage REFT to another level, and then may be restored to the level of the main reference voltage VREFT. However, regardless of the levels of the inputs VINP and VINN, the amount of change VT20 of the level of the reference voltage REF1 may remain stable.

[0134] Reference Fig.18, while the reference voltage REF2 is supplied to the main sampler circuit 1400 and the replica sampler circuit 2200, the level of the reference voltage REF2 may be changed from the level of the main reference voltage REFB to another level, and then may be restored to the level of the main reference voltage VREFB. However, regardless of the levels of the inputs VINP and VINN, the amount of change VB20 in the level of the reference voltage REF2 may remain stable.

[0135] According to reference Figures 9 to 18 In the example embodiment described above, the amount of change in the level of reference voltages REF1 and REF2 can be predictable, and the linearity and accuracy of the operation of switched capacitor circuit 2000 can be improved compared to switched capacitor circuit 1000. In some examples, switched capacitor circuit 1000 can be implemented to include capacitors of relatively large capacitance connected to the output terminals of reference buffers 1110 and 1120 for improved linearity. However, these capacitors can result in an increase in circuit area and implementation cost. Compared to the above example implementations, reference capacitor circuit 1000 can be implemented to include capacitors of relatively large capacitance connected to the output terminals of reference buffers 1110 and 1120 for improved linearity. However, these capacitors can result in an increase in circuit area and implementation cost. Figures 9 to 18 The described example embodiments can be implemented in a small circuit area and at low cost.

[0136] Fig.19 is a block diagram illustrating an example configuration of a switched capacitor circuit 3000 according to some example embodiments.

[0137] The switched capacitor circuit 3000 may include reference buffers 1110 and 1120, charge supply circuits 3110 and 3120, master sampler circuits 1200 and 1400, replica sampler circuits 2200 and 2400, a switch element 1305, an amplifier 1510, and capacitive elements 1512 and 1514. The switched capacitor circuit 3000 may be employed for the same or similar purpose or function as that of the switched capacitor circuit 1000.

[0138] The construction and operation of the reference buffers 1110 and 1120, the main sampler circuits 1200 and 1400, the replica sampler circuits 2200 and 2400, the switch element 1305, the amplifier 1510, and the capacitor elements 1512 and 1514 may be similar to those of the reference buffers 1110 and 1120. Figures 1 to 18 For the sake of simplicity, repeated descriptions related to these components will be omitted below.

[0139] As reference Fig.16 and Fig.18As described, the capacitive elements 1240, 1440, 2240, and 2440 may require additional charge in response to the transition from the sampling period to the holding period. Due to the use of the replica sampler circuits 2200 and 2400, the amount of charge required in the switch capacitor circuit 2000 may become greater than the amount of charge required in the switch capacitor circuit 1000. That is, the amount of additional charge supplied based on the reference voltages REF1 and REF2 may increase, and this may result in an increase in the power consumption of the reference buffers 1110 and 1120.

[0140] If you will refer to Figures 20 to 27 As described above, charge supply circuits 3110 and 3120 may be employed to supply additional charge for reference voltages REF1 and REF2, i.e., additional charge required in capacitive elements 1240, 1440, 2240, and 2440. Charge supply circuit 3110 may provide reference voltage REF1 based on charge supply voltage VR or based on a buffered reference voltage from reference buffer 1110. Charge supply circuit 3120 may provide reference voltage REF2 based on charge supply voltage VR or based on a buffered reference voltage from reference buffer 1120. Charge supply voltage VR may be received from a voltage source such as a bandgap reference circuit, a PMIC, a voltage regulator, and the like.

[0141] Fig. 20 It is shown Fig.19 3000 is a circuit diagram of an example configuration of a switched capacitor circuit. For example, Fig. 20 A charge supply circuit 3110 is shown connected to the reference buffer 1110 to provide a reference voltage REF1.

[0142] The charge supply circuit 3110 may include switch elements 3111, 3113, and 3114 and a capacitor element 3112. The charge accumulation switch element 3111 may provide a charge supply voltage VR to the capacitor element 3112 in response to a sampling signal Psam. Therefore, the capacitor element 3112 may store charge based on the charge supply voltage VR in response to the sampling signal Psam. The capacitor element 3112 may have a capacitance value Ca.

[0143] For the reference voltage REF1, the charge supply switch element 3113 may transfer the charge stored in the capacitor element 3112 in response to the sub-hold signal Phold1. For the reference voltage REF1, the voltage stabilization switch element 3114 may provide the buffered reference voltage from the reference buffer 1110 in response to the sub-hold signal Phold2. The sub-hold signals Phold1 and Phold2 may be received from a separate clock generation circuit or a separate control circuit.

[0144] Therefore, the charge supply circuit 3110 can provide the reference voltage REF1 based on the charge stored in the capacitive element 3112 in response to the sub-hold signal Phold1. In addition, the charge supply circuit 3110 can provide the buffered reference voltage from the reference buffer 1110 as the reference voltage REF1 in response to the sub-hold signal Phold2. The reference voltage REF1 can be selectively provided based on the buffered reference voltage from the reference buffer 1110 or the charge stored in the capacitive element 3112.

[0145] Fig.21 It is used to describe the control Fig. 20 Graphs of example signals Psam, Phold, Phold1 and Phold2 of switches in FIG.

[0146] The time period between time t11 and t12 may be a sampling period in which the sampling signal Psam may have a logic "1" level and the holding signal Phold may have a logic "0" level. The time period between time t12 and t14 may be a holding period in which the sampling signal Psam may have a logic "0" level and the holding signal Phold may have a logic "1" level.

[0147] The holding period may include a time period between time t12 and t13 and a time period between time t13 and t14. The time period between time t12 and t13 may provide a charge supply phase. The time period between time t13 and t14 may provide a voltage stabilization phase. The time period of the voltage stabilization phase may be after the time period of the charge supply phase. The time period of the voltage stabilization phase may not overlap with the time period of the charge supply phase.

[0148] In the charge supply phase, the sub-hold signal Phold1 may have a logic "1" level, and the sub-hold signal Phold2 may have a logic "0" level. In the voltage stabilization phase, the sub-hold signal Phold1 may have a logic "0" level, and the sub-hold signal Phold2 may have a logic "1" level. In the sampling period, the sub-hold signals Phold1 and Phold2 may have a logic "0" level.

[0149] For example, the logic "1" level of the sub-hold signals Phold1 and Phold2 can be understood as the sub-hold signals Phold1 and Phold2 being received. On the other hand, the logic "0" level of the sub-hold signals Phold1 and Phold2 can be understood as the sub-hold signals Phold1 and Phold2 not being received. In this regard, it can be understood that the sampling signal Psam, the sub-hold signal Phold1, and the sub-hold signal Phold2 can be received continuously and sequentially.

[0150] Figure 22 to Figure 24 Is used to describe Fig. 20 The charge supply circuit 3110 in Fig.21 A conceptual diagram of the operation of example signals Psam, Phold, Phold1, and Phold2.

[0151] Fig. 22 The operation of the charge supply circuit 3110 in a sampling period provided in response to the sampling signal Psam is shown. During the sampling period, while the main sampler circuits 1200 and 1400 and the replica sampler circuits 2200 and 2400 receive inputs VINP and VINN, the capacitive element 3112 can store charge based on the charge supply voltage VR. At the same time, since the hold signal Phold is not received, the connection with the capacitive elements 1240 and 2440 can float (e.g., disconnected).

[0152] Fig.23 The operation of the charge supply circuit 3110 is shown in a period of a charge supply phase provided in response to the sub-hold signal Phold1. While the sub-hold signal Phold1 is received, the sampling signal Psam may not be received and the hold signal Phold may be received.

[0153] In the charge supply phase, the charge supply circuit 3110 can provide a reference voltage REF1 based on the charge stored in the capacitor 3112. Fig.16 and Fig.18 As described, reference voltage REF1 may be provided to supply additional charge required by capacitors 1240 and 2440. When charge supply circuit 3110 is used, additional charge may be supplied based on the charge stored in capacitor 3112 instead of from reference buffer 1110.

[0154] Fig.24 The operation of the charge supply circuit 3110 in a period of a voltage stabilization phase provided in response to the sub-hold signal Phold2 is shown. While the sub-hold signal Phold2 is received, the sampling signal Psam may not be received and the hold signal Phold may be received.

[0155] In the voltage stabilization phase, the charge supply circuit 3110 may provide the buffered reference voltage from the reference buffer 1110 as the reference voltage REF1. Therefore, the level of the reference voltage REF1 may be stabilized to the level of the main reference voltage REFT.

[0156] In some example embodiments, it may be determined that the voltage level of the charge supply voltage VR and / or the capacitance value Ca of the capacitive element 3112 is sufficient to fully supply the additional charge required by the capacitive elements 1240 and 2440, referring to Fig.25 and Fig.26 To describe this point. In this example embodiment, the reference buffer 1110 may not output the charge for the reference voltage REF1. That is, while the charge supply circuit 3110 provides the buffered reference voltage from the reference buffer 1110 as the reference voltage REF1, the amount of charge transferred from the reference buffer 1110 to the capacitive elements 1240 and 2440 may be zero (0).

[0157] When the reference buffer 1110 does not supply the charge to the capacitive elements 1240 and 2440, the reference buffer 1110 consumes almost no power. Even if the capacitive element 3112 does not completely supply the additional charge due to the insufficient capacitance Ca of the capacitive element 3112, the power consumption of the reference buffer 1110 can be significantly reduced. Therefore, when the charge supply circuit 3110 is adopted to supply the additional charge, the power consumption of the switched capacitor circuit 3000 can be reduced.

[0158] Reference Fig.23 , the additional charge required by the capacitors 1240 and 2440 can be provided from the charge stored in the capacitor 3112. That is, the additional charge can be transferred by charge sharing between the capacitors 1240 and 2440 and the capacitor 3112. Therefore, the additional charge can be supplied in a relatively short time, and the level of the reference voltage REF1 can be quickly stabilized.

[0159] In addition, refer to Fig.24 , there may be no or may be minimized the charge additionally transferred from the reference buffer 1110 to the capacitive elements 1240 and 2440. As a result, the switched capacitor circuit 3000 may be operated quickly and may be usefully employed in high-speed systems.

[0160] Refer to Figure 21 to Figure 24 , when the length of the time period of the charge supply phase becomes longer, the charge supply circuit 3110 can supply a larger amount of additional charge. Therefore, the power consumption of the switched capacitor circuit 3000 can be further reduced. On the other hand, when the length of the time period of the voltage stabilization phase becomes longer, the level of the reference voltage REF1 can be stabilized quickly and smoothly. In this regard, the power consumption and stability can be considered to appropriately determine the lengths of the time periods of the charge supply phase and the voltage stabilization phase.

[0161] Fig.25 and Fig.26 is used to describe the determination of the capacitance value Ca of the capacitor element 3112 or Fig. 20 A conceptual diagram of an example method of adjusting the level of the charge supply voltage VR in FIG.

[0162] Fig.25 The voltages provided to the capacitive elements 1240, 2440, and 3112 during the sampling period are shown. During the sampling period, the capacitive elements 1240 and 2440 can receive inputs VINP and VINN, respectively, and the capacitive element 3112 can receive the charge supply voltage VR. The total amount of charge "Qsam" stored in the capacitive elements 1240, 2440, and 3112 during the sampling period can be described by the following equation 1.

[0163] [Equation 1]

[0164] Qsam=Ca×VR+Cs×(VINP+VINN)=Ca×VR+2×Cs×CML

[0165] Fig.26 1 shows the voltage provided to the capacitive elements 1240, 2440 and 3112 in the charge supply phase. In the charge supply phase, the capacitive elements 1240, 2440 and 3112 can receive the reference voltage REF1. The reference voltage REF1 can be driven to have the level of the main reference voltage REFT. The total amount of charge "Qhold1" stored in the capacitive elements 1240, 2440 and 3112 in the charge supply phase can be described by the following equation 2.

[0166] [Equation 2]

[0167] Qhold1=(Ca+2×Cs)×REFT

[0168] In response to the transition from the sampling period to the charge supply phase, the charges stored in the capacitive elements 1240, 2440, and 3112 may be redistributed. Considering the charge redistribution, it can be understood that the charge amount "Qsam" is equal to the charge amount "Qhold1". ​​Therefore, the level of the charge supply voltage VR may be determined according to the following equation 3.

[0169] [Equation 3]

[0170]

[0171] For example, when the switched capacitor circuit 3000 is designed so that the capacitance value Ca of the capacitor element 3112 is four times the capacitance value Cs of each of the capacitor elements 1240 and 2440 (ie, Ca=4×Cs), the level of the charge supply voltage VR can be determined according to the following equation 4.

[0172] [Equation 4]

[0173]

[0174] In this example, the voltage source for providing the charge supply voltage VR may be configured to output a voltage having a level determined according to the above Equation 4. However, in other examples, when the relationship between the capacitance value Ca and the capacitance value Cs changes, the level of the charge supply voltage VR may be determined in a manner different from the above Equation 4.

[0175] The above description provides an example method for determining the level of the charge supply voltage VR. Similarly, the above example method can be changed or modified to determine the capacitance value Ca of the capacitive element 3112. For example, the above equation 3 can be converted to describe the capacitance value Ca, and the capacitance value Ca can be determined based on the relationship between the levels of the charge supply voltage VR, the main reference voltage REFT, and the common mode voltage CML. The process can be easily understood by calculation of elementary algebra, and therefore a detailed description thereof will be omitted below.

[0176] Fig. 27 It is shown Fig.19 3000 is a circuit diagram of an example configuration of a switched capacitor circuit. For example, Fig. 27 A charge supply circuit 3120 is shown connected to the reference buffer 1120 to provide a reference voltage REF2.

[0177] The charge supply circuit 3120 may include switch elements 3121, 3123, and 3124 and a capacitor element 3122. In the sampling period, the charge accumulation switch element 3121 may provide the charge supply voltage VR to the capacitor element 3122 in response to the sampling signal Psam. Therefore, the capacitor element 3122 may store charge based on the charge supply voltage VR in response to the sampling signal Psam. The capacitor element 3122 may have a capacitance value Ca.

[0178] In the charge supply phase, for the reference voltage REF2, the charge supply switch element 3123 may transfer the charge stored in the capacitor element 3122 in response to the sub-hold signal Phold1. The charge supply circuit 3120 may provide the reference voltage REF2 based on the charge stored in the capacitor element 3122 in response to the sub-hold signal Phold1. The additional charge required by the capacitor elements 1440 and 2240 may be supplied based on the charge stored in the capacitor element 3122, rather than being supplied from the reference buffer 1120.

[0179] In the voltage stabilization phase, for the reference voltage REF2, the voltage stabilization switch element 3124 may provide a buffered reference voltage from the reference buffer 1120 in response to the sub-hold signal Phold2. The charge supply circuit 3120 may provide a buffered reference voltage from the reference buffer 1120 as the reference voltage REF2 in response to the sub-hold signal Phold2. The reference buffer 1120 may not output a charge for the reference voltage REF2, and the amount of charge transferred from the reference buffer 1120 to the capacitive elements 1440 and 2240 may be zero or may be minimized.

[0180] The reference voltage REF2 may be selectively provided based on a buffered reference voltage from the reference buffer 1120 or a charge stored in the capacitive element 3122. Figure 20 to Figure 26 The configuration, operation, and method described above are substantially identical or similarly applied to the charge supply circuit 3120. Therefore, the detailed description will be omitted below.

[0181] As a conventional practice in the field of the present invention, embodiments can be described and illustrated according to the blocks that perform the one or more functions. These blocks, which may be referred to herein as units or modules, are physically implemented by analog and / or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc., and may be optionally driven by firmware and / or software. For example, the circuit may be implemented in one or more semiconductor chips, or implemented on substrate supports such as printed circuit boards. The circuit constituting the block may be implemented by dedicated hardware or by a processor (e.g., one or more programmable microprocessors and associated circuits), or by a combination of dedicated hardware for performing some functions of the block and a processor for performing other functions of the block. The various blocks of the embodiments may be physically divided into two or more interacting and discrete blocks without departing from the scope of the present disclosure. Similarly, the blocks of the embodiments may be physically combined into more complex blocks without departing from the scope of the present disclosure.

[0182] The above description is intended to provide example configurations and operations for implementing the present disclosure. In addition to the above example embodiments, the scope and spirit of the present disclosure may include implementations obtained by simply changing or modifying the above example embodiments. In addition, the scope and spirit of the present disclosure include implementations achieved by easily changing or modifying the above example embodiments afterwards.

Claims

1. A switched capacitor circuit, include: a first master sampler circuit that samples a first input of the differential inputs and generates a first output corresponding to the sampled first input based on a first reference voltage; a second master sampler circuit that samples a second input of the differential input and generates a second output corresponding to the sampled second input based on a second reference voltage different from the first reference voltage; a first replica sampler circuit that receives the first input and holds the received first input based on the second reference voltage; as well as A second replica sampler circuit receives the second input and holds the received second input based on the first reference voltage.

2. The switched capacitor circuit according to claim 1, in, The amount of charge supplied to the first main sampler circuit and the second replica sampler circuit based on the first reference voltage is equivalent to the amount of charge supplied to the second main sampler circuit and the first replica sampler circuit based on the second reference voltage.

3. The switched capacitor circuit according to claim 1, in, Regardless of the levels of the first input and the second input, the amount of charge supplied to the first main sampler circuit and the second replica sampler circuit based on the first reference voltage remains stable.

4. The switched capacitor circuit according to claim 1, in: While the first reference voltage is supplied to the first main sampler circuit and the second replica sampler circuit, a level of the first reference voltage is changed and then restored, and Regardless of the levels of the first input and the second input, the amount of change in the level of the first reference voltage remains stable.

5. The switched capacitor circuit according to claim 1, in, The amount of charge supplied to the first main sampler circuit based on the first reference voltage and to the first replica sampler circuit based on the second reference voltage is equivalent to the amount of charge supplied to the second main sampler circuit based on the second reference voltage and to the second replica sampler circuit based on the first reference voltage. 6 . The switched capacitor circuit of claim 1 , further comprising an amplifier that generates a differential output based on the first output and the second output without using outputs from the first replica sampler circuit and the second replica sampler circuit.

7. The switched capacitor circuit according to claim 1, in: The first master sampler circuit and the second master sampler circuit respectively sample the first input and the second input in response to a sampling signal, and respectively receive the first reference voltage and the second reference voltage in response to a holding signal, The first replica sampler circuit and the second replica sampler circuit receive the first input and the second input, respectively, in response to the sampling signal, and receive the second reference voltage and the first reference voltage, respectively, in response to the holding signal, and The sampling signal and the holding signal are received continuously and alternately.

8. The switched capacitor circuit according to claim 7, further comprising: include: a reference buffer that buffers a main reference voltage to output a buffered reference voltage; as well as A charge supply circuit provides the first reference voltage based on a charge supply voltage or based on the buffered reference voltage.

9. The switched capacitor circuit according to claim 8, in: The charge supply circuit includes a capacitive element that stores charge based on the charge supply voltage in response to the sampling signal, and The charge supply circuit: providing the first reference voltage based on the charge stored in the capacitive element in response to a first sub-hold signal, and In response to a second sub-hold signal, the buffered reference voltage is provided as the first reference voltage.

10. The switched capacitor circuit according to claim 9, in: The first time period in which the hold signal is received includes a second time period in which the first sub-hold signal is received and a third time period in which the second sub-hold signal is received, and The third time period is after the second time period.

11. The switched capacitor circuit according to claim 9, in, The sampling signal, the first sub-hold signal, and the second sub-hold signal are received continuously and sequentially.

12. The switched capacitor circuit according to claim 9, in, While the charge supply circuit provides the buffered reference voltage as the first reference voltage, the reference buffer does not output charge.

13. A switched capacitor circuit, include: a main sampler circuit comprising: a first capacitive element storing a charge corresponding to one input of a differential input; a first sampling switch element transferring the one input to the first capacitive element; and a first holding switch element providing a first reference voltage to the first capacitive element; a replica sampler circuit comprising: a second capacitive element storing a charge corresponding to the one input; a second sampling switch element transferring the one input to the second capacitive element; and a second holding switch element providing the second capacitive element with a second reference voltage different from the first reference voltage; and An amplifier generates an output based on the charge stored in the first capacitive element.

14. The switched capacitor circuit according to claim 13, in, The amplifier does not use the charge stored in the second capacitive element.

15. The switched capacitor circuit according to claim 13, in, The connection between the second capacitive element, the second sampling switch element, and the second holding switch element is the same as the connection between the first capacitive element, the first sampling switch element, and the first holding switch element.

16. The switched capacitor circuit according to claim 13, in, Regardless of the level of the one input, the amount of charge supplied to the main sampler circuit based on the first reference voltage and to the replica sampler circuit based on the second reference voltage remains stable.

17. A switched capacitor circuit, include: a primary sampler circuit comprising a first capacitive element storing a charge corresponding to a first input of a differential input, wherein the primary sampler circuit generates an output corresponding to the charge stored in the first capacitive element based on a reference voltage; and a replica sampler circuit comprising a second capacitive element storing a charge corresponding to a second input of the differential input, wherein the replica sampler circuit maintains the charge stored in the second capacitive element based on the reference voltage, wherein Regardless of the levels of the first input and the second input, the amount of charge supplied to the main sampler circuit and the replica sampler circuit based on the reference voltage remains stable.

18. The switched capacitor circuit according to claim 17, in, While the main sampler circuit generates the output and the replica sampler circuit holds the charge stored in the second capacitive element, voltages supplied to opposite ends of the first capacitive element are equivalent to voltages supplied to opposite ends of the second capacitive element.

19. The switched capacitor circuit of claim 17, further comprising: include: a reference buffer that buffers a main reference voltage to output a buffered reference voltage; as well as a charge supply circuit including a third capacitive element storing charge based on a charge supply voltage while the master sampler circuit and the replica sampler circuit receive the first input and the second input, respectively, wherein The reference voltage is selectively provided based on the buffered reference voltage or the charge stored in the third capacitive element.

20. The switched capacitor circuit of claim 19, in, The charge supply circuit: providing the reference voltage in a first period of time based on the charge stored in the third capacitive element, and The buffered reference voltage is provided as the reference voltage in a second time period, wherein The second time period is after the first time period and does not overlap with the first time period.

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