Semiconductor device including self-aligned contacts and method of manufacturing the same

Abstract

A semiconductor device with improved product reliability and a method for manufacturing the same are provided. The semiconductor device comprises: a substrate; a gate electrode on the substrate; a first spacer on a sidewall of the gate electrode; a conductive contact on a sidewall of the first spacer, the conductive contact protruding beyond a top surface of the gate electrode; a trench defined by a top surface of the gate electrode, a top surface of the first spacer, and a sidewall of the conductive contact; an etch stop layer extending along at least a portion of the sidewall of the trench and a bottom surface of the trench; and a capping pattern on the etch stop layer and filling the trench, wherein the capping pattern comprises silicon oxide or a low-k material having a dielectric constant lower than that of silicon oxide.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0033286, filed on March 22, 2018, the disclosure of which is hereby incorporated by reference into this application in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a self-aligned contact (SAC) and a method for manufacturing the same. Background Art

[0004] A self-aligned contact (SAC) process is used to form contact holes of semiconductor devices.

[0005] However, with the high integration of semiconductor devices, short circuits are very likely to occur during the SAC process due to lack of selectivity between films. For example, during the formation of contact holes for forming source / drain contacts of transistors using the SAC process, short circuits may occur between the gate and the source / drain contacts due to lack of selectivity between films. Summary of the invention

[0006] Exemplary embodiments of the present disclosure provide a semiconductor device capable of preventing a short circuit between a gate and a contact, thereby improving product reliability.

[0007] Exemplary embodiments of the present disclosure also provide a method of manufacturing a semiconductor device capable of preventing a short circuit between a gate and a contact, thereby improving product reliability.

[0008] However, the exemplary embodiments of the present disclosure are not limited to those described herein. For those skilled in the art to which the present disclosure pertains, the above and other exemplary embodiments of the present disclosure will become more apparent by referring to the detailed description of the present disclosure given below.

[0009] According to certain exemplary embodiments of the present disclosure, a semiconductor device includes: a substrate; a gate electrode located on the substrate; a first spacer located on the sidewall of the gate electrode; a conductive contact located on the sidewall of the first spacer, the conductive contact protruding beyond the top surface of the gate electrode; a groove defined by the top surface of the gate electrode, the top surface of the first spacer and the sidewall of the conductive contact; an etch stop layer extending along at least a portion of the sidewall of the groove and the bottom surface of the groove; and a covering pattern located on the etch stop layer and filling the groove, wherein the covering pattern includes silicon oxide or a low-k material having a dielectric constant lower than that of silicon oxide.

[0010] According to the above and other exemplary embodiments of the present disclosure, a semiconductor device includes: a substrate; an interlayer insulating film formed on the substrate and including a groove, the groove having a lower portion and an upper portion; a gate electrode filling the lower portion of the groove; an etch stop layer extending along at least a first side wall of the upper portion of the groove and a top surface of the gate electrode; a covering pattern formed on the etch stop layer and filling the upper portion of the groove; and a conductive contact formed on the sidewall of the gate electrode and the sidewall of the covering pattern, the conductive contact penetrating the interlayer insulating film, wherein the etch stop layer extends at least partially along a portion of the sidewall of the conductive contact, and the covering pattern includes silicon oxide or a low-k material having a dielectric constant lower than that of silicon oxide.

[0011] According to the foregoing and other exemplary embodiments of the present disclosure, a semiconductor device includes: a substrate; a gate electrode located on the substrate; a gate spacer located on the sidewall of the gate electrode; a covering pattern covering the top surface of the gate electrode and the top surface of the gate spacer; an interlayer insulating film formed on the substrate and adjacent to the gate spacer and the covering pattern; and a conductive contact penetrating the interlayer insulating film and defined by the sidewall of the gate spacer and the sidewall of the covering pattern. The covering pattern and the interlayer insulating film include substantially the same material; and the sidewall of the covering pattern adjacent to the conductive contact includes a first sidewall portion and a second sidewall portion, the second sidewall portion is formed above the first sidewall portion, and the slope of the second sidewall portion is smaller than the slope of the first sidewall portion.

[0012] According to the above and other exemplary embodiments of the present disclosure, a method for manufacturing a semiconductor device includes: forming a gate electrode on a substrate; forming an interlayer insulating film surrounding the gate electrode; forming a first groove defined by the sidewalls of the interlayer insulating film and the top surface of the gate electrode by recessing the upper portion of the gate electrode; forming a mask pattern filling the first groove, the mask pattern including a semiconductor material; forming a conductive contact penetrating the interlayer insulating film on the sidewalls of the gate electrode and the sidewalls of the mask pattern; and replacing the mask pattern with a covering pattern.

[0013] Other features and exemplary embodiments may be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other exemplary embodiments and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0015] Figure 1 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure.

[0016] Figure 2 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure.

[0017] Figure 3 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure.

[0018] Figure 4 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure.

[0019] Figure 5 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure.

[0020] Figure 6 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure.

[0021] Figure 7 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure.

[0022] Figure 8 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure.

[0023] Fig. 9 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure.

[0024] Fig.10 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure.

[0025] Fig.11 is a perspective view of a semiconductor device according to some exemplary embodiments of the present disclosure.

[0026] Fig.12 is along Fig.11 A cross-sectional view taken along line AA'.

[0027] Fig.13 is along Fig.11 A cross-sectional view taken along line BB'.

[0028] Fig.14 is a perspective view of a semiconductor device according to some exemplary embodiments of the present disclosure.

[0029] Fig.15 is along Fig.14 A cross-sectional view taken along line CC'.

[0030] Fig.16 is along Fig.14 A cross-sectional view taken along line D-D'.

[0031] Figures 17 to 28B are cross-sectional views illustrating intermediate steps of a method of fabricating a semiconductor device according to some exemplary embodiments of the present disclosure.

[0032] Figure 29 to Figure 31 are cross-sectional views illustrating intermediate steps of a method of fabricating a semiconductor device according to some exemplary embodiments of the present disclosure.

[0033] Figures 32 to 44 are cross-sectional views illustrating intermediate steps of a method of fabricating a semiconductor device according to some exemplary embodiments of the present disclosure. DETAILED DESCRIPTION

[0034] The following will refer to Figures 1 to 16 Semiconductor devices according to some exemplary embodiments of the present disclosure are described.

[0035] Figure 1 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure.

[0036] Reference Figure 1 , a semiconductor device according to some exemplary embodiments of the present disclosure includes a substrate 100 , a gate insulating film 122 , a gate electrode 124 , a gate spacer 126 , an etch stop layer 130 , a capping pattern 140 , a first interlayer insulating film 150 , and a contact 160 .

[0037] The substrate 100 may include, for example, bulk silicon or silicon on insulator (SOI). The substrate 100 may be a silicon substrate, or may include another material such as, for example, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate 100 may be a base substrate on which an epitaxial layer is formed.

[0038] The first interlayer insulating film 150 may be formed on the substrate 100. The first interlayer insulating film 150 may surround the gate electrode 124 and the capping pattern 140. For example, the first interlayer insulating film 150 may include a trench T, and the gate electrode 124 and the capping pattern 140 may be formed in the trench T.

[0039] The first interlayer insulating film 150 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide. The low-k material may include, for example, flowable oxide (FOX), torene silazene (TOSZ), undoped silicate glass (USG), borosilica glass (BSG), phosphosilica glass (PSG), borophosphosilica glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), carbon-doped silicon oxide (CDO), dry gel, aerogel, fluorinated amorphous carbon, organic silicate glass (OSG), parylene, bis-benzocyclobutenes (BCB), SiLK, polyimide, porous polymer material, and at least one of a combination thereof, but the present disclosure is not limited thereto.

[0040] The gate spacer 126 may be formed on the substrate 100 and the first interlayer insulating film 150. For example, the gate spacer 126 may be formed along the sidewall of the first interlayer insulating film 150 on the substrate 100. The gate spacer 126 may define a trench T.

[0041] In some exemplary embodiments, the top surface of the gate spacer 126 may be lower than the top surface of the first interlayer insulating film 150. Therefore, the gate spacer 126 may define a trench T, and the trench T includes a lower portion TL and an upper portion TU. For example, the lower portion TL of the trench T may be defined by the top surface of the substrate 100 and the sidewall of the gate spacer 126. For example, the upper portion TU of the trench T may be defined by the top surface of the gate electrode 124, the top surface of the gate insulating film 122, the top surface of the gate spacer 126, and the sidewall of the first interlayer insulating film 150.

[0042] The gate spacer 126 is shown as a single-layer film, but the present disclosure is not limited thereto. For example, alternatively, the gate spacer 126 may be a multi-layer film.

[0043] The gate spacer 126 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), and at least one of a combination thereof.

[0044] The gate insulating film 122 may be interposed between the substrate 100 and the gate electrode 124. The gate insulating film 122 may be formed in the lower portion TL of the trench T. For example, the gate insulating film 122 may extend along the contour of the lower portion TL of the trench T. Therefore, the gate insulating film 122 may extend along the top surface of the substrate 100 and the sidewalls of the gate spacer 126. Alternatively, the gate insulating film 122 may extend along the top surface of the substrate 100 but not along the sidewalls of the gate spacer 126.

[0045] The gate insulating film 122 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a dielectric constant higher than that of silicon oxide. The high-k material may include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0046] The gate electrode 124 may be formed on the gate insulating film 122. The gate electrode 124 may be formed in the lower portion TL of the trench T. For example, the gate electrode 124 may fill a portion of the lower portion TL of the trench T that is not filled with the gate insulating film 122. Therefore, the gate insulating film 122 may extend along the bottom surface and sidewalls of each gate electrode 124.

[0047] The gate electrode 124 may include a conductive material. For example, the gate electrode 124 may include a metal layer. For example, the gate electrode 124 may include at least one of Ti, Ta, W, Al, Co, and a combination thereof, but the present disclosure is not limited thereto. In another example, the gate electrode 124 may be formed of silicon or silicon germanium instead of being formed of a metal.

[0048] The gate electrode 124 is shown as a single layer film, but the present disclosure is not limited thereto. For example, the gate electrode 124 may be formed by stacking a plurality of conductive materials. For example, the gate electrode 124 may include a work function control film that controls the work function and a filling conductive film that fills the gap formed by the work function control film. The work function control film may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and a combination thereof. The filling conductive film may include, for example, W or Al.

[0049] The gate electrode 124 may be formed by, for example, a replacement process, but the present disclosure is not limited thereto.

[0050] The etch stop layer 130 may be formed on the gate electrode 124. In some exemplary embodiments, the etch stop layer 130 may be formed in the upper portion TU of the trench T. For example, the etch stop layer 130 may extend along the contour of the upper portion TU of the trench T. For example, the etch stop layer 130 may extend along the top surface of the gate electrode 124, the top surface of the gate insulating film 122, the top surface of the gate spacer 126, and the sidewall of the first interlayer insulating film 150.

[0051] In some exemplary embodiments, the etch stop layer 130 may extend at least partially along a sidewall of the contact 160. For example, a portion of the etch stop layer 130 may be interposed between the capping pattern 140 and the contact 160.

[0052] The etch stop layer 130 may protect the gate electrode 124 or the contact 160 from being etched. The etch stop layer 130 may include, for example, at least one of aluminum nitride, aluminum oxide, silicon oxide, silicon nitride, and a combination thereof.

[0053] The capping pattern 140 may cover the top surface of the gate electrode 124 and the top surface of the gate spacer 126. In addition, the capping pattern 140 may fill the trench T defined by the top surface of the gate electrode 124, the top surface of the gate spacer 126, the sidewall of the first interlayer insulating film 150, and the sidewall of the contact 160 (e.g., the upper portion TU of the trench T).

[0054] In some exemplary embodiments, the capping pattern 140 may be formed on the etch stop layer 130. In addition, the capping pattern 140 may be formed in the upper portion TU of the trench T. For example, the capping pattern 140 may fill a portion of the upper portion TU that is not filled by the etch stop layer 130. Therefore, the etch stop layer 130 may at least partially extend along the sidewall and bottom surface of each capping pattern 140.

[0055] In some exemplary embodiments, the sidewall of the capping pattern 140 adjacent to the contact 160 may have a plurality of inclined surfaces. For example, the sidewall of the capping pattern 140 adjacent to the contact 160 may include a first sidewall portion 140S1 and a second sidewall portion 140S2, the second sidewall portion 140S2 being disposed above the first sidewall portion 140S1, and the slope of the second sidewall portion 140S2 being smaller than the slope of the first sidewall portion 140S1. This will be described later with reference to Figures 24 to 28A Therefore, the capping pattern 140 may ensure a sufficiently large distance between the gate electrode 124 and the contact 160 , and thus can reduce leakage current between the gate electrode 124 and the contact 160 .

[0056] The first sidewall portion 140S1 of the capping pattern 140 may be substantially perpendicular to the top surface of the substrate 100, and the second sidewall portion 140S2 of the capping pattern 140 may be inclined relative to the top surface of the substrate 100. However, the present disclosure is not limited thereto. For example, the first sidewall portion 140S1 may also be inclined relative to the top surface of the substrate 100.

[0057] The capping pattern 140 may include, for example, a low-k material. Therefore, the capping pattern 140 can effectively reduce the parasitic capacitance or leakage current between the gate electrode 124 and the contact 160. For example, the capping pattern 140 may include silicon oxide or a low-k material having a dielectric constant lower than that of silicon oxide. In some exemplary embodiments, the capping pattern 140 may include a material substantially the same as the first interlayer insulating film 150.

[0058] The contact 160 may be formed on the substrate 100 and the gate spacer 126. The contact 160 may protrude beyond the top surface of the gate electrode 124. Since the capping pattern 140 is disposed on the gate electrode 124, the contact 160 may be formed on the sidewalls of the gate spacer 126 and on the sidewalls of the capping pattern 140. A portion of the contact 160 may be formed on the etch stop layer 130 and may contact the etch stop layer 130, and a portion of the contact 160 may contact the gate spacer 126. It should be understood that when an element is referred to as "on another element", the element may be directly on another element, or there may be an intermediate element. In contrast, when an element is referred to as "directly on another element" or "contacting another element", there is no intermediate element. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" and "directly between", "adjacent" and "directly adjacent", etc.).

[0059] The contact 160 may penetrate the first interlayer insulating film 150. For example, the contact 160 may penetrate the first interlayer insulating film 150 to extend along the sidewalls of the gate spacer 126 and the sidewalls of the capping pattern 140. Figure 1 As shown, the shape of the sidewall of the contact 160 may follow the shape of the sidewall (eg, the first sidewall portion 140S1 and the second sidewall portion 140S2 ) of the capping pattern 140 .

[0060] The contact 160 may be formed by a self-aligned contact (SAC) process. For example, the sidewalls of the contact 160 may be defined by the sidewalls of the capping pattern 140 and the sidewalls of the gate spacer 126. For example, the gate spacer 126 may include a material having an etching selectivity with respect to the first interlayer insulating film 150.

[0061] However, in some exemplary embodiments, the capping pattern 140 may include a material having no etching selectivity with respect to the first interlayer insulating film 150. For example, the capping pattern 140 may include silicon oxide or a low-k material having a dielectric constant lower than that of silicon oxide. In another example, the capping pattern 140 may include substantially the same material as the first interlayer insulating film 150.

[0062] Since the sidewall of the capping pattern 140 adjacent to the contact 160 includes the first sidewall portion 140S1 and the second sidewall portion 140S2, the contact 160 may include an extension portion 160A and an expansion portion 160B having a different width from the extension portion 160A. The extension portion 160A of the contact 160 may be disposed on the sidewall of the gate spacer 126 and on the first sidewall portion 140S1 of the capping pattern 140 (for example, an etch stop layer 130 is formed between the extension portion 160A and the first sidewall portion 140S1). The expansion portion 160B of the contact 160 may be disposed on the second sidewall portion 140S2 of the capping pattern 140.

[0063] Since the slope of the second sidewall portion 140S2 of the capping pattern 140 is smaller than the slope of the first sidewall portion 140S1 of the capping pattern 140, the width of the expanded portion 160B may be greater than the width of the extended portion 160A. For example, the width of the extended portion 160A may be substantially uniform regardless of the distance from the top surface of the substrate 100. On the other hand, the width of the expanded portion 160B may gradually increase away from the top surface of the substrate 100. Therefore, the width W2 of the top surface of the expanded portion 160B may be greater than the width W1 of the bottom surface of the extended portion 160A.

[0064] Figure 2 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure. Figure 1 Description of the various elements or features that are the same as the elements or features.

[0065] Reference Figure 2 The etch stop layer 130 extends along the second sidewall portion 140S2 of the capping pattern 140 and along the sidewall of the gate spacer 126 by more than Figure 1 For example, the etch stop layer 130 may include a first film 132 and a second film 134.

[0066] The first film 132 may extend along a portion of the sidewall of the capping pattern 140 and along a bottom surface of the capping pattern 140. For example, the first film 132 may extend along a portion of the sidewall of the contact 160, a top surface of the gate electrode 124, a top surface of the gate insulating film 122, a top surface of the gate spacer 126, and a sidewall of the first interlayer insulating film 150. The first film 132 may also be formed on the first sidewall portion 140S1 of the capping pattern 140, and in some embodiments does not contact the first sidewall portion 140S1 of the capping pattern 140. Figure 2 In the illustrated embodiment, the first film 132 is not formed on the second sidewall portion 140S2 of the capping pattern 140 .

[0067] The second film 134 may extend along the sidewalls of the contact 160. For example, the second film 134 may extend along and contact the sidewalls of the gate spacer 126 and may extend along and contact the first and second sidewall portions 140S1 and 140S2 of the capping pattern 140.

[0068] Thus, the etch stop layer 130 may extend along and may contact the sidewalls of the contact 160 , and may extend along and contact the top surface of the gate electrode 124 .

[0069] In some exemplary embodiments, a portion of the second film 134 may overlap a portion of the first film 132. Figure 2 As shown, a portion of the first film 132 and a portion of the second film 134 may be sequentially stacked on the first sidewall portion 140S1 of the capping pattern 140 .

[0070] Alternatively, the second film 134 may extend along the bottom surface of the contact 160. Still alternatively, the second film 134 may not extend along the second sidewall portion 140S2 of the capping pattern 140. In some embodiments, the first film 132 may continue to extend along the second sidewall portion 140S2 of the capping pattern 140 and contact the second sidewall portion 140S2 of the capping pattern 140 instead of the second film 134. In other embodiments, neither the first film 132 nor the second film 134 extends along the second sidewall portion 140S2 of the capping pattern 140.

[0071] Figure 3 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure. Figure 1 and Figure 2 Descriptions of elements or features that are identical to those in any of the figures.

[0072] Reference Figure 3 The etch stop layer 130 extends along the second sidewall portion 140S2 of the capping pattern 140 to a greater extent than Figure 1For example, the etch stop layer 130 may include a first film 132 and a third film 136 .

[0073] The third film 136 may extend along the bottom surface of the capping pattern 140 and the sidewalls of the capping pattern 140. For example, the third film 136 may extend along the bottom surface of the capping pattern 140, along the sidewalls of the capping pattern 140 adjacent to the contacts 160 (e.g., the first sidewall portion 140S1 and the second sidewall portion 140S2), and along the sidewalls of the capping pattern 140 adjacent to the first interlayer insulating film 150.

[0074] Thus, the etch stop layer 130 may extend along a portion of the sidewalls of the contact 160 and along a top surface of the gate electrode 124 .

[0075] In some exemplary embodiments, the third film 136 may be formed on the first film 132. Since the first film 132 is not formed on the second sidewall portion 140S2 of the capping pattern 140, the contact 160 and the third film 136 may contact each other. It should be noted that the term "contact" as used herein refers to direct connection (i.e., touching) of two components unless the context clearly indicates otherwise.

[0076] Figure 4 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure. Figures 1 to 3 Descriptions of elements or features that are identical to those in any of the figures.

[0077] Reference Figure 4 The etch stop layer 130 extends along the second sidewall portion 140S2 of the capping pattern 140 and along the sidewall of the gate spacer 126 by more than Figure 1 For example, the etch stop layer 130 may include a first film 132, a second film 134, and a third film 136.

[0078] Thus, the etch stop layer 130 may extend along the sidewalls of the contact 160 and along the top surface of the gate electrode 124 .

[0079] In some exemplary embodiments, a portion of the first film 132 may be interposed between the second film 134 and the third film 136. Since the first film 132 is not formed on the second sidewall portion 140S2 of the capping pattern 140, the second film 134 and the third film 136 may contact each other. Figure 4 As shown, a portion of the third film 136 and a portion of the second film 134 may be sequentially stacked on the second sidewall portion 140S2 of the capping pattern 140 .

[0080] In some exemplary embodiments, a portion of the second film 134 may overlap a portion of the first film 132 and a portion of the third film 136. Figure 4 As shown, portions of the third film 136 , the first film 132 , and the second film 134 may be sequentially stacked on the first sidewall portion 140S1 of the capping pattern 140 .

[0081] Figure 5 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure. Figures 1 to 4 Descriptions of elements or features that are identical to those in any of the figures.

[0082] Reference Figure 5 ,and Figure 2 Unlike the etch stop layer 130 of the embodiment of the present invention, the etch stop layer 130 does not extend along the top surface of the gate electrode 124. For example, the etch stop layer 130 may include only the second film 134.

[0083] Thus, the etch stop layer 130 may extend along the sidewalls of the contacts 160 .

[0084] In some exemplary embodiments, since the first film 132 is not formed, the second film 134 may contact the first sidewall portion 140S1 and the second sidewall portion 140S2 of the covering pattern 140. It should be noted that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts in this document, these elements, components, regions, layers and / or parts should not be limited by these terms. Unless otherwise specified in the context, these terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part, for example as a naming convention. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed in one part of the specification may be referred to as the second element, component, region, layer or part in another part of the specification or in the claims. In addition, in some cases, even if "first", "second", etc. are not used to describe the term in the specification, the term may still be referred to as "first" or "second" in the claim in order to distinguish different elements claimed for protection.

[0085] Figure 6 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure. Figures 1 to 4 Descriptions of elements or features that are identical to those in any of the figures.

[0086] Reference Figure 6The etch stop layer 130 extends along the second sidewall portion 140S2 of the capping pattern 140 and along the sidewall of the gate spacer 126 by more than Figure 1 For example, the etch stop layer 130 may include a second film 134 and a third film 136.

[0087] Thus, the etch stop layer 130 may extend along the sidewalls of the contact 160 and along the top surface of the gate electrode 124 .

[0088] In some exemplary embodiments, a portion of the second film 134 may overlap a portion of the third film 136. Figure 6 As shown, a portion of the third film 136 and a portion of the second film 134 may be sequentially stacked on the first sidewall portion 140S1 and the second sidewall portion 140S2 of the capping pattern 140 .

[0089] Figure 7 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure. Figures 1 to 4 Descriptions of elements or features that are identical to those in any of the figures.

[0090] Reference Figure 7 ,and Figure 3 Unlike the etch stop layer 130 of FIG. 1 , the etch stop layer 130 does not include Figure 3 In contrast, the etch stop layer 130 may include only a single film, for example, the third film 136 .

[0091] Therefore, the etch stop layer 130 may extend along the top surface of the gate electrode 124 .

[0092] In some exemplary embodiments, since the first film 132 is not formed and only one film is used instead of two or more stacked films, the third film 136 may contact the first sidewall portion 140S1 and the second sidewall portion 140S2 of the capping pattern 140. As discussed in the above embodiments, in some cases, only a single film or layer is used to form the etch stop layer 130 or a portion of the etch stop layer. Therefore, in those embodiments, the portion of the etch stop layer 130 including only a single film may have a completely uniform thickness. Similarly, for portions including two films stacked on each other, these portions may also have a completely uniform thickness.

[0093] When referring to orientation, layout, position, shape, size, quantity or other measurement in this article, the terms such as "uniform", "same", "equal", "flat" or "coplanar" used do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity or other measurement, but are intended to cover nearly the same orientation, layout, position, shape, size, quantity or other measurement within acceptable variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used to emphasize this meaning in this article. For example, items described as "substantially the same", "substantially equal" or "substantially flat" can be exactly the same, equal or flat, or can be the same, equal or flat within acceptable variations that may occur, for example, due to manufacturing processes.

[0094] Figure 8 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure. Figure 1 Description of the various elements or features that are the same as the elements or features.

[0095] Reference Figure 8 ,and Figure 1 Unlike the semiconductor device of FIG. 1 , the semiconductor device according to some exemplary embodiments of the present disclosure does not include the etch stop layer 130 .

[0096] Thus, the sidewalls of the contacts 160 contact the sidewalls of the gate spacers 126 and the first and second sidewall portions 140S1 and 140S2 of the capping pattern 140 .

[0097] Fig. 9 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure. Figure 1 Description of the various elements or features that are the same as the elements or features.

[0098] Reference Fig. 9 The gate spacer 126 may be formed as a multi-layer film. For example, the gate spacer 126 may include a first spacer 126A and a second spacer 126B formed on the first spacer 126A.

[0099] The first spacer 126A may be formed on the sidewall of the gate electrode 124 (for example, with the gate insulating film 122 therebetween). The top surface of the first spacer 126A may be lower than the top surface of the first interlayer insulating film 150. For example, the top surface of the first spacer 126A may be disposed on substantially the same plane as the top surface of the gate electrode 124. Therefore, the first spacer 126A may define the lower portion TL of the trench T.

[0100] The first spacer 126A may include, for example, silicon oxide or a low-k material having a dielectric constant lower than that of silicon oxide. Therefore, the first spacer 126A may reduce parasitic capacitance between the gate electrode 124 and the contact 160.

[0101] The second spacer 126B may be formed along the sidewall of the first interlayer insulating film 150 on the substrate 100. For example, the second spacer 126B may be interposed between the first interlayer insulating film 150 and the first spacer 126A. The second spacer 126B may also be placed between the contact 160 and the first spacer 126A. In some exemplary embodiments, the second spacer 126B may protrude beyond the top surface of the first spacer 126A.

[0102] A sidewall of the second spacer 126B adjacent to the contact 160 may define a sidewall of the contact 160. For example, the second spacer 126B may include a material having an etching selectivity with respect to the first interlayer insulating film 150. For example, the second spacer 126B may include silicon nitride.

[0103] In some exemplary embodiments, the sidewall of the second spacer 126B may have a plurality of slopes. For example, the sidewall of the second spacer 126B adjacent to the contact 160 may include a third sidewall portion 126S1 and a fourth sidewall portion 126S2 having a smaller slope than the third sidewall portion 126S1. As described above, labels such as "first", "second", "third", and "fourth" are used only as naming conventions for naming certain elements unless the context indicates that these terms have additional meanings. For example, Fig. 9 As shown, the third sidewall portion 126S1 of the second spacer 126B may be substantially perpendicular to the top surface of the substrate 100, and the fourth sidewall portion 126S2 of the second spacer 126B may be inclined relative to the top surface of the substrate 100. However, the present disclosure is not limited thereto. For example, the third sidewall portion 126S1 may also be inclined relative to the top surface of the substrate 100 (e.g., more inclined than the fourth sidewall portion 126S2).

[0104] In some exemplary embodiments, the slope of the second sidewall portion 140S2 of the capping pattern 140 may be smaller than the slope of the fourth sidewall portion 126S2 of the second spacer 126B. This will be described later with reference to Figure 29 to Figure 31 Give a description.

[0105] Fig. 9 The second spacer 126B adjacent to the contact 160 is shown to have substantially the same height as the first sidewall portion 140S1 of the capping pattern 140, but the disclosure is not limited thereto. For example, the second spacer 126B adjacent to the contact 160 may have a height less than that of the first sidewall portion 140S1 of the capping pattern 140.

[0106] Fig.10 is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present disclosure. Figure 1 Description of the various elements or features that are the same as the elements or features.

[0107] Reference Fig.10 , the capping pattern 140 may include a void V.

[0108] A void V may be formed in the capping pattern 140. The void V may be, for example, an air gap. The dielectric constant of the void V may be lower than the dielectric constant of the material of the capping pattern 140. Therefore, the capping pattern 140 can reduce the parasitic capacitance between the gate electrode 124 and the contact 160.

[0109] Fig.10 The void V is shown as being adjacent to the first sidewall portion 140S1 and the second sidewall portion 140S2 of the capping pattern 140, but the present disclosure is not limited thereto. For example, the void V may be formed at any position in the capping pattern 140. A plurality of voids V may be formed in each capping pattern 140.

[0110] Fig.10 A void is shown, but similarly placed voids may be included in conjunction with Figures 1 to 9 The various embodiments discussed. Therefore, including gaps is not limited to Fig.10 In those examples where voids are present, the overlay pattern fills the trenches and includes the voids in the overlay pattern.

[0111] Fig.11 is a perspective view of a semiconductor device according to some exemplary embodiments of the present disclosure. Fig.12 is along Fig.11 A cross-sectional view taken along line AA'. Fig.13 is along Fig.11 For the sake of convenience, the cross-sectional view taken along the line BB' will be omitted or at least simplified. Figure 1 Description of the various elements or features that are the same as the elements or features.

[0112] Reference Figures 11 to 13 , a semiconductor device according to some exemplary embodiments of the present disclosure includes a substrate 100, a field insulating film 110, an interface film 105, a gate insulating film 122, a gate electrode 124, a gate spacer 126, an epitaxial pattern 170, an etch stop layer 130, a capping pattern 140, a first interlayer insulating film 150 and a contact 160.

[0113] The substrate 100 may include a fin pattern F. The fin pattern F may protrude and extend from the top of the substrate 100 . The fin pattern F may be a portion of the substrate 100 , and may include an epitaxial layer grown from the substrate 100 .

[0114] The fin pattern F may intersect the gate electrode 124. For example, the fin pattern F may extend in a first direction, and the gate electrode 124 may extend in a second direction (eg, in a perpendicular direction) intersecting the first direction.

[0115] The fin pattern F may include, for example, an elemental semiconductor material (eg, silicon or germanium). The fin pattern F may also include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0116] For example, in the case where the fin pattern F includes a group IV-IV compound semiconductor, the fin pattern F may include a binary or ternary compound including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or may include a compound obtained by doping the above binary or ternary compound with a group IV element. For example, in the case where the fin pattern F includes a group III-V compound semiconductor, the fin pattern F may include a binary, ternary, or quaternary compound obtained by combining at least one of aluminum (Al), gallium (Ga), and indium (In) with one of phosphorus (P), arsenic (As), and antimony (Sb). It is assumed that the fin pattern F may be a silicon fin pattern including silicon.

[0117] The channel region of the transistor including the gate electrode 124 may include a fin pattern F, but the present disclosure is not limited thereto. Alternatively, the channel region of the transistor including the gate electrode 124 may include a nanowire pattern, a nanosheet pattern, or the like.

[0118] The field insulating film 110 may be formed on the substrate 100 . The field insulating film 110 may surround a portion of a sidewall of the fin pattern F. For example, the fin pattern F may be defined by the field insulating film 110 . Fig.11 The sidewall of the fin pattern F is illustrated as being entirely surrounded by the field insulating film 110 , but the present disclosure is not limited thereto.

[0119] The field insulating film 110 may include, for example, at least one of an oxide film, a nitride film, an oxynitride film, and a combination thereof, but the present disclosure is not limited thereto.

[0120] The interface film 105 may be interposed between the substrate 100 and the gate insulating film 122. The interface film 105 may be formed on the outside of the fin pattern F. For example, the interface film 105 may extend along the contour of the bottom surface of the lower portion TL of the trench T, but the present disclosure is not limited thereto. In another example, the interface film 105 may extend along the contour of the bottom surface and the sidewall of the lower portion TL of the trench T. In some exemplary embodiments, the interface film 105 may not be provided.

[0121] The interface film 105 may include, for example, silicon oxide. The interface film 105 may also include other materials depending on the type of the substrate 100 , the type of the fin pattern F, or the type of the gate insulating film 122 .

[0122] The epitaxial pattern 170 may be formed in the fin pattern F at both sides of the gate electrode 124. However, the epitaxial pattern 170 may be insulated from the gate electrode 124. The epitaxial pattern 170 may function as a source and a drain of a transistor.

[0123] In some exemplary embodiments, the epitaxial pattern 170 may be an elevated source and an elevated drain. For example, the uppermost portion of the epitaxial pattern 170 may protrude beyond the top surface of the fin pattern F. In some exemplary embodiments, the epitaxial pattern 170 may be a shared source and a shared drain shared between a plurality of gate electrodes.

[0124] The epitaxial pattern 170 is shown as a single-layer film, but the present disclosure is not limited thereto. For example, the epitaxial pattern 170 may be formed as a multi-layer film.

[0125] Fig.11 The epitaxial pattern 170 is shown to have a pentagonal cross-sectional shape, but the present disclosure is not limited thereto. Alternatively, the epitaxial pattern 170 may have various cross-sectional shapes, such as a rhombus or hexagonal cross-sectional shape.

[0126] In the case where the semiconductor device according to some exemplary embodiments of the present disclosure is a P-type metal oxide semiconductor (PMOS) transistor, the epitaxial pattern 170 may include P-type impurities or impurities for preventing the diffusion of P-type impurities. For example, the epitaxial pattern 170 may include at least one of B, C, In, Ga, Al, and combinations thereof.

[0127] In addition, in the case where the semiconductor device according to some exemplary embodiments of the present disclosure is a PMOS transistor, the epitaxial pattern 170 may include a compressive stress material. For example, in the case where the fin pattern F is formed of silicon, the epitaxial pattern 170 may include a material having a lattice constant greater than that of silicon, such as silicon germanium. The compressive stress material may apply compressive stress to the fin pattern F, and thus may improve the mobility of carriers in the channel region.

[0128] On the other hand, in the case where the semiconductor device according to some exemplary embodiments of the present disclosure is an N-type metal oxide semiconductor (NMOS) transistor, the epitaxial pattern 170 may include N-type impurities or impurities for preventing the diffusion of N-type impurities. For example, the epitaxial pattern 170 may include at least one of P, Sb, As, and combinations thereof.

[0129] In addition, in the case where the semiconductor device according to some exemplary embodiments of the present disclosure is an NMOS transistor, the epitaxial pattern 170 may include a tensile stress material. For example, in the case where the fin pattern F is formed of silicon, the epitaxial pattern 170 may include a material having a lattice constant smaller than that of silicon, such as SiC. The tensile stress material may apply tensile stress to the fin pattern F, and thus may improve the mobility of carriers in the channel region.

[0130] The etch stop layer 130 may extend along a portion of the sidewall of the capping pattern 140 and along the bottom surface of the capping pattern 140. For example, the etch stop layer 130 may extend along a portion of the sidewall of the contact 160, along the top surface of the gate electrode 124, along the top surface of the gate insulating film 122, along the top surface of the gate spacer 126, and along the sidewall of the first interlayer insulating film 150. In addition, the etch stop layer 130 may be formed on the first sidewall portion 140S1 of the capping pattern 140. However, in one embodiment, the etch stop layer 130 is not formed on the second sidewall portion 140S2 of the capping pattern 140.

[0131] The capping pattern 140 may cover the top surface of the gate electrode 124 and the top surface of the gate spacer 126. The capping pattern 140 may fill a portion or the entirety of the trench T defined by the top surface of the gate electrode 124, the top surface of the gate spacer 126, the sidewall of the first interlayer insulating film 150, and the sidewall of the contact 160.

[0132] In some exemplary embodiments, a capping pattern 140 may be formed on the etch stop layer 130. The capping pattern 140 may be formed in an upper portion TU of the trench T.

[0133] The contact 160 may be formed on the epitaxial pattern 170. The contact 160 may be electrically connected to the epitaxial pattern 170. Thus, the contact 160 may apply a voltage to the epitaxial pattern 170.

[0134] like Fig.11 and Fig.12 As shown, the contact 160 may be formed on both sides of the gate electrode 124. For example, the contact 160 may penetrate a portion of the first interlayer insulating film 150 on both sides of the gate electrode 124.

[0135] Fig.14 is a perspective view of a semiconductor device according to some exemplary embodiments of the present disclosure. Fig.15 is along Fig.14 A cross-sectional view taken along line CC'. Fig.16 is along Fig.14 For the sake of convenience, the cross-sectional view taken along the line D-D' will be omitted or at least simplified. Figures 1 to 4 Descriptions of elements or features that are identical to those in any of the figures.

[0136] Reference Figures 14 to 16 The etch stop layer 130 extends along the second sidewall portion 140S2 of the capping pattern 140 and along the sidewall of the gate spacer 126 by more than Figures 11 to 13 For example, the etch stop layer 130 may include a first film 132, a second film 134, and a third film 136.

[0137] Thus, the etch stop layer 130 may extend along the sidewalls of the contact 160 and along the top surface of the gate electrode 124 .

[0138] In some exemplary embodiments, a portion of the first film 132 may be interposed between the second film 134 and the third film 136. Since the first film 132 is not formed on the second sidewall portion 140S2 of the capping pattern 140, the second film 134 and the third film 136 may contact each other. Figures 14 to 16 As shown, a portion of the second film 134 and a portion of the third film 136 may be sequentially stacked on the second sidewall portion 140S2 of the capping pattern 140 .

[0139] In some exemplary embodiments, a portion of the second film 134 may overlap a portion of the first film 132 and a portion of the third film 136. Figures 14 to 16 As shown, a portion of the third film 136 , a portion of the first film 132 , and a portion of the second film 134 may be sequentially stacked on the first sidewall portion 140S1 of the capping pattern 140 .

[0140] The following will refer to Figures 1 to 3 , Fig. 9 , Fig.11 and Figures 17 to 44 A method of manufacturing a semiconductor device according to some exemplary embodiments of the present disclosure is described.

[0141] Figures 17 to 28B 1 is a cross-sectional view showing an intermediate step of a method of manufacturing a semiconductor device according to some exemplary embodiments of the present disclosure. Figures 1 to 3 Descriptions of elements or features that are identical to those in any of the figures.

[0142] Reference Fig.17, a dummy gate insulating film 210 and a dummy gate electrode 220 are formed on the substrate 100 .

[0143] For example, an insulating film and a conductive film may be sequentially formed on the substrate 100 and then patterned using the first mask pattern 230. As a result, a dummy gate insulating film 210 and a dummy gate electrode 220 may be formed on the substrate 100.

[0144] Thereafter, a gate spacer 126 is formed on the sidewall of the dummy gate insulating film 210 and on the sidewall of each dummy gate electrode 220 .

[0145] For example, a spacer film may be formed on the contours of the substrate 100, the dummy gate insulating film 210, the dummy gate electrode 220, and the first mask pattern 230. Thereafter, the spacer film may be removed from the top surface of the substrate 100 and the top surface of the first mask pattern 230. As a result, the gate spacer 126 may be formed on the sidewall of the dummy gate insulating film 210 and on the sidewall of each dummy gate electrode 220.

[0146] Reference Fig.18 , a first interlayer insulating film 150 is formed on the substrate 100 . The first interlayer insulating film 150 may be formed to surround the sidewall of the gate spacer 126 .

[0147] For example, the first interlayer insulating film 150 may be formed to cover the dummy gate electrode 220 and the dummy gate insulating film 210. Thereafter, the planarization process may be continued until the top surface of the dummy gate electrode 220 is exposed. The planarization process may include, for example, a chemical mechanical polishing (CMP) process. In some exemplary embodiments, the first mask pattern 230 may be removed by the planarization process.

[0148] Therefore, the top surface of the first interlayer insulating film 150 , the top surface of the gate spacer 126 , and the top surface of the dummy gate electrode 220 may be disposed on substantially the same plane.

[0149] Reference Fig.19 , remove the dummy gate insulating film 210 and the dummy gate electrode 220.

[0150] As a result, a first trench T1 is formed in the first interlayer insulating film 150. The first trench T1 may be defined by the sidewalls of the gate spacer 126 and the top surface of the substrate 100.

[0151] Reference Fig. 20 , a gate insulating film 122 and a gate electrode 124 are sequentially formed in the first trench TL.

[0152] For example, the gate insulating film 122 may be formed to extend along the contours of the top surface of the first interlayer insulating film 150 , the top surface of the gate spacer 126 , the sidewalls of the gate spacer 126 , and the top surface of the substrate 100 .

[0153] Thereafter, the gate electrode 124 may be formed on the gate insulating film 122. The gate electrode 124 may fill the space formed by the gate insulating film 122 in the first trench T1.

[0154] Reference Fig.21 , the upper portion of the gate insulating film 122 and the upper portion of the gate electrode 124 are recessed.

[0155] Upper portions of the gate insulating film 122 and the gate electrode 124 may be recessed such that top surfaces of the gate insulating film 122 and the gate electrode 124 become lower than a top surface of the first interlayer insulating film 150 .

[0156] As a result, a second trench T2 may be formed in the first interlayer insulating film 150. The second trench T2 may be defined by a top surface of the gate electrode 124, a top surface of the gate insulating film 122, a top surface of the gate spacer 126, and a sidewall of the first interlayer insulating film 150.

[0157] As a result, a trench T including a lower portion TL and an upper portion TU may be defined in the first interlayer insulating film 150. The gate insulating film 122 and the gate electrode 124 may fill the lower portion TL of the trench T.

[0158] Reference Fig. 22 , an etch stop layer 130 and a second mask pattern 310 are formed on the gate electrode 124 .

[0159] For example, the etch stop layer 130 and the second mask pattern 310 are sequentially formed on Fig.21 Thereafter, the planarization process may be continued until the top surface of the first interlayer insulating film 150 is exposed.

[0160] As a result, the etch stop layer 130 may be formed to extend along the outline of the upper portion TU of the trench T. The etch stop layer 130 may extend along the top surface of the gate electrode 124 , the top surface of the gate insulating film 122 , the top surface of the gate spacer 126 , and the sidewall of the first interlayer insulating film 150 .

[0161] The etch stop layer 130 may include, for example, at least one of aluminum nitride, aluminum oxide, silicon oxide, silicon nitride, and a combination thereof.

[0162] The second mask pattern 310 may be formed on the etch stop layer 130. The second mask pattern 310 may fill a portion of the upper portion TU of the trench T that is not filled by the etch stop layer 130.

[0163] In some exemplary embodiments, the second mask pattern 310 may include a semiconductor material. For example, the second mask pattern 310 may include a semiconductor material such as silicon or silicon germanium. In some exemplary embodiments, the second mask pattern 310 may include amorphous silicon or polycrystalline silicon.

[0164] In some exemplary embodiments, the etch stop layer 130 is not formed.

[0165] Reference Fig.23 ,exist Fig. 22 A second interlayer insulating film 320 is formed on the structure shown.

[0166] Thus, the second interlayer insulating film 320 may be formed to cover the top surface of the first interlayer insulating film 150 , the top surface of the etch stop layer 130 , and the top surface of the second mask pattern 310 .

[0167] The second interlayer insulating film 320 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide. In some exemplary embodiments, the second interlayer insulating film 320 may include substantially the same material as the first interlayer insulating film 150 .

[0168] Reference Fig.24 , a contact hole H penetrating the first interlayer insulating film 150 and the second interlayer insulating film 320 is formed.

[0169] The contact hole H may be formed on the sidewall of the gate electrode 124 and on the sidewall of the second mask pattern 310. The contact hole H may be formed to expose the top surface of the substrate 100.

[0170] The contact hole H may be formed by a SAC process. For example, the sidewall of the contact hole H may be defined by the sidewall of the second interlayer insulating film 320, the sidewall of the second mask pattern 310, and the sidewall of the gate spacer 126. In the case of using the etch stop layer 130, the contact hole H may be further defined by a portion of the etch stop layer 130. When forming the contact hole H, the sidewall of the capping pattern 140 may include a first inclined surface 310S. The first inclined surface 310S of the capping pattern 140 may be inclined relative to the top surface of the substrate 100.

[0171] The second mask pattern 310 including a semiconductor material such as silicon or silicon germanium may have greater etching resistance than silicon oxide or silicon nitride. For example, the second mask pattern 310 may have a lower etching selectivity than silicon oxide or silicon nitride relative to the first interlayer insulating film 150 and the second interlayer insulating film 320. Therefore, the first inclined surface 310S of the second mask pattern 310 may have a gentle slope, and a sufficiently large distance may be ensured between the gate electrode 124 and the contact hole H.

[0172] Reference Fig.25A , forming a contact 160 filling the contact hole H. The contact 160 discussed here and in other embodiments may be formed, for example, of a conductive material (e.g., a metal or silicon doped with impurities). For example, the contact 160 may be formed by filling the hole H with a conductive material. The contact 160 discussed in various embodiments may be referred to herein as a conductive contact, a via contact, a plug, or a contact plug. From a top view, the contact 160 may be a circular or other bilaterally symmetrical shape, or may be an elongated shape such as a line.

[0173] Therefore, the sidewall of the contact 160 may be defined by the sidewall of the second interlayer insulating film 320, the sidewall of the second mask pattern 310, and the sidewall of the gate spacer 126. In the case where the etch stop layer 130 is used, the sidewall of the contact 160 may be further defined by a portion of the etch stop layer 130. The sidewall described as being defined by certain components may be shaped based on those components and / or may be positioned at a specific location based on those components.

[0174] Reference Fig.25B In some exemplary embodiments, before forming the contact 160 , the etch stop layer 130 may be further formed to extend along the sidewall of the contact hole H.

[0175] For example, Fig.25B As shown, the etch stop layer 130 may include a first film 132 and a second film 134 .

[0176] The second film 134 may be formed on Fig.24 Thereafter, a contact 160 filling a space in the contact hole H that is not filled by the second film 134 may be formed. The second film 134 may protect the contact 160 from an etching process for removing the second mask pattern 310.

[0177] In some exemplary embodiments, the second film 134 may be selectively removed from the top surface of the substrate 100. In some exemplary embodiments, the second film 134 may be removed from the first inclined surface 310S. For example, in the process of selectively removing the second film 134 from the top surface of the substrate 100, the second film 134 may also be removed from the first inclined surface 310S.

[0178] Reference Fig.26 , performing a planarization process. Fig.26 It is used to illustrate Fig.25A A cross-sectional view of the process performed on the structure shown.

[0179] As a result of the planarization process, the second interlayer insulating film 320 may be removed. The planarization process may be continued until the top surface of the second mask pattern 310 is exposed.

[0180] Reference Fig. 27 , the second mask pattern 310 is removed. As a result, a third trench T3 is formed in the first interlayer insulating film 150.

[0181] For example, the second mask pattern 310 may be removed using an etching process including a wet etching process or a dry etching process.

[0182] In some exemplary embodiments, the etch stop layer 130 may protect the gate electrode 124 or the contact 160. For example, the etch stop layer 130 extending along a portion of the sidewall of the contact 160 or the top surface of the gate electrode 124 may protect the gate electrode 124 or the contact 160 from the etching process for removing the second mask pattern 310.

[0183] Reference Fig.28A , a capping pattern 140 is formed in the third trench T3.

[0184] Thus, the etch stop layer 130 filling the upper portion TU of the trench T and the capping pattern 140 may be formed.

[0185] The capping pattern 140 may include, for example, a low-k material. Therefore, the capping pattern 140 may effectively reduce parasitic capacitance or leakage current between the gate electrode 124 and the contact 160. For example, the capping pattern 140 may include silicon oxide or a low-k material having a dielectric constant lower than that of silicon oxide. In some exemplary embodiments, the capping pattern 140 may include a material substantially the same as the first interlayer insulating film 150.

[0186] Reference Fig.28B Before forming the capping pattern 140 , an etch stop layer 130 may be further formed in the third trench T3 .

[0187] For example, Fig.28B As shown, the etch stop layer 130 may include a first film 132 and a third film 136 .

[0188] The third film 136 may be formed on Fig. 27 Thereafter, a capping pattern 140 filling a space in the third trench T3 that is not filled by the third film 136 may be formed. The third film 136 may protect the gate electrode 124 or the contact 160.

[0189] Figure 29 to Figure 31 1 is a cross-sectional view showing an intermediate step of a method of manufacturing a semiconductor device according to some exemplary embodiments of the present disclosure. Fig. 9 and Figures 17 to 28B Descriptions of elements or features that are identical to those in any of the figures.

[0190] Reference Fig.29, a dummy gate insulating film 210 and a dummy gate electrode 220 are formed on the substrate 100 . Thereafter, a gate spacer 126 including a first spacer 126A and a second spacer 126B is formed on the sidewalls of the dummy gate insulating film 210 and the sidewalls of the dummy gate electrode 220 .

[0191] The first spacer 126A may be formed on the sidewall of the dummy gate electrode 220. The first spacer 126A may include, for example, silicon oxide or a low-k material having a dielectric constant lower than that of silicon oxide.

[0192] The second spacer 126B may be formed on a sidewall of the first spacer 126 A. The second spacer 126B may include, for example, silicon nitride.

[0193] Reference Fig.30 , an etch stop layer 130 and a second mask pattern 310 are formed.

[0194] The formation of the etch stop layer 130 and the second mask pattern 310 is similar to Figures 18 to 22 The etch stop layer 130 and the second mask pattern 310 are formed, and therefore, a detailed description thereof will be omitted.

[0195] In some exemplary embodiments, during the formation of the second trench T2 ( Fig.21 ), the upper portion of the second spacer 126B may not be recessed.

[0196] Reference Fig.31 , a contact hole H penetrating the first interlayer insulating film 150 and the second interlayer insulating film 320 is formed.

[0197] The contact hole H may be formed by the SAC process. That is, the sidewalls of the contact hole H may be defined by the sidewalls of the second interlayer insulating film 320 , the sidewalls of the second mask pattern 310 , and the sidewalls of the second spacer 126B.

[0198] When forming the contact hole H, the sidewall of the second mask pattern 310 may include the first inclined surface 310S. The sidewall of the second spacer 126B may include the second inclined surface 126S.

[0199] In some exemplary embodiments, the second mask pattern 310 may include a semiconductor material such as silicon or silicon germanium, and the second spacer 126B may include silicon nitride. Therefore, the second mask pattern 310 may have a lower etching selectivity than the second spacer 126B with respect to the first interlayer insulating film 150 and the second interlayer insulating film 320. Therefore, in some exemplary embodiments, the slope of the first inclined surface 310S may be smaller than the slope of the second inclined surface 126S.

[0200] Afterwards, refer to Fig. 9 , a contact 160 may be formed in the contact hole H.

[0201] Figures 32 to 44 1 is a cross-sectional view showing an intermediate step of a method of manufacturing a semiconductor device according to some exemplary embodiments of the present disclosure. Fig.11 and Figures 17 to 28B Descriptions of elements or features that are identical to those in any of the figures.

[0202] Reference Fig.32 , a dummy gate insulating film 210 and a dummy gate electrode 220 are formed on the substrate 100 .

[0203] The substrate 100 may include a fin pattern F. The fin pattern F may protrude and extend from the top of the substrate 100 . The fin pattern F may be a portion of the substrate 100 , or may include an epitaxial layer grown from the substrate 100 .

[0204] The fin pattern F may intersect the dummy gate electrode 220. For example, the fin pattern F may extend in a first direction, and the dummy gate electrode 220 may extend in a second direction intersecting the first direction.

[0205] Reference Fig.33 , an epitaxial pattern 170 is formed on the substrate 100 .

[0206] The epitaxial pattern 170 may be formed on the sidewalls of the gate electrode 124 . For example, the epitaxial pattern 170 may include an epitaxial layer formed on the fin pattern F. The epitaxial pattern 170 may be elevated source and drain regions whose top surfaces protrude beyond the top surface of the substrate 100 .

[0207] For example, a portion of the fin pattern F may be etched using an etching process using the gate electrode 124 and the gate spacer 126 as an etching mask. Thereafter, an epitaxial pattern 170 may be formed in the etched portion of the fin pattern F using an epitaxial growth method.

[0208] Reference Fig.34 , a first interlayer insulating film 150 is formed on the substrate 100 . The first interlayer insulating film 150 may be formed to surround the sidewall of the gate spacer 126 .

[0209] Reference Fig.35 , the dummy gate insulating film 210 and the dummy gate electrode 220 are removed. As a result, a first trench T1 is formed in the first interlayer insulating film 150 .

[0210] Reference Fig.36 , a gate insulating film 122 and a gate electrode 124 are sequentially formed in the first trench T1.

[0211] Reference Fig.37, the upper portion of the gate insulating film 122 and the upper portion of the gate electrode 124 are recessed. As a result, a second trench T2 may be formed in the first interlayer insulating film 150. In addition, a trench including a lower portion TL and an upper portion TU may be defined in the first interlayer insulating film 150.

[0212] Reference Fig.38 , an etch stop layer 130 and a second mask pattern 310 are formed on the gate electrode 124 .

[0213] Reference Fig.39 ,exist Fig.38 A second interlayer insulating film 320 is formed on the structure shown.

[0214] Reference Fig.40 , a contact hole H penetrating the first interlayer insulating film 150 and the second interlayer insulating film 320 is formed. The contact hole H may be formed on the sidewall of the gate electrode 124 and the sidewall of the second mask pattern 310. The contact hole H may be formed by a SAC process.

[0215] Reference Fig.41 , a contact 160 is formed filling the contact hole H. Therefore, a sidewall of the contact 160 may be defined by a sidewall of the second interlayer insulating film 320 , a sidewall of the second mask pattern 310 , and a sidewall of the gate spacer 126 .

[0216] Reference Fig.42 , a planarization process is performed. The planarization process may be continued until the top surface of the second mask pattern 310 is exposed.

[0217] Reference Fig.43 , the second mask pattern 310 is removed. As a result, a third trench T3 is formed in the first interlayer insulating film 150.

[0218] Reference Fig.44 , a capping pattern 140 is formed in the third trench T3. Thus, the etch stop layer 130 filling the upper portion TU of the trench T and the capping pattern 140 may be formed.

[0219] The semiconductor device shown in each figure may be, for example, a semiconductor chip, which may be included in a package such as a semiconductor package. The semiconductor chip may be a logic chip or a memory chip. The semiconductor device may include a semiconductor chip combined with a semiconductor chip. Figures 1 to 16 , Fig.28A , Fig.28B and Fig.44 One or more of the various structures described.

[0220] Although the concept of the present invention has been specifically shown and described with reference to exemplary embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the present invention as defined by the appended claims. Therefore, it is desired that the disclosed embodiments be considered in all respects as illustrative and not restrictive, and reference is made to the appended claims rather than the preceding description to determine the scope of the present invention.

Claims

1. A semiconductor device, comprising: substrate; a gate electrode located on the substrate; a first spacer located on a sidewall of the gate electrode; a conductive contact on a sidewall of the first spacer, the conductive contact protruding beyond a top surface of the gate electrode; a trench defined by a top surface of the gate electrode, a top surface of the first spacer, and a sidewall of the conductive contact; an etch stop layer extending along at least a portion of a sidewall of the trench and a bottom surface of the trench; as well as a capping pattern located on the etch stop layer and filling the trench, wherein the capping pattern comprises silicon oxide or a low-k material having a dielectric constant lower than that of silicon oxide, The uppermost surface of the etch stop layer and the uppermost surface of the capping pattern are coplanar, A portion of the etch stop layer is between the conductive contact and the capping pattern, A sidewall of the capping pattern adjacent to the conductive contact includes a first sidewall portion and a second sidewall portion, the second sidewall portion being formed above the first sidewall portion and having a slope smaller than a slope of the first sidewall portion, and The etch stop layer includes a first film and a second film, the first film extending along the first sidewall portion and along the top surface of the gate electrode, the second film extending along the first sidewall portion and the second sidewall portion and along the sidewall of the first spacer, or the second film is formed on the first film and extends along the bottom surface of the covering pattern and the first sidewall portion and the second sidewall portion.

2. The semiconductor device according to claim 1, wherein The coverage pattern includes voids.

3. The semiconductor device according to claim 1, wherein The etch stop layer includes at least one of aluminum nitride, aluminum oxide, silicon oxide, silicon nitride, and combinations thereof.

4. The semiconductor device according to claim 1, further comprising: a second spacer, the second spacer being located between the first spacer and the conductive contact and protruding beyond a top surface of the first spacer, The conductive contact extends along a sidewall of the capping pattern and along a sidewall of the second spacer.

5. The semiconductor device according to claim 4, wherein: A sidewall of the second spacer adjacent to the conductive contact includes a third sidewall portion and a fourth sidewall portion, the fourth sidewall portion being formed above the third sidewall portion and having a slope less than a slope of the third sidewall portion, and The slope of the second side wall portion is smaller than the slope of the fourth side wall portion.

6. The semiconductor device according to claim 5, wherein: The second spacer includes silicon nitride.

7. A semiconductor device comprising: substrate; an interlayer insulating film formed on the substrate and including a trench having a lower portion and an upper portion; a gate electrode filling a lower portion of the trench; an etch stop layer extending along at least a first sidewall of an upper portion of the trench and along a top surface of the gate electrode; a capping pattern formed on the etch stop layer and filling an upper portion of the trench; as well as forming a conductive contact on a sidewall of the gate electrode and a sidewall of the capping pattern, the conductive contact penetrating the interlayer insulating film, wherein the etch stop layer at least partially extends along a portion of a sidewall of the conductive contact, The capping pattern includes silicon oxide or a low-k material having a dielectric constant lower than that of silicon oxide, The uppermost surface of the etch stop layer and the uppermost surface of the capping pattern are coplanar, A portion of the etch stop layer is between the conductive contact and the capping pattern, A sidewall of the capping pattern adjacent to the conductive contact includes a first sidewall portion and a second sidewall portion, the second sidewall portion being formed above the first sidewall portion and having a slope smaller than a slope of the first sidewall portion, and The etch stop layer includes a first film extending along the first sidewall portion and along a top surface of the gate electrode, and a second film formed on the first film and extending along a bottom surface of the capping pattern and the first and second sidewall portions.

8. The semiconductor device according to claim 7, further comprising: a gate spacer located on a sidewall of the gate electrode; The lower portion of the trench is defined by the top surface of the substrate and the sidewalls of the gate spacer.

9. The semiconductor device according to claim 7, wherein: The conductive contact includes an extension portion and an expansion portion, the extension portion extending along the first sidewall portion of the capping pattern, the expansion portion being formed on the extension portion and extending along the second sidewall portion of the capping pattern, and The width of the expansion portion is greater than the width of the extension portion.

10. The semiconductor device according to claim 7, wherein: The etch stop layer extends along a side wall of an upper portion of the trench adjacent to the interlayer insulating film, along a top surface of the gate electrode, and along the first side wall portion.

11. The semiconductor device according to claim 7, wherein: The interlayer insulating film and the capping pattern include the same material.

12. The semiconductor device according to claim 7, wherein: The substrate includes a fin pattern extending along a first direction, and The gate electrode extends in a second direction intersecting the first direction.

13. The semiconductor device according to claim 12, further comprising: an epitaxial pattern located on a sidewall of the gate electrode and in the fin pattern, Wherein, the conductive contact is electrically connected to the epitaxial pattern.

14. A semiconductor device comprising: substrate; a gate electrode located on the substrate; a gate spacer located on a sidewall of the gate electrode; a covering pattern covering a top surface of the gate electrode and a top surface of the gate spacer; an interlayer insulating film formed on the substrate and adjacent to the gate spacer and the capping pattern; a conductive contact penetrating the interlayer insulating film and defined by a sidewall of the gate spacer and a sidewall of the capping pattern; as well as an etch stop layer extending along the sidewalls of the interlayer insulating film and along the bottom surface and the sidewalls of the capping pattern, wherein the capping pattern and the interlayer insulating film comprise the same material; and The sidewall of the capping pattern adjacent to the conductive contact includes a first sidewall portion and a second sidewall portion, the second sidewall portion is formed above the first sidewall portion, and a slope of the second sidewall portion is smaller than a slope of the first sidewall portion, The uppermost surface of the etch stop layer and the uppermost surface of the capping pattern are coplanar, A portion of the etch stop layer is interposed between the conductive contact and the capping pattern, and The etch stop layer includes a first film and a second film, the first film extending along the first sidewall portion and along the top surface of the gate electrode, the second film extending along the first sidewall portion and the second sidewall portion and along the sidewall of the gate spacer, or the second film is formed on the first film and extends along the bottom surface of the covering pattern and the first sidewall portion and the second sidewall portion.

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