Method and apparatus for error handling in communications between distributed software components

Abstract

A method and device for error handling in communication, by reading from a first data area for temporary data storage and storing the read data in a second data area for temporary data storage to communicate data to be communicated between a first task and a second task in a data transmission interval, presetting a time interval for executing the first task and a communication interval for executing the second task, a) if the first task is directly before the communication interval in time in a time interval of the communication interval directly before the communication interval, wherein the last time interval has started, continues beyond the end time point of the last time interval, and execution of the second task in the communication interval has started, execution of the data transmission interval is omitted in the communication interval; or b) if the second task is directly before the communication interval in time in a communication interval, continues beyond the end time point of the previous communication interval, and execution of the first task has started in the first communication interval, execution of the data transmission interval is omitted in the first communication interval.

Description

Technical Field

[0001] The invention relates to a method and a device for error handling in communication between software components, wherein the software components are distributed over two or more tasks, wherein the tasks are executed in particular in time intervals with different predefined cycle times. Background Art

[0002] Due to an error, the expiration of a cycle time, ie, a time interval, can occur before the termination of a task whose results are to be handed over to other tasks at the expiration of the time interval. For such errors, deterministic error handling is desirable. Summary of the invention

[0003] This is achieved by a method and a device according to the independent claims.A computer program and a computer program product are likewise provided.

[0004] In a method for error handling in communication, a time interval is predefined for executing a first task and a communication interval is predefined for executing a second task, wherein in the method, data to be communicated are communicated between the first task and the second task in the data transmission interval by reading from a first data area for temporary data storage and by storing the read data in a second data area for temporary data storage, wherein:

[0005] a) omitting the execution of the data transmission interval in the first communication interval if a first task which directly precedes a first communication interval in time has already started in the last time interval of the communication interval directly preceding the communication interval and is continued beyond the end time of the last time interval, and the execution of the second task of the first communication interval has already started; or

[0006] b) If the second task has already begun in a second communication interval immediately preceding the first communication interval in terms of time, is continued beyond the end time of the preceding second communication interval, and the execution of the first task has already begun in the first communication interval, the execution of the data transmission interval is omitted in the first communication interval. The time interval and the communication interval are logical intervals of the scheduler, which can be based on fixed time slices and cannot be shifted. However, the described implementation of the scheduler does not force compliance with the logical interval, but only considers the actual interval as ended when the scheduler actually implements the execution of the task in a new interval immediately following the actual interval. As a result, deterministic communication is also possible in the case of load peaks, which affect the computing system in such a way that the task cannot comply with the end of the logical interval assigned to the task for executing the task. This achieves effective error handling with different specific details, according to different, predefined, statistical task distributions and categories of task scheduling. This is an effective error handling solution for sporadic failures in task execution.

[0007] Preferably, if the execution of the first task is terminated later than the execution of the second task, the start of the data transfer interval is triggered by the termination of the execution of the first task; or if the execution of the second task is terminated later than the execution of the first task, the start of the data transfer interval is triggered by the termination of the execution of the second task.

[0008] Preferably, if the execution of the first task continues beyond the end of a communication interval in which the execution of the first task has already begun, and if the start of a data transmission interval is triggered by the end of the execution of the first task, the execution of the second task following the execution of the first task is delayed until the end of the data transmission interval. Inconsistent data therefore do not occur.

[0009] Preferably, if the execution of the second task continues beyond the end of a communication interval in which the execution of the second task has already begun, and if the start of the data transmission interval is triggered by the end of the execution of the first task, the triggering of the data transmission interval does not occur in the communication interval. Therefore, inconsistent data does not occur.

[0010] Preferably, the data to be communicated in the data transmission interval is communicated via one or more entities outside the hardware for executing the first task and the second task. By transferring the communication tasks to one or more entities, deterministic processing is ensured, for example, via direct memory access, DMA, or interrupt service routines, ISRs.

[0011] The error handling concept mentioned ensures that data consistency is guaranteed at all times. The execution of a transaction or task for communication is only canceled if data consistency can no longer be guaranteed in other respects. The error handling concept enables the system load to be reduced by the failure of the execution of individual tasks and by the failure of individual transactions in order to increase the robustness of the overall system. The error handling concept can access scheduling information in order to detect runtime errors, such as multiple process activations.

[0012] Preferably, the duration of the communication interval is an integer multiple of the duration for the time interval, wherein the communication interval comprises a plurality of time intervals, wherein the earliest of the plurality of time intervals starts simultaneously with the communication interval. Thus, the logical intervals are synchronized.

[0013] Preferably, during the communication interval, at least one time interval begins, wherein the time intervals do not overlap in time, wherein the data transmission interval ends either in the earliest of the plurality of time intervals before the first execution of the first task or in the latest of the plurality of time intervals after the last execution of the first task ends. Cooperative scheduling ensures that the communication ends completely before the execution of the first task occurs in a new interval. In preemptive scheduling, the scheduler ensures that no interruptions occur by the participating processes and that processes with a lower priority are squeezed out if necessary.

[0014] Preferably, a state variable is determined as a function of a first state of execution of the first process and as a function of a second state of execution of the second process, wherein a data transmission interval is started as a function of the value of the state variable. The state variable is determined, for example, by means of a first counter reading of a first state counter for the first state and by means of a second counter reading of a second state counter for the second state.

[0015] Advantageously, if one of the first processes that should have run during the communication interval fails in the communication interval and the execution of the first task therefore fails because, with the exception of the last of the first processes that should have run during the communication interval, it is not terminated at the end of the first time interval assigned to the processes, the first state counter is corrected to the state it would have had when executing the already failed first task.

[0016] Advantageously, the state variable is determined as a function of the following priorities, wherein the priorities are assigned to the first task and the second task, wherein if the task to which the lowest priority is assigned is executed as the last task in one of the communication intervals, the start of the following data transmission interval is shifted to the immediately following communication interval, wherein the data transmission interval immediately follows the termination of the task with the lowest priority. The task with the highest priority is activated first or simultaneously with other tasks in the time interval. If the communication interval has already ended, the task with the lowest priority is also continued. The communication then takes place in the data transmission interval.

[0017] With respect to a device for error handling in communication, a processor and at least one temporary data memory are provided, which are constructed to communicate data to be communicated between a first task and a second task according to one of the methods in a data transmission interval by reading from a first data area of ​​the at least one temporary data memory and by storing the read data in a second data area of ​​the at least one temporary data memory.

[0018] Advantageously, the device comprises means for communicating the data to be communicated by means of direct memory access, ie DMA, or by means of an interrupt service routine. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Further advantageous embodiments are apparent from the following description and the accompanying drawings. In the drawings:

[0020] Figure 1 schematically illustrates a time-controlled first behavior of a task;

[0021] Figure 2 A first error handling scheme is schematically illustrated;

[0022] Figure 3 A second error handling scheme is schematically illustrated;

[0023] Figure 4 schematically illustrating a time-controlled second behavior of a task;

[0024] Figure 5 A third error handling scheme is schematically illustrated;

[0025] Figure 6 A fourth error handling scheme is schematically illustrated;

[0026] Figure 7 schematically illustrates a time-controlled third behavior of a task;

[0027] Figure 8 A fifth error handling scheme is schematically illustrated;

[0028] Fig. 9 A sixth error handling scheme is schematically illustrated;

[0029] Fig.10 Devices for communication are schematically shown. DETAILED DESCRIPTION

[0030] A task is a computer program at runtime, the execution of which is dynamically monitored by the operating system through certain activities. The tasks are managed by the task control of the operating system, which is also called a scheduler. The task control can either continue to calculate a task until it is terminated or ensure that the running task is interrupted after a short duration. The task control can thus switch back and forth between different active tasks. Tasks can be of different lengths and start at different times.

[0031] For the temporal execution of the tasks, a repetitive time interval for the periodic execution of the first task is set in the task control device, and a repetitive time interval for the periodic execution of the second task is set. In the example, the duration of the time interval for the second task is longer than the duration of the time interval for the first task. For example, the time interval for the first task has a length of 5 ms. For example, the time interval for the second task has a length of 10 ms. The time intervals are logical intervals of the scheduler, wherein the logical intervals can be based on fixed time slices and cannot be shifted.

[0032] The software components in a task can exchange data with each other. For communication between the tasks, the data can be stored in a temporary data memory, especially a buffer. For communication, the data to be communicated is communicated between the first task and the second task in a data transmission interval, for example, by reading from a first buffer and storing the read data in a second buffer. In the example, the first task is assigned a first channel, which has a first 5ms buffer for read-only access and a second 5ms buffer for read and write access. In the example, the second task is assigned a second channel, which has a first 10ms buffer for read-only access and a second 10ms buffer for read and write access. In general, n channels with 2n such buffers can be set for n tasks.

[0033] The implementation of the scheduler described according to the following example does not enforce compliance with the logical intervals, but rather considers the actual interval as ended only when the scheduler actually also carries out the execution of tasks in the new interval following the actual interval. In general, the error situations described below can be classified in error handling in communication between tasks.

[0034] Scheduling Error:

[0035] a) The schedule is incomplete or non-deterministic;

[0036] b) The task is not activated (has been omitted);

[0037] c) the task is spontaneously activated;

[0038] d) The channel's buffer is used before it is initialized.

[0039] Load-related errors:

[0040] a) Task termination is exceeded (in case of multiple task activations);

[0041] b) the communication has not been terminated during the last data transmission interval;

[0042] c) Communication has not been performed in the last data transmission interval.

[0043] Memory Error:

[0044] a) The channel status is corrupted.

[0045] Scheduling errors a) to c) can be detected only with the aid of an external time reference, for example a clock or a counter.

[0046] The remaining errors can be reliably detected with the aid of the channel state machine. The following example describes the details of the communication method and error detection and error correction based on the channel state machine.

[0047] An algorithm for selecting a communication method and / or an error handling scheme in a computing system based on scheduling information uses the assignment of tasks to cores, the scheduling type, for example preemptive or cooperative, as well as the priorities of the tasks participating in the communication and a possible sequential execution via an activation mode in the system.

[0048] The category "concurrency level" is determined. A communication method and / or a corresponding error handling scheme is assigned to the category.

[0049] The possible categories for "Concurrency Level" are:

[0050] Cooperative Core Local:

[0051] Tasks participating in the communication have only cooperative scheduling and are executed on the same computing core.

[0052] Preemtive Core Local:

[0053] Tasks participating in the communication have preemptive scheduling and are executed on the same computing core.

[0054] Parallel Cross Core:

[0055] The task is executed on at least two computing cores.

[0056] Sequential Core Local:

[0057] Tasks are executed sequentially on the same computing core.

[0058] Sequential Cross Core:

[0059] Tasks are executed sequentially on at least two computing cores.

[0060] according to Figure 1 To describe the communication method for communications in the category "Cooperative Core Local".

[0061] The communication method achieves: distribution of the communication load to all participating tasks. The communication behavior achieves: efficient deterministic communication in real-time systems. In this case, the state variable S is used to determine the communication time point. The state variable S can exhibit one of the following states: The state is also denoted as the phase of the state variable below.

[0062] PROC_ACTIVE:

[0063] At least one of the participating tasks uses the data provided in the buffer. Overwriting of the read buffer is not permitted for consistency reasons.

[0064] PROC_COMPLETE:

[0065] All tasks have completed the number of activations required in a logical interval (taking into account possible error scenarios) and the provided data are no longer required in this logical interval.

[0066] TRANS_ACTIVE:

[0067] The read buffers of the individual tasks are updated. Calculations with the data contained therein are not permitted for consistency reasons.

[0068] TRANS_COMPLETE:

[0069] The update of the buffer is finished. The data can be used for calculations. However, no tasks are active.

[0070] In the communication interval, the state variable S goes through the states PROC_ACTIVE, PROC_COMPLETE, TRANS_ACTIVE, TRANS_COMPLETE, in the order described. The states PROC_COMPLETE and TRANS_COMPLETE can be skipped. In each communication interval, a data transmission interval K should be executed. During the data transmission interval K, the buffer is accessed in a write and or read manner to update the buffer. The communication interval is defined synchronously with the logical interval of the scheduler as described in the following example. In the described example, if at least one task is executed, the state variable S is then always placed in the state PROC_ACTIVE. The state variable S is placed in the state TRANS_ACTIVE during the data transmission interval K. The state PROC_COMPLETE is set after all executions of the communication interval are terminated. The state TRANS_COMPLETE is set only after the data transmission interval is terminated.

[0071] For communications that occur periodically, the communication interval I2 is calculated from the intervals T1, T2, ... Tn that should communicate with each other, as the lowest common multiple, KGV.

[0072] Tn represents the interval of task n. The logical interval is defined in time to run synchronously with the period (Periode) of each task. The task is activated by the scheduler. Until the end of the communication interval I2, all tasks and data transmission intervals K should be executed. Deadlines are assigned to each task, and the task must be terminated by the deadline. If the calculation of the task cannot be terminated in time before the deadline assigned to the task after its activation, the subsequent activation of the task is not performed by the scheduler. If the calculation of the task is terminated in time before the deadline assigned to the task after its activation, but the data transmission interval K set in the communication interval I2 is not terminated, error handling for the communication is required.

[0073] For those from Figure 1 The example in is for communication intervals:

[0074] I2 = KGV (10ms, 5ms) = 10ms.

[0075] Other common multiples can also be used instead of KGV.

[0076] In the following, according to Figure 1 To describe how the phases of the state variable S are sequentially experienced, the state variable S is determined according to a first state of execution of a first task and according to a second state of execution of a second task.

[0077] The communication takes place in data transmission intervals K, wherein the data transmission intervals are started depending on the value of the state variable S.

[0078] The state variable S is determined, for example, by means of a first counter reading of a first state counter Z1 for the first state and by means of a second counter reading of a second state counter Z2 for the second state. The first state counter can be as described in Figure 1 As shown, the second state counter can be as shown in Figure 1 The states 1 and 0 are shown as shown in .

[0079] The first state counter Z1 is Figure 1The time course shown in FIG. 1 starts on the left with a first counter reading of 2. At time t1, which starts synchronously with the first logical interval I1, the first execution of the first task T1 starts. At time t2, when the first execution of the first task T1 ends, the first counter reading is set to 1. At time t3, which starts synchronously with the first repetition of the first logical interval I1, the second execution of the first task T1 starts. At time t4, when the second execution of the first task T1 ends, the first counter reading is set to 0.

[0080] Next, at time point t4, a data transmission interval K is started. The data transmission interval K ends at time point t5. At time point t5, the first counter reading is set to 2.

[0081] The second and third repetitions of the first logical interval I1 are Figure 1 In the second repetition, the third execution of the first task T1 starts synchronously with the second repetition of the first logic interval I1 at time t6 and ends at time t7. The first counter reading is set from 2 to 1 at time t7.

[0082] In the third repetition, the fourth execution of the first task T1 starts at time t8 synchronously with the third repetition of the first logic interval I1 and ends at time t9. The first counter reading is set from 1 to 0 at time t9.

[0083] The second state counter Z2 is Figure 1 1 starts on the left with the second counter reading 1. At time t1, the second logic interval I2 starts synchronously with the first logic interval I1. The first execution of the second task T2 starts at time t2 after the termination of the first execution of the first task T1, that is, the first task T1 is processed as the second task T2 between time t1 and time t2.

[0084] The first execution of the second task T2 ends at time t10, before time t3 in the example. At time t10, the second counter reading is set from 1 to 0. At the end of the data transmission interval K, that is, at time t5, the second counter reading is set from 0 to 1.

[0085] The repetition of the second logic interval I2 is Figure 1. At time point t6, the repetition of the second logical interval I2 starts synchronously with the third repetition of the first logical interval I1. The second execution of the second task T2 starts at time point t7 after the third execution of the first task T1 is terminated. That is, the first task T1 is processed as the second task T2 between time point t6 and time point t7. In the repetition, the second execution of the second task T2 is interrupted between time points t8 and t9 for the fourth execution of the first task T1 so as to perform the fourth repetition of the first task T1. At time point t9, the repetition of the second task T2 is continued and terminated at time point t11. At time point t11, the second counter reading is set to 0 and the data transmission interval K is repeated. The repetition of the data transmission interval K terminates at time point t12. The first counter reading is set to 2 at time point t12. The second counter reading is set to 1 at time point t12.

[0086] Between the time points t1 and t4 and t6 and t9, access to the first 5ms buffer B51 and the second 5ms buffer B52 is allowed. Between the time points t1 and t10 and t6 and t11, access to the first 10ms buffer B101 and the second 10ms buffer B102 is allowed. In the example, access from the 5ms task is performed between t1 and t2, t3 and t4, t6 and t7 and t8 and t9, that is, during the execution of the first task T1. Access from the 10ms task is performed in the example between t2 and t10, that is, during the first execution of the second task T2, and between t6 and t7, that is, preemptively before the repeated execution of the second task T2. In the data transmission interval K, access to all buffers is prohibited for the task. Access from the task to the first 5ms buffer B51 and the first 10ms buffer B101 is prohibited during the data transmission interval K. Figure 1 Accesses from the task to other buffers are shown in Figure 1 In the data transmission interval K, the second 5 ms buffer B52 is written to the second 10 ms buffer B102 and the first 10 ms buffer B101 is written to the first 5 ms buffer B51.

[0087] The state variable S has the state PROC_ACTIVE between the times t1 and t4.

[0088] The state variable S has the state TRANS_ACTIVE between the times t4 and t5 , wherein between these times both the first state counter Z1 has the first state value 0 and the second state counter Z2 has the second state value 0 .

[0089] The state variable S has the state TRANS_COMPLETE between the points in time t5 and t6.

[0090] The state variable S has the state PROC_ACTIVE between the times t6 and t11.

[0091] The state variable S has the state TRANS_ACTIVE between the times t11 and t12 , wherein between these times both the first state counter Z1 has the first state value 0 and the second state counter Z2 has the second state value 0 .

[0092] The state variable S is Figure 1 From time t12 onwards, the state is TRANS_COMPLETE.

[0093] Since communication takes place in the context of the task (in context), PROC_COMPLETE is a purely logical state in the context, which is cancelled in the case of a direct transition from PROC_ACTIVE to TRANS_ACTIVE.

[0094] In the actual execution of the task, the communication interval actually necessary for the complete execution of the task and the communication may deviate from the communication interval due to the mentioned errors. Figure 2 and Figure 3 For Figure 1 For the elements described, the same reference numerals are used and reference is made to Figure 1 Description.

[0095] and Figure 1 The situation shown in Figure 2 As shown in FIG. 1 , during the first repetition of the first logical interval I1, the second execution of the first task T1 is interrupted at time t20. The second execution is continued at time t21 before time t6 and terminated at time t22 before time t6. At time t6, the data transmission interval K is started. The data transmission interval K terminates at time t23, wherein the time t23 is after time t6 in this example. This means that the data transmission interval K terminates after the start of the second repetition of the first logical interval I1.

[0096] The second execution of the second task T2 starts at time point T23. Therefore, the second execution of the second task T2 obtains the latest data from the first task T1. The third execution of the first task T1 is prohibited in the third repetition of the first interval I1. Therefore, the second execution of the second task T2 can be ended before the end of the third repetition of the first interval I1.

[0097] and Figure 1 The conditions shown in are different, such as Figure 3 As shown in , the first execution of the second task T2 is interrupted at time point t3 during the first repetition of the first logical interval I1. The second execution of the first task T1 starts at time point t30 after time point t3 and ends at time point 31 before time point t6, that is, during the first repetition of the first logical interval I1. At time point t31, the first execution of the second task T2 is continued. At time point t6, the first execution of the second task T2 is interrupted again so that the third execution of the first task T1 is performed until time point T32. At time point T32, the first execution of the first task T1 is continued and ends at time point t33 before time point t8. At time point t8, the fourth execution of the first task T1 begins. At time point t34, the fourth execution of the first task T1 ends. At time point t34, the data transmission interval K is started. The data transmission interval K ends at time point t35.

[0098] The second execution of the second task T2 is inhibited during the repetition of the second logic interval I2.

[0099] By suppressing, i.e. omitting, the corresponding execution, the computing system is deloaded deterministically. Exceeding the logical interval limit by the task being executed is referred to below as a task deadline violation. As a reaction to such a task deadline violation, the next periodic task execution is caused to fail via the communication infrastructure.

[0100] Basically, two variants should be distinguished here.

[0101] Variant 1:

[0102] Deadline violations occur during the last execution of a task during a data transfer interval.

[0103] In variant 1, a distinction is made between two further variants:

[0104] Variant 1A:

[0105] The deadline violation occurred before the transaction started. One of the participating tasks has already started with the calculation in a new interval. The state transition from PROC_ACTIVE is transitioned to a new data transmission interval. The update of the buffer is canceled.

[0106] Variant 1B:

[0107] Here, as in Figure 2As shown in , the buffer update has occurred. The state TRANS_ACTIVE is set and a deadline violation occurs. The cooperative scheduling ensures that the communication is completely completed before the first task execution occurs in the new interval.

[0108] Variant 2:

[0109] The deadline violation did not occur during the data transmission interval in the last execution of the task.

[0110] In variant 2, only the counter readings that are falsified by a failure in task execution are corrected. This has no effect on the communication.

[0111] exist Figure 4 , a communication method for communication corresponding to the category "Parallel Cross Core" is shown. For elements with identical reference numerals, reference is also made to the reference numerals in the description. Figure 1 Description.

[0112] Unlike the previously described examples, the tasks are also calculated in parallel. Furthermore, the communication is implemented in the data transmission interval K by means of a module 400 for communicating the data to be communicated by means of direct memory access, i.e. DMA, or by means of an interrupt service routine. A first trigger 301 is used to start the data transmission interval K, and a second trigger 302 is used to start the repetition of the data transmission interval K.

[0113] By offloading the communication tasks to one or more entities, such as DMA hardware or ISRs, deterministic processing is ensured. These entities can also be prioritized in accordance with the requirements and enable the communication load to be distributed to other computing cores or dedicated hardware resources.

[0114] As in Figure 4 As shown in , only the activation of the update occurs in each of the tasks. The actual update of the buffer is carried out by other entities. Since all participating tasks can run completely in parallel, the status must be checked at the beginning of execution.

[0115] In the case of TRANS_ACTIVE, the execution is delayed until the updating of the data is complete. When using the Basic Task Model, this is achieved by busy waiting. Only in this case is the state TRANS_COMPLETE set, in which the updating takes place.

[0116] In this case, an error handling scheme for sporadic failures in the execution of the task is implemented for communications corresponding to the class "Parallel Cross Core". Figure 5 and Figure 6 For elements with identical reference numerals, reference is also made to Figure 2 Description.

[0117] Unlike the example described above, the first execution of the second task is interrupted at time t51 after time t2 and continued at time t52 before time t3. In addition, the first execution of the second task T2 is terminated at time t53 after time t3 and after time t20 and before time t21. This means that the first task and the second task are calculated in parallel at least temporarily in the example.

[0118] Furthermore, the communication is implemented in the data transmission interval K by means of a module 400 for transmitting the data to be transmitted by means of direct memory access, ie DMA, or by means of an interrupt service routine. A third trigger 501 is used to start the data transmission interval K, wherein the third trigger is triggered when the second execution of the first task T1 ends.

[0119] exist Figure 6 As shown in Figure 3 For elements with identical reference numerals, reference is made to Figure 3 Description.

[0120] Unlike the previously described example, the first execution of the second task T2 is not continued at time t31, but already at time t61, wherein the time t61 is before time t31 and after time t30. In addition, the first execution of the second task T2 is not interrupted at time t6. This means that the first task and the second task are calculated in parallel in the example at least temporarily.

[0121] In contrast to the previously described examples, the communication is implemented in a data transmission interval K by means of a module 400 for communicating the data to be communicated by means of direct memory access, i.e. DMA, or by means of an interrupt service routine. A fourth trigger 601 is used to start the data transmission interval K, wherein the fourth trigger is triggered when the fourth execution of the first task T1 is terminated.

[0122] exist Figure 7 , for the communication corresponding to the category "Preemptive Core Local", the communication of the error handling scheme for occasional failures in task execution is shown. For elements with consistent reference numerals, reference is also made to the reference numerals for Figure 1Description.

[0123] In the following, according to Figure 7 In the example described, the tasks are calculated sequentially. The first task T1 is calculated here with a higher priority than the second task T2. This means that the scheduler interrupts the execution of the second task T2 as soon as the first task T1 needs to be calculated according to its schedule.

[0124] In the example, Figure 7 In the time sequence shown in , at time t1, both the first logic interval I1 and the second logic interval I2 start synchronously. The first counter reading is at the value 2 at the start, and the second counter reading is at the value 1 at the start. The state variable S has the state TRANS_COMPLETE before time t1 and has the state PROC_ACTIVE from time t1. Based on the prioritization, the first execution of the first task T1 starts at time t1 and ends at time t2. At time T1, the first counter reading is set to 1. The execution of the second task T2 starts at time t2 and is interrupted at time t3, wherein at time t3, the first repetition of the first logic interval I1 starts simultaneously with the second execution of the first task T1. At time t4, the second execution of the first task T1 ends and the first counter reading is set to 0. The execution of the second task T2 is continued at time t4 and ends at time t5, at which time t5 the second counter reading is set to 0. The state variable S is set to the value PROC_COMPLETE at time t5.

[0125] Since the execution of the second task T2 has terminated after the second execution of the first task T1, the data transmission interval K does not start until the time t6, wherein the second repetition of the first logical interval I1 and the repetition of the second logical interval I2 start synchronously at the time t6. The state variable S is set to TRANS-ACTIVE between the time points t6 and t7. The third execution of the first task T1 starts at the end of the data transmission interval K at the time point t7. At the time point t7, the first counter reading is set to 2, the second counter reading is set to 1 and the state variable S is set to PROC_ACTIVE.

[0126] The third execution of the first task T1 ends at time t8, wherein at said time t8 the first counter reading is set to 1. The repetition of the execution of the second task T2 begins at time t8 and ends at time t9, wherein at said time t9 the second counter reading is set to 0. At time t10, which follows after time t9, the third repetition of the first logic interval I1 and the fourth execution of the first task T1 begin. At time t11, the fourth execution of the first task T1 ends. The first counter reading is set to 0. Since the repetition of the second task T2 has ended at time t11, the state variable S is set to the state TRANS_ACTIVE. The repetition of the communication interval begins at time t11 and ends at time t12. At time t12, the state variable S is set to the state TRANS_COMPLETE. The first counter reading is set to the value 2 and the second counter reading is set to the value 1. The access of the tasks to the buffer occurs during the execution of the tasks as described above.

[0127] In this case, the following error handling scheme is possible, wherein the error handling scheme is based on Figure 8 and Fig. 9 Further elaboration. With respect to elements having identical reference numerals, Figure 8 Also refer to Figure 2 Description and about Fig. 9 Also refer to Figure 3 Description.

[0128] exist Figure 8 In the example shown in , the first task T1 is executed with a higher priority than the second task T2. At time point t22, the second execution of the first task T1 is terminated. At time point t22, the data transmission interval K begins. The time point t22 is shortly before the time point t6, wherein at the time point t6, the second repetition of the first interval I1 should begin. The data transmission interval K therefore also begins during the second logical interval I2, but continues beyond the time point t6 until the time point t23. Therefore, the repetition of the second task T2 is delayed until the end of the data transmission interval K, that is, until the time point t23. Despite the higher priority of the first task T1, in this case the second task T2 is executed in an uninterrupted manner because the first task T1 is omitted in the second repetition of the first interval I1. This means that although the first task T1 is executed with a higher priority, the first task T1 is omitted for error handling, if this is necessary.

[0129] exist Fig. 9In the example shown in , the first task T1 is executed with a higher priority than the second task T2. The execution of the second task T2 continues until the time point t33, which is after the time point t6, that is, within the repetition of the second logical interval I2. The second task T2 is executed until its termination. Since the data transmission interval K has not been executed by then, the repetition of the second task T2 is not executed, but is cancelled in a manner independent of the priority of the tasks.

[0130] If one of the scheduling errors "d) channel buffer used before it was initialized", the load-related errors "a) task termination exceeded (in case of multiple task activation)", "b) communication not already terminated in the last data transmission interval", c) "communication not already executed in the last data transmission interval" or the memory error "a) channel status corrupted" is detected, then in the example either the task is deactivated or the data transmission interval K is shifted. In this example, the task is deactivated because the execution of the task is not activated by the scheduler. The data transmission interval is shifted in this example because the scheduler activates the execution of the task and the data transmission interval at a suitable point in time.

[0131] The application of the individual communication methods and error handling schemes is not limited to the mentioned category "Concurrency Level". They can also be applied in other contexts or categories such as "Sequential Core Local" or "Sequential Cross Core".

[0132] The communication method and error handling scheme are not limited to communication between two tasks. In the figure, execution with more than two tasks is omitted for clarity.

[0133] The device 1000 for communication is Fig.10 The device 1000 comprises a processor 1001 and at least one temporary data memory 1002, which is configured to communicate data to be communicated between a first task T1 and a second task T2 in a data transmission interval K according to the described method by reading from a first data area B51, B52 of the at least one temporary data memory 1002 and by storing the read data in a second data area B101, B102 of the at least one temporary data memory 1002.

[0134] In the example, the device according to the claim comprises a module 1003 which, as described for the module 400 , is designed to communicate the data to be communicated by means of direct memory access, DMA, or by means of an interrupt service routine.

Claims

1. A method for error handling in communication, wherein in the method, data to be communicated are communicated between a first task (T1) and a second task (T2) in a data transmission interval (K) by reading from a first data area for temporary data storage and by storing the read data in a second data area for temporary data storage, characterized in that A time interval (I1) is predefined for executing the first task (T1), and a communication interval (I2) is predefined for executing the second task (T2), wherein: a) if a first task (T1) immediately preceding a first communication interval (I2) in time has already started in the last time interval (I1) of a second communication interval (I2) immediately preceding the first communication interval (I2), is continued beyond the end time point (t6) of the last time interval (I1), and execution of the second task (T2) of the first communication interval (I2) has already started, then execution of the data transmission interval (K) is omitted in the first communication interval (I2); or b) If a second task (T2) has already started in a second communication interval (I2) that directly precedes the first communication interval (I2) in time and is continued beyond the end time point (t6) of the preceding second communication interval (I2), and execution of the first task (T1) has already started in the first communication interval (I2), execution of the data transmission interval (K) is omitted in the first communication interval (I2).

2. The method according to claim 1, characterized in that: If the execution of the first task (T1) is terminated later than the execution of the second task (T2), the start of the data transmission interval (K) is triggered by the termination of the execution of the first task (T1) (301, 501); or if the execution of the second task (T2) is terminated later than the execution of the first task (T1), the start of the data transmission interval (K) is triggered by the termination of the execution of the second task (T2) (302, 601).

3. The method according to claim 2, characterized in that If the execution of the first task (T1) continues beyond the termination of the following communication interval (I2): the execution of the first task (T1) has started in the communication interval (I2), and if the start of the data transmission interval (K) is triggered (501) by the termination of the execution of the first task (T1), then the execution of the second task (T2) immediately after the execution of the first task (T1) is delayed until the termination of the data transmission interval (K).

4. The method according to claim 2, characterized in that: If the execution of the second task (T2) continues beyond the termination of the following communication interval (I2): the execution of the second task (T2) has started in the communication interval (I2), and if the start of the data transmission interval (K) is triggered (601) by the termination of the execution of the first task (T1), the triggering of the data transmission interval (K) does not occur in the communication interval.

5. The method according to any one of claims 2 to 4, characterized in that The data to be communicated in the data transmission interval (K) is communicated via one or more entities external to hardware for performing the first task (T1) and the second task (T2).

6. The method according to any one of claims 1 to 4, characterized in that The duration of the communication interval (I2) is an integer multiple of the duration of the time interval (I1), wherein the communication interval (I2) includes one or more time intervals (I1), wherein the earliest time interval of the multiple time intervals (I1) starts simultaneously with the communication interval (I2).

7. The method according to claim 6, characterized in that During the communication interval (I2), at least one time interval (I1) starts, wherein the time intervals (I1) do not overlap in time, wherein the data transmission interval (K) either ends in the earliest time interval among the multiple time intervals (I1) before the first execution of the first task (T1), or starts in the latest time interval among the multiple time intervals (I1) after the termination of the last execution of the first task (T1).

8. The method according to any one of claims 1 to 4, characterized in that A state variable (S) is determined depending on a first state of execution of the first task (T1) and depending on a second state of execution of the second task (T2), wherein the data transmission interval (K) is started depending on the value of the state variable (S).

9. The method according to claim 8, characterized in that If one of the first tasks (T1) that should be run during the communication interval (I2) is not terminated at the end of the first time interval (I1) assigned to it, with the exception of the last first task among the first tasks (T1) that should be run during the communication interval (I2), so that one of the first tasks (T1) fails in the communication interval (I2) and the execution of the first task (T1) is therefore failed, the first state counter (Z1) is corrected, wherein the first state counter (Z1) is corrected to the state that the first state counter (Z1) may have when executing the first task (T1) that has failed.

10. The method according to claim 8, characterized in that The state variable (S) is determined according to the following priorities, wherein the priorities are assigned to the first task (T1) and the second task (T2), wherein if the task to which the lowest priority is assigned is executed as the last task in one of the communication intervals (I2), the start of the following data transmission interval (K) is shifted to the immediately following communication interval (I2), wherein the data transmission interval (K) immediately follows the termination of the task having the lowest priority.

11. A device (1000) for error handling in communications, characterized in that A processor (1001) and at least one temporary data memory (1002), which is configured to switch between a first task (T1) and a second task (T2) by reading from a first data area (B51, B52) of the at least one temporary data memory (1002) and by storing the read data in a second data area (B101, B102) of the at least one temporary data memory (1002). According to the method according to any one of claims 1 to 10, the data to be transmitted are transmitted in a data transmission interval (K).

12. The device according to claim 11, characterized in that The device comprises means (1003) for communicating the data to be communicated by means of direct memory access, ie DMA, or by means of an interrupt service routine.

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