Gate voltage bootstrap switch circuit, sampling and holding module and electronic device

Abstract

The present invention provides a gate voltage bootstrap switch circuit, a sampling and holding module and an electronic device, wherein the gate voltage bootstrap switch circuit comprises a charge pump and a MOS switch tube used as a switch, wherein the charge pump comprises a gate voltage supply circuit for providing a gate terminal control voltage to the MOS switch tube under the control of a first clock signal, a gate voltage discharge circuit for discharging the gate terminal voltage of the MOS switch tube under the control of a second clock signal, and an auxiliary circuit for providing the voltage of a first power supply to the gate voltage discharge circuit during the conduction phase of the MOS switch tube, wherein the auxiliary circuit can reduce the adverse effects of parasitic capacitance and improve the turn-on efficiency of the MOS switch tube. The sampling and holding module and the electronic device of the present invention adopt the gate voltage bootstrap switch circuit of the present invention, and the performance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a gate voltage bootstrap switch circuit, a sampling and holding module and an electronic device. Background Art

[0002] The high-speed, high-performance sampling capacitor sample-and-hold circuit (Switch-Capacitor Sample & Hold Circuit) is one of the key modules in many integrated circuit applications. The sampling switch is a crucial unit in the sampling capacitor sample-and-hold circuit. Its performance determines the accuracy and linearity of the entire sampling and holding. Therefore, in order to prevent the sampling signal from being distorted, it is necessary to reduce the nonlinearity of the on-resistance of the sampling switch to ensure that the on-resistance of the sampling switch is relatively stable within the entire input signal swing. However, with the increase in the sampling clock frequency and the decrease in the first power supply, the linearity of the traditional MOS switch continues to decrease, limiting the dynamic range and sampling accuracy of the sample-and-hold circuit, and can no longer meet the design requirements of the high-speed, high-precision sampling capacitor sample-and-hold circuit. Summary of the invention

[0003] The object of the present invention is to provide a gate voltage bootstrap switch circuit, a sampling and holding module and an electronic device, which can reduce the adverse effects of parasitic capacitance to improve the turn-on efficiency of the gate voltage bootstrap switch circuit.

[0004] In order to achieve the above-mentioned object, the present invention provides a gate voltage bootstrap switch circuit, comprising a MOS switch tube as a switch, a first power supply, a second power supply and a charge pump connected to the gate terminal and the drain terminal of the MOS switch tube, the source terminal of the MOS switch tube receives an input signal, the charge pump is simultaneously connected to the first power supply and the second power supply, and provides a gate terminal control voltage to the MOS switch tube under the control of a first clock signal, and keeps the gate-source voltage difference of the MOS switch tube unchanged when it is turned on; the charge pump comprises a gate voltage supply circuit, a gate voltage discharge circuit and an auxiliary circuit; the gate voltage supply circuit is used to provide the voltage of the second power supply to the gate terminal or drain terminal of the MOS switch tube under the control of the first clock signal The sum of the voltage of the input signal and the voltage of the first power supply is provided to the gate terminal of the MOS switch tube as the gate terminal control voltage of the MOS switch tube, so that the gate-source voltage difference of the MOS switch tube remains unchanged when it is turned on; the gate voltage discharge circuit is used to discharge the gate terminal control voltage of the gate terminal of the MOS switch tube under the control of a second clock signal that is inverted with the first clock signal, so as to adjust the gate terminal voltage of the MOS switch tube; one end of the auxiliary circuit is connected to the gate voltage discharge circuit, and the other end is connected to the first power supply, so as to provide the voltage of the first power supply to the gate voltage discharge circuit when the MOS switch tube is turned on, so as to serve as a reference voltage of the gate voltage discharge circuit.

[0005] Optionally, the gate voltage supply circuit includes a bootstrap capacitor, a capacitor charging branch, a capacitor discharging branch and a gate voltage control branch; the bootstrap capacitor is used to increase the gate control voltage of the MOS switch tube to the sum of the voltage of the input signal and the voltage of the first power supply when the MOS switch tube is turned on; the capacitor charging branch is respectively connected to the gate end of the MOS switch tube, the first power supply and the upper plate of the bootstrap capacitor, and is used to charge the bootstrap capacitor under the control of the gate end control voltage of the MOS switch tube; the capacitor discharging branch is respectively connected to the lower plate of the bootstrap capacitor, the drain end of the MOS switch tube and the second power supply, and is used to discharge the bootstrap capacitor under the control of the first clock signal; the gate voltage control branch is respectively connected to the gate and drain ends of the MOS switch tube and the gate voltage discharge circuit, and is also connected to the connection node between the capacitor charging branch and the upper plate of the bootstrap capacitor, and is used to provide the gate end control voltage to the MOS switch tube under the control of the first clock signal.

[0006] Optionally, the capacitor charging branch includes a first PMOS tube, a gate end of the first PMOS tube is connected to the gate end of the MOS switch tube, a source end of the first PMOS tube is connected to the first power supply, and a drain end of the first PMOS tube is connected to the upper plate of the bootstrap capacitor and the gate voltage control branch.

[0007] Optionally, the capacitor discharge branch includes a first inverter and a first NMOS tube, the input end of the first inverter is connected to the first clock signal, the output end of the first inverter outputs the second clock signal, the gate end of the first NMOS tube is connected to the output end of the first inverter, and the drain end of the first NMOS tube is connected to the lower plate of the bootstrap capacitor, the drain end of the MOS switch tube and the gate voltage control branch.

[0008] Optionally, the gate voltage control branch includes a second inverter, a second PMOS tube and a second NMOS tube, the source end of the second PMOS tube is connected to the connection node between the capacitor charging branch and the upper plate of the bootstrap capacitor, the drain end of the second PMOS tube is simultaneously connected to the gate end of the MOS switch tube and the gate voltage discharge circuit, the gate end of the second PMOS tube is simultaneously connected to the drain end of the second NMOS tube and the signal output end of the second inverter; the gate end of the second NMOS tube is connected to the gate end of the MOS switch tube, and the source end of the second NMOS tube is respectively connected to the drain end of the MOS switch tube and the connection node between the bootstrap capacitor and the capacitor discharge branch; the signal input end of the second inverter is connected to the first clock signal, and the second inverter is also respectively connected to the first power supply and the connection node between the bootstrap capacitor and the capacitor discharge branch.

[0009] Optionally, the second inverter includes a third PMOS tube and a third NMOS tube, the source end of the third PMOS tube is connected to the first power supply, the drain end of the third PMOS tube and the drain end of the third NMOS tube are interconnected to serve as the signal output end of the second inverter, the source end of the third NMOS tube is connected to the connection node between the bootstrap capacitor and the capacitor discharge branch, and the gate end of the third PMOS tube and the gate end of the third NMOS tube are interconnected to serve as the signal input end of the second inverter.

[0010] Optionally, the gate voltage discharge circuit includes fourth to fifth NMOS tubes, the drain end of the fourth NMOS tube is respectively connected to the gate end of the MOS switch tube and the gate voltage supply circuit, the gate end of the fourth NMOS tube is connected to the first power supply, and the source end of the fourth NMOS tube is respectively connected to the drain end of the fifth NMOS tube and the auxiliary circuit; the gate end of the fifth NMOS tube is connected to the second clock signal, and the source end of the fifth NMOS tube is connected to the second power supply.

[0011] Optionally, the auxiliary circuit includes a fourth PMOS tube or a resistor connected in series between the first power supply and the connection node between the fourth NMOS tube and the fifth NMOS tube; when the auxiliary circuit includes the fourth PMOS tube, the source end of the fourth PMOS tube is connected to the first power supply, the gate end of the fourth PMOS tube is connected to the second clock signal, and the drain end of the fourth PMOS tube is connected to the connection node between the fourth NMOS tube and the fifth NMOS tube.

[0012] The present invention also provides a sampling and holding module, comprising one of the above-mentioned gate voltage bootstrap switch circuits.

[0013] The present invention also provides an electronic device, comprising the above-mentioned sampling and holding module.

[0014] Optionally, the electronic device is an analog-to-digital converter.

[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0016] 1. The gate voltage bootstrap switch circuit of the present invention provides a gate control voltage to the MOS switch tube through a charge pump and keeps the gate-source voltage of the MOS switch tube unchanged when the MOS switch tube is turned on, and the charge pump includes a gate voltage supply circuit for providing a gate control voltage to the MOS switch tube under the control of a first clock signal, a gate voltage discharge circuit for discharging the gate voltage of the MOS switch tube under the control of a second clock signal to adjust the gate voltage of the MOS switch tube, and an auxiliary circuit for providing the voltage of the first power supply to the gate voltage discharge circuit as a reference voltage during the conduction phase of the MOS switch tube, and the auxiliary circuit can reduce the adverse effects of some parasitic capacitances in the gate voltage bootstrap switch circuit and improve the turn-on efficiency of the gate voltage bootstrap switch circuit (i.e., the MOS switch tube). Furthermore, the auxiliary circuit is only a PMOS tube or a resistor, the circuit is simple, and the cost is low.

[0017] 2. The sampling and holding module and the electronic device of the present invention adopt the gate voltage bootstrap switch circuit of the present invention, and the performance is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is an equivalent circuit of a sampling capacitor sample-and-hold circuit in the sampling stage;

[0019] Figure 2 It is a structural schematic diagram of a gate voltage bootstrap switch circuit;

[0020] Figure 3 is a module schematic diagram of a gate voltage bootstrap switch circuit according to an embodiment of the present invention;

[0021] Figure 4A is a schematic diagram of a specific circuit structure of a gate voltage bootstrap switch circuit according to an embodiment of the present invention;

[0022] Figure 4B yes Figure 4A The equivalent circuit diagram of the gate voltage bootstrap switch circuit shown;

[0023] Figure 5 yes Figure 4B Schematic diagram of simulation test results of the gate voltage bootstrap switch circuit shown;

[0024] Figure 6 It is a schematic diagram of a specific circuit structure of a gate voltage bootstrap switch circuit according to another embodiment of the present invention. DETAILED DESCRIPTION

[0025] Figure 1The figure shows the equivalent circuit of the sampling capacitor sample-and-hold circuit in the sampling stage, wherein the sampling switch is turned on in the sampling stage, which is equivalent to a constant resistance R0 (i.e., on-resistance) connected in series with the sampling capacitor C0. The input signal is VIN, and the sampling is performed and the sampling signal is output as the amplitude of the input signal VIN changes, and the sampling capacitor C0 is charged. Obviously, the nonlinearity of the on-resistance of the sampling switch affects the linear characteristics of the sampling switch to a great extent. Therefore, in order to prevent the sampling signal from being distorted, it is necessary to reduce the nonlinearity of the on-resistance of the sampling switch to ensure that the on-resistance of the sampling switch is relatively stable within the entire input signal swing. At present, a solution to reduce the nonlinearity of the on-resistance of the sampling switch is to use a transmission gate (TG for short). The transmission gate is mainly composed of a pair of drain terminals (Drain) and source terminals (Source) of an NMOS tube and a PMOS tube in parallel. When the input signal amplitude is relatively small, the NMOS tube is turned on, and when the input signal amplitude is relatively large, the PMOS tube is turned on. However, for deep submicron technology, the device operating voltage is relatively low. When the input signal amplitude is in the middle state (near half of the power supply voltage), both the NMOS tube and the PMOS tube are not turned on, which leads to a relatively large on-resistance of the TG in this area. Therefore, the sampling switch of the TG structure has poor linearity within the full swing of the signal, which is not conducive to high-speed and high-precision applications. Another solution to reduce the nonlinearity of the switch on-resistance is to use a gate voltage bootstrap (Boot-Strap) switch. The basic principle of the gate voltage bootstrap switch is to use a single MOS switch tube as a sampling switch. The source end of the MOS switch tube is the sampling signal input end VIN, and the drain end of the MOS switch tube is the sampling signal output end VOUT. Through the gate voltage bootstrap technology, the gate-source voltage difference of the MOS switch tube when it is turned on is maintained at the power supply voltage VDD, thereby maintaining a high linearity of the MOS switch tube. In order to further improve the linearity of the NMOS tube within the entire signal swing, a charge pump is usually introduced to bootstrap the gate voltage of the MOS switch tube. The source end of the MOS switch tube is connected to the input signal VIN, and the gate and drain ends of the MOS switch tube are both connected to the charge pump. The charge pump can increase the gate voltage of the MOS switch tube to VDD+VIN, where VIN is the voltage of the input signal and VDD is the power supply voltage. That is, the charge pump can keep the gate-source voltage of the MOS switch tube close to VDD at all times.

[0026] like Figure 2As shown, a gate voltage bootstrap switch circuit with a charge pump includes a MOS switch tube M4 used as a sampling switch and a charge pump connected to the NMOS tube M4, the source end of the NMOS tube M4 is connected to the input signal VIN, and the drain end of the NMOS tube M4 outputs a signal. The charge pump includes an inverter U0, a bootstrap capacitor C1, NMOS tubes M0, M3, M6, M7, M8 and PMOS tubes M1, M2, M5. The input end of the inverter U0 receives the clock signal CLK, and outputs the clock signal CLK_N with a phase opposite to that of the clock signal CLK, and the output end of the inverter U0 is respectively connected to the gate end of the NMOS tube M0 and the gate end of the NMOS tube M8, the source end of the NMOS tube M0 and the source end of the NMOS tube M8 are both connected to the ground line VSS, the PMOS tube M5 and the NMOS tube M6 constitute a CMOS inverter, the source end of the PMOS tube M5 is connected to the power supply voltage VDD, the drain end of the PMOS tube M5 and the drain end of the NMOS tube M6 are connected as the output end of the CMOS inverter, and the output end of the CMOS inverter is also respectively connected to the gate end of the PMOS tube M1 and the drain end of the NMOS tube M3. The gate end of the PMOS tube M5 and the gate end of the NMOS tube M6 are connected to each other to form the input end of the CMOS inverter, and the clock signal CLK is connected. The source end of the NMOS tube M6, the lower plate of the bootstrap capacitor C1, the drain end of the NMOS tube M0 and the drain end of the NMOS tube M4 are connected together to form a connection node BOT. The upper plate of the bootstrap capacitor C1, the drain end of the PMOS tube M2 and the source end of the PMOS tube M1 are connected together to form a connection node TOP. The gate end of the PMOS tube M2 and the gate end of the NMOS tube M3 are both connected to the gate end of the NMOS tube M4. The source end of the NMOS tube M3 is connected to the drain end of the NMOS tube M4. The source end of the PMOS tube M2 and the gate end of the NMOS tube M7 are connected to the power supply voltage VDD. The drain end of the NMOS tube M7 and the drain end of the NMOS tube M1 are connected together to form a connection node O. The source end of the NMOS tube M7 and the drain end of the NMOS tube M8 are connected together to form a connection node P. The working process of the gate voltage bootstrap switch circuit includes:

[0027] When CLK=0, the circuit is reset, the potential of the top plate of C1 (i.e. the potential at the connection node TOP) is equal to the power supply voltage, i.e. V(TOP)=VDD, the potential of the bottom plate of C1 (i.e. the potential at the connection node BOT) V(BOT)=0, and the potentials at the connection nodes O and P are both 0, i.e. V(O)=V(P)=0;

[0028] When CLK=1, NMOS tube M4 is turned on, and the potential of the lower plate of C1 (that is, the potential at the connection node BOT) is equal to the potential of the input signal, that is, V(BOT)=VIN. In the ideal case where parasitic capacitance is ignored, the potential of the upper plate of C1 V(TOP)=VDD+VIN, which is the output voltage at the connection node O, that is, the voltage of the output signal.

[0029] In consideration of the parasitic capacitance CP1 at the connection node O and the parasitic capacitance CP2 at the connection node P, the calculation process of the output voltage at the connection node O is as follows:

[0030] First, when CLK=0, V(P)=0, V(O)=0, V(BOT)=0, V(TOP)=VDD;

[0031] Secondly, when CLK=1, V(P)=VDD, V(BOT)=VIN;

[0032] From the charge conservation of the two clock quadrants, we get:

[0033] C0*VDD=C0*[V(O)-(IN]+CP1*V(O)+CP2*V(P),

[0034] Therefore, we can calculate that V(O)=VDD*(C0-CP2) / (C0+CP1) + C0*VIN / (C0+CP1).

[0035] It can be seen from the above expression that the larger the CP1, the smaller the V(O), and the larger the CP2, the smaller the V(O). Therefore, from the perspective of circuit design, on the one hand, we need to reduce the parasitic capacitances CP1 and CP2 as much as possible to improve the turn-on efficiency of the gate voltage bootstrap switch circuit, but this method is easily limited by process conditions; on the other hand, the gate voltage bootstrap switch circuit can be improved and designed to minimize the adverse effects of parasitic capacitance to improve the turn-on efficiency of the gate voltage bootstrap switch circuit.

[0036] Based on this, the present invention provides a gate voltage bootstrap switch circuit, which improves the circuit and adds an auxiliary circuit that can assist the gate voltage discharge of the NMOS tube M4, thereby reducing the adverse effects of parasitic capacitance and improving the opening efficiency of the gate voltage bootstrap switch circuit.

[0037] In order to make the purpose and features of the present invention more obvious and understandable, the specific implementation methods of the present invention are further described below in conjunction with the accompanying drawings. However, the present invention can be implemented in different forms and should not be limited to the described embodiments.

[0038] Please refer to Figure 3The present invention provides a gate voltage bootstrap switch circuit, comprising a MOS switch tube M13 (which may be an NMOS tube) used as a switch, a first power supply VDD, a second power supply VSS (usually ground, i.e., 0V), and a charge pump connected to a gate terminal (G) and a drain terminal (D) of the MOS switch tube M13, wherein a source terminal (S) of the MOS switch tube M13 receives an input signal VIN, and a gate terminal outputs a discrete signal for sampling, and the charge pump is simultaneously connected to the first power supply VDD and the second power supply VSS, and provides a gate terminal control voltage to the MOS switch tube M13 under the control of a first clock signal CLK, and keeps the gate-source voltage difference of the MOS switch tube M13 unchanged when it is turned on, i.e., VGS=VDD. The charge pump includes a gate voltage supply circuit 1, a gate voltage discharge circuit 2 and an auxiliary circuit 3; the gate voltage supply circuit 1 is respectively connected to a first power supply VDD (which may also be an input working voltage), a second power supply VSS (which may be 0V, i.e., ground), a gate terminal and a drain terminal of the MOS switch tube M13, and is used to provide the voltage of the second power supply VSS to the gate terminal of the MOS switch tube M13 or provide the sum of the voltage of the input signal VIN and the voltage of the first power supply VDD (VDD+VIN) to the gate terminal of the MOS switch tube M13 under the control of a first clock signal CLK, so as to serve as a gate terminal control voltage of the MOS switch tube M13, and to keep the gate-source voltage difference of the MOS switch tube M13 constant when it is turned on. The gate voltage discharge circuit 2 is respectively connected to the first power supply VDD, the second power supply VSS, and the gate terminal of the MOS switch tube M13, and is used for discharging the gate terminal control voltage of the MOS switch tube M13 under the control of a second clock signal CLK_N which is inversely phased with the first clock signal CLK, so as to adjust the gate terminal voltage of the MOS switch tube M13; one end of the auxiliary circuit 3 is connected to the gate voltage discharge circuit 2, and the other end is connected to the first power supply VDD, and is used for providing the voltage of the first power supply VDD to the gate voltage discharge circuit 2 when the MOS switch tube M13 is turned on, so as to serve as a reference voltage of the gate voltage discharge circuit 2, and eliminate the influence of the corresponding parasitic capacitance on the MOS switch tube M13.

[0039] Please continue to refer to Figure 3The gate voltage supply circuit 1 includes a bootstrap capacitor C2, a capacitor charging branch 11, a capacitor discharging branch 12 and a gate voltage control branch 13. The bootstrap capacitor C2 is used to increase the gate control voltage of the MOS switch tube M13 to the sum of the voltage of the input signal VIN and the voltage of the first power supply VDD (VDD+VIN) when the MOS switch tube M13 is turned on, according to the characteristic that the voltage difference between the upper and lower plates of the capacitor remains unchanged; the capacitor charging branch 11 is respectively connected to the gate end of the MOS switch tube M13, the first power supply VDD and the upper plate of the bootstrap capacitor C2, and is used to charge the upper plate of the bootstrap capacitor C2 to VDD under the control of the gate control voltage of the MOS switch tube M13; the capacitor discharging branch 12 is respectively connected to the lower plate of the bootstrap capacitor C2, the drain end of the MOS switch tube M13 and the second power supply VSS, and is used to discharge the lower plate of the bootstrap capacitor C2 to VSS under the control of the first clock signal CLK; the gate voltage control branch 13 is used to provide a gate control voltage to the gate end of the MOS switch tube M13 under the control of the first clock signal CLK.

[0040] Please refer to Figure 4A In one embodiment of the present invention, the capacitor charging branch 11 includes a first PMOS tube M11, the capacitor discharging branch 12 includes a first inverter U1 for receiving a first clock signal CLK and generating a second clock signal CLK_N and a first NMOS tube M18 for discharging the lower plate of the bootstrap capacitor C2, the gate voltage control branch 13 includes a second inverter 130, a second PMOS tube M10 and a second NMOS tube M12, the second inverter 130 includes a third PMOS tube M14 and a third NMOS tube M15, the gate voltage discharge circuit 2 includes a fourth NMOS tube M16 and a fifth NMOS tube M17, the auxiliary circuit 3 is a fourth PMOS tube M19, and the specific circuit connection of the gate voltage bootstrap switch circuit of this embodiment is as follows:

[0041] The gate end of the first PMOS tube M11 is connected to the gate end of the MOS switch tube M13, the source end of the first PMOS tube M11 is connected to the first power supply VDD, the drain end of the first PMOS tube M11 is connected to the upper plate of the bootstrap capacitor C12 and the source end of the second PMOS tube M10, forming a connection node TOP; the input end of the first inverter U1 is connected to the first clock signal CLK, and the output end of the first inverter U1 outputs the second clock signal CLK_N; the gate end of the first NMOS tube M18 is connected to the output end of the first inverter U1, the drain end of the first NMOS tube M18 is connected to the lower plate of the bootstrap capacitor C2, the The drain end of the second PMOS tube M10 is connected to the gate end of the MOS switch tube M13 and the drain end of the fourth NMOS tube M16, and the connection point between the drain end of the second PMOS tube M10 and the drain end of the fourth NMOS tube M16 forms a connection node O as a discrete signal output end to output a discrete signal for sampling, and the gate end of the second PMOS tube M10 is connected to the drain end of the second NMOS tube M12 and the signal output end of the second inverter 130 (that is, the mutual connection point of the drain end of the third PMOS tube M14 and the drain end of the third NMOS tube M15); the gate end of the second NMOS tube M12 is connected to The gate end of the MOS switch tube M13 and the source end of the second NMOS tube M12 are connected to the connection node BOT (i.e., they are simultaneously connected to the drain end of the MOS switch tube M13, the lower plate of the bootstrap capacitor C2, and the drain end of the first NMOS tube M18); the source end of the third PMOS tube M14 is connected to the first power supply VDD, the drain end of the third PMOS tube M14 and the drain end of the third NMOS tube M15 are connected to each other as the signal output end of the second inverter 130, and are connected to the connection node TOP, and the source end of the third NMOS tube M15 is connected to the connection node BOT (i.e., they are connected to the lower plate of the bootstrap capacitor C2, the drain end of the first NMOS tube M18, the MOS switch The drain end of the fourth NMOS tube M16 is connected to the connection node O, the gate end of the fourth NMOS tube M16 is connected to the first power supply VDD, the source end of the fourth NMOS tube M16 is respectively connected to the drain end of the fifth NMOS tube M17 and the drain end of the fourth PMOS tube M19 to form a connection node P; the gate end of the fifth NMOS tube M17 is connected to the second clock signal CLK_N, and the source end of the fifth NMOS tube M17 is connected to the second power supply VSS;The source end of the fourth PMOS tube M19 is connected to the first power supply VDD, and the gate end of the fourth PMOS tube M19 is connected to the second clock signal CLK_N. ;

[0042] In consideration of the parasitic capacitance at the connection node O and the connection node P, the equivalent circuit of the gate voltage bootstrap switch circuit of this embodiment is as shown in FIG. Figure 4B As shown, a parasitic capacitor CP1' is connected between the connection node O and the second power supply VSS, and a parasitic capacitor CP2' is connected between the connection node P and the second power supply VSS. The working process of the bootstrap switch circuit of this embodiment under the control of the first clock signal CLK includes:

[0043] When CLK=0, M18, M16, M17 and M11 are all turned on, M10, M12, M19 and M13 are all turned off, the upper plate of the bootstrap capacitor C2 is charged to VDD through M11, the lower plate is discharged to VSS=0 through M18, and the voltage at the gate of M13 is discharged to 0 through M16 and M17. At this time, V(P)=0, V(O)=0, V(BOT)=0, and V(TOP)=VDD;

[0044] When CLK=1, M18, M11, M16, and M17 are all turned off, M19 is turned on, and the connection node P receives the charge from VDD through M19 (instead of Figure 2 From point O), V(P)=VDD, the bootstrap capacitor C2 maintains the voltage difference VDD between the upper and lower plates, the second inverter composed of M14 and M15 pulls down the gate voltage of M10, M10 is turned on, and then M13 is turned on. At this time, the circuit enters the sampling stage, the input signal VIN is slowly input, VBOT=VIN, the potential at BOT is slowly raised, M12 is turned on, the gate of M10 is shorted with the connection node BOT, M10 is turned off, and the connection node O will output a discrete signal at this stage;

[0045] According to the charge conservation in the two clock quadrants CLK=0 and CLK=1: C2*VDD=C2*[V(O)-VIN] + CP1'*V(O), it can be calculated that V(O)=VDD*C2 / (C2+CP1') + C2*VIN / (C2+CP1'). It can be seen that the influence of the parasitic capacitance CP2' of the connection node P on the turn-on efficiency of the gate voltage bootstrap switch circuit is completely eliminated by the connected fourth POMS tube M19. The fundamental reason is that in the CLK=1 quadrant, the charge of the connection node P is no longer provided by the connection node O, but directly provided by the first power supply VDD.

[0046] In order to better illustrate the technical effect of the technical solution of the present invention, we also Figure 2 and Figure 4AThe gate voltage bootstrap switch circuit shown in the figure is simulated. The simulation conditions are as follows: C0=C2=100fF, CP1=CP2=CP1'=CP2'=10 fF. The simulation results are shown in Figure 5 As shown, the dotted waveform is Figure 4B The output voltage simulation waveform at the connection node O of the gate voltage bootstrap switch circuit shown in FIG. 1 is a solid line waveform. Figure 2 The output voltage simulation waveform at the connection node O of the gate voltage bootstrap switch circuit shown in FIG. 1 is shown in FIG. 2 . It can be seen from the two waveforms that Figure 4B The gate voltage bootstrap switch circuit scheme shown can increase the output voltage of the gate voltage bootstrap switch circuit by 239mV. This shows that, under the condition of constant parasitic capacitance, by adding a PMOS tube M19, the turn-on efficiency of the gate voltage bootstrap switch circuit can be improved, and then the nonlinearity of the on-resistance of the MOS switch tube M13 can be further reduced, the distortion of the input signal can be reduced, and the accuracy of the gate voltage bootstrap switch circuit can be improved.

[0047] It should be noted that the specific circuit structures of the gate voltage supply circuit 1, the gate voltage discharge circuit 2 and the auxiliary circuit 3 in the gate voltage bootstrap switch circuit of the present invention are not limited to the design methods listed in the above embodiments, as long as the functions of the gate voltage supply circuit 1, the gate voltage discharge circuit 2 and the auxiliary circuit 3 can be achieved. For example, the auxiliary circuit 3 can also be a resistor R1 connected in series between the first power supply VDD and the connection node P, such as Figure 6 As shown, the resistance value of the resistor R1 is preferably equal to the internal resistance of the fourth PMOS tube M19 when it is turned on, thereby also achieving Figure 4A The role of the fourth PMOS tube M19 is that when the parasitic capacitance is constant, by adding a resistor R1, the turn-on efficiency of the gate voltage bootstrap (Boot-Strap) switch circuit can be improved to a certain extent. In other embodiments of the present invention, the auxiliary circuit 3 can also be a circuit including the fourth PMOS tube M19 and / or the resistor R1.

[0048] The present invention also provides a sampling and holding module, comprising one of the above-mentioned gate voltage bootstrap switch circuits.

[0049] The present invention further provides an electronic device, comprising the above-mentioned sampling and holding module. The electronic device may be an analog-to-digital converter.

[0050] Since the sampling and holding module and the electronic device of the present invention both adopt the gate voltage bootstrap switch circuit of the present invention, their linearity and sampling accuracy are improved.

[0051] In summary, the present invention provides a gate voltage bootstrap switch circuit, a sampling and holding module, and an electronic device, which are suitable for various applications of high-precision and high-speed sampling.

[0052] Obviously, those skilled in the art can make various changes and modifications to the invention without departing from the spirit and scope of the invention. Thus, if these modifications and variations of the invention fall within the scope of the claims of the invention and their equivalents, the invention is also intended to include these modifications and variations.

Claims

1. A gate voltage bootstrap switch circuit, comprising a MOS switch tube as a switch, a first power supply, a second power supply and a charge pump connected to the gate terminal and the drain terminal of the MOS switch tube, wherein the source terminal of the MOS switch tube receives an input signal, the gate terminal of the MOS switch tube outputs a discrete signal for sampling, the charge pump is connected to the first power supply and the second power supply at the same time, provides a gate terminal control voltage to the MOS switch tube under the control of a first clock signal, and keeps the gate-source voltage difference of the MOS switch tube unchanged when it is turned on; wherein ... The charge pump includes a gate voltage supply circuit, a gate voltage discharge circuit and an auxiliary circuit; the gate voltage supply circuit is used to provide the voltage of the second power supply to the gate terminal of the MOS switch tube under the control of the first clock signal, or to provide the sum of the voltage of the input signal and the voltage of the first power supply to the gate terminal of the MOS switch tube as the gate terminal control voltage of the MOS switch tube, and to keep the gate-source voltage difference of the MOS switch tube unchanged when it is turned on; the gate voltage discharge circuit is used to discharge the gate terminal control voltage of the gate terminal of the MOS switch tube under the control of a second clock signal that is inversely phase with the first clock signal, so as to adjust the gate terminal voltage of the MOS switch tube; one end of the auxiliary circuit is connected to the gate voltage discharge circuit, and the other end is connected to the first power supply, and is used to provide the voltage of the first power supply to the gate voltage discharge circuit when the MOS switch tube is turned on, so as to serve as a reference voltage of the gate voltage discharge circuit; Wherein, the gate voltage discharge circuit includes fourth to fifth NMOS tubes, the drain end of the fourth NMOS tube is respectively connected to the gate end of the MOS switch tube and the gate voltage supply circuit, forming a discrete signal output end of the gate voltage bootstrap switch circuit to output a discrete signal for sampling, the gate end of the fourth NMOS tube is connected to the first power supply, and the source end of the fourth NMOS tube is respectively connected to the drain end of the fifth NMOS tube and the auxiliary circuit; the gate end of the fifth NMOS tube is connected to the second clock signal, and the source end of the fifth NMOS tube is connected to the second power supply; The auxiliary circuit includes a resistor connected in series between the first power supply and a connection node between the fourth NMOS transistor and the fifth NMOS transistor; A first parasitic capacitor is connected between the gate terminal of the MOS switch tube and the second power supply, and a second parasitic capacitor is connected between the connection node and the second power supply.

2. The gate voltage bootstrap switch circuit according to claim 1, characterized in that: The gate voltage supply circuit includes a bootstrap capacitor, a capacitor charging branch, a capacitor discharging branch and a gate voltage control branch; the bootstrap capacitor is used to increase the gate control voltage of the MOS switch tube to the sum of the voltage of the input signal and the voltage of the first power supply when the MOS switch tube is turned on; the capacitor charging branch is respectively connected to the gate terminal of the MOS switch tube, the first power supply and the upper plate of the bootstrap capacitor, and is used to charge the bootstrap capacitor under the control of the gate terminal control voltage of the MOS switch tube; the capacitor discharging branch is respectively connected to the lower plate of the bootstrap capacitor, the drain terminal of the MOS switch tube and the second power supply, and is used to discharge the bootstrap capacitor under the control of the first clock signal; the gate voltage control branch is respectively connected to the gate terminal and the drain terminal of the MOS switch tube and the gate voltage discharge circuit, and is also connected to the connection node between the capacitor charging branch and the upper plate of the bootstrap capacitor, and is used to provide the gate terminal control voltage to the MOS switch tube under the control of the first clock signal.

3. The gate voltage bootstrap switch circuit according to claim 2, characterized in that: The capacitor charging branch includes a first PMOS tube, a gate end of the first PMOS tube is connected to the gate end of the MOS switch tube, a source end of the first PMOS tube is connected to the first power supply, and a drain end of the first PMOS tube is connected to the upper plate of the bootstrap capacitor and the gate voltage control branch.

4. The gate voltage bootstrap switch circuit according to claim 2, characterized in that: The capacitor discharge branch includes a first inverter and a first NMOS tube, the input end of the first inverter is connected to the first clock signal, the output end of the first inverter outputs the second clock signal, the gate end of the first NMOS tube is connected to the output end of the first inverter, and the drain end of the first NMOS tube is connected to the lower plate of the bootstrap capacitor, the drain end of the MOS switch tube and the gate voltage control branch.

5. The gate voltage bootstrap switch circuit according to claim 2, characterized in that: The gate voltage control branch includes a second inverter, a second PMOS tube and a second NMOS tube, the source end of the second PMOS tube is connected to the connection node between the capacitor charging branch and the upper plate of the bootstrap capacitor, the drain end of the second PMOS tube is simultaneously connected to the gate end of the MOS switch tube and the gate voltage discharge circuit, the gate end of the second PMOS tube is simultaneously connected to the drain end of the second NMOS tube and the signal output end of the second inverter; the gate end of the second NMOS tube is connected to the gate end of the MOS switch tube, the source end of the second NMOS tube is respectively connected to the drain end of the MOS switch tube and the connection node between the bootstrap capacitor and the capacitor discharge branch; the signal input end of the second inverter is connected to the first clock signal, and the second inverter is also respectively connected to the first power supply and the connection node between the bootstrap capacitor and the capacitor discharge branch.

6. The gate voltage bootstrap switch circuit according to claim 5, characterized in that: The second inverter includes a third PMOS tube and a third NMOS tube, the source end of the third PMOS tube is connected to the first power supply, the drain end of the third PMOS tube and the drain end of the third NMOS tube are connected to each other to serve as the signal output end of the second inverter, the source end of the third NMOS tube is connected to the connection node between the bootstrap capacitor and the capacitor discharge branch, and the gate end of the third PMOS tube and the gate end of the third NMOS tube are connected to each other to serve as the signal input end of the second inverter.

7. A sample-and-hold module, characterized in that: A gate voltage bootstrap switch circuit comprising the gate voltage bootstrap switch circuit according to any one of claims 1 to 6.

8. An electronic device, characterized in that: Includes the sample-and-hold module as claimed in claim 7.

9. The electronic device as claimed in claim 8, characterized in that: The electronic device is an analog-to-digital converter.

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