Adaptive Voltage System for Aging Protection Tape Reduction

Abstract

A device is provided that includes: a first power node; a second power node; a memory bit cell coupled to the second power node; a circuit coupled to the first power node and the second power node, the circuit being operative in a diode-connected mode; and a transistor coupled in parallel to the circuit, wherein the transistor is controllable by a digital signal such that when the transistor is turned on, it is operative to apply a voltage stress and / or a current stress to the memory bit cell.

Description

[0001] Priority Statement

[0002] This application claims priority to U.S. Patent Application Serial No. 15 / 477,913, filed on April 3, 2017, entitled "ADAPTIVE VOLTAGE SYSTEM FOR AGING GUARD - BAND REDUCTION", which is incorporated herein by reference in its entirety.

[0003] Background

[0004] In advanced processing technology nodes, process (P), voltage (V), and temperature (T) variations (also known as "PVT" variations) and aging behavior can degrade the performance and reliability of a design. To mitigate these issues, modern microprocessors and / or system - on - chip (SoC) designs add fixed voltage / timing margin guard - bands or margins to ensure the target performance and reliability of the microprocessor or SoC. Moreover, these PVT variations and aging may not be common in nature. Thus, adding guard - bands or margins to avoid errors caused by variations can compromise energy efficiency and performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Embodiments of the present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of the embodiments of the present disclosure. However, it should not be considered that the present disclosure is limited to the specific embodiments, but is for explanation and understanding only.

[0006] Figure 1 Shows a high - level architecture of an adaptive voltage system according to some embodiments of the present disclosure.

[0007] Figure 2 Shows a high - level architecture of an adaptive voltage system with a retention Vmin (V minimum) monitor (RVM) for a memory array according to some embodiments of the present disclosure.

[0008] Figure 3A -F shows an RVM circuit according to some embodiments of the present disclosure.

[0009] Figure 4A -B shows graphs of static noise margin (SNM) before and after aging, respectively.

[0010] Figure 5A Shows a graph according to some embodiments, which shows the Vmin (V minimum) of a memory array with and without an RVM circuit across process variations and aging.

[0011] Figure 5BShows a graph according to some embodiments, the graph showing Vmin (minimum V) of a memory bit cell and a double-stack diode-connected RVM having aging cycles.

[0012] Figure 6 Shows a graph having a waveform showing a sampling and stress timing diagram according to some embodiments of the present disclosure.

[0013] Figure 7A -B shows a graph of power savings of an RVM circuit using some embodiments.

[0014] Figure 8 Shows an intelligent device or computer system or SoC (system-on-chip) having an adaptive voltage system according to some embodiments. Detailed Description

[0015] Since the aging effect of transistors occurs differently depending on the usage and conditions of the user of the integrated circuit (IC or chip), even a large fixed aging guard band or margin may ultimately be added to a less aged chip (or IC), which in turn increases the power consumption during the chip's lifetime. Transistor or device aging occurs in both the memory array and the logic of the IC, which increases the threshold voltage of the device, resulting in higher propagation delays and higher active Vmin (minimum V). Here, the term "Vmin" generally refers to the minimum operating power supply voltage below which logic or memory cannot operate properly. For example, the Vmin of a memory is the minimum power supply voltage below which a memory bit cell may lose its data or be unable to write data to it. However, increasing the power supply voltage of the IC or chip will increase the speed of aging of the chip's transistors. Therefore, a larger Vmin is specified for the semiconductor chip in order to provide sufficient power supply voltage to the chip's transistors during the lifetime of the chip, thereby allowing the chip to operate at least at the minimum specified clock speed throughout its lifetime.

[0016] In addition, in the case of a memory circuit (e.g., a static random access memory (SRAM)), as the transistors of the memory cells age, a larger power supply voltage needs to be provided to the memory cells to prevent the memory cells from losing their stored data. Therefore, a larger Vmin is specified for the semiconductor chip so that sufficient power supply voltage is applied to the memory cells of the memory circuit so that they retain their data during the lifetime of the semiconductor chip.

[0017] Accordingly, the specified Vmin of the semiconductor chip is set to an artificially high power level during an earlier time range of the chip's operating life. During the early stages of the chip's life, the transistors of the semiconductor chip are substantially not aged. Thus, they can operate at a lower power supply voltage. However, the minimum power supply voltage is set to a higher voltage level to ensure that when the transistors eventually age during the life of the semiconductor chip, the transistors will receive sufficient power supply voltage. The artificially high power supply voltage supplied to the semiconductor chip in its early life corresponds to low efficiency of the semiconductor chip. This low efficiency consumes more power at the artificially high power supply voltage compared to the power required in other ways. Memory arrays in the semiconductor chip with a very low activation probability (e.g., rows and columns of SRAM bit cells) are in a hold mode (e.g., low power mode, standby mode, sleep mode, etc.) for most of the time. Accordingly, maintaining Vmin reduction / monitoring is used to mitigate degradation caused by aging.

[0018] Some embodiments describe an adaptive voltage system (AVS) that uses an adjustable replica circuit (TRC) as a logic aging monitor, an adjustable replica bit (TRB) circuit for the memory array, and a bit cell hold vmin monitor (RVM) circuit as a memory array aging monitor. In some embodiments, the TRC pre-detects timing margins and errors and provides an output to a power management unit (PMU). In some embodiments, the TRB circuit provides a timing margin for the memory array. Although the TRC tracks the Vmin of the logic block and the TRB circuit tracks the timing margin of the memory array, the TRC and the TRB circuit may not track the memory bit cell hold Vmin.

[0019] Some embodiments describe an RVM circuit for the memory array to track bit cell aging across operating modes (e.g., normal mode or active mode, and low power mode or sleep mode). In some embodiments, the RVM circuit provides an output to the PMU. In some embodiments, the PMU modulates the power supply voltages for the memory array and the logic (e.g., generated by a voltage regulator, a low dropout (LDO) circuit, a DC-DC converter, etc.) and any logic / memory failures due to degradation caused by aging.

[0020] In the following description, many details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present disclosure.

[0021] Note that in the corresponding drawings of the embodiments, lines are used to represent signals. Some lines may be thicker to indicate more component signal paths, and / or have arrows at one or more ends to indicate the main information flow direction. Such indication is not intended to be restrictive. Rather, such lines are used in conjunction with one or more exemplary embodiments to help more easily understand the circuit or logic unit. As indicated by design needs or preferences, any represented signal may actually include one or more signals that can propagate in either direction, and any suitable type of signal scheme may be used to implement it.

[0022] Throughout the specification, and in the claims, the term "connected" refers to a direct connection (e.g., electrical, mechanical, or magnetic connection) between the connected objects, without any intervening device. The term "coupled" refers to a direct or indirect connection, e.g., a direct electrical, mechanical, or magnetic connection between the connected objects, or an indirect connection through one or more passive or active intervening devices. The term "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide the desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a", "an", and "the" include plural references. "In" means both "in" and "on".

[0023] The terms "substantially", "close", "approximately", "near", and "about" generally mean within + / - 10% of the target value (unless otherwise specified). Unless otherwise stated, the use of the ordinal adjectives "first", "second", "third", etc. to describe a common object only indicates different instances of the same object are being referred to, and is not intended to imply that the objects so described must be in a given sequence, whether in time, space, ranking, or in any other way.

[0024] For the purposes of the present disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0025] For purposes of the embodiments, the transistors in the various circuits and logic blocks described herein are metal-oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include a drain, a source, a gate, and a boost terminal. The transistors and / or MOS transistor derivatives also include triple-gate and fin field-effect transistors (FinFETs), gate all around cylindrical transistors, tunnel FETs (TFETs), square wires, or rectangular strip transistors, ferroelectric FETs (FeFETs), or other devices such as carbon nanotubes or spintronic devices that perform transistor functions. The symmetric source and drain terminals of a MOSFET are identical terminals and may be used interchangeably herein. On the other hand, a TFET device has asymmetric source and drain terminals. Those skilled in the art will understand that other transistors (e.g., bipolar junction transistors - BJT PNP / NPN, BiCMOS, CMOS, eFET, etc.) may be used without departing from the scope of the present disclosure. The term "MN" denotes an n-type transistor (e.g., NMOS, NPN BJT, etc.), and the term "MP" indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0026] Figure 1 FIG. 4 shows a high-level architecture of an adaptive voltage system (AVS) 100 in accordance with some embodiments of the present disclosure. The adaptive voltage system 100 includes a bit cell array 101, logic 102 (e.g., column multiplexers, decoders, etc.), a TRB circuit 101a, an RVM circuit 101b, a TRC 102a, a PMU circuit 103, a power generator circuit 104, an input power supply 105, an output power supply node (also simply referred to as a node) 106, a monitor node 107, and a power control node 108.

[0027] In some embodiments, the bit cell array 101 is a memory array (e.g., a content-addressable memory (CAM), a four-transistor (4T) SRAM, a 6T SRAM, an 8T SRAM, a register file (RF), a dual-port memory, etc.). In some embodiments, the memory array 101 has an associated TRB circuit 101a and an RVM circuit 101b. In some embodiments, the TRB circuit 101a and the RVM circuit 101b may be fully integrated with the memory cells of the memory array 101. In some embodiments, the TRB circuit 101a measures the speed / timing of the memory cells of the memory array. In some embodiments, the RVM circuit 101b includes an RVM unit that measures the Vmin required for the memory cells of the memory array 101 to retain or hold their data.

[0028] In some embodiments, logic 102 (which can be any logic in the chip) has an associated TRC 102a. In some embodiments, TRC 102a monitors the speed / timing of certain logic units in logic 102 (e.g., transistors in an AND gate).

[0029] In some embodiments, the PMU 103 (or power management controller or circuit) is used to periodically monitor the information or output of the TRB circuit 101a, RVM circuit 101b, and TRC 102a (e.g., every few milliseconds, nanoseconds, and / or picoseconds) and control the power generator 104 to modulate the power on one or more power nodes. For simplicity purposes, one node 106 is shown as being shared for the memory array 101 and logic 102. However, a semiconductor chip can have many voltage domains and different power generators that supply power to different voltage domains. In that case, the PMU 103 can instruct different power generators to regulate the power to different voltage domains based on monitoring circuits such as the TRB circuit 101a, RVM circuit 101b, and TRC 102a. In some embodiments, in addition to an RVM unit 101b failure, if the TRB circuit 101a or TRC 102a unit exhibits sufficient failures, the power voltage on node 106 can also be increased. Thus, in some embodiments, each of these test units (i.e., the TRB circuit 101a, RVM circuit 101b, and TRC 102a) is coupled to a PMU 403, which controls the power voltage via a power generator 404 in response to the output of the test units (i.e., the TRB circuit 101a, RVM circuit 101b, and TRC 102a).

[0030] In some embodiments, the power generator 104 is a DC-DC converter that receives the input power on the input power 105 and generates a regulated power on node 106. In some embodiments, the power generator 104 is a low dropout (LDO) regulator. For example, the power generator 104 includes a digital LDO, an analog LDO, or a combination thereof. Any suitable power generator can be used for generator 104, which is operable to modulate the power on node 106 based on the control node 108.

[0031] In some embodiments, the RVM circuit 101b acts as a test unit associated with the memory array 101, which is designed to measure the minimum supply voltage at which the memory cells of the memory array 101 can reliably hold their stored information. Initially, during the early life of the semiconductor chip, the RVM circuit 101b indicates that the memory cells in the memory array 101 can hold their data at a particularly low supply voltage. In some embodiments, data from the RVM circuit 101b reaches the PMU circuit 103 via the monitor node 107. In some embodiments, the PMU circuit 103 sets a low supply voltage for the memory 101 and the logic 102. In this way, the above-mentioned inefficiency is alleviated because the semiconductor chip (here, indicated by the memory 101 and the logic 102) can operate at a lower supply voltage during its early life.

[0032] Over time, as the transistors of the semiconductor chip age, the RVM circuit 101b indicates that a higher supply voltage is required on node 106 to ensure that the memory array cells can hold their data. Data from the RVM circuit 101b reaches the PMU circuit 103, which requests the power generator 104 to increase its supply voltage on node 106 to a higher voltage level. For example, the PMU 103 provides a new voltage identification (VID) 108 to the power generator 104 to set the supply voltage on node 106 to a higher voltage.

[0033] This behavior increases over time, where the RVM circuit 101b indicates that an even higher voltage is required, and the PMU circuit 103 provides a higher voltage on node 106 during the life of the semiconductor chip. In this way, the above-mentioned supply voltage inefficiency is avoided because the semiconductor chip increases its supply voltage as needed, rather than operating its supply voltage at the worst-case scenario at the end of its entire life cycle.

[0034] Figure 2 A high-level architecture of an adaptive voltage system with an RVM for a memory array according to some embodiments of the present disclosure is shown. It should be noted that Figure 2 Those elements having the same reference numerals (or names) as the elements in any other figure can operate or run in any manner similar to the described manner, but are not limited to such a manner.

[0035] The adaptive voltage system 200 provides a detailed view of the memory 101. In this example, the RVM circuit 101b is integrated within the memory array 101. The memory 101 includes rows / columns of memory bit cells 201 1-N where "N" is an integer. In some embodiments, the RVM circuit 101b includes RVM bit cells 202 1-M, where "M" is an integer (e.g., M = 16). In some embodiments, the RVM bit cell 202 1-M has the same circuit as the memory bit cell. For example, when the memory bit cell is a 6T SRAM bit cell, the RVM bit cell is also a 6T bit cell. In some embodiments, the RVM circuit 101b includes a power supply voltage modulator 203. In some embodiments, the power supply voltage modulator 203 receives power from the node 106 and modulates the power to apply stress to the RVM bit cell, and then samples or senses the behavior of the stressed RVM bit cell. For example, the power supply voltage modulator 203 receives the voltage on the node 106 and provides a power supply node (also simply referred to as a node) 204 to the RVM bit cell 2021- M

[0036] In some embodiments, the RVM circuit 101b tracks the holding Vmin of the RVM bit cell 202 1-M , which is affected by transistor aging and other variations. The adaptive voltage system 200 periodically samples the RVM output 107. Aging is a slowly varying behavior, so the periodic sampling may be much slower than the chip's clock frequency. For example, the adaptive voltage system 200 samples the RVM output 107 every day. When the RVM circuit 101b detects a change in Vmin due to aging, it provides a warning signal to the PMU 103 via the node 107 to change the Vcc on the node 106 through the power generator 104. Here, the same stress conditions are applied to the RVM aging sensor 101b and the memory bit cell 201 1-N

[0037] Here, the storage cell failure is a function of manufacturing process variations, which causes some transistors to age faster than others. Thus, according to some embodiments, designing multiple RVM cells into the same semiconductor chip provides greater RVM cell performance scalability (e.g., some RVM cells will fail before other RVM cells). According to some embodiments, due to the failure of the RVM cell(s), the decision point regarding when the power supply voltage on the node 106 should be raised can be made based on, for example, the number of RVM cells that have been observed to fail.

[0038] For example, if the RVM cells 202 1-M are designed to be particularly weak during measurement reads (e.g., they have multiple pull-up transistors and a reduced read power supply voltage), then the decision to raise the power supply voltage on the node 106 may require the failure of multiple RVM cells. In some embodiments, if the RVM cells 202 1-M ​​If it is designed to be not too weak during measurement reading (e.g., only a small power supply voltage drop is achieved during measurement reading), then the decision to increase the power supply voltage may involve a failure of fewer (e.g., only one) RVM cells in RVM unit 202 1-M in RVM unit 202.

[0039] In some embodiments, the performance of RVM unit 202 is averaged by connecting their input nodes and output nodes together 1-M In some embodiments, each RVM cell is effectively coupled in parallel because its input node and output node are coupled to the same node. According to some embodiments, coupling RVM unit 202 in this way 1-M allows multiple mechanisms to trigger errors during measurement reading, which in turn reflects the overall performance of the group of RVM cells 202 1-M In some embodiments, for example, if any of the following occurs, incorrect data may be read at the output: more than half of the RVM cells 202

[0040] weakly fail (e.g., each cell only weakly pulls the output data node towards the wrong logic level, but more than half of the cells pulling in this way are sufficient to pull the entire data node towards the wrong level), some RVM cells 202 1-M fail with a certain strength (e.g., some failed RVM cells pull the data output node with sufficient strength to override other properly working RVM cells and place the output data node at the wrong logic level), or one RVM cell in unit 202 1-M fails with a great strength (e.g., one cell pulls the data output node with sufficient strength to override all other RVM cells). 1-M In some embodiments, one or more sense amplifiers (not shown) associated with the RVM bit cells 202 in RVM circuit 101b are used to determine the logical states stored in the RVM bit cells 202

[0041] before and after applying voltage stress and / or current stress to the RVM bit cells 202 1-M In this way, PMU 103 determines whether the RVM bit cells 202 1-M retain their data when applying voltage stress and / or current stress through power supply node 204. 1-M 1-M 1-M Figures -F respectively show RVM circuits 300, 320, 330, 340, 350, and 360 according to various embodiments of the present disclosure. It should be noted that

[0042] Figure 3A -F respectively show RVM circuits 300, 320, 330, 340, 350, and 360 according to various embodiments of the present disclosure. It should be noted that Figures 3A to 3FThose elements having the same reference numbers (or names) as elements in any other figure may operate or function in any manner similar to the described manner, but are not limited to such a manner. All RVM circuits track the aging trend of holding Vmin in the array 101.

[0043] Figure 3A The RVM circuit 300 of 1-M shows the power supply voltage modulator 203 as an embodiment of the circuit 303. Here, the circuit 303 includes a p-type device MP coupled to the node 106 and the node 204. In some embodiments, the gate terminal of the p-type device MP is coupled to ground. In some embodiments, when the p-type device MP is fully turned on (e.g., when its gate is grounded), the RVM bit cell 202 1-M is stressed by the full Vcc from the node 106. In some embodiments, it is expected that the p-type device MP will reveal that the aging problem is approaching, while the actual memory cell 201 1-N begins to fail. Therefore, the sensitivity level of tracking aging by the circuit 303 is low, which may leave the system with little time to adjust its memory power supply voltage 106.

[0044] In another embodiment, the gate of the p-type device MP is coupled to a control node that biases the p-type device MP. In some embodiments, the control voltage on the control node affects the power supply voltage on the node 204 provided to the RVM bit cell 202 1-M . For example, the control voltage on the control node only weakly or moderately turns on the p-type device MP, which increases its channel resistance, thereby introducing a voltage drop across the p-type device MP. The voltage drop across the p-type device MP in turn reduces the power supply voltage applied to the node 204 of the storage cell. In the case of a reduced power supply voltage, the RVM cell 202 1-M exhibits a fault before the actual storage cell 201 1-N in the memory array 101. For example, the RVM cell 202 1-M is designed to have a smaller voltage margin than the actual storage cell 201 1-N in the memory array 101.

[0045] However, because the RVM cells 202 1-M continuously receive a lower power supply voltage, they may not be stressed to the same extent as the actual storage cells 201 1-N in the memory array 101 (since their cells do not include the p-type device MP, the actual storage cells 201 1-N receive a higher power supply from the voltage of the node 106). Due to the smaller power supply voltage received by the RVM cells 202 1-M , the smaller stress received is offset, and they tend to exhibit errors faster.

[0046] Figure 3B The RVM circuit 320 shows an embodiment of the power supply voltage modulator 203 as the circuit 323, which includes at least two p-type devices MP1 and p-type device MP2 coupled in parallel, and can be controlled by two different control signals provided at node 325 and node 324 respectively. The RVM circuit 320 combines two embodiments of the RVM circuit 300, where one p-type device MP1 is controlled by an analog signal provided to node 325, and the other device p-type MP2 is digitally controlled. In some embodiments, the PMU 103 applies voltage stress to the RVM bit cell 202 by turning on the p-type device MP2 324 1-M . In some embodiments, the PMU 103 senses the RVM cell 202 by turning off the p-type device MP2 and providing an analog voltage to the gate terminal of the p-type device MP1 1-M such that the RVM bit cell 202 1-M is more sensitive to retention failures. According to various embodiments, the more sensitive the sensing mechanism for retention failures, the earlier the detection of the failures. In some embodiments, a biasing circuit (or programmable voltage divider) is used to provide a biasing voltage at node 325

[0047] Although various embodiments herein describe the power supply voltage modulator 203 as having only p-type transistors, in some embodiments, n-type transistors can also be used alone or in combination with p-type transistors to apply voltage stress to the bit cell and then sense retention failures. Additionally, according to various embodiments, the illustration of a single transistor can be replaced with multiple transistors coupled in parallel and controllable to turn on to adjust the stress level and / or retention sensitivity level

[0048] Figure 3C The RVM circuit 330 shows an embodiment of the power supply voltage modulator 203 as the circuit 333, which includes a diode-connected device MPd coupled in parallel to the device MP2, and the device MP2 is controlled by node 324. In some embodiments, the diode-connected device MPd causes a forward bias voltage drop on the power supply voltage rail that supplies the RVM memory cell 201 1-M while reading their stored data during the measurement or sampling mode

[0049] In some embodiments, the power supply voltage path to the RVM memory cell 201 1-M includes two circuit paths. The first path is through the device MP2, which applies the full power supply voltage to the RVM memory cell 201 1-M so as to cause the actual memory cells 201 in the memory array 101 1-NStress the cells in a manner substantially the same as the way they are stressed. A second path is to apply the reduced supply voltage to the RVM memory cell 201 through the diode-connected device MPd 1-M At this time, measure the RVM memory cell 201 1-M to understand whether the reduced supply voltage at the current stress level is low enough to cause the RVM memory cell 201 1-M to be unable to correctly store its data. If so, the RVM memory cell 201 1-M will provide an "early warning" that the supply voltage has not yet reached, but will soon reach, the level at which the cells 101 of the memory array 101 1-N will start to exhibit errors. Using a viable warning indicator, the supply voltage can be increased before any cell in the memory array actually starts to fail.

[0050] In some embodiments, in the sampling mode, the device MP2 is turned off to force the supply current to flow from node 106 to node 204 through the diode-connected device MPd, thereby causing the above-mentioned supply voltage drop. In some embodiments, the supply voltage drop induced by the diode-connected device MPd "weakens" the ability of the RVM cell to hold its stored data, similar to Figure 3B the control device MP1.

[0051] Return reference Figure 3C In some embodiments, the RVM cell 202 1-M is only weakened when the supply voltage for the read operation performed during the measurement mode (also referred to as the sampling mode or sensing mode) is low. In some embodiments, during the stress mode, the RVM cell 202 1-M is not substantially supplied through the diode-connected device MPd, but instead is supplied through the stress device MP2 that conducts strongly when the RVM cell 202 1-M is stressed. Since the stress device MP2 is strongly turned on during the stress mode, according to some embodiments, the stress device MP2 has a very low channel resistance and thus the voltage drop across it can be negligible.

[0052] Therefore, during the stress mode, the RVM cell 202 1-M receives the full Vcc supply voltage via node 204. As mentioned here, according to some embodiments, in order to measure the stored data of the cells during the (e.g., periodic) measurement mode between extended stress times, the stress device MP2 is turned off, which forces all the supply current to flow through the diode-connected device MPd, which weakens the cells by reducing its supply voltage during the read mode.

[0053] Figure 3D The RVM circuit 340 shows an embodiment of the power supply voltage modulator 203 as the circuit 343, which includes two or more serially-coupled diode-connected devices MPd1 and MPd2, which are together coupled in parallel to the device MP2, and the device MP2 is controlled by the voltage / current at the node 324. In this example, two serially-coupled diode-connected devices are shown. However, more than two such devices can also be serially-coupled to adjust the sensitivity level for hold faults.

[0054] Similar to the RVM circuit 330, according to some embodiments, the RVM circuit 340 introduces a voltage drop along the power supply voltage path during the measurement read mode, but introduces more power supply voltage drop than Figure 3C the circuit of. For example, although Figure 3C the RVM circuit 330 of introduces a forward bias voltage drop along the power supply rail during the test mode, in contrast, the RVM circuit 340 introduces two forward bias voltage drops along the power supply rail through a pair of diode-connected devices MPd1 and the device MPd2 during the test mode. Therefore, according to some embodiments, the RVM circuit 340 can provide a warning signal even earlier than the RVM circuit 330. Although Figure 3D the embodiment of shows two serially-coupled diode-connected devices, more diode-connected devices can be serially cascaded to further increase the sensitivity for hold faults.

[0055] Figure 3E The RVM circuit 350 shows an embodiment of the power supply voltage modulator 203 as the circuit 353, which includes a plurality of pull-up devices (e.g., MPul1 and MPur1) along each branch (e.g., the right branch and the left branch), rather than just a single pull-up transistor on each branch. Here, the term "branch" generally refers to the circuit path of the transistors MP1 and MN1 of the RVM bit cell to the ground or the low potential node, or the circuit path of the devices MP2 and MN2 of the RVM bit cell to the ground or the low potential node. In this example, a 6T RVM bit cell is shown. However, the embodiment is applicable to 4T SRAM, 8T SRAM, dual-port, or CAM bit cells, etc. The 6T RVM bit cell 2021 includes a bit line BL, a bit line bar BLB (which provides a signal opposite to the signal on BL), a word line (WL), a word line bar (WLB) (which provides a signal opposite to the signal on WLB), access devices MNa1 and MNa2, cross-coupled inverter devices MP1, MN1, MP2, and MN2, and storage nodes n0 and n1 coupled together as shown.

[0056] In some embodiments, the more pull-up transistors linked together, the weaker their pull-up effect. Thus, according to some embodiments, the output nodes n0 and n1 of the RVM cell 2021 tend to be pulled down rather than pulled up. For example, if the gain of the pull-up transistors decreases due to aging, the RVM cell 2021 may reach a point where one of its output nodes cannot be pulled up to a logic high when the logic high at the output node corresponds to the correctly stored data. When such a point is reached, the RVM cell 2021 fails, which corresponds to a warning signal that the power supply voltage on node 106 to the memory array 101 should be increased soon.

[0057] In some embodiments, the RVM circuit 350 does not include a voltage drop along its power rails (e.g., node 204a and node 204b) during the read mode. For example, the RVM cell 2021 is attenuated with additional pull-up transistors of the circuit 353 instead of with a lower power supply voltage. Since such a circuit 353 may not require two power paths, as Figures 3B to 3D the method of Figure 3E Returning to reference 1-N in some embodiments, the RVM cell 2021 is directly connected to the power supply voltage, so its constituent transistors are stressed synchronously with the transistors of the actual storage cells 201 in the memory array 101.

[0058] Figure 3F The RVM circuit 360 of

[0059] According to some embodiments, taking advantage of this imbalance or asymmetry, the RVM memory cell 2021 may not be able to store the logical value (first state) corresponding to the logical high value on the branch with multiple pull-up transistors in a manner as reliable as it can store the logical value (second state) corresponding to the logical low value on the branch with multiple pull-up transistors. For example, the RVM memory cell 2021 may have a tendency to stick in the second state rather than the first state. In some embodiments, the RVM memory cell 2021 is loaded with data corresponding to the first state, and when it is observed that the RVM memory cell 2021 has flipped to the second state, this failure corresponds to an early warning signal that the power supply voltage should be increased soon. In some embodiments, the circuit 363 may not require Figure 3B the two power supply paths of the method to FIG. D because the RVM memory cell 2021 is directly connected to the power supply voltage on the node 106. Thus, the transistors of the RVM memory cell 2021 are stressed synchronously with the transistors of the actual memory cells 201 1-N in the memory array 101.

[0060] Some of the embodiments herein are merely some of the ways: in which the RVM memory cell can be weakened for its measurement read, but will still be stressed at full power supply voltage, and this particular purpose of various embodiments can be achieved using a large number of other RVM cell designs.

[0061] Figure 4A -B respectively show the graph 400 and the graph 420 of the static noise margin (SNM) before and after aging. Figure 4A The SNM of 226 mV before aging at 0.7V and a temperature of 110 °C is shown, while Figure 4B the zero SNM of the memory array 101 after 5.6 years of aging is shown, which fails to hold the data in the memory array 101. Various embodiments use the RVM circuit 101b to maintain the decreasing SNM during the entire life of the IC.

[0062] Figure 5A The graph 500 showing Vmin of the memory array across process variations and aging according to some embodiments is illustrated. The graph 500 shows two hold Vmin monitors tracking the hold Vmin of the memory array with process corners (e.g., σ) having a small difference. In this example, each RVM has a different Vmin tracking. The waveform 501 is the Vmin of a 2-stack diode-connected RVM (e.g., Figure 3D ), and the waveform 502 is the Vmin of a 1-stack diode-connected RVM (e.g., Figure 3C)'s Vmin, and waveform 503 is the Vmin of a memory bit cell (e.g., 2011). Based on the simulation results, the 2-stack diode-connected RVM shows better tracking with minimum margin across process and aging variations. Here, the 2-stack diode-connected RVM with 0 to approximately 3σ (e.g., Figure 3D ) has a Vmin slightly higher than the Vmin of the bit cell with 6σ.

[0063] Figure 5B Figure 520 shows a graph of the Vmin with aging cycles showing a memory bit cell and a 2-stack diode-connected RVM according to some embodiments. Waveform 521 is the Vmin of the 2-stack diode-connected RVM with signal 3 (e.g., Figure 3D )'s Vmin, waveform 522 is the Vmin of the 2-stack diode-connected RVM with σ1 (e.g., Figure 3D )'s Vmin, and waveform 523 is the Vmin of the memory bit cell (e.g., 2011). Curve 520 shows the Vmin trend of the 2-stack diode-connected RVM and array 101, where the Vmin of the RVM and the array increases with the number of years. Here, the RVM tracks the retention Vmin of the array well across the entire process limits.

[0064] Figure 6 Figure 600 shows a graph according to some embodiments of the present disclosure having waveforms showing a sampling and stress timing diagram. It should be noted that Figure 6 Those elements having the same reference numerals (or names) as the elements of any other figure may operate or function in any manner similar to the manner described, but are not limited to such a manner. Here, the x-axis is time, and the y-axis of each waveform is voltage. By selecting sampling and stress signals at the head of the p-type device of the RVM circuit, the RVM bit cell 2021 is subjected to full-swing stress and continuously samples the retention Vmin of the bit cell 2021. In some embodiments, when the RVM error signal fails before the array function, the PMU 103 changes the voltage level (e.g., by changing the VID code) via 108 of the power generator 104 until the error signal at node 107 disappears.

[0065] Figure 7A-B shows graphs 700 and 720 of the power savings of the RVM circuit using various embodiments. Graph 700 shows the variation over time of the fixed Vcc 701 and the adaptive Vcc on node 106 regulated by the RVM circuit 101b via the PMU 103 and the power generator 104. Curve 720 shows the corresponding power associated with the fixed Vcc 721 and the adaptive Vcc 722 on node 106. The adaptive voltage scaling (AVS) of various embodiments can start with a lower Vcc than a fixed Vcc scenario that sets (deposit) an aging guard band or margin from the beginning. According to some embodiments, due to the lower Vcc startup, AVS consumes less power throughout the IC usage.

[0066] Figure 8 Shows a smart device or a computer system or a SoC (system on chip) with an adaptive voltage system according to some embodiments. It should be noted that Figure 8 Those elements having the same reference numerals (or names) as the elements in any other figure can operate or run in any manner similar to the described manner, but are not limited to such a manner.

[0067] Figure 8 Shows a block diagram of an embodiment of a mobile device that can use a flat surface interface connector. In some embodiments, the computing device 1600 represents a mobile computing device (such as a computing tablet, a mobile phone or a smart phone, a wireless-enabled e-reader or other wireless mobile device). It should be understood that certain components are generally shown, and not all components of this device are shown in the computing device 1600.

[0068] In some embodiments, as discussed according to some embodiments, the computing device 1600 includes a first processor 1610 having an adaptive voltage system. According to some embodiments, other blocks of the computing device 1600 may also include an adaptive voltage system. In some embodiments, the entire SoC is provided with an adaptive voltage system. Various embodiments of the present disclosure may also include a network interface (such as a wireless interface) within 1670 such that the system embodiments can be incorporated into a wireless device (e.g., a cellular phone or a personal digital assistant).

[0069] In some embodiments, the processor 1610 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing device. Processing operations performed by the processor 1610 include the execution of an operating platform or operating system, on which application programs and / or device functions are executed. Processing operations include operations related to I / O (input / output) with a human user or with other devices, operations related to power management, and / or operations related to connecting the computing device 1600 to another device. Processing operations may also include operations related to audio I / O and / or display I / O.

[0070] In some embodiments, the computing device 1600 includes an audio subsystem 1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functionality to the computing device. Audio functionality may include speaker and / or headphone output, as well as microphone input. Devices for these functions may be integrated into the computing device 1600 or connected to the computing device 1600. In one embodiment, the user interacts with the computing device 1600 by providing audio commands that are received and processed by the processor 1610.

[0071] In some embodiments, the computing device 1600 includes a display subsystem 1630. The display subsystem 1630 represents hardware (e.g., a display device) and software (e.g., drivers) components that provide a visual and / or tactile display for a user to interact with the computing device 1600. The display subsystem 1630 includes a display interface 1632, which includes a particular screen or hardware device for providing a display to the user. In one embodiment, the display interface 1632 includes logic separate from the processor 1610 to perform at least some of the processing related to the display. In one embodiment, the display subsystem 1630 includes a touchscreen (or touchpad) device that provides output and input to the user.

[0072] In some embodiments, the computing device 1600 includes an I / O controller 1640. The I / O controller 1640 represents hardware devices and software components related to interaction with a user. The I / O controller 1640 is operable to manage hardware that is part of the audio subsystem 1620 and / or the display subsystem 1630. Additionally, the I / O controller 1640 represents connection points to additional devices connected to the computing device 1600 through which the user may interact with the system. For example, devices that may be attached to the computing device 1600 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I / O devices for specific applications (such as a card reader or other device).

[0073] As mentioned above, I / O controller 1640 may interact with audio subsystem 1620 and / or display subsystem 1630. For example, input via a microphone or other audio device may provide input or commands to one or more applications or functions of computing device 1600. Additionally, audio output may be provided in lieu of or in addition to a display output. In another example, if display subsystem 1630 includes a touchscreen, the display device also acts as an input device that may be at least partially managed by I / O controller 1640. There may also be additional buttons or switches on computing device 1600 for providing I / O functions that are managed by I / O controller 1640.

[0074] In some embodiments, I / O controller 1640 manages devices such as accelerometers, cameras, light sensors, or other environmental sensors, or other hardware that may be included in computing device 1600. Input may be part of a direct user interaction as well as providing environmental input to the system to affect its operation (such as filtering noise, adjusting the display for brightness detection, applying a flash to a camera, or other features).

[0075] In some embodiments, computing device 1600 includes power management 1650, which manages battery power usage, battery charging, and features related to power-saving operations. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. The memory may include non-volatile (state does not change if the memory device is powered off) and / or volatile (state is indeterminate if the memory device is powered off) memory devices. Memory subsystem 1660 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of computing device 1600.

[0076] The elements of the embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing computer-executable instructions (e.g., instructions for implementing any of the other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to: flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS), which may be transmitted in the form of a data signal via a communication link (e.g., a modem or network connection) from a remote computer (e.g., a server) to a requesting computer (e.g., a client).

[0077] In some embodiments, computing device 1600 includes connection 1670. Connection 1670 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable computing device 1600 to communicate with external devices. Computing device 1600 can be a separate device (such as other computing devices, wireless access points or base stations) and peripheral devices (such as head-mounted devices, printers or other devices).

[0078] Connection 1670 can include various different types of connections. For generality, the illustrated computing device 1600 has a cellular connection 1672 and a wireless connection 1674. Cellular connection 1672 generally refers to a cellular network connection provided by a wireless carrier, such as a cellular network connection provided via GSM (Global System for Mobile Communications) or its variants or derivatives, CDMA (Code Division Multiple Access) or its variants or derivatives, TDM (Time Division Multiplexing) or its variants or derivatives, or other cellular service standards. Wireless connection (or wireless interface) 1674 refers to a non-cellular wireless connection and can include a personal area network (such as Bluetooth, near field, etc.), a local area network (such as Wi-Fi), and / or a wide area network (e.g., WiMAX), or other wireless communications.

[0079] In some embodiments, computing device 1600 includes a peripheral connection 1680. Peripheral connection 1680 includes a hardware interface and connector for making peripheral connections, as well as software components (e.g., drivers, protocol stacks). It should be understood that computing device 1600 can be a peripheral device to other computing devices ("to" 1682) and can have peripheral devices connected to it ("from" 1684). Computing device 1600 typically has a "docking" connector for connecting to other computing devices for purposes such as managing (e.g., downloading and / or uploading, changing, synchronizing) content on computing device 1600. Additionally, the docking connector can allow computing device 1600 to connect to certain peripheral devices that allow computing device 1600 to control, for example, content output to an audiovisual or other system.

[0080] In addition to dedicated docking connectors or other dedicated connection hardware, computing device 1600 can make peripheral connection 1680 via a common or standard-based connector. Common types can include Universal Serial Bus (USB) connectors (which can include any number of different hardware interfaces), DisplayPort including Mini DisplayPort (MDP), High-Definition Multimedia Interface (HDMI), Firewire, or other types.

[0081] References to "embodiments", "one embodiment", "certain embodiments", or "other embodiments" in this specification mean that the particular features, structures, or characteristics described in connection with these embodiments are included in at least some embodiments, but not necessarily in all embodiments. Multiple occurrences of "embodiment", "one embodiment", or "some embodiments" do not necessarily all refer to the same embodiment. If the specification states that a component, feature, structure, or characteristic "may", "might", or "could" be included, that particular component, feature, structure, or characteristic need not be included. If the specification or claim refers to "a" or "an" element, it does not mean that there is only one element. If the specification or claim refers to "additional" elements, that does not preclude the presence of more than one additional element.

[0082] In addition, specific features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, the first embodiment may be combined with the second embodiment as long as the specific features, structures, functions, or characteristics associated with the first and second embodiments are not mutually exclusive.

[0083] Although the present disclosure has been described in connection with specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. Embodiments of the present disclosure are intended to embrace all such alternatives, modifications, and changes that fall within the broad scope of the appended claims.

[0084] In addition, for simplicity of illustration and discussion, and so as not to obscure the present disclosure, power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented figures. Further, in order to avoid obscuring the present disclosure and also in view of the fact that details regarding the implementation of such block diagram arrangements largely depend on the platform on which the present disclosure is to be implemented, the arrangements may be shown in block diagram form (i.e., such details are entirely within the purview of those of ordinary skill in the art). In cases where specific details (e.g., circuits) are set forth to describe example embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that the present disclosure may be practiced without those specific details or with variations of those specific details. The specification is, therefore, to be regarded as illustrative rather than restrictive.

[0085] The following examples relate to further embodiments. Details in the examples may be used anywhere in one or more embodiments. All optional features of the devices described herein may also be implemented with respect to methods or processes. The various embodiments herein may be combined with any other embodiment, allowing for various combinations.

[0086] Example 1 is a device that includes: a first power node; a second power node; a memory bit cell coupled to the second power node; a circuit coupled to the first power node and the second power node, the circuit being operative in a diode-connected mode; and a transistor coupled in parallel to the circuit, wherein the transistor can be controlled by a digital signal such that when the transistor is turned on, it is operative to apply a voltage stress and / or a current stress to the memory bit cell.

[0087] Example 2 includes all of the features of Example 1, wherein the device of Example 2 includes a power management circuit operative to generate a digital signal such that the transistor is turned on in a low-power mode or a hold mode and is turned off in a normal mode or an active mode.

[0088] Example 3 includes all of the features of Example 2, wherein the device of Example 2 includes a sense amplifier operative to determine a logic state stored in the memory bit cell before and after applying the voltage stress and / or the current stress to the memory bit cell.

[0089] Example 4 includes all of the features of Example 3, wherein the device of Example 4 includes a voltage regulator coupled to the power management circuit, wherein the voltage regulator is operative to supply power to the first power node.

[0090] Example 5 includes all of the features of Example 4, wherein the power management circuit is operative to instruct the voltage regulator to adjust the power supply based on an output of the sense amplifier associated with the memory bit cell.

[0091] Example 6 includes all of the features of Example 5, wherein the power management circuit is operative to adjust a value of a voltage identification (VID) code to adjust the power supply.

[0092] Example 7 is according to any one of Examples 2 to 6, wherein the power management circuit is operative to ramp up the power supply on the first power node over time.

[0093] Example 8 is according to any one of Examples 1 to 6, wherein the memory bit cell is a static random access memory bit cell.

[0094] Example 9 is according to any one of Examples 1 to 6, wherein the circuit includes one of the following: a stack of transistors connected as a diode or a single transistor connected as a diode.

[0095] Example 10 is according to any one of Examples 1 to 6, wherein the circuit and the transistor are shared by a column of memory bit cells, and wherein the column of memory bit cells is operative to provide early detection of a memory failure during a standby or hold mode.

[0096] Example 11 is a device that includes: a first power node; a Retention Vmin Monitor (RVM) coupled to a memory, where the RVM is used to detect an aging fault of the memory, where the RVM and the memory are coupled to the first power node, and where the RVM includes: a memory bit cell coupled to a second power node; a circuit coupled to the first power node and the second power node, the circuit being configured to operate in a diode-connected mode; and a transistor coupled in parallel to the circuit, where the transistor can be controlled by a digital signal such that when the transistor is turned on, it is used to apply voltage stress and / or current stress to the memory bit cell.

[0097] Example 12 includes all features of Example 11, where the device of Example 12 includes an Adjustable Replica Bit (TRB) circuit coupled to the memory, where the TRB circuit is used to detect the timing margin of the memory.

[0098] Example 13 includes all features of Example 12, where the device of Example 12 includes an Adjustable Replica Circuit (TRC) coupled to a logic block, where the TRC is used to detect the timing margin and error of the logic block in advance, and where the logic block and the TRC are coupled to the first power node.

[0099] Example 14 includes all features of Example 13, where the device of Example 13 includes power management logic communicatively coupled to the TRB circuit, the TRC, and the RVM.

[0100] Example 15 includes all features of Example 14, where the device of Example 14 includes a voltage regulator coupled to the power management logic, where the power management logic is used to cause the voltage regulator to modulate the power supplied to the first power node according to the outputs of the TRB, the TRC, and the RVM.

[0101] Embodiment 16 is a system that includes: a power regulator; voltage management logic coupled to the power regulator; a first power node coupled to the power regulator; and a processor coupled to the first power node and the power management logic, where the processor includes a memory having memory bit cells coupled to the first power node and a second power node, and where the processor includes: a circuit coupled to the first power node and the second power node, the circuit being configured to operate in a diode-connected mode; and a transistor coupled in parallel to the circuit, where the transistor can be controlled by a digital signal such that when the transistor is turned on, it is used to apply voltage stress and / or current stress to the memory bit cells.

[0102] Example 17 includes all features of Example 16, where the system of Example 16 includes a wireless interface to allow the processor to communicate with another device.

[0103] Example 18 includes all the features of Example 16, wherein the power management logic is used to generate a digital signal such that the transistor is turned on in the low power mode or the hold mode, and is used to turn off in the normal mode.

[0104] Example 19 includes all the features of Example 18, wherein the system of Example 19 includes a sense amplifier for determining the logic state stored in the memory bit cell before and after applying voltage stress and / or current stress to the memory bit cell.

[0105] Example 20 includes all the features of Example 19, wherein the power management circuit is used to instruct the voltage regulator to adjust the power supply on the first power supply node according to the output of the sense amplifier associated with the memory bit cell.

[0106] Example 21 includes all the features of Example 16, wherein the circuit and the transistor are shared by a column of memory bit cells, and wherein the column of memory bit cells is used to provide early detection of memory failures during the standby mode.

[0107] Example 22 includes all the features of Example 16, wherein the voltage regulator is used to supply power to the first power supply node.

[0108] Example 23 includes all the features of Example 16, wherein the power management circuit is used to adjust the value of the voltage identification (VID) code to adjust the power supply on the first power supply node.

[0109] Embodiment 24 is a system that includes: a memory; a processor coupled to the memory, the processor including a device according to any one of Examples 11 to 15; and a wireless interface for allowing the processor to communicate with another device.

[0110] Example 25 is a method that includes: operating in a diode-connected mode; wherein the circuit is coupled to a first power supply node and a second power supply node, wherein the second power supply node is coupled to the memory bit cell; and controlling the transistor by a digital signal such that when the transistor is turned on, it is used to apply voltage stress and / or current stress to the memory bit cell.

[0111] Example 26 includes all the features of Example 25, wherein the method of Example 26 includes: generating a digital signal such that the transistor is turned on in the low power mode or the hold mode, and is used to turn off in the normal mode or the active mode.

[0112] Example 27 includes all the features of Example 26, wherein the method of Example 27 includes: determining the logic state stored in the memory bit cell before and after applying voltage stress and / or current stress to the memory bit cell.

[0113] Example 28 includes all features of Example 27, wherein the method of Example 28 includes: providing power to a first power node.

[0114] Example 29 includes all features of Example 28, wherein the method of Example 29 includes instructing a voltage regulator to adjust the power supply according to a determined logic state associated with a memory bit cell.

[0115] Example 30 includes all features of Example 29, wherein the method of Example 30 includes: adjusting a value of a voltage identification (VID) code to adjust the power supply.

[0116] Example 31 includes all features of Example 25, wherein the method of Example 31 includes: gradually increasing the power supply on the first power node over time.

[0117] Example 32 is according to any one of Examples 25 to 31, wherein the memory bit cell is a static random access memory bit cell.

[0118] Example 33 is according to any one of Examples 25 to 31, wherein the circuit includes one of the following: a transistor stack connected as a diode or a single transistor connected as a diode.

[0119] Example 34 is according to any one of Examples 25 to 31, wherein the circuit and the transistor are shared by a column of memory bit cells, and wherein the column of memory bit cells is used to provide early detection of memory faults during standby or hold mode.

[0120] Example 35 is a device, including: means for operating in a diode-connected mode; wherein the circuit is coupled to a first power node and a second power node, wherein the second power node is coupled to the memory bit cell; and means for controlling the transistor by a digital signal such that when the transistor is turned on, it is used to apply voltage stress and / or current stress to the memory bit cell.

[0121] Example 36 includes all features of Example 35, wherein the device of Example 36 includes: means for generating a digital signal such that the transistor is turned on in a low-power mode or a hold mode and turned off in a normal mode or an active mode.

[0122] Example 37 includes all features of Example 36, wherein the device of Example 37 includes: means for determining the logic state stored in the memory bit cell before and after applying voltage stress and / or current stress to the memory bit cell.

[0123] Example 38 includes all features of Example 37, wherein the device of Example 38 includes: means for providing power to a first power node.

[0124] Example 39 includes all of the features of Example 38, wherein the apparatus of Example 39 includes: means for instructing a voltage regulator to adjust a power supply according to a determined logic state associated with a memory bit cell.

[0125] Example 40 includes all of the features of Example 39, wherein the apparatus of Example 40 includes: means for adjusting a value of a voltage identification (VID) code to adjust a power supply.

[0126] Example 41 includes all of the features of Example 35, wherein the apparatus of Example 41 includes: means for gradually increasing a power supply on a first power supply node over time.

[0127] Example 42 is according to any one of Examples 35 to 41, wherein the memory bit cell is a static random access memory bit cell.

[0128] Example 43 is according to any one of Examples 35 to 41, wherein the circuit includes one of the following: a transistor stack connected as a diode or a single transistor connected as a diode.

[0129] Example 44 is according to any one of Examples 35 to 41, wherein the circuit and the transistor are shared by a column of memory bit cells, and wherein the column of memory bit cells is used to provide early detection of a memory failure during a standby or hold mode.

[0130] Embodiment 45 is a system that includes: a memory; a processor, coupled to the memory, the processor having an apparatus according to any one of Examples 35 to 44; and a wireless interface for allowing the processor to communicate with another device.

[0131] A summary is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. It should be understood that the summary will not be used to limit the scope or meaning of the claims. The appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. An apparatus for reducing aging protection band, the apparatus comprising: A first power node; A second power node; A memory bit cell, the memory bit cell being coupled to the second power node; A circuit, the circuit being coupled to the first power node and the second power node, the circuit being operative in a diode-connected mode; A transistor, the transistor being coupled in parallel with the circuit, wherein the transistor can be controlled by a digital signal such that when the transistor is turned on, the transistor is operative to apply a voltage stress and / or a current stress to the memory bit cell, wherein a column of memory bit cells is operative to provide early detection of memory faults during a standby or hold mode.

2. The apparatus of claim 1, comprising a power management circuit operative to generate the digital signal such that the transistor is turned on in a low power mode or a hold mode and is turned off in a normal mode or an active mode.

3. The apparatus of claim 2, wherein a sense amplifier is operative to determine a logic state stored in the memory bit cell before and after applying the voltage stress and / or the current stress to the memory bit cell.

4. The apparatus of claim 3, comprising a voltage regulator coupled to the power management circuit, wherein the voltage regulator is operative to supply power to the first power node.

5. The device according to claim 4, characterized in that, The power management circuit is operative to instruct the voltage regulator to adjust the power supply based on an output of a sense amplifier associated with the memory bit cell.

6. The device according to claim 5, wherein, The power management circuit is operative to adjust a value of a voltage identification (VID) code to adjust the power supply.

7. The device according to any one of claims 2 to 6, characterized in that, The power management circuit is operative to ramp up the power supply on the first power node over time.

8. The device according to any one of claims 1 to 6, characterized in that, The memory bit cell is a static random access memory bit cell.

9. The device according to any one of claims 1 to 6, characterized in that, The circuit comprises one of the following: a stack of transistors connected as a diode or a single transistor connected as a diode.

10. The device according to any one of claims 1 to 6, characterized in that, The circuit and the transistor are shared by a column of memory bit cells.

11. An apparatus for reducing aging protection band, the apparatus comprising: A first power node; and A hold Vmin monitor RVM, the hold Vmin monitor RVM being coupled to a memory, wherein the hold Vmin monitor RVM is operative to detect an aging fault of the memory, wherein the hold Vmin monitor RVM and the memory are coupled to the first power node, and wherein the hold Vmin monitor RVM comprises: A memory bit cell, the memory bit cell being coupled to a second power node; A circuit, the circuit being coupled to the first power node and the second power node, the circuit being operative in a diode-connected mode; A transistor, the transistor being coupled in parallel with the circuit, wherein the transistor can be controlled by a digital signal such that when the transistor is turned on, the transistor is operative to apply a voltage stress and / or a current stress to the memory bit cell, wherein a column of memory bit cells is operative to provide early detection of memory faults during a standby or hold mode.

12. The device as claimed in claim 11, comprising an adjustable replica bit (TRB) circuit coupled to a memory, wherein the adjustable replica bit (TRB) circuit is configured to detect the timing margin of the memory.

13. The device as claimed in claim 12, comprising an adjustable replica circuit (TRC) coupled to a logic block, wherein the adjustable replica circuit (TRC) is configured to detect in advance the timing margin and error of the logic block, and wherein the logic block and the adjustable replica circuit (TRC) are coupled to the first power supply node.

14. The device as claimed in claim 13, comprising power management logic communicatively coupled to the adjustable replica bit (TRB) circuit, the adjustable replica circuit (TRC), and the hold Vmin monitor (RVM).

15. The device as claimed in claim 14, comprising a voltage regulator coupled to the power management logic, wherein the power management logic is configured to cause the voltage regulator to modulate the power supplied to the first power supply node according to the outputs of the adjustable replica bit (TRB), the adjustable replica circuit (TRC), and the hold Vmin monitor (RVM).

16. A system capable of aging protection with reduction, the system comprising: A voltage regulator; Power management logic coupled to the voltage regulator; A first power supply node coupled to the voltage regulator; And A processor coupled to the first power supply node and the power management logic, wherein the processor includes a memory having memory bit cells coupled to the first power supply node and a second power supply node, and wherein the processor includes: A circuit coupled to the first power supply node and the second power supply node, the circuit being configured to operate in a diode-connected mode; A transistor coupled in parallel to the circuit, wherein the transistor can be controlled by a digital signal such that when the transistor is turned on, the transistor is configured to apply voltage stress and / or current stress to the memory bit cells; Wherein a column of memory bit cells is configured to provide early detection of memory faults during standby or hold mode.

17. The system as claimed in claim 16, comprising a wireless interface for allowing the processor to communicate with another device.

18. The system according to claim 16, wherein The power management logic is configured to generate the digital signal such that the transistor is turned on in low power mode or hold mode and is turned off in normal mode.

19. The system as claimed in claim 18, comprising a sense amplifier configured to determine the logic state stored in the memory bit cells before and after applying the voltage stress and / or current stress to the memory bit cells.

20. The system according to claim 19, wherein, The power management logic is configured to instruct the voltage regulator to adjust the power on the first power supply node according to the output of the sense amplifier associated with the memory bit cells.

21. The system according to claim 16, wherein, The circuit and the transistor are shared by a column of memory bit cells.

22. The system according to claim 16, wherein, The voltage regulator is configured to supply power to the first power supply node.

23. The system according to claim 16, wherein, The power management logic is used to adjust the value of the Voltage Identification (VID) code to adjust the power supply on the first power supply node.

24. A system, comprising: a memory; a processor, the processor being coupled to the memory, the processor including a device for aging protection band reduction, the device according to any one of claims 11 to 15; and a wireless interface for allowing the processor to communicate with another device.

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