A package structure of a DFN device, a leadless frame carrier and a packaging method of the DFN device

Abstract

The application discloses a packaging structure of a DFN device, which comprises a leadless frame carrier, a plurality of first metal pads arranged on the surface of the carrier, a second metal pad arranged on the surface of the first metal pad, a solder layer arranged on the surface of the second metal pad, a lower pad of a chip connected to one end of a bonding wire, and an upper pad of the chip connected to the other end of the bonding wire; a first plastic sealing layer is arranged around the surface of the carrier, the first metal pad, the second metal pad, the solder layer, the chip and the bonding wire, or a second plastic sealing layer is arranged around the surface of the carrier and the first metal pad, and a first plastic sealing layer is arranged around the surface of the second plastic sealing layer, the second metal pad, the solder layer, the chip and the bonding wire; the cross-sectional area of the second metal pad is larger than that of the first metal pad, or the second metal pad is offset to one side of the first metal pad. The application solves the problems of easy virtual welding of the lead frame packaging body pin electrode and the plastic sealing material in the same plane, burr caused by the cutting line of the packaging body, and deformation of the frame.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of microelectronic packaging, in particular to a DFN device packaging structure, a leadless frame carrier and a DFN device packaging method. BACKGROUND

[0002] DFN packaging (also known as double-sided flat no-pin packaging) is developed in recent years with the emergence of communication and portable small digital electronic products, and is suitable for packaging of small and medium scale integrated circuits with high frequency, small size, high speed and other electrical performance requirements. DFN packaging can effectively utilize the packaging space of lead pins, thereby greatly improving the assembly efficiency of the product and reducing the actual occupied area.

[0003] The ordinary DFN packaging usually includes a lead frame, a chip, a metal wire and a plastic encapsulant. Specifically, according to the chip size and circuit connection design frame pattern, the frame processing is completed through etching process, the chip mounting and curing are completed through equipment, and the chip electrode lead-out is completed through wire bonding, and then the whole device is processed through plastic encapsulation.

[0004] However, for super miniaturized devices such as DFN1006 (size 1.0mm*0.6mm*0.4mm), DFN0603 (size 0.6mm*0.3mm*0.3mm) and the like, the packaging structure using the existing lead frame has the following defects:

[0005] (1) The pin electrodes and the plastic encapsulant of the packaging body are in the same plane, which is not conducive to the overall welding of the device and is prone to false welding and other defects;

[0006] (2) The packaging body needs to be cut to the bonding wire part, resulting in partial metal burrs on the side surface of the device, which is not conducive to the subsequent processing of the device;

[0007] (3) The packaging body is limited by the production process of the lead frame, and the thickness of the frame itself is about 125μm at the thinnest. If the frame is too thin, it will be severely deformed, resulting in low yield.

[0008] In view of the above problems, it is an urgent problem to be solved to realize the packaging structure processing of the leadless frame. SUMMARY

[0009] The present application aims to solve the problems of the existing lead frame packaging structure, the pin electrodes and the plastic encapsulant of the packaging body in the same plane, which is not conducive to the overall welding of the device and is prone to false welding, the packaging body needs to be cut to the bonding wire part, resulting in partial metal burrs on the side surface of the device, which is not conducive to the subsequent processing of the device, the packaging body is limited by the production process of the lead frame, the frame is too thin, which will be severely deformed, resulting in low yield, and the packaging body cannot realize super miniaturization. The specific solution is as follows:

[0010] A leadless frame carrier, comprising a carrier, the carrier is composed of a lower substrate layer, a middle peelable layer and an upper metal layer, the substrate layer is any one of metal or inorganic or organic material, the thickness ranges from 0.6mm to 2.0mm, the peelable layer is any one of metal or organic material, the thickness ranges from 0.1μm to 20μm, the peelable layer is on the surface of the substrate layer, the metal layer is any one of copper or nickel or tin, the thickness ranges from 10μm to 30μm, the metal layer is on the surface of the peelable layer or on the surface of the peelable layer and around the peelable layer and the substrate layer.

[0011] Further, the substrate layer is any one of stainless steel or glass or epoxy resin or triazine resin, the material of the substrate layer can be reused after peeling.

[0012] A packaging structure of DFN device, comprising the above-mentioned leadless frame carrier, the surface of the carrier is provided with a plurality of first metal pads, the surface of the first metal pad is provided with a second metal pad, the surface of the second metal pad is provided with a solder layer, the solder layer is connected with the lower pad of the chip or one end of the bonding wire, the other end of the bonding wire is connected with the upper pad of the chip. Optionally 1: the surface of the carrier and around the first metal pad, the second metal pad, the solder layer, the chip and the bonding wire are provided with a first plastic sealing layer, or optionally 2: the surface of the carrier and around the first metal pad are provided with a second plastic sealing layer, the surface of the second plastic sealing layer and around the second metal pad, the solder layer, the chip and the bonding wire are provided with a first plastic sealing layer.

[0013] Further, the packaging structure is peeled off the peelable layer, the substrate layer and the metal layer by physical or chemical methods.

[0014] Further, the first metal pad is any one of copper or nickel, the thickness of the first metal pad ranges from 30μm to 50μm. Further, the solder layer is any one of tin or indium or alloy.

[0015] Further, the bonding wire is a bonding wire, the bonding wire is any one of gold wire or copper wire.

[0016] Further, the second metal pad is any one of copper or nickel, the thickness of the second metal pad ranges from 5μm to 10μm or 30μm to 50μm, the cross-sectional area of the second metal pad is larger than that of the first metal pad, or the second metal pad is offset to one side of the first metal pad.

[0017] A packaging method of DFN device, scheme 1 is carried out according to the following steps:

[0018] Step 1, take a substrate material with thickness ranging from 0.6mm to 2.0mm as a substrate layer;

[0019] Step 2, on the surface of the substrate layer, attach a layer of material with peeling properties with thickness ranging from 0.1μm to 20μm to form a peelable layer;

[0020] Step 3, on the entire surface of the peelable layer or on the entire surface of the peelable layer and the periphery of the peelable layer and the substrate layer, add a layer of metal by physical or chemical means, with the thickness of the metal ranging from 10μm to 30μm to form a metal layer;

[0021] Step 4, according to the on-circuit design of the chip, expose the multiple metal pads to be processed on the surface of the metal layer by covering the photosensitive material and exposing and developing, with the thickness of the photosensitive material ranging from 30μm to 50μm;

[0022] Step 5, process multiple first metal pads on the metal pads by electroplating, with the thickness of the first metal pads ranging from 30μm to 50μm; the thickness of the first metal pads is equal to the thickness of the photosensitive material;

[0023] Step 6, continue to add the electroplating current on the first metal pads to form second metal pads, and remove the photosensitive material by chemical means, with the thickness of the second metal pads ranging from 5μm to 10μm, and the size of the second metal pads being 5μm to 10μm larger than the size of the first metal pads as a whole;

[0024] Step 7, attach a layer of photosensitive material on the second metal pads to generate multiple metal solder patterns by exposing and developing;

[0025] Step 8, complete the processing of the metal solder layer by electroplating or chemical plating, and then remove the excess photosensitive material by chemical means;

[0026] Step 9, complete the soldering by coating the flux and attaching the chip lower pads to the soldered second metal pads, and then heating;

[0027] Step 10, weld one end of the bonding wire to the second metal pads by ultrasonic welding, and weld the other end of the bonding wire to the chip pads;

[0028] Step 11, perform plastic packaging on the surface of the carrier and the periphery of the first metal pads, the second metal pads, the solder layer, the chip, and the bonding wire to complete the packaging of the first plastic packaging layer;

[0029] Step 12, separate the device and the carrier from the peelable layer by physical or chemical means, and the substrate layer after peeling can be reused;

[0030] Step 13, on the bottom surface of the device, by physical or chemical means, according to the structure design of the device, remove the excess metal part, complete the processing of the device pad and the processing of the device.

[0031] A packaging method of DFN device, scheme 2 is carried out according to the following steps:

[0032] Step 1, take a substrate material with a thickness range of 0.6mm-2.0mm as a substrate layer;

[0033] Step 2, on the surface of the substrate layer, attach a layer of material with peeling property with a thickness range of 0.1μm-20μm to form a peelable layer;

[0034] Step 3, by physical or chemical means, add a layer of metal with a thickness range of 10μm-30μm on the entire surface of the peelable layer or on the entire surface of the peelable layer and the four sides of the peelable layer and the substrate layer to form a metal layer;

[0035] Step 4, according to the on-off circuit design of the chip, expose the multiple metal pads to be processed on the surface of the metal layer by covering photosensitive material and exposing and developing, and the thickness of the photosensitive material ranges from 30μm to 50μm;

[0036] Step 5, by electroplating, process multiple first metal pads on the metal pads, and the thickness of the first metal pads ranges from 30μm to 50μm; the thickness of the first metal pads is equal to that of the photosensitive material, and the photosensitive material is removed by chemical method;

[0037] Step 6, the surface of the carrier and the four sides of the first metal pads are plasticized to complete the packaging of the second plastic sealing layer and expose the upper surface of the first metal pads;

[0038] Step 7, attach a layer of photosensitive material on the second plastic sealing layer and the upper surface of the first metal pads, and generate multiple second metal pad patterns by exposure and development;

[0039] Step 8, by electroplating, process second metal pads on the patterns of the second metal pads, and the thickness of the second metal pads ranges from 30μm to 50μm; the photosensitive material is removed by chemical method;

[0040] Step 9, attach a layer of photosensitive material on the upper surface of the second metal pads, and generate multiple metal solder patterns by exposure and development;

[0041] Step 10, by electroplating or chemical plating, complete the processing of the metal solder layer, and then remove the excess photosensitive material by chemical method;

[0042] Step 11, the welding is completed by pasting the chip lower pad to the second metal pad with soldering flux, and heating;

[0043] Step 12, one end of the bonding wire is welded to the second metal pad by ultrasonic welding, and the other end of the bonding wire is welded to the chip pad;

[0044] Step 13, the second plastic encapsulation layer surface and the second metal pad, the solder layer, the chip and the bonding wire are plastic encapsulated, and the encapsulation of the first plastic encapsulation layer is completed;

[0045] Step 14, the carrier with the completed encapsulation is separated from the peelable layer by physical or chemical methods, and the substrate layer after peeling can be reused;

[0046] Step 15, the excess metal part is removed from the bottom surface of the device by physical or chemical methods according to the structure design of the device, and the device pad processing and the device processing are completed.

[0047] In summary, the technical scheme of the present application has the following beneficial effects:

[0048] The present application solves the problems of the existing lead frame packaging structure, the pin electrode and the plastic encapsulation of the packaging body in the same plane, which is not conducive to the overall welding of the device, is easy to produce virtual welding, the packaging body needs to be cut to the bonding wire part, resulting in the existence of part of the metal burr on the side of the device, which is not conducive to the subsequent processing of the device, the packaging body is limited by the production process of the lead frame, the frame is too thin, which will cause serious deformation, resulting in low qualified rate, and the packaging body cannot realize the problem of super miniaturization.

[0049] The present application has the following advantages:

[0050] (1) The ultra-thin frame processing can be completed, and the frame thickness (metal layer + first metal pad + second metal pad) can be controlled to be 40-80 mu m;

[0051] (2) The leadless frame processing can be realized, that is, there is no exposed metal phenomenon on the side of the packaging body device;

[0052] (3) The device pad can be higher than the surface of the plastic encapsulation body, which is more conducive to the welding of the device, and the exposed device pad height can be controlled to be 10-30 mu m;

[0053] (4) The T-shaped structure design composed of the second metal pad and the first metal pad enhances the reliability of the pad;

[0054] (5) The stepped structure design composed of the second metal pad and the first metal pad can reduce the distance between the pads;

[0055] (6) The carrier is wrapped with a metal layer, a peelable layer and a substrate layer around the four sides, which ensures that the entire peelable material is more stable in subsequent processes and is not prone to water ingress. BRIEF DESCRIPTION OF DRAWINGS

[0056] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0057] Figure 1 A structure diagram of a leadless frame carrier according to Embodiment 1 of the present application;

[0058] Figure 2 A structure diagram of a DFN device packaging structure according to Embodiment 1 of the present application;

[0059] Figure 3 A structure diagram of a peelable layer peeling according to Embodiment 1 of the present application;

[0060] Figure 4 A structure diagram of a device and device pad according to Embodiment 1 of the present application;

[0061] Figure 5 A structure diagram of a device and device pad according to Embodiment 2 of the present application;

[0062] Figure 6 A structure diagram of a leadless frame carrier according to Embodiment 3 of the present application;

[0063] Figure 7 A structure diagram of a DFN device packaging structure according to Embodiment 3 of the present application;

[0064] Figure 8 A structure diagram of a DFN device packaging structure according to Embodiment 4 of the present application;

[0065] Figure 9 A structure diagram of a device and device pad according to Embodiment 4 of the present application;

[0066] Figure 10 A structure diagram of a DFN device packaging method scheme 1 of a photosensitive material, a metal pad, a first metal pad and a second metal pad.

[0067] Explanation of reference signs:

[0068] 1-substrate layer, 2-peelable layer, 3-metal layer, 4-first metal pad, 5-second metal pad, 6-solder layer, 7-chip, 8-lower pad, 9-bonding wire, 10-first plastic layer, 11-device pad, 12-cutting line, 13-second plastic layer, 14-photosensitive material, 15-metal pad. DETAILED DESCRIPTION

[0069] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0070] It should be noted that all the drawings in this solution are cross-sectional structural diagrams, which are only used to help understand the inventive concept and structural principles of this solution and are not equivalent to physical products.

[0071] Embodiment 1:

[0072] like Figure 1 As shown, a leadless frame carrier includes a carrier, which is composed of a lower substrate layer 1, a middle peelable layer 2 and an upper metal layer 3. The substrate layer 1 is any one of metal, inorganic or organic materials, and its thickness ranges from 0.6mm to 2.0mm. The peelable layer 2 is any one of metal or organic materials, and its thickness ranges from 0.1μm to 20μm. The peelable layer 2 is located on the surface of the substrate layer 1. The metal layer 3 is any one of copper, nickel or tin, and its thickness ranges from 10μm to 30μm. The metal layer 3 is located on the surface of the peelable layer.

[0073] Furthermore, the substrate layer 1 is made of any one of stainless steel, glass, epoxy resin, and triazine resin. After the material of the substrate layer 1 is peeled off, it can be reused.

[0074] like Figure 2 As shown, a package structure for a DFN (also known as double-sided flat no-lead) device includes the aforementioned leadframe-free carrier. A plurality of first metal pads 4 are provided on the carrier's surface (i.e., the surface of the metal layer 3). Second metal pads 5 are provided on the surface of the first metal pads 4. A solder layer 6 is provided on the surface of the second metal pads 5. The solder layer 6 connects to a lower pad 8 of a chip 7 or one end of a bonding wire 9. The other end of the bonding wire 9 connects to an upper pad of the chip 7 (not shown). Optionally, a first plastic encapsulation layer 10 is provided on the carrier's surface and around the first metal pads 4, second metal pads 5, solder layer 6, chip 7, and bonding wires 9.

[0075] Furthermore, the first metal pad 4 is made of copper or nickel, and the thickness of the first metal pad 4 is in the range of 30 μm to 50 μm.

[0076] Furthermore, the second metal pad 5 is either copper or nickel, the thickness of the second metal pad 5 is in the range of 5μm-10μm, the cross-sectional area of ​​the second metal pad 5 is larger than the cross-sectional area of ​​the first metal pad 4, and the second metal pad 5 and the first metal pad 4 form a T-shaped pad (viewed from the longitudinal section), which enhances the pad reliability.

[0077] Furthermore, the solder layer 6 is made of tin, indium or an alloy.

[0078] Furthermore, the bonding wire 9 is either a gold wire or a copper wire.

[0079] Further, if Figure 3 As shown in the above packaging structure, the peelable layer 2, the base material layer 1 and the metal layer 3 are peeled off by physical or chemical means. Then, on the bottom surface of the device (referring to the bottom surface of the metal layer 3), the excess metal part is removed by physical or chemical means according to the structural design of the device, completing the processing of the device pad 11 and the processing of the device, as shown in FIG. Figure 4 As shown in the figure, it can be seen that the feature of this embodiment 1 is that a first metal pad 4 is connected to a device pad 11.

[0080] Example 2:

[0081] like Figure 5 As shown, the difference from Example 1 is that multiple first metal pads 4 from the lower pads 8 of chip 7 are connected to one device pad 11, and one first metal pad 4 from the upper pad of chip 7 and the bonding wire 9 is connected to another device pad 11. The advantage of this Example 2 is that it can effectively improve the temperature rise of chip 7 or the problem of multi-pin (referring to multiple lower pads 8 or metal pads 4) parallel connection. The rest of the content is exactly the same as that of Example 1 and will not be repeated here.

[0082] Example 3:

[0083] like Figure 6 、 7 As shown, unlike Example 1, the carrier's metal layer 3 is located on the surface of the peelable layer 2 and around both the peelable layer 2 and the substrate layer 1. This structure ensures that the entire peelable material (including the peelable layer 2 and the substrate layer 1) is more stable during subsequent manufacturing processes and is less susceptible to the ingress of chemical solutions. After the package structure is completed, the package is cut along the cutting lines 12 around the package body. The peelable layer 2, substrate layer 1, and metal layer 3 are then physically separated. The remaining details are identical to those of Example 1 and will not be repeated here.

[0084] Example 4:

[0085] As Figure 8 , 9 shown, different from example 3, the surface of the carrier and the periphery of the first metal pad 4 are provided with a second plastic sealing layer 13, the surface of the second plastic sealing layer 13 and the periphery of the second metal pad 5, the solder layer 6, the chip 7 and the bonding wire 9 are provided with a first plastic sealing layer 10. The second metal pad 5 is offset to one side of the first metal pad 4, and the thickness of the second metal pad 5 is in the range of 30 μm-50 μm. The second metal pad 5 of this embodiment 4 and the first metal pad 4 form a stepped pad structure (as viewed from the longitudinal section), which can change the smaller interval of the lower pad 8 and the second metal pad 5 inside the chip 7 into the larger interval of the device pad 11 outside the device through the first metal pad 4. The rest of the content is exactly the same as example 3, and will not be repeated here.

[0086] A packaging method of a DFN device, scheme 1 is implemented according to the following steps:

[0087] Step 1, take a substrate material with a thickness in the range of 0.6mm-2.0mm as a substrate layer 1 (as shown in Figure 1 );

[0088] Step 2, on the surface of the substrate layer 1, attach a layer of material with peeling properties with a thickness in the range of 0.1 μm-20 μm to form a peelable layer 2 (as shown in Figure 1 );

[0089] Step 3, through physical or chemical means, add a layer of metal on the entire surface of the peelable layer 2 (as shown in Figure 1 as optional way one), or on the entire surface of the peelable layer 2 and the periphery of the peelable layer 2 and the substrate layer 1 (as shown in Figure 6 as optional way two), the thickness of the metal is in the range of 10 μm-30 μm to form a metal layer 3;

[0090] Step 4, according to the on-off circuit design of the chip 7, expose the multiple metal pads 15 (actually part of the metal layer 3) that need to be processed on the surface of the metal layer 3 through covering the photosensitive material 14 and exposing and developing, the thickness of the photosensitive material 14 is in the range of 30 μm-50 μm; (as shown in Figure 10 );

[0091] Step 5, through electroplating, process multiple first metal pads 4 on the metal pads 15, the thickness of the first metal pads 4 is in the range of 30 μm-50 μm; the thickness of the first metal pads 4 is equal to that of the photosensitive material 14; (as shown in Figure 10 );

[0092] Step 6, continue to add the current of electroplating, form the second metal pad 5 on the first metal pad 4, remove the photosensitive material 14 by chemical method, the thickness of the second metal pad 5 is 5-10 μm, and the size of the second metal pad is 5-10 μm larger than the size of the first metal pad.(As shown in Figure 10

[0093] Step 7, attach a layer of photosensitive material on the second metal pad 5, and generate a plurality of metal solder patterns by exposure and development;

[0094] Step 8, complete the processing of the metal solder layer 6 by electroplating or chemical plating, and then remove the excess photosensitive material by chemical method;(As shown in Figure 2 5

[0095] Step 9, attach the chip 7 to the second metal pad 5 with the solder by coating the flux on the solder, and complete the soldering after heating;(As shown in Figure 2 5

[0096] Step 10, weld one end of the bonding wire 9 to the second metal pad 5 and the other end of the bonding wire 9 to the pad of the chip 7 by ultrasonic welding;(As shown in Figure 2 5

[0097] Step 11, perform plastic packaging on the surface of the carrier, the first metal pad 4, the second metal pad 5, the solder layer 6, the chip 7, and the bonding wire 9, and complete the packaging of the first plastic packaging layer 10;(As shown in Figure 2 5

[0098] Step 12, separate the device and the carrier from the peelable layer 2 by physical or chemical methods, and the substrate layer 1 after peeling can be reused;(As shown in Figure 3

[0099] The physical method here refers to mechanical force peeling, and the chemical method refers to heating, soaking in chemical solution, etc. to achieve peeling. One side of the device after peeling is black plastic packaging material, and the other side is the bottom metal (i.e. the metal layer 3);

[0100] Step 13, remove the excess metal part on the bottom surface of the device (i.e. the bottom surface of the metal layer 3) by physical or chemical methods according to the structure design of the device, complete the processing of the device pad 11 and the processing of the device.(As shown in Figure 4 5

[0101] ​​​​​​​​​​​​The physical method refers to removing metal by laser ablation and the like, and the chemical method refers to processing the device pad 11 by photo-sensitive material, exposure, development and etching. The size of the device pad 11 can be equal to, larger than or smaller than the size of the first metal pad 4 inside the device.

[0102] A packaging method of a DFN device, scheme 2 is implemented according to the following steps:

[0103] Step 1, a substrate material with a thickness ranging from 0.6 mm to 2.0 mm is taken as a substrate layer 1;

[0104] Step 2, a material with a thickness ranging from 0.1 μm to 20 μm with a peeling property is attached to the surface of the substrate layer 1 to form a peelable layer 2;

[0105] Step 3, a metal layer 3 with a thickness ranging from 10 μm to 30 μm is added to the entire surface of the peelable layer 2 or to the entire surface of the peelable layer 2 and the periphery of the peelable layer 2 and the substrate layer 1 by physical or chemical means;

[0106] Step 4, according to the on-circuit design of the chip 7, a plurality of metal pads 15 to be processed are exposed by covering photo-sensitive material and exposure and development on the surface of the metal layer 3, and the thickness of the photo-sensitive material ranges from 30 μm to 50 μm;

[0107] Step 5, a plurality of first metal pads 4 are processed and formed on the metal pads 15 by electroplating, and the thickness of the first metal pads 4 ranges from 30 μm to 50 μm; the thickness of the first metal pads 4 is equal to the thickness of the photo-sensitive material, and the photo-sensitive material is removed by chemical means;

[0108] Step 6, the surface of the carrier and the periphery of the first metal pads 4 are plasticized to complete the packaging of the second plastic layer 13 and expose the upper surface of the first metal pads 4; (as shown in Figure 8 、 9 )

[0109] Step 7, a photo-sensitive material is attached to the second plastic layer 13 and the upper surface of the first metal pads 4, and a plurality of second metal pads 5 are generated by exposure and development;

[0110] Step 8, a plurality of second metal pads 5 are processed and formed on the patterns of the second metal pads 5 by electroplating, and the thickness of the second metal pads 5 ranges from 30 μm to 50 μm, and the photo-sensitive material is removed by chemical means; (as shown in Figure 8 、 9 )

[0111] Step 9, on the surface of the second metal pad 5, a layer of photosensitive material is attached, and a plurality of metal solder patterns are generated by exposure and development. Figure 8 、 9

[0112] Step 10, the metal solder layer 6 is processed by electroplating or electroless plating, and then the excess photosensitive material is removed by chemical method. Figure 8 、 9

[0113] Step 11, the chip 7 is attached to the second metal pad 5 with solder by applying flux and heating. Figure 8 、 9

[0114] Step 12, the bonding wire 9 is welded to the second metal pad 5 by ultrasonic welding, and the other end of the bonding wire 9 is welded to the pad on the chip 7. Figure 8 、 9

[0115] Step 13, the surface of the second plastic encapsulation layer 13 and the second metal pad 5, solder layer 6, chip 7, bonding wire 9 are encapsulated, and the first plastic encapsulation layer 10 is completed. Figure 8 、 9

[0116] Step 14, the carrier with completed packaging is separated from the peelable layer 2 by physical or chemical means, and the substrate layer 1 after peeling can be reused. Figure 9

[0117] Step 15, on the bottom surface of the device, the excess metal part is removed by physical or chemical means according to the structure design of the device, and the device pad 11 is processed and the device is processed. Figure 9

[0118] In summary, the technical scheme of the present application has the following advantages:

[0119] The present application solves the problem of the packaging structure of the existing lead frame, the pin electrode of the packaging body and the plastic encapsulation material in the same plane, which is not conducive to the overall welding of the device, and is prone to false welding. The packaging body needs to be cut to the bonding wire part, resulting in metal burrs on the side of the device, which is not conducive to the subsequent processing of the device. The packaging body is limited by the production process of the lead frame, and the frame is too thin, which may cause serious deformation, resulting in low yield and the problem that the packaging body cannot be miniaturized.

[0120] The present application has the following advantages: ​​​​​​​

[0121] (1) can complete the processing of ultra-thin frame, frame thickness (referring to the metal layer 3 + the first metal pad 4 + the second metal pad 5) can be controlled to 40μm-80μm thinnest;

[0122] (2) can realize the frame processing without lead, that is, there is no exposed metal phenomenon on the side of the packaged device;

[0123] (3) can realize that the device pad 11 is higher than the surface of the plastic package body, which is more beneficial to the welding of the device, and the exposed device pad 11 height can be controlled to 10μm-30μm;

[0124] (4) the T-shaped structure design of the second metal pad 5 and the first metal pad 4 is adopted, which enhances the reliability of the pad;

[0125] (5) the step-shaped structure design of the second metal pad 5 and the first metal pad 4 is adopted, which can reduce the spacing between the pads;

[0126] (6) the carrier adopts the metal layer 3 wrapping the peelable layer 2 and the four sides of the peelable layer 2 and the substrate layer 1, which ensures that the entire peelable material is more stable in performance in the subsequent process, and is not easy to exist into the medicine phenomenon.

[0127] The above-mentioned embodiments do not constitute a limitation on the protection scope of the technical solutions. Any modification, equivalent replacement and improvement made within the spirit and principles of the above-mentioned embodiments shall be included in the protection scope of the technical solutions.

Claims

1. A packaging method for a double-sided flat leadless DFN device, characterized in that: According to the following steps: Take a substrate material, thickness range of 0.6 mm-2.0 mm, as a substrate layer; In the surface of the substrate layer, a layer of material with a thickness range of 0.1 μm-20 μm is attached to form a peelable layer; A layer of metal with a thickness range of 10 μm-30 μm is added to the entire surface of the peelable layer and the four corners of the peelable layer and the substrate layer to form a metal layer; According to the chip's circuit design, expose the multiple metal pads that need to be processed on the surface of the metal layer by covering the photosensitive material, exposing and developing, and the thickness of the photosensitive material is 30 μm-50 μm; Process multiple first metal pads on the metal pads by electroplating, and the thickness of the first metal pads is equal to that of the photosensitive material; Form second metal pads on the first metal pads by electroplating, and remove the photosensitive material by chemical method, and the thickness of the second metal pads is 5 μm-10 μm, and the size of the second metal pads is 5 μm-10 μm larger than that of the first metal pads to form a T-shaped structure in vertical cross-section; Attach a layer of photosensitive material to the second metal pads, and generate multiple metal solder patterns by exposing and developing; Complete the processing of the metal solder layer by electroplating or chemical plating, and then remove the excess photosensitive material by chemical method; Complete the welding by coating the flux and attaching the chip's lower pads to the soldered second metal pads, and then heating; Weld one end of the bonding wire to another second metal pad by ultrasonic welding, and weld the other end of the bonding wire to the chip's pad; Encapsulate the surface of the metal layer and the four corners of the first metal pads, second metal pads, solder layer, chip, and bonding wire to complete the packaging of the first encapsulation layer; Separate the device and the metal layer from the peelable layer for the metal layer that has completed packaging, and the peeled substrate layer can be reused; Remove the excess metal parts according to the device's structure design on the bottom surface of the device to complete the processing of the device's pads and the device.

2. A method of packaging a dual-sided flat no-lead (DFN) device, the method comprising: According to the following steps: Form a peelable layer with a thickness of 0.1 μm-20 μm on the surface of a substrate layer with a thickness of 0.6 mm-2.0 mm; Form a metal layer with a thickness of 10 μm-30 μm on the entire surface of the peelable layer and the four corners of the peelable layer and the substrate layer; According to the chip's circuit design, cover the photosensitive material with a thickness of 30 μm-50 μm on the surface of the metal layer, expose and develop to expose multiple metal pads that need to be processed; Electroplate multiple first metal pads on the metal pads, and the thickness of the first metal pads is equal to that of the photosensitive material, and remove the photosensitive material by chemical method; Encapsulate the surface of the metal layer and the four corners of the first metal pads to complete the packaging of the second encapsulation layer and expose the upper surface of the first metal pads; Attach a layer of photosensitive material to the second encapsulation layer and the upper surface of the first metal pads, and generate multiple second metal pad patterns by exposing and developing; On the second metal pad pattern, a plurality of second metal pads with thickness of 30-50 μm are formed by electroplating, the second metal pads and the first metal pads form a structure with stepped longitudinal section, the interval between the second metal pads is smaller than the interval between the first metal pads, and the photo-sensitive material is removed by chemical method; A layer of photo-sensitive material is attached to the surface of the second metal pads, and a plurality of metal solder patterns are formed by exposure and development; The electroplating or chemical plating is completed to process the metal solder layer, and the excess photo-sensitive material is removed by chemical method; The solder paste is coated, the chip lower pads are attached to the second metal pads with solder, and the welding is completed after heating; The ultrasonic welding is used to weld one end of the bonding wire to the other second metal pads, and the other end of the bonding wire is welded to the chip upper pads; The surface of the second plastic encapsulation layer and the second metal pads, the solder layer, the chip, and the bonding wire are plastic encapsulated, and the encapsulation of the first plastic encapsulation layer is completed; The device and the metal layer are separated from the peelable layer, and the substrate layer after peeling can be reused; The excess metal parts are removed from the bottom surface of the device according to the structure design of the device, and the processing of the device pads and the device is completed.

3. A packaging structure of a dual flat no-lead (DFN) device, implemented by the packaging method of the dual flat no-lead (DFN) device of any one of claim 1 or claim 2, comprising a leadless frame carrier, characterized in that: The carrier is composed of a lower substrate layer, a middle peelable layer, and an upper metal layer, the substrate layer is any one of stainless steel, glass, epoxy resin, or triazine resin, and has a thickness of 0.6-2.0 mm, the peelable layer is any one of metal or organic material, and has a thickness of 0.1-20 μm, the peelable layer is on the surface of the substrate layer, the metal layer is any one of copper, nickel, or tin, and has a thickness of 10-30 μm, the metal layer is on the surface of the peelable layer and around the peelable layer and the substrate layer, the material of the substrate layer can be reused after peeling, the surface of the carrier is provided with a plurality of first metal pads, the surface of the first metal pads is provided with second metal pads, one end of the bonding wire is connected to the second metal pads, and the other end of the bonding wire is connected to the chip upper pads.

4. The package structure of a dual-sided flat no-lead (DFN) device according to claim 3, wherein: The first metal pads are any one of copper or nickel, and have a thickness of 30-50 μm.

5. The package structure of a dual-sided flat no-lead (DFN) device according to claim 4, wherein: The second metal pads are any one of copper or nickel.

6. The package structure of a dual-sided flat no-lead (DFN) device according to claim 5, wherein: The solder layer is any one of tin, indium, or alloy.

7. The package structure of a dual-sided flat no-lead (DFN) device according to claim 6, wherein: The bonding wire is any one of gold wire or copper wire.

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