Semiconductor device and semiconductor testing equipment

Abstract

A semiconductor device and a semiconductor test equipment are provided. The semiconductor device includes a signal generator and a decoding and timing skew adjustment circuit. The signal generator is configured to receive n multi-level signals with m signal levels and convert the n multi-level signals into n*(m-1) single-level signals with two signal levels. The decoding and timing skew adjustment circuit is configured to receive the single-level signal, perform a predefined operation on the single-level signal to generate an output signal, and use the single-level signal to compensate for the timing skew between the n multi-level signals. n and m are natural numbers, wherein n>=2 and m>=3.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The Korean Patent Application No. 10-2018-0060551, entitled “Semiconductor device including a high-speed receiver being capable of adjusting timing skew for multi-level signal and testing equipment including the receiver,” filed on May 28, 2018 in the Korean Intellectual Property Office, is incorporated herein in its entirety by reference. Technical Field

[0003] Embodiments of the inventive concept relate to a semiconductor device including a high-speed multi-level signal receiver capable of adjusting timing and a semiconductor test equipment including the receiver. Background Art

[0004] As the operating speed of semiconductor devices increases, there is a need to similarly increase the communication speed between devices. Multi-level signals having three or more signal levels can be utilized to meet the increased communication speed requirements.

[0005] Due to certain environmental factors, timing skew may occur in signals exchanged between devices. However, timing skew reduces the reliability of signal communication between devices. Therefore, it is necessary to adjust the timing skew to improve the reliability of signal communication. Summary of the invention

[0006] At least one embodiment of the inventive concept provides a semiconductor device capable of adjusting a timing skew between multi-level signals.

[0007] At least one embodiment of the inventive concept provides a semiconductor test apparatus capable of performing reliable testing by adjusting a timing skew between received multi-level signals.

[0008] According to an exemplary embodiment of the inventive concept, a semiconductor device is provided, the semiconductor device comprising: a signal generator configured to receive n multilevel signals having m signal levels and convert the n multilevel signals into n*(m-1) single-level signals having two signal levels; and a decoding and timing skew adjustment circuit configured to receive the single-level signal, perform a predefined operation on the single-level signal to generate an output signal, and use the single-level signal to compensate for the timing skew between the n multilevel signals. n and m are natural numbers, wherein n>=2 and m>=3.

[0009] According to an exemplary embodiment of the inventive concept, a semiconductor device is provided, the semiconductor device comprising: a comparator circuit configured to receive a first analog signal having m signal levels and compare the first analog signal with m-1 reference signals to output a first digital signal and a second digital signal, receive a second analog signal having m signal levels and compare the second analog signal with the m-1 reference signals to output a third digital signal and a fourth digital signal; and a timing skew adjustment circuit configured to use the first digital signal to the fourth digital signal to compensate for a timing skew between the first analog signal and the second analog signal. m is a natural number >=3.

[0010] According to an exemplary embodiment of the inventive concept, a semiconductor test device is provided, the semiconductor test device comprising: a receiver configured to receive a first multi-level signal and a second multi-level signal from a circuit, convert the first multi-level signal and the second multi-level signal into a plurality of single-level signals, and generate an output signal using the plurality of single-level signals; and a tester configured to test the circuit using the output signal, wherein the first multi-level signal and the second multi-level signal each have m levels, wherein m is a natural number greater than or equal to 3, each of the single-level signals has two levels, and the receiver uses the plurality of single-level signals to compensate for a timing skew between the first multi-level signal and the second multi-level signal to generate the output signal.

[0011] According to an exemplary embodiment of the present invention, a semiconductor device is provided, comprising: a signal generator configured to convert n multi-level first signals having m signal levels into n*(m-1) single-level first signals having two signal levels; and a decoding and timing skew adjustment circuit configured to perform a predefined operation on the single-level first signal to generate a control signal. The signal generator is configured to convert n multi-level second signals having m signal levels into n*(m-1) single-level second signals having two signal levels. The decoding and timing skew adjustment circuit uses the control signal to compensate for the timing skew between the n multi-level second signals. n and m are natural numbers, n>=2 and m>=3. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0013] Figure 1 is a block diagram for explaining a semiconductor device according to an exemplary embodiment of the inventive concept;

[0014] Figure 2 It is used to illustrate Figure 1 A diagram of a multi-level signal;

[0015] Figure 3 yes Figure 1 An exemplary detailed block diagram of a converter of;

[0016] Figure 4 is a diagram for explaining a process of converting a multi-level signal into a single-level signal;

[0017] Figure 5 yes Figure 1 An exemplary detailed block diagram of a decoding and timing skew adjustment circuit of;

[0018] Figure 6 is a block diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0019] Figure 7 yes Figure 6 An exemplary detailed block diagram of a decoding circuit and a timing skew adjustment circuit;

[0020] Figure 8 is a block diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0021] Fig. 9 yes Figure 8 An exemplary detailed block diagram of;

[0022] Fig.10is a diagram for explaining an operation of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0023] Fig.11 is a block diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0024] Fig.12 It is an example Fig.11 A diagram of a register;

[0025] Fig.13 and Fig.14 is a diagram illustrating an operation of a semiconductor device according to an exemplary embodiment of the inventive concept; and

[0026] Fig.15 is a block diagram illustrating a semiconductor testing apparatus according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0027] Reference will now be made to exemplary embodiments of the present inventive concept illustrated in the accompanying drawings, wherein like reference numerals refer to like components throughout.

[0028] The term "multi-level signal" used below refers to a signal having more than three signal levels. For example, in the case of a multi-level signal having three signal levels, the multi-level signal may have signal levels such as H (logic high), M (logic medium), and L (logic low). For example, the multi-level signal may be set to have a first voltage level, a second voltage level, or a third voltage level, wherein the second voltage level is higher than the first voltage level, and the third voltage level is higher than the second voltage level.

[0029] In some embodiments, an analog signal may be described as such a “multi-level signal.” That is, in some embodiments, a “multi-level signal” may be, for example, an analog signal.

[0030] In addition, the term "single-level signal" used below refers to a signal having two signal levels. The single-level signal may have signal levels such as H (logic high) and L (logic low). For example, the single-level signal may be set to a first voltage level or a second voltage level, wherein the second voltage level is higher than the first voltage level.

[0031] In one embodiment, the signal level of logic high (H) of the single-level signal is represented as 1, and the signal level of logic low (L) is represented as 0. A signal having such two signal levels is called a "single-level signal" because the above-mentioned multi-level signal transmits more than two pieces of other information with the L signal level as a reference value, while the single-level signal transmits only one piece of other information with the L signal level as a reference value.

[0032] In some embodiments, a digital signal may be expressed as such a “single-level signal.” That is, in some embodiments, a “single-level signal” may be, for example, a digital signal.

[0033] Figure 1 is a block diagram for explaining a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 2 It is used to illustrate Figure 1 Schematic diagram of a multi-level signal. Figure 3 yes Figure 1 An exemplary detailed block diagram of a converter. Figure 4 is a diagram for explaining a process of converting a multi-level signal into a single-level signal. Figure 5 yes Figure 1 An exemplary detailed block diagram of a decoding and timing skew adjustment circuit is shown in FIG.

[0034] First refer to Figure 1 , a semiconductor device 1 includes a converter 100 (eg, a signal generator or a signal converter) and a decoding and timing skew adjustment circuit 200 .

[0035] In an exemplary embodiment, the semiconductor device 1 is a receiver coupled to a specific device to receive and process a signal or a receiving module including a receiver. For example, the semiconductor device 1 may include a transceiver and an antenna that enables the device to wirelessly transmit / receive signals. However, the inventive concept is not limited to a receiver and can therefore be applied to other circuit types.

[0036] The term "circuit" or "block" used herein may refer to a hardware component, such as hardware or an application specific circuit (ASIC) implemented in a field programmable gate array (FPGA). Moreover, a "circuit" or "block" may be implemented as a separate chip. Furthermore, the term "block" may be implemented as software rather than hardware.

[0037] Such a "circuit" or "block" plays a specific role or performs a specific function. The functionality provided in a component and "circuit" or "block" may be combined into fewer components and "circuit" or "blocks", or may be further divided into additional components and "circuit" or "blocks".

[0038] The converter 100 receives a plurality of multi-level signals (MLS1 to MLSn) from an external source, and converts the plurality of provided multi-level signals (MLS1 to MLSn) into a plurality of single-level signals (SLS11 to SLSn(m-1)). In an exemplary embodiment, the converter 100 receives n (where n is a natural number of 2 or more) multi-level signals (MLS1 to MLSn) from an external source, and outputs n*(m-1) single-level signals (SLS11 to SLSn(m-1)) by comparing each multi-level signal (MLS1 to MLSn) with m-1 reference signals (R1 to R(m-1)). In one embodiment, n is a natural number of 2 or more, and m is a natural number of 3 or more. In one embodiment, n is less than m.

[0039] As described above, each multi-level signal (MLS1 to MLSn) can be a signal having m (m is a natural number of 3 or greater) signal levels, and each single-level signal (SLS11 to SLSn(m-1)) can be a signal having two signal levels of logic high (H, 1) and logic low (L, 0).

[0040] These multi-level signals (MLS1 to MLSn) and reference signals (R1 to R(m-1)) will be described in more detail below.

[0041] Reference Figure 2 , each multi-level signal (MLS1 to MLSn) has m signal levels from a first signal level (L1) to an mth signal level (Lm) (e.g., L1, L2, L3, etc.). In some embodiments, the first signal level (L1) is a logic low value represented by 0, but embodiments of the present invention are not limited thereto.

[0042] In one embodiment, the amplitude of each reference signal (R1 to R(m-1)) (e.g., R1, R2, etc.) is defined as a value (e.g., a median value) between the signal levels (L1 to Lm) of the multi-level signals (MLS1 to MLSn). In one embodiment, the amplitude of the first reference signal (R1) is defined as a value between the first signal level (L1) and the second signal level (L2), the amplitude of the second reference signal (R2) is defined as a value between the second signal level (L2) and the third signal level (L3), and the amplitude of the (m-1)th reference signal (R(m-1)) is defined as a value between the (m-1)th signal level (L(m-1)) and the mth signal level (Lm). In an exemplary embodiment, the amplitude of the first reference signal (R1) is an average value of the first signal level (L1) and the second signal level (L2), and the amplitude of the second reference signal (R2) is an average value of the second signal level (L2) and the third signal level (L3).

[0043] Refer again Figure 1 , for each multi-level signal (MLS1 to MLSn), the converter 100 outputs m-1 single-level signals (SLS11 to SLSn(m-1)). In one embodiment, the converter 100 receives the multi-level signal (MLS1) and converts the received multi-level signal (MLS1) into m-1 single-level signals (SLS11 to SLS1(m-1)) using m-1 reference signals (R1 to R(m-1)). In addition, the converter 100 receives the multi-level signal (MLSn) and converts the multi-level signal (MLSn) into m-1 single-level signals (SLSn1 to SLSn(m-1)) using m-1 reference signals (R1 to R(m-1)). For example, when n is 2 and m is 3, the converter 100 converts the first multilevel signal MLS1 into two single level signals by comparing the first multilevel signal MLS1 with the first reference signal R1 and the second reference signal R2, and converts the second multilevel signal MLS2 into two other single level signals by comparing the second multilevel signal MLS2 with the first reference signal R1 and the second reference signal R2.

[0044] The converter 100 that receives n multi-level signals (MLS1 to MLSn) and compares each multi-level signal (MLS1 to MLSn) with m-1 reference signals (R1 to R(m-1)) to output n*(m-1) single-level signals (SLS11 to SLSn(m-1)) is not limited to a specific configuration. Hereinafter, as an example of an embodiment, an embodiment in which the converter 100 is configured using a comparator will be described, but the inventive concept is not limited thereto.

[0045] Reference Figure 3 , the converter 100 includes n*(m-1) comparators (C11 to Cn(m-1)). Each comparator (C11 to Cn(m-1)) compares one of the multi-level signals (MLS1 to MLSn) with one of the reference signals (R1 to R(m-1)) and outputs the comparison result as a corresponding one of the single-level signals (SLS11 to SLSn(m-1)).

[0046] In one embodiment, the comparator C11 compares the multi-level signal (MLS1) with the reference signal (R1) and outputs the comparison result as a single-level signal (SLS11), the comparator C12 compares the multi-level signal (MLS1) with the reference signal (R2) and outputs the comparison result as a single-level signal (SLS12), and the comparator C1(m-1) compares the multi-level signal (MLS1) with the reference signal (R(m-1)) and outputs the comparison result as a single-level signal (SLS1(m-1)). In addition, the comparator Cn1 compares the multi-level signal (MLSn) with the reference signal (R1) and outputs the comparison result as a single-level signal (SLSn1), the comparator Cn2 compares the multi-level signal (MLSn) with the reference signal (R2) and outputs the comparison result as a single-level signal (SLSn2), and the comparator Cn(m-1) compares the multi-level signal (MLSn) with the reference signal (R(m-1)) and outputs the comparison result as a single-level signal (SLSn(m-1)).

[0047] In the following, reference will be made to Figure 3 and Figure 4 Describe this in more detail.

[0048] Figure 4 is a diagram illustrating an example in which a multi-level signal ( MLS1 ) has four signal levels ( L1 to L4 ) (ie, an example in which m=4).

[0049] Reference Figure 4 The multi-level signal (MLS1) has a first signal level (L1) in a first portion (T1), a third signal level (L3) in a second portion (T2), a fourth signal level (L4) in a third portion (T3), and a second signal level (L2) in a fourth portion (T4).

[0050] Thus, when the multilevel signal (MLS1) has four levels, Figure 3 The converter 100 requires three comparators (C11, C12, and C13) to convert the multi-level signal (MLS1) into three single-level signals (SLS11, SLS12, and SLS13).

[0051] In the first part (T1), the comparator C11 compares the multi-level signal (MLS1) with the reference signal (R1), and since the multi-level signal (MLS1) is less than the reference signal (R1), the comparator C11 outputs 0. That is, the single-level signal (SLS11) has a logic low (L) value. The fact that the single-level signal (SLS11) has a logic low (L) value or 0 is merely an example for ease of explanation, and the type of the value of the single-level signal (SLS11) may be changed according to the embodiment. For example, in some embodiments, if the multi-level signal (MLS1) is less than the reference signal (R1), the embodiment is modified so that the single-level signal (SLS11) has a logic high (H) or 1 value.

[0052] In the first section (T1), the comparator C12 compares the multi-level signal (MLS1) with the reference signal (R2), and outputs 0 because the multi-level signal (MLS1) is smaller than the reference signal (R2). Therefore, the single-level signal (SLS12) is also 0. In addition, the comparator C13 compares the multi-level signal (MLS1) with the reference signal (R3), and outputs 0 because the multi-level signal (MLS1) is smaller than the reference signal (R3). Therefore, the single-level signal (SLS13) is also 0.

[0053] Since the multi-level signal (MLS1) is greater than the reference signal (R1) and the reference signal (R2) but less than the reference signal (R3) in the second portion (T2), the single-level signal (SLS11) and the single-level signal (SLS12) are 1, and the single-level signal (SLS13) is 0.

[0054] Since the multi-level signal (MLS1) is greater than the reference signal (R1), the reference signal (R2) and the reference signal (R3) in the third section (T3), the single-level signal (SLS11), the single-level signal (SLS12) and the single-level signal (SLS13) are 1.

[0055] Since the multi-level signal (MLS1) is greater than the reference signal (R1) but less than the reference signal (R2) and the reference signal (R3) in the fourth section (T4), the single-level signal (SLS11) is 1, and the single-level signal (SLS12) and the single-level signal (SLS13) are 0.

[0056] That is, the multilevel signal (MLS1) is represented by converting the multilevel signal (MLS1) having four signal levels (L1 to L4) into three single level signals (SLS11 to SLS13) having two signal levels (0, 1) in each section (T1 to T4).

[0057] Refer again Figure 1The decoding and timing skew adjustment circuit 200 receives n*(m-1) single-level signals (SLS11 to SLSn(m-1)) from the converter 100 and performs or executes a predefined operation to generate an output signal (OS), and can use the n*(m-1) single-level signals (SLS11 to SLSn(m-1)) to compensate for the timing skew between the n multi-level signals (MLS1 to MLSn). For example, the converter 100 performs a predefined operation on the single-level signal to generate the output signal.

[0058] As a result, even if there is a timing skew between the n multilevel signals (MLS1 to MLSn), the output signal (OS) outputted from the decoding and timing skew adjusting circuit 200 can be outputted by compensating for the timing skew existing between the n multilevel signals (MLS1 to MLSn).

[0059] although Figure 1 One output signal (OS) is illustrated, but the present invention is not limited thereto. For example, the timing skew adjustment circuit 200 may be configured to output a plurality of output signals. In addition, the output signal (OS) may be implemented by being modified into a plurality of segments according to the form of the operation performed by the decoding and timing skew adjustment circuit 200.

[0060] The decoding and timing skew adjustment circuit 200 is not limited to a specific configuration. That is, the decoding and timing skew adjustment circuit 200 that receives n*(m-1) single-level signals (SLS11 to SLSn(m-1)) and performs a predefined operation to generate an output signal (OS), and uses the n*(m-1) single-level signals (SLS11 to SLSn(m-1)) to compensate for the timing skew between n multi-level signals (MLS1 to MLSn) is not limited to a specific configuration.

[0061] In the following, reference will be made to Figure 5 1 to describe an exemplary embodiment of the decoding and timing skew adjustment circuit 200, but as mentioned above, embodiments of the present invention are not limited thereto.

[0062] Reference Figure 5 The decoding and timing skew adjustment circuit 200 includes a buffer circuit 210 , a decoding circuit 220 and a timing skew adjustment circuit 230 .

[0063] The buffer circuit 210 receives n*(m-1) single level signals (SLS11 to SLSn(m-1)), buffers the n*(m-1) single level signals (SLS11 to SLSn(m-1)) and outputs buffered (or delayed) single level signals (BSLS11 to BSLSn(m-1)).

[0064] In some embodiments, when the decoding circuit 220 performs the buffering function, the buffer circuit 210 is omitted.

[0065] The decoding circuit 220 performs a predefined operation on the buffered single-level signals (BSLS11 to BSLSn(m-1)) provided from the buffer circuit 210 to generate an output signal. In addition, the decoding circuit 220 may output the generated output signal (OS) to a circuit (not shown) at a subsequent stage. Here, the circuit at the subsequent stage may be, for example, a circuit that performs an operation using the output signal (OS) or a circuit that controls the operation of another circuit using the output signal (OS). For example, the circuit may use the output signal (OS) as a clock signal to control the timing of another circuit.

[0066] As described above, a plurality of output signals (OS) may exist according to an embodiment, and when the buffer circuit 210 is omitted, the decoding circuit 220 directly receives the single level signal (SLS11 to SLSn(m-1)).

[0067] The timing skew adjustment circuit 230 compensates for the timing skew between the n multilevel signals (MLS1 to MLSn) using the buffered single level signals (BSLS11 to BSLSn(m-1)) or the single level signals (SLSn11 to SLSn(m-1)) when the buffer circuit 210 is omitted.

[0068] Specifically, the timing skew adjustment circuit 230 can control the decoding circuit 220 so that the decoding circuit 220 outputs n multi-level signals ( Figure 1 In one embodiment, the output signal (OS) is composed of a plurality of sub-signals, which are synchronized with each other (e.g., there is no skew between the sub-signals). In one embodiment, one or more sub-signals are used to control the operation of another circuit or control the timing of another circuit.

[0069] Although the decoding circuit 220 and the timing skew adjustment circuit 230 are illustrated separately in the drawings, the embodiment is not limited thereto. In some embodiments, the timing skew adjustment circuit 230 is implemented by being integrated into the decoding circuit 220 .

[0070] In the case of a multi-level signal having a plurality of signal levels, compensating for the timing skew between the multi-level signals is more difficult and more complicated than compensating for the timing skew between the single-level signals having two signal levels. Therefore, in the present embodiment, each multi-level signal having n signal levels is converted into n*(m-1) single-level signals by m-1 reference signals and n*(m-1) comparators, and the converted single-level signals are used to compensate for the timing skew between the multi-level signals. Therefore, it is easier to compensate for the timing skew between the multi-level signals.

[0071] Figure 6 is a block diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 7 yes Figure 6 An exemplary detailed block diagram of a decoding and timing skew adjustment circuit of FIG. 1 is shown in FIG. 1 . Hereinafter, repeated description of the above-mentioned embodiment will be omitted, and the differences will be mainly described.

[0072] Reference Figure 6 The timing skew adjustment circuit 400 of the semiconductor device 2 compensates for the timing skew between the n multi-level signals (MLS1 to MLSn) based on the output signal (OS) output from the decoding circuit 300. In one embodiment, the timing skew adjustment circuit 400 generates a control signal (CS) for compensating for the timing skew between the n multi-level signals (MLS1 to MLSn) based on the output signal (OS) output from the decoding circuit 300, and provides the control signal (CS) to the decoding circuit 300, so that the decoding circuit 300 outputs the output signal (OS) in which the timing skew between the n multi-level signals (MLS1 to MLSn) is compensated.

[0073] According to such a configuration, in some embodiments, the output signal (OS) initially output by the decoding circuit 300 is a signal in which the timing signal skew between the n multi-level signals (MLS1 to MLSn) is not compensated. Therefore, the semiconductor device 2 does not output the output signal (OS) to the outside, but only provides the output signal (OS) to the timing skew adjustment circuit 400. In other words, the semiconductor device 2 may require a fixed time of initialization time until the decoding circuit 300 outputs the output signal (OS) in which the timing skew between the n multi-level signals (MLS1 to MLSn) is compensated. For example, the decoding circuit 300 may output a first output signal based on a first buffered single-level signal during a first time period, the timing skew adjustment circuit 400 may generate a control signal (CS) based on the first output signal during a second time period, the decoding circuit 300 may perform a timing skew compensation operation on the second buffered single-level signal using the control signal (CS) during a third time period to generate a second output signal, and then output the second output signal (e.g., a clock signal) to an external circuit during a fourth time period.

[0074] The configuration of the decoding circuit 300 and the timing skew adjustment circuit 400 for performing these actions is not limited to any particular embodiment. Figure 7 Examples are described herein, however, embodiments of the present invention are not limited thereto.

[0075] Reference Figure 7 , the decoding circuit 300 includes a buffer circuit 310 and a decoder 320 .

[0076] The buffer circuit 310 receives n*(m-1) single level signals (SLS11 to SLSn(m-1)) and buffers the n*(m-1) single level signals (SLS11 to SLSn(m-1)) to output buffered single level signals (BSLS11 to BSLSn(m-1)).

[0077] The decoder 320 performs a predefined operation on the buffered single level signals (BSLS11 to BSLSn(m-1)) provided from the buffer circuit 310 to generate an output signal (OS), and outputs the generated output signal (OS). As described above, a plurality of output signals OS may be provided according to embodiments.

[0078] The timing skew adjustment circuit 400 generates a control signal (CS) for compensating for the timing skew between the n multilevel signals (MLS1 to MLSn) based on the output signal (OS) output from the decoder 320, and provides the control signal (CS) to the buffer circuit 310. As a result, the buffer circuit 310 provides the buffered single level signal (BSLS11 to BSLSn(m-1)) in which the timing skew between the n multilevel signals (MLS1 to MLSn) is compensated to the decoder 320, and the decoder 320 can also output the output signal (OS) in which the timing skew between the n multilevel signals (MLS1 to MLSn) is compensated. For example, the buffer circuit 310 may output a first buffered single-level signal based on the first unbuffered single-level signal during a first time period, the decoder 320 may output a first output signal to the timing skew adjustment circuit 400 based on the first buffered single-level signal during a second time period, the timing skew adjustment circuit 400 may generate a control signal (CS) based on the first output signal during a third time period, the buffer circuit 310 may perform a timing skew compensation operation on the second unbuffered single-level signal using the control signal (CS) during a fourth time period to output a second buffered single-level signal, and the decoder 300 may output a second output signal to an external circuit based on the second buffered single-level signal during a fifth time period.

[0079] Figure 8 is a block diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 9 yes Figure 8 An exemplary detailed block diagram of .

[0080] Hereinafter, although the semiconductor device will be described based on the assumption that three (i.e., n=3) multi-level signals (e.g., C-PHY signals) having three signal levels (i.e., m=3) are provided from an external source, the embodiments of the inventive concept are not limited thereto. Hereinafter, the differences from the above-described embodiments will be mainly described.

[0081] Reference Figure 8 and Fig. 9 , the semiconductor device 3 includes a comparison circuit 1100 (eg, a signal comparator), a delay circuit 1200 , an OR gate circuit 1300 , a CDR (Clock and Data Recovery) circuit 1400 , and a flip-flop circuit 1500 .

[0082] Here, for example, the comparison circuit 1100 corresponds to the above-mentioned converter (for example, Figure 1 100), the delay circuit 1200 corresponds to the above-mentioned buffer circuit (for example, Figure 5 210), the OR gate circuit 1300 and the trigger circuit 1500 correspond to the above-mentioned decoding circuit (for example, Figure 5220), the CDR circuit 1300 corresponds to the above-mentioned timing skew adjustment circuit (for example, Figure 5 230), but the present invention is not limited thereto.

[0083] Three multilevel signals (A, B, and C) having three signal levels are provided to the comparison circuit 1100. The comparison circuit 1100 includes nine comparators 1110 to 1190 (e.g., 1110, 1120, 1130, 1140, 1150, 1160, 1170, 1180, and 1190). Here, since when the multilevel signals (A, B, and C) are C-PHY signals, the three comparators 1130, 1160, and 1190 are required to detect a specific signal included in the multilevel signals (A, B, and C), but if the multilevel signals (A, B, and C) are not C-PHY signals, the three comparators 1130, 1160, and 1190 may be omitted.

[0084] The six comparators 1110 , 1120 , 1140 , 1150 , 1170 , and 1180 compare two reference signals ( R1 and R2 ) with three multi-level signals (A, B, and C) to output single-level signals (AH, AL, BH, BL, CH, and CL).

[0085] The delay circuit 1200 receives the single-level signals (AH, AL, BH, BL, CH, and CL) and buffers (or delays) the single-level signals (AH, AL, BH, BL, CH, and CL) to output delayed single-level signals (BAH, BAL, BBH, BBL, BCH, and BCL). To this end, the delay circuit 1200 includes a plurality of variable delay elements 1210 to 1260 (e.g., 1210, 1220, 1230, 1240, 1250, and 1260). In an embodiment where such a delay circuit 1200 is omitted, the single-level signals (AH, AL, BH, BL, CH, and CL) are directly provided to the OR gate circuit 1300.

[0086] The OR gate circuit 1300 performs an OR operation on two single-level signals among the provided single-level signals (BAH, BAL, BBH, BBL, BCH, and BCL). In one embodiment, the OR gate circuit 1300 includes: an OR gate 1310 that performs an OR operation on the single-level signals (BAH and BBL), an OR gate 1320 that performs an OR operation on the single-level signals (BBH and BCL), and an OR gate 1330 that performs an OR operation on the single-level signals (BCH and BAL).

[0087] In the present embodiment, since the required value of the output signal of the semiconductor device 3 is the difference between the multi-level signals (A, B and C), such a configuration of the OR gate circuit 1300 is provided. Specifically, the OR gate 1310 performs an OR operation on the single-level signals (BAH and BBL) to output the difference between the multi-level signal (A) and the multi-level signal (B), the OR gate 1320 performs an OR operation on the single-level signals (BBH and BCL) to output the difference between the multi-level signal (B) and the multi-level signal (C), and the OR gate 1330 performs an OR operation on the single-level signals (BCH and BAL) to output the difference between the multi-level signal (C) and the multi-level signal (A). Therefore, when the content of the necessary output signal of the semiconductor device 3 changes, the configuration of the OR gate circuit 1300 can be modified as needed.

[0088] The CDR circuit 1400 extracts the clock signal of the multi-level signal (A, B, and C) from the output of the OR gate circuit 1300 and provides the extracted clock signal to the flip-flop circuit 1500. That is, the CDR circuit 1400 controls the output timing of the flip-flop circuit 1500 based on the extracted clock signal.

[0089] The CDR circuit 1400 includes first clock extraction circuits 1405, 1410, and 1415, second clock extraction circuits 1425, 1430, and 1435, and third clock extraction circuits 1445, 1460, and 1465. The first clock extraction circuits 1405, 1410, and 1415 receive a first difference between a multi-level signal (A) and a multi-level signal (B) from an OR gate 1310, and extract a first clock signal from the first difference. The second clock extraction circuits 1425, 1430, and 1435 receive a second difference between a multi-level signal (B) and a multi-level signal (C) from an OR gate 1320, and extract a second clock signal from the second difference. The third clock extraction circuits 1445, 1460, and 1465 receive a third difference between a multi-level signal (C) and a multi-level signal (A) from an OR gate 1330, and extract a clock signal from the third difference. In one embodiment, components 1410, 1430, and 1460 are XOR gates. In one embodiment, components 1415, 1435, and 1465 are AND gates. In one embodiment, gate 1415 receives clock signal ABCKE, gate 1435 receives clock signal BCCKE, and gate 1465 receives clock signal CACKE.

[0090] The OR gate 1450 performs an OR operation on the extracted clock signals to finally calculate a single clock signal of the multi-level signals (A, B, and C). The output of the OR gate 1450 is stored in the buffer 1475 and controls the operation timing of the flip-flop circuit 1500.

[0091] The trigger circuit 1500 outputs the difference between the multi-level signal (A) and the multi-level signal (B) provided from the OR gate 1310, the difference between the multi-level signal (B) and the multi-level signal (C) provided from the OR gate 1320, and the difference between the multi-level signal (C) and the multi-level signal (A) provided from the OR gate 1330, which are synchronized with the single clock signal provided from the buffer 1475.

[0092] Specifically, the flip-flop 1510 outputs the difference between the multilevel signal (A) and the multilevel signal (B) stored in the buffer (BF1) as an output signal (RxAB) according to the single clock signal extracted by the CDR circuit 1400; the flip-flop 1520 outputs the difference between the multilevel signal (B) and the multilevel signal (C) stored in the buffer (BF2) as an output signal (RxBC) according to the single clock signal extracted by the CDR circuit 1400; the flip-flop 1530 outputs the difference between the multilevel signal (C) and the multilevel signal (A) stored in the buffer (BF3) as an output signal (RxCA) according to the single clock signal extracted by the CDR circuit 1400. As a result, the flip-flop circuit 1500 outputs the necessary signals (RxAB, RxBC, and RxCA) to the subsequent stage in a form in which the timing skew between the multilevel signals (A, B, and C) is compensated. For example, the signals RxAB, RxBC, and RxCA can be output so that there is no skew between them.

[0093] Fig.10 is a diagram for explaining an operation of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0094] Reference Fig. 9 and Fig.10 For example, when there is a timing skew (delay d) between the multilevel signal (A) and the multilevel signal (B) as shown in the figure, the multilevel signal (A) and the multilevel signal (B) are provided to the semiconductor device 3. The semiconductor device 3 receiving these multilevel signals (A and B) converts the multilevel signals (A and B) into a plurality of single-level signals, extracts a clock signal from the converted single-level signals, and outputs the output signals (RxAB, RxBC, and RxCA) of the semiconductor device 3 according to the extracted clock signal. Therefore, the output signals (RxAB, RxBC, and RxCA) are output in a form in which the timing skew (delay d) is compensated through the above process.

[0095] Fig.11 is a block diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Fig.12 It is used to illustrate Fig.11The following description will be based on the assumption that three (ie, n=3) multi-level signals (eg, C-PHY signals) having three signal levels (ie, m=3) are provided from an external source. Fig.11 The present invention is a semiconductor device, but the embodiments of the present inventive concept are not limited thereto. Hereinafter, the differences from the above-mentioned embodiments will be mainly described.

[0096] Reference Fig.11 , the semiconductor device 4 includes a comparison circuit 2100 , a buffer circuit 2200 , an OR gate circuit 2300 and a timing skew adjustment circuit 2400 .

[0097] Here, the comparison circuit 2100 may correspond to the aforementioned converter (eg, Figure 6 100), the buffer circuit 2200 may correspond to the aforementioned buffer circuit (eg, Figure 7 310), the OR gate circuit 2300 may correspond to the aforementioned decoder (eg, Figure 7 320), but not limited thereto.

[0098] Three multi-level signals (A, B, and C) having three signal levels are provided to the comparison circuit 2100. The comparison circuit 2100 includes six comparators 2110 to 2160 (e.g., 2110, 2120, 2130, 2140, 2150, and 2160). The six comparators 2110 to 2160 compare the two reference signals (R1 and R2) with the three multi-level signals (A, B, and C) to output six single-level signals (AH, AL, BH, BL, CH, and CL).

[0099] The buffer circuit 2200 includes a receiver 2210 (for example, a plurality of transceivers may be included) and a register circuit 2220. The receiver 2210 samples the provided single-level signals (AH, AL, BH, BL, CH, and CL) using a high-frequency clock (HCK) signal provided from a phase-locked loop (PLL) 2250, and stores the sampled results in the register circuit 2220. For example, the register circuit 2220 may include a plurality of registers, each of which stores a sampled single-level signal. Here, the high-frequency clock (HCK) signal may be a signal that converts a low-frequency clock (LCK) provided from an oscillator (OSC) 2260 into a high-frequency clock (HCK) signal through the phase-locked loop 2250.

[0100] The register circuit 2220 can store the sampling result provided from the receiver 2210 in units of bits. Fig.11 and Fig.12In some embodiments, the register circuit 2220 includes a deserialization register 2221 used in a receiving device for receiving a signal. The deserialization register 2221 receives a control signal (CS) from the timing skew adjustment circuit 2400 and reflects a predetermined delay (DELAY) in the bit data stored in the deserialization register 2221. In some embodiments, the method by which the deserialization register 2221 reflects the delay (DELAY) may be, for example, performing a shift on the data stored in the deserialization register 2221, but the embodiments of the inventive concept are not limited thereto.

[0101] Reference Fig.11 , the register circuit 2220 provides the single-level signals (AH, AL, BH, BL, CH, and CL) shifted by the control signal (CS) to the OR gate circuit 2300.

[0102] The OR gate circuit 2300 performs an OR operation on the provided single-level signals (BAH, BAL, BBH, BBL, BCH, and BCL) in pairs. In one embodiment, the OR gate circuit 2300 includes: an OR gate 2331 for performing an OR operation on the single-level signals (AH and BL), an OR gate 2332 for performing an OR operation on the single-level signals (BH and CL), and an OR gate 2333 for performing an OR operation on the single-level signals (CH and AL).

[0103] Similarly, in the present embodiment, since the required value of the output signal of the semiconductor device 4 is the difference between the multi-level signals (A, B, and C), such a configuration of the OR gate circuit 2300 is provided. Therefore, when the content of the necessary output signal of the semiconductor device 4 changes, the configuration of the OR gate circuit 2300 can be modified as needed.

[0104] The timing skew adjustment circuit 2400 checks whether there is a timing skew between the multi-level signals (A, B, and C) output from the OR gate circuit 2300. If there is a timing skew, the timing skew adjustment circuit 2400 generates a control signal (CS) for compensating for the timing skew and outputs the control signal (CS) to the register circuit 2220. When this compensation is completed, the timing skew adjustment circuit 2400 outputs the difference between the multi-level signals (A, B, and C) as the output signal (RxAB, RxBC, and RxCA). As a result, the signals (RxAB, RxBC, and RxCA) required in the subsequent stage are output in a form in which the timing skew between the multi-level signals (A, B, and C) is compensated.

[0105] Fig.13 and Fig.14 is a diagram for explaining an operation of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0106] Reference Fig.10 , Fig.11 and Fig.13 ,exist Fig.10 At time t2, the single-level signal (AH) converted from the multi-level signal (A) changes from 0 to 1, and the single-level signal (AL) continues to be 1. Since the multi-level signal (B) is delayed by d relative to the multi-level signal (A), the single-level signal (BH) changes from 1 to 0 at time t2+d, and the single-level signal (BL) continues to be 1.

[0107] The receiver 2210 samples such single-level signals (AH, AL, BH, and BL) using a high-frequency clock (HCK) signal and stores the sampled results in the register circuit 2220. Since there is a delay (d) in the single-level signals (AH, AL, BH, and BL), there is also a delay (d) in the bit data stored in the register circuit 2220.

[0108] Since this delay (d) also exists in the output signals (AB, BC and CA) output by the OR gate circuit 2300, the timing skew adjustment circuit 2400, for example, provides a control signal (CS) for delaying the single-level signal (AH and AL) to the register circuit 2220 to compensate for the timing skew.

[0109] Reference Fig.14 In this way, the register circuit 2220 provided with the control signal (CS) from the timing skew adjustment circuit 2400 compensates for the delay (d) between the single-level signals (AH and AL) and the single-level signals (BH and BL) by performing a shift on the single-level signals (AH and AL) that need to be delayed. For example, a two-bit right shift is performed on the single-level signals (AH and AL) so that the single-level signals (AH and AL) and the single-level signals (BH and BL) are synchronized with each other.

[0110] Fig.15 is a block diagram illustrating a semiconductor testing apparatus according to an exemplary embodiment of the inventive concept.

[0111] Reference Fig.15 , the semiconductor testing apparatus 3000 includes a receiver 3100 and a tester 3200 (eg, a tester device or a tester circuit).

[0112] The receiver 3100 receives a multi-level signal (MLS) from a test object (TO) (eg, a semiconductor circuit to be tested) and generates an output signal (OS) required in the tester 3200 .

[0113] The tester 3200 can test the test object (TO) (e.g., the semiconductor device being tested) using the output signal (OS) provided from the receiver 3100. For example, if there is a skew between the multi-level signals (MLS) and the test device 3000 performs a test on the multi-level signal, the test device 3000 may erroneously determine that the test object (TO) has failed. The output signal (OS) may include a plurality of sub-signals that are synchronized with each other (i.e., there is no skew between the sub-signals). Therefore, if the tester 3200 performs a test on the sub-signals and determines from the test that there is a fault, the test result is more likely to be accurate (e.g., it is less likely to infer that an error has occurred due to timing skew).

[0114] In some embodiments, the test object (TO) may include an image sensor (contact image sensor (CIS): complementary metal oxide semiconductor (CMOS) image sensor), but embodiments of the inventive concept are not limited thereto.

[0115] The receiver 3100 may adopt the configuration of one of the above-described embodiments (e.g., semiconductor device 1, 2, 3, or 4). That is, the receiver 3100 receives a plurality of multi-level signals (MLS), converts the plurality of multi-level signals (MLS) into a plurality of single-level signals, and then generates an output signal (OS) using the plurality of single-level signals. In addition, the receiver 3100 compensates for the timing skew between the plurality of multi-level signals (MLS) using the plurality of single-level signals, and may reflect the result on the output signal (OS).

[0116] In summary, those skilled in the art will appreciate that many variations and modifications may be made to the above-described exemplary embodiments without substantially departing from the principles of the present invention.

Claims

1. A semiconductor device, comprising: a signal generator configured to receive n multi-level signals having m signal levels and convert the n multi-level signals into n*(m-1) single-level signals having two signal levels; as well as a decoding and timing skew adjustment circuit, the decoding and timing skew adjustment circuit being configured to receive the single-level signal, perform a predefined operation on the single-level signal to generate an output signal, and use the single-level signal to compensate for the timing skew between the n multi-level signals, Where n and m are natural numbers, n>=2 and m>=3; Wherein, the decoding and timing skew adjustment circuit comprises: a decoding circuit that performs a predefined operation on the single-level signal to generate and output a first output signal and a second output signal, and a timing skew adjustment circuit, wherein the timing skew adjustment circuit controls the decoding circuit to output the first output signal and the second output signal in which the timing skew between the n multi-level signals is compensated by using the single-level signal; Wherein, the decoding circuit comprises: an OR gate circuit that performs an OR operation on the pairs of the single-level signals, and a trigger circuit that receives the output of the OR gate circuit and outputs the first output signal and the second output signal at a predetermined timing, and The timing skew adjustment circuit uses the output of the OR gate circuit to control the output timing of the trigger circuit.

2. The semiconductor device according to claim 1, wherein The signal generator receives m-1 reference signals and generates the single-level signal using the multi-level signal and the reference signals.

3. The semiconductor device according to claim 2, wherein: The signal generator includes a plurality of comparators comparing the reference signal with the multi-level signal.

4. The semiconductor device according to claim 3, wherein: The number of the comparators is n*(m-1).

5. The semiconductor device according to claim 1, wherein Each output of the OR gate circuit includes a difference between two multi-level signals among the n multi-level signals.

6. The semiconductor device according to claim 1, wherein The decoding circuit further includes a delay circuit for delaying the single-level signal, and The OR gate circuit performs an OR operation on paired outputs of the delay circuits.

7. The semiconductor device according to claim 1, wherein The timing skew adjustment circuit includes a clock and data recovery circuit, which extracts a clock signal from the output of the OR gate circuit and uses the extracted clock signal to control the output timing of the flip-flop circuit.

8. The semiconductor device according to claim 1, wherein The timing skew adjustment circuit generates a control signal for compensating for the timing skew between the n multi-level signals based on the first output signal and the second output signal, and provides the control signal to the decoding circuit.

9. The semiconductor device according to claim 8, wherein: The decoding circuit comprises: a buffer circuit, the buffer circuit buffering the single-level signal, and a decoder that performs a predefined operation on the buffered single-level signal to generate and output the first output signal and the second output signal, The timing skew adjustment circuit provides the control signal to the buffer circuit.

10. The semiconductor device according to claim 9, wherein The buffer circuit samples the single-level signal using a clock signal and stores the sampling result in a register.

11. The semiconductor device according to claim 10, wherein The buffer circuit receives the control signal and performs shifting on the data stored in the register to compensate for a timing skew between the n multi-level signals.

12. A semiconductor device comprising: a comparator circuit configured to receive a first analog signal having m signal levels and compare the first analog signal with m-1 reference signals to generate a first digital signal and a second digital signal, receive a second analog signal having m signal levels and compare the second analog signal with the m-1 reference signals to generate a third digital signal and a fourth digital signal; as well as a decoding and timing skew adjustment circuit configured to compensate for a timing skew between the first analog signal and the second analog signal using the first to fourth digital signals, Wherein, m is a natural number >= 3; Wherein, the decoding and timing skew adjustment circuit comprises: a decoding circuit configured to perform a predefined operation on the first to fourth digital signals to generate a first output signal and a second output signal, and output the first output signal and the second output signal, and a timing skew adjustment circuit configured to control the decoding circuit to output the first output signal and the second output signal in which the timing skew between the first analog signal and the second analog signal is compensated by using the first digital signal to the fourth digital signal; Wherein, the decoding circuit comprises: an OR gate circuit that performs an OR operation on pairs of digital signals from the first to the fourth digital signals, and a trigger circuit that receives the output of the OR gate circuit and outputs the first output signal and the second output signal at a predetermined timing, and The timing skew adjustment circuit uses the output of the OR gate circuit to control the output timing of the trigger circuit.

13. The semiconductor device according to claim 12, wherein: The comparator circuit includes a comparator that outputs m-1 digital signals.

14. The semiconductor device according to claim 13, wherein: The comparator compares the first analog signal with the m-1 reference signals to output m-1 digital signals.

15. The semiconductor device according to claim 12, in, The timing skew adjustment circuit generates a control signal for compensating for a timing skew between the first analog signal and the second analog signal based on the first output signal and the second output signal, and provides the control signal to the decoding circuit.

16. A semiconductor testing device, comprising: a receiver configured to receive a first multilevel signal and a second multilevel signal from a circuit, convert the first multilevel signal and the second multilevel signal into a plurality of single-level signals, and generate an output signal using the plurality of single-level signals; as well as a tester configured to test the circuit using the output signal, The first multi-level signal and the second multi-level signal both have m levels, where m is a natural number greater than or equal to 3. wherein each of the single-level signals has two levels, and wherein the receiver uses the plurality of single-level signals to compensate for a timing skew between the first multi-level signal and the second multi-level signal to generate the output signal; Wherein, the receiver comprises: a decoding circuit that performs a predefined operation on the plurality of single-level signals to generate and output a first output signal and a second output signal, and A timing skew adjustment circuit, wherein the timing skew adjustment circuit controls the decoding circuit to output the first output signal and the second output signal using the plurality of single-level signals to compensate for the timing skew between the first multi-level signal and the second multi-level signal; Wherein, the decoding circuit comprises: an OR gate circuit that performs an OR operation on the pairs of the single-level signals, and a trigger circuit that receives the output of the OR gate circuit and outputs the first output signal and the second output signal at a predetermined timing, and The timing skew adjustment circuit uses the output of the OR gate circuit to control the output timing of the trigger circuit.

17. The semiconductor testing device according to claim 16, wherein: The receiver further comprises: A comparator receives the first multi-level signal and the second multi-level signal and compares the first multi-level signal and the second multi-level signal with a reference signal to output the plurality of single-level signals.

18. A semiconductor device comprising: a signal generator configured to convert n multi-level first signals having m signal levels into n*(m-1) single-level first signals having two signal levels; as well as a decoding and timing skew adjustment circuit configured to perform a predefined operation on the single-level first signal to generate a control signal, wherein the signal generator is configured to convert n multi-level second signals having m signal levels into n*(m-1) single-level second signals having two signal levels, wherein the decoding and timing skew adjustment circuit uses the control signal to compensate for the timing skew between the n multi-level second signals, Where n and m are natural numbers, n>=2 and m>=3; Wherein, the decoding and timing skew adjustment circuit comprises: a decoding circuit that performs the predefined operation on the single-level first signal to generate and output a first output signal; and the decoding circuit that performs the predefined operation on the single-level second signal to generate and output a second output signal; and a timing skew adjustment circuit, the timing skew adjustment circuit using the first output signal to generate the control signal; and the timing skew adjustment circuit is configured to use the control signal to control the decoding circuit to output the first output signal in which the timing skews between the n multi-level first signals are compensated, and the timing skew adjustment circuit is configured to use the control signal to control the decoding circuit to output the second output signal in which the timing skews between the n multi-level second signals are compensated; Wherein, the decoding circuit comprises: an OR gate circuit that performs an OR operation on the paired single-level first signals, and that performs an OR operation on the paired single-level second signals; and a trigger circuit that receives the output of the OR gate circuit and outputs the first output signal and the second output signal at a predetermined timing, and The timing skew adjustment circuit uses the output of the OR gate circuit to control the output timing of the trigger circuit.

19. The semiconductor device according to claim 18, wherein: The signal generator receives m-1 reference signals, generates the single-level first signal using the multi-level first signal and the reference signal, and generates the single-level second signal using the multi-level second signal and the reference signal.

20. The semiconductor device according to claim 19, wherein A first reference signal among the m-1 reference signals is between a first signal level and a second signal level among the m signal levels, and a second reference signal among the m-1 reference signals is between the second signal level and a third signal level among the m signal levels.

Images