Digital Glitch Filter

Abstract

The present invention provides a digital glitch filter, comprising: a first trigger, generating a filtered output signal; a self-oscillation circuit, generating a self-oscillation signal when the filtered output signal is not equal to an input signal; a first logic gate, when the filtered output signal is not equal to the input signal, the output of the first logic gate enables the self-oscillation circuit; a ripple counter, generating a divided clock signal by dividing the self-oscillation signal; a counter and comparator, counting the divided self-oscillation signal to obtain a count value, and comparing the obtained count value with a count target; a second trigger, generating a valid signal, the valid signal is activated when the count value reaches the count target, and the filtered output signal is flipped when the valid signal is activated.

Description

Technical Field

[0001] The present invention relates to glitch filters, and more particularly, to digital glitch filters for filtering glitches in signals. Background Art

[0002] A glitch is an accidental and unintended switching of the input signal level to a high or low state followed by a return to the original state. The presence of a glitch in a digital circuit can cause the circuit to malfunction and result in spurious outputs from the circuit.

[0003] Conventional digital glitch filters require a free-running clock, which consumes power continuously during clock generation and propagation. As a result, conventional digital glitch filters have high power consumption.

[0004] Therefore, it would be advantageous to design a glitch filter with low power. Summary of the invention

[0005] This Summary provides a selection of concepts in a simplified form that are further described in the Detailed Description. This Summary is not intended to identify key features or essential features of the subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0006] According to one aspect of the present invention, there is provided a digital glitch filter for filtering glitches in an input signal, comprising: a first trigger for generating a filtered output signal; a self-oscillation circuit for generating a self-oscillation signal when the filtered output signal is not equal to the input signal; a first logic gate for enabling the self-oscillation circuit when the filtered output signal is not equal to the input signal, and disabling the self-oscillation circuit when the filtered output signal is equal to the input signal; a ripple counter connected to the self-oscillation circuit for generating a divided clock signal by dividing the self-oscillation signal; a counter and comparator connected to the ripple counter for counting the divided self-oscillation signal to obtain a count value, and comparing the obtained count value with a count target; a second trigger connected to the counter and comparator for generating a valid signal, wherein the valid signal is activated when the count value reaches the count target, and the filtered output signal flips when the valid signal is activated.

[0007] The self-oscillation circuit includes a delay unit for generating a self-oscillation clock signal.

[0008] The delay cells have configurable delay length.

[0009] The self-oscillation circuit further includes an AND gate connected between the first logic gate and the delay unit.

[0010] The self-oscillation circuit includes a feedback path in which the self-oscillation clock signal is inverted and fed back to an input terminal of the AND gate, and the output of the first logic gate is provided to the other input terminal of the AND gate.

[0011] The divided clock signal is provided to the clock input terminal of the second flip-flop, the output of the counter and comparator is provided to the data input terminal of the second flip-flop, the output of the first logic gate is provided to the reset terminal of the second flip-flop, and the self-oscillating clock signal is provided to the clock input terminal of the first flip-flop.

[0012] The digital glitch filter further includes a second logic gate connected between the second flip-flop and the first flip-flop, wherein an output of the second logic gate is provided to a data input terminal of the first flip-flop.

[0013] The filtered output signal generated by the first flip-flop and the valid signal generated by the second flip-flop are provided to the input terminal of the second logic gate.

[0014] According to another aspect of the present invention, a digital glitch filter for filtering glitches in an input signal is provided, comprising: a first trigger for generating a filtered output signal; a self-oscillating circuit for generating a self-oscillating clock signal; a first logic gate for enabling the self-oscillating circuit when the filtered output signal is not equal to the input signal, and disabling the self-oscillating circuit when the filtered output signal is equal to the input signal; a counter and comparator for counting pulses of the self-oscillating clock signal to obtain a count value and comparing the count value with a predetermined count target; a second trigger connected to the counter and comparator for generating a valid signal, wherein the valid signal is activated when the count value is equal to the count target; and a second logic gate having an output terminal connected to a data input terminal of the first trigger, a first input terminal receiving the valid signal and a second input terminal receiving the filtered output signal, so that the filtered output signal flips when the valid signal is activated. The self-oscillating clock signal is used to clock the first trigger and the second trigger. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] So that the manner in which the features of the invention described above can be understood in detail, according to the specific description of the invention of the embodiments and the above invention content, some embodiments are shown in the accompanying drawings. It will be noted, however, that the drawings only show typical embodiments of the invention and are therefore not to be considered as limiting the scope, because the invention may have other equally effective embodiments. It should be understood that the drawings are only schematic and are not drawn to scale. The advantages of the claimed subject matter will be apparent to those skilled in the art upon reading this specification and the resulting drawings, in which reference numerals are used to represent elements such as:

[0016] Figure 1A schematic diagram of a digital glitch filter according to an embodiment of the present invention is shown;

[0017] Figure 2 Shows Figure 1 Timing diagram of the circuit;

[0018] Figure 3 Shows Figure 1 Another timing diagram of the circuit;

[0019] Figure 4 A schematic diagram of a digital glitch filter according to another embodiment of the present invention is shown. DETAILED DESCRIPTION

[0020] Reference Figure 1 , Figure 1 A schematic diagram of a digital glitch filter according to an embodiment of the present invention is shown. The digital glitch filter 100 receives an input signal and generates a filtered output signal. The digital glitch filter 100 includes a first trigger 101, a first XOR gate 102, a self-oscillation circuit 103, an AND gate 104, a delay unit 105, a ripple counter 106, a counter and comparator 107, a second trigger 108 and a second XOR gate 109.

[0021] The first flip-flop 101 is configured to generate a filtered output signal. The first flip-flop 101 has a data input terminal, which is connected to the output terminal of the first XOR gate 102. The input signal and the filtered output signal are respectively provided to two input terminals of the first XOR gate 102. When the input signal is not equal to the filtered output signal, the XOR gate 102 outputs a logic 1, thereby enabling the self-oscillation circuit 103. When the input signal is equal to the filtered output signal, the XOR gate 102 outputs a logic 0, thereby disabling the self-oscillation circuit 103.

[0022] The self-oscillation circuit 103 is configured to generate a first self-oscillation signal a1. In one embodiment, the self-oscillation circuit 103 includes an AND gate 104 and a delay unit 105. The AND gate 104 is connected to the first XOR gate 102. More specifically, the output of the XOR gate 102 is provided to an input terminal of the AND gate 104. The first self-oscillation signal a1 generated by the delay unit 105 is inverted and provided to the other input terminal of the AND gate 104. The AND gate 104 outputs a second self-oscillation signal a2, and the second self-oscillation signal a2 is provided to the delay unit 105 to generate the first self-oscillation signal a1.

[0023] The ripple counter 106 is connected to the self-oscillation circuit 103, and the first self-oscillation signal a1 is provided to the ripple counter 106. In one embodiment, the ripple counter 106 is a binary counter. The ripple counter 106 is configured to convert the first self-oscillation signal a1 into a binary signal. NThe frequency is divided and then the divided clock signal (DIV_CLK) is output. The ripple counter 106 provides an efficient way to convert the first self-oscillating signal a1 into a signal with a lower frequency.

[0024] The output of the ripple counter 106 is connected to the input of the counter and comparator 107. The counter and comparator 107 counts the pulses of the divided clock signal and compares the count value with a predetermined count target, where the count target is configurable. For example, in one embodiment, the count target is 3. In other embodiments, the count target can be any number required. If the input signal changes state before the count value reaches the count target, the input signal is considered a glitch and is filtered out. In this way, the digital glitch filter achieves high efficiency and high precision.

[0025] In one counting cycle, when the count value reaches the count target from the start of counting, the input signal maintains the same state, the input signal is considered to be a valid signal and the valid signal output by the second flip-flop 108 is activated. The output terminal of the counter and comparator 107 is connected to the data input terminal of the second flip-flop 108. The divided clock signal generated by the ripple counter 106 is connected to the clock input terminal of the second flip-flop 108. The output terminal of the first XOR gate 102 is connected to the reset terminal of the second flip-flop 108. When the first XOR gate 102 becomes logic 1, the second flip-flop 108 is reset. If the state of the input signal does not change when the count value reaches the count target, the valid signal output by the second flip-flop 108 is activated. That is, the count value reaches the count target within a predetermined time configured by the counter and comparator 107, and the valid signal is activated when the input signal maintains the same state, and the input signal is considered to be a valid signal.

[0026] When the valid signal is activated, the filtered output signal flips. In one embodiment, the valid signal is activated when the valid signal is equal to logic 1, and the filtered output signal flips. In one embodiment, the valid signal output by the second flip-flop 108 is provided to one of the inputs of the second XOR gate 109. The other input of the second XOR gate 109 is connected to the output of the first flip-flop 101 and receives the filtered output signal. Then, the output of the second XOR gate 109 is provided to the data input of the first flip-flop 101. The clock input of the first flip-flop 101 is connected to the output of the delay unit 105. The first flip-flop 101 receives a POR reset (por_b) signal. In one embodiment, the POR reset signal is The clock input of the first flip-flop 101 may alternatively be connected to the output of the AND gate 104. If the valid signal is activated, the filtered output signal is flipped and equal to the input signal. In the illustrated embodiment, when the valid signal switches logic 1, the second XOR gate 109 is used to flip the filtered output signal. In other embodiments, the second XOR gate 109 may be replaced by other circuit structures so that when the valid signal is activated, the filtered output signal is flipped. The following describes in detail the use of the second XOR gate 109 to flip the filtered output signal when the valid signal switches logic 1.

[0027] If the filtered output signal was originally equal to logic 0, then when the valid signal is equal to logic 1, the XOR gate 109 outputs logic 1. Then the filtered output signal is inverted and switched to logic 1. If the filtered output signal was originally equal to logic 1, then when the valid signal is equal to logic 1, the XOR gate 109 outputs logic 0, and the filtered output signal is inverted and switched to logic 0. In this way, when the valid signal is equal to logic 1, the filtered output signal is inverted. This is a simple method of inverting the filtered output signal.

[0028] When the filtered output signal is flipped, the signal is equal to the input signal. Then the XOR gate 102 outputs a logic 0. In this way, the XOR gate 102 disables the self-oscillation circuit. At the same time, the second flip-flop 108 is reset by the output of the XOR gate 102, and the valid signal is reset to a logic 0. When the XOR gate 102 outputs a logic 0, it also resets the ripple counter 106, and the counter and comparator 107.

[0029] The delay unit 105, the ripple counter 106 and the counter and comparator 107 are all configurable so that the width of the filtered glitch can be changed from about 30 ps (10 -12 s) to several microseconds (10 -6 s) or milliseconds (10 -3 s) time period.

[0030] Reference now Figure 2 , Figure 2 The corresponding embodiment of the present invention is shown. Figure 1 The timing diagram 200 of the digital glitch filter 100 is shown. The timing diagram 200 includes an input signal (SIGNAL_IN), an enable signal (ENABLE), a first self-oscillation signal (a1), signals generated by a ripple counter (q1, q2, q3 and DIV_CLK), a counter and a comparator, a counter target, a POR (power-on reset) signal (POR_B), a valid signal (SIG_VALID) and a filtered output signal (FILTER_OUT). The function of the digital glitch filter 100 will now be explained in detail in conjunction with the timing diagram 200.

[0031] At time t1, the input signal switches to a high state. The filtered output signal generated by the first flip-flop 101 is still in a low state, so the filtered output signal is not equal to the input signal. The input signal and the filtered output signal are provided to the input terminal of the XOR gate 102, so the enable signal generated by the XOR gate 102 switches to a high state, thereby enabling the self-oscillation circuit 103. The first self-oscillation signal (a1) switches to a high state. When the first oscillation signal (a1) is provided to the ripple counter 106, the ripple counter 106 is oscillated at 2 N The first oscillation signal (a1) is divided. As a result, the frequency of q1 is half the frequency of the first oscillation signal (a1). The frequency of q2 is one quarter of the frequency of the first oscillation signal (a1), and the frequency of q3 is one eighth of the frequency of the first oscillation signal (a1).

[0032] The frequency of the divided clock signal (DIV_CLK) is 1 / 16 of the first oscillation signal (a1). The ripple counter 106 is configurable. In one embodiment, the ripple counter is a 4-bit counter. In other embodiments, depending on the design criteria, the ripple counter can be a 5-bit counter or any bit counter, so at time t1, the signal DIV_CLK switches to a high state. Then, the counter and comparator 107 counts the pulses of the divided clock signal (DIV_CLK) and compares the count value of the divided clock signal with a configurable count target. For example, in one embodiment, the count target is 3. In other embodiments, the target can be set to other values.

[0033] At time t2, the input signal switches to a low state, and the count value is 2. In this embodiment, the count target is set to 3. The input signal changes when the count value is less than the count target, so the input signal is considered to be a glitch, and the valid signal remains in a low state. Moreover, since the input signal switches to a low state, the input signal is equal to the filtered output signal. The enable signal switches to a low state, thereby disabling the self-oscillation circuit 103, the ripple counter 106, and the counter and comparator 107, so that the first self-oscillation signal a1 and the divided clock signal are both switched to a low state.

[0034] At time t3, the input signal switches to a high state. Therefore, the self-oscillating circuit 103, the ripple counter 106 and the counter and comparator 107 are enabled again.

[0035] At time t4, the counter and comparator 107 counts the divided clock signal, and since the count value reaches 3, the count value reaches the count target. It can be seen that at t4, until the count value reaches the count target, the input signal remains in a high state. So the input signal is considered to be a valid signal, so the valid signal generated by the second flip-flop 108 switches to a high state, which causes the filtered output signal to flip. Therefore, the filtered output signal switches to a high state. At the same time, the input signal is in a high state, so the filtered output signal is equal to the input signal. The enable signal is then switched to a low state to disable the self-oscillation circuit 103. The first self-oscillation signal a1 and the divided clock signal switch to a low state. The second flip-flop 108 is reset and the valid signal switches to a low state.

[0036] Reference now Figure 3 , Figure 3 is corresponding to Figure 1 Another timing diagram 300 of the digital glitch filter 100 is shown. One difference between the diagram 300 and the diagram 200 is that the values ​​of the input signals are reversed. The function of the digital filter 100 will now be explained in detail in conjunction with the timing diagram 300.

[0037] At time t1 , the input signal switches from a high state to a low state. The filtered output signal is in a high state, so the enable signal switches to a high state, enabling the self-oscillation circuit 103 .

[0038] At time t2, the input signal switches to a high state. The filtered output signal remains in a high state, so the input signal is equal to the filtered output signal. The enable signal switches to a low state, disabling the self-oscillation circuit 103.

[0039] At time t3, the input signal switches to a low state, and since the filtered output signal is in a high state, the enable signal switches to a high state. The divided clock signal switches to a high state, and the counter and comparator 107 counts the pulses of the divided clock signal and compares the count value with the count target.

[0040] At time t4, the input signal remains in a high state until the count value of the divided clock signal reaches the count target. The input signal is considered to be a valid signal. Then the valid signal generated by the second flip-flop 108 switches to a high state, so the filtered output signal flips and switches to a low state. So the filtered output signal is equal to the input signal. The enable signal switches to a low state and the self-oscillation circuit 103 is disabled. The first self-oscillation signal a1 and the divided clock signal switch to a low state, and the valid signal generated by the second flip-flop 108 switches to a low state.

[0041] As described above, the self-oscillation circuit 103 does not need to run continuously, but is only enabled when the input signal is not equal to the filtered output signal, and is disabled when the input signal is equal to the filtered output signal.

[0042] Reference now Figure 4 , Figure 4 Schematic diagram of a digital glitch filter 400 according to another embodiment of the present invention is shown. The digital glitch filter 400 includes a first trigger 401, a first XOR gate 402, a self-oscillation circuit 403, an AND gate 404, a delay unit 405, a counter and comparator 407, a second trigger 408 and a second XOR gate 409.

[0043] The first flip-flop 401 is configured to generate a filtered output signal. The output terminal of the first flip-flop 401 is connected to one input terminal of the first XOR gate 402. The input signal is provided to the other input terminal of the first XOR gate 402. When the input signal is not equal to the filtered output signal, the XOR gate 402 outputs a logic 1, enabling the self-oscillation circuit 403. When the input signal is equal to the filtered output signal, the XOR gate 402 outputs a logic 0, disabling the self-oscillation circuit 403.

[0044] The self-oscillation circuit 403 is configured to generate a first self-oscillation signal (a1). The self-oscillation circuit 403 may include an AND gate 404 and a delay unit 405. One input end of the AND gate 404 is connected to the output end of the XOR gate 402, and the other input end of the AND gate 404 receives the inverted signal of the first self-oscillation signal generated by the delay unit 105. The AND gate 404 outputs a second self-oscillation signal (a2), and inputs the second self-oscillation signal to the delay unit 405 to generate the first self-oscillation signal.

[0045] The counter and comparator 407 is connected to the self-oscillation circuit 403 and receives the first self-oscillation signal (a1) as input. The counter and comparator 407 counts the first self-oscillation signal (a1) and compares the count value with a configurable count target. If the input signal changes level state before the count value reaches the count target, the input signal is considered to be a glitch and will be filtered out.

[0046] When the count value reaches the count target, the input signal maintains the same level state, the input signal is regarded as a valid signal, and the valid signal output by the second flip-flop 408 will be activated. The output end of the counter and comparator 407 is connected to the data input end of the second flip-flop 408. In this embodiment, the divided clock signal generated by the self-oscillation circuit 403 is connected to the clock input end of the second flip-flop 408. The output end of the first XOR gate 402 is connected to the reset end of the second flip-flop 408. When the first XOR gate 402 generates a logic 1 (when the input signal is not equal to the filtered output signal), the second flip-flop 408 is reset. When the count value reaches the count target and the input signal maintains the same level state, the valid signal output by the second flip-flop 408 is activated.

[0047] The valid signal output by the second flip-flop 408 is provided to one of the input terminals of the second XOR gate 409, and the filtered output signal output by the first flip-flop 401 is provided to the other input terminal of the second XOR gate 409. The output of the second XOR gate 409 is provided to the data input terminal of the first flip-flop 401. The clock input terminal of the first flip-flop 401 is connected to the output terminal of the delay unit 405, and the reset terminal of the first flip-flop 401 receives the POR (POR_B) signal. In one embodiment, the POR_B voltage is In another embodiment, the clock input of the first flip-flop 401 can also be connected to the output of the AND gate 404. As a result, if the valid signal is equal to the filtered output signal, the filtered output signal will flip and the XOR gate 402 will output a logic 0. In this way, the first XOR gate 402 will disable the self-oscillation circuit 403.

[0048] The above describes a digital glitch filter that does not work continuously. Specifically, at least the self-oscillation circuit in the digital glitch filter does not need to work continuously, so that the digital glitch filter of the present invention does not consume power continuously, and is therefore beneficial for low-power design.

[0049] "A" and "this" and similar terms describing the subject matter herein (especially in the claims) are considered to cover both the singular and the plural, unless otherwise indicated or clearly contradicted by the context. The numerical ranges recorded here are merely a convenient way to represent discrete values ​​falling within the range, and unless otherwise indicated, each discrete value is included in the specification as if it were recorded separately. In addition, the above description is only an embodiment and is not intended to be limiting, and the scope of protection is defined by the claims. Any and all embodiments provided herein, or the use of illustrative terms (such as "for example"), are only for the purpose of better illustrating the subject matter, and unless otherwise claimed, this is not a limitation on the scope of the subject matter. The use of the term "based on" and other similar phrases recorded in the claims and the specification indicates conditions for producing a result, and is not intended to exclude any other conditions for producing the result. Any term in the specification is not considered to indicate an element that is not necessarily claimed as an implementation claimed by the present invention.

[0050] Preferred embodiments are described herein. Of course, variations of those preferred embodiments are apparent to those skilled in the art based on what is described herein. Those skilled in the art appropriately use these variations, and the inventors intend to implement the claimed claims in different ways specifically described herein. Therefore, the claimed subject matter includes all modifications of the subject matter described in the claims and their equivalents as permitted by applicable law. In addition, unless otherwise specified or explicitly contradicted herein, combinations of the elements described above in all possible variations are encompassed herein.

Claims

1. A digital glitch filter for filtering glitches in an input signal, comprising: The first trigger is used to generate the filtered output signal: A self-oscillating circuit for generating a self-oscillating clock signal when the filtered output signal is not equal to the input signal; a first logic gate connected to the self-oscillation circuit, for enabling the self-oscillation circuit when the filtered output signal is not equal to the input signal, and disabling the self-oscillation circuit when the filtered output signal is equal to the input signal, wherein the input signal and the filtered output signal are respectively provided to two input terminals of the first logic gate; a ripple counter connected to the self-oscillation circuit, for generating a divided clock signal by dividing the frequency of the self-oscillation clock signal; A counter and comparator connected to the ripple counter, for counting the divided self-oscillating clock signal to obtain a count value, and comparing the obtained count value with a count target; a second flip-flop connected to the counter and the comparator for generating a valid signal, wherein the valid signal is activated when the count value reaches a count target, and wherein the filtered output signal is flipped when the valid signal is activated; a second logic gate connected between the second flip-flop and the first flip-flop, wherein an output of the second logic gate is provided to a data input terminal of the first flip-flop; The filtered output signal generated by the first flip-flop and the valid signal generated by the second flip-flop are provided to the input terminal of the second logic gate. 2 . The digital glitch filter according to claim 1 , wherein the self-oscillation circuit comprises a delay unit for generating the self-oscillation clock signal.

3. The digital glitch filter of claim 2, wherein the delay unit has a configurable delay length. 4 . The digital glitch filter according to claim 2 , wherein the self-oscillation circuit further comprises an AND gate connected between the first logic gate and the delay unit.

5. The digital glitch filter according to claim 4, wherein the self-oscillation circuit includes a feedback path, wherein the self-oscillation clock signal is inverted and fed back to an input terminal of the AND gate, and the output of the first logic gate is provided to another input terminal of the AND gate.

6. The digital glitch filter according to claim 1, wherein: The divided clock signal is provided to the clock input terminal of the second flip-flop. The output of the counter and comparator is supplied to the data input of the second flip-flop. The output of the first logic gate is provided to the reset terminal of the second flip-flop, The self-oscillating clock signal is supplied to a clock input terminal of the first flip-flop.

7. A digital glitch filter for filtering glitches in an input signal, comprising: A first trigger, for generating a filtered output signal; A self-oscillating circuit for generating a self-oscillating clock signal; a first logic gate connected to the self-oscillation circuit, for enabling the self-oscillation circuit when the filtered output signal is not equal to the input signal, and disabling the self-oscillation circuit when the filtered output signal is equal to the input signal, wherein the input signal and the filtered output signal are respectively provided to two input terminals of the first logic gate; a counter and comparator connected to the self-oscillation circuit for counting pulses of the self-oscillation clock signal to obtain a count value and comparing the count value with a predetermined count target; a second flip-flop connected to the counter and the comparator, for generating a valid signal, wherein the valid signal is activated when the count value is equal to the count target; and The second logic gate has an output terminal connected to the data input terminal of the first flip-flop, a first input terminal receiving a valid signal and a second input terminal receiving the filtered output signal, so that the filtered output signal is flipped when the valid signal is activated.

8. The digital glitch filter of claim 7, wherein the self-oscillating clock signal is used to clock the first flip-flop and the second flip-flop.

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