Digitally eliminates noise caused by clock jitter

Abstract

Digitally eliminate noise caused by clock jitter. A system for processing signals from a gyroscope, comprising: at least one drive channel and at least one sense channel. The drive channel includes an analog-to-digital converter (ADC), an in-phase demodulator, at least one filter, and a phase-locked loop. The sense channel includes an ADC, an in-phase demodulator, an orthogonal phase demodulator, and filters for the in-phase and quadrature phase demodulators. The system includes a digital subtraction circuit that subtracts an in-phase component of a drive signal from the drive channel from an in-phase component of a rate signal from the sense channel to generate a sense axis output signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application Serial No. 62 / 691,576, filed on June 28, 2018 by Mayer et al., entitled “DIGITAL CANCELATION OF CLOCK JITTER INDUCED NOISE,” the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to gyroscopic sensors and, more particularly, to circuits for correcting errors in output signals from gyroscopic sensors. Background Art

[0004] Gyroscopes are commonly used to sense the rotation or attitude of an object along one or more rotational axes. For example, gyroscopes have long been used in naval ships, aircraft, and spacecraft to identify the rotation of the aircraft, and in stability control systems. More recently, gyroscopes have been incorporated into microelectromechanical (MEM) devices. While classic gyroscopes rotate around an axis, MEMS gyroscopes typically include a vibrating element that is formed using a photolithography process in an integrated circuit that is suitable for mounting to a printed circuit board or with other electronic components. Because the MEMS device rotates around the axis, the oscillation plane of the vibrating element tends to remain constant, and the modulated electrical signal from the MEMS sensor corresponds to the attitude of the support for the MEMS device around the axis. Some MEMS devices include: multiple vibrating gyroscope elements, which enable sensing of rotation along multiple axes in three-dimensional space.

[0005] To continue to scale gyroscopes into more demanding CE applications, a move to smaller process nodes for ASIC implementations and a shift to more digital-centric designs can be observed. An effective way to achieve the shift to more digitalization is to digitize the signal from the gyroscope at the beginning.

[0006] The output of a vibrating MEMS gyroscope has two main signal components: the desired so-called rate signal and the so-called quadrature signal. The latter is an unwanted error signal that has the same frequency but is 90° phase-shifted compared to the rate signal. This quadrature signal can be several times larger than the full-scale rate signal that needs to be measured by the system.

[0007] Since the quadrature signal has the same frequency as the rate signal, sampling the quadrature signal will cause the in-close phase noise of the oscillator to fold into the signal band, thus degrading the noise performance of the system. The larger the quadrature, the greater the noise penalty.

[0008] Due to the large quadrature signals of today's MEMS gyroscopes, direct sampling of the gyroscope output requires a clock signal with very small clock jitter to avoid noise folding of this jitter in the presence of the large quadrature signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A first embodiment of a circuit for eliminating clock jitter induced noise in a digital gyroscope is depicted.

[0010] Figure 2 A second embodiment of a circuit for eliminating clock jitter induced noise in a digital gyroscope is depicted.

[0011] Figure 3 A third embodiment of a circuit for eliminating clock jitter-induced noise in a digital gyroscope is depicted. DETAILED DESCRIPTION

[0012] For the purpose of promoting an understanding of the principles of the present disclosure, reference will now be made to the embodiments illustrated in the accompanying drawings and described in the following written specification. It is to be understood that no limitation of the scope of the invention is intended thereby. It is further understood that the present disclosure includes any changes and modifications to the illustrated embodiments, and includes further applications of the principles of the present disclosure, as would normally occur to one of ordinary skill in the art to which the present disclosure pertains.

[0013] As used herein, the term in-phase signal refers to a signal from a sensor, such as a gyroscopic sensor, that carries information from the sensor corresponding to a property measured by the sensor during operation. For example, an in-phase signal from a vibrating gyroscope is a modulated signal corresponding to the motion of a vibrating element in the gyroscopic sensor.

[0014] As used herein, the term quadrature signal refers to another signal from the sensor that has a quadrature phase (90° phase offset) with the in-phase signal. The quadrature-phase signal is also called a quadrature error signal. Ideally, the in-phase signal is completely separated from the quadrature-phase signal. However, in practical circuits, phase offset errors may make it difficult to measure only the in-phase signal.

[0015] In a highly digital gyroscope, the ADC is used to sample not only the rate signal (including quadrature), but also the displacement signal of the drive section. The displacement signal has the same frequency and phase as the quadrature signal sampled in the rate channel. Since the drive signal is sampled with the same clock, the sampled drive signal will have the same close-in phase noise folded into the signal band as the sampled quadrature in the rate signal. Therefore, we can subtract the sampled drive signal from the sampled rate signal to eliminate the noise caused by clock jitter in the rate signal. The advantage of this technique is that it relaxes the close-in phase noise requirement of the PLL because it can eliminate this noise in the digital back end, thus allowing a low-power PLL implementation.

[0016] Compared to building a very low noise oscillator with very high limits on the power and noise tradeoff, the technique presented here allows the noise caused by clock jitter to be removed later in the digital part. As a result, the noise requirements of the oscillator become less stringent and a much better power and noise tradeoff can be achieved.

[0017] Figure 1 1 is a schematic diagram of one embodiment of an open-loop gyroscope circuit 100 configured to remove clock jitter-induced noise from an output signal. Circuit 100 includes a gyroscope 102 and an integrated circuit 103, such as an application specific integrated circuit (ASIC). Gyroscope 102 includes at least one sensing element 108 for sensing along at least one axis. Gyroscope 102 may include three sensing elements 108 for sensing along three axes (e.g., x, y, z). The gyroscope also includes at least one drive axis 110.

[0018] In circuit 100, gyroscope 102 is a vibrating gyroscope, such as a MEMS gyroscope, which is used in mobile electronic devices or any other suitable vibrating gyroscope. Sensing element 108 senses rotation about three sensing axes, each sensing axis is configured to generate a signal corresponding to the movement of the vibrating element and the corresponding rotation of the gyroscope along each of the x, y and z axes, respectively. The x, y and z axes correspond to the three orthogonal rotation axes in the physical world. In another embodiment, the gyroscope includes only one axis or a different configuration of multiple sensing elements arranged on multiple axes.

[0019] exist Figure 1In the embodiment, the ASIC 103 includes a sensing channel 106, a driving channel 104, and digital processors 119, 125. The individual sensing channels 106 are electrically connected to the output of each sensing axis 108. Each sensing channel 106 includes an analog-to-digital converter (ADC) 124 and a digital processor 125 (i.e., a digital back end). The digital processors 119, 125 are embodied as a microprocessor, a microcontroller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or any other digital processing device. The digital processor 125 is configured to implement a digital in-phase demodulator 126, a digital quadrature phase demodulator 128, and filters 130, 132 for the demodulators.

[0020] The in-phase demodulator 126 generates an in-phase component (I sense The quadrature phase demodulator 128 generates a quadrature phase component (Q sense ) corresponding to the demodulated signal. The digital processor 125 applies at least one filter 130 (eg, a low pass filter) to the in-phase signal (I sense ), and applying at least one filter 132 (eg, a low pass filter) to the quadrature phase signal (Q sense ).

[0021] The drive shaft 110 receives a drive signal that generates oscillations in the vibrating member of each sensing shaft 108. The drive shaft 110 drives the sensing mass at a predetermined frequency so that each sensing shaft 108 can oscillate at the predetermined frequency. The drive channel 104 is connected to the output of the drive shaft 110. The drive channel 104 includes an ADC 112, an in-phase component (I drive ) of the digital in-phase demodulator 114, for demodulating the quadrature phase component (Q drive ) and a digital quadrature phase demodulator 116 for demodulating the in-phase component I drive At least one filter 118 for filtering, such as a low pass filter.

[0022] The drive channel 104 may also include a phase locked loop (PLL) controller 120 and an amplitude regulator 122. The output (Q drive) is received by the amplitude adjuster 122. The amplitude adjuster 122 generates a drive signal that is fed back to the drive shaft 110. The amplitude adjuster 122 controls the amplitude of the drive signal to maintain the oscillation amplitude of the gyroscope 102 at a predetermined level. The demodulators 114, 116 and the filter(s) 118 may be implemented by a digital processor.

[0023] The PLL controller 120 receives the filtered in-phase component (I drive ), and generates a clock control signal that is provided to a digitally controlled oscillator (DCO) 121. The DCO 121 outputs a clock signal to a demodulation clock signal generator 123 based on the clock control signal, and the demodulation clock signal generator 123 generates a demodulation clock signal for the I / Q demodulators 114, 116, 126, 128.

[0024] In order to eliminate the noise caused by clock jitter, the filtered in-phase component (I drive ) and the filtered in-phase component of the rate signal from filter 130 (I sense ) is provided as an input to a digital adder / subtractor 134, where the digital in-phase rate signal I sense Subtract the digital in-phase drive signal (I drive ) to remove the noise caused by clock jitter from the rate signal. Before reaching the adder / subtractor 134, the in-phase component (I drive ). The scaling factor is set by the output of the quadrature phase demodulator 128, which is provided to the multiplier 131 after being filtered by at least one filter 132 (eg, a low pass filter). The output of the digital adder / subtractor 134 is the output signal for the associated sensing axis of the gyroscope.

[0025] Figure 2 Another embodiment of an open-loop gyroscope readout circuit 100 ′ configured to eliminate clock jitter-induced noise in a digital gyroscope is depicted. Figure 2 represents a more general solution to the problem of eliminating noise caused by clock jitter. Figure 2 In FIG. 1 , the circuit 100 ′ includes a gyroscope 102 and an ASIC 103 having at least one drive channel 104 and at least one sense channel 106. Figure 2In the embodiment of the present invention, the drive channel 104 includes an ADC 112, a digital PLL controller 120, and a digital amplitude adjuster 122. At least one sense channel 106 includes an ADC 124 and a digital signal processor 140. In this embodiment, the back-end digital signal processor 140 is configured to subtract the sampled drive signal from the sampled rate signal to eliminate noise caused by clock jitter in the rate signal.

[0026] Figure 3 An embodiment similar to Figure 1 In addition to the in-phase drive signal I drive The quadrature phase demodulator 114 and the filter 118 are incorporated into the digital processing circuit for the sensing channel. In the above embodiment, the sensing and driving ADCs can be implemented by a delta-sigma modulator. In addition, in the above embodiment, the digital filter can be implemented by a decimation filter.

[0027] Although the present disclosure has been described and illustrated in detail in the drawings and foregoing description, such description and illustration should be considered illustrative rather than restrictive. It is understood that only preferred embodiments have been presented and protection is desired for all changes, modifications and further applications that fall within the spirit of the present disclosure.

Claims

1. A system for processing a signal from a gyroscope, wherein include: at least one drive channel configured to receive an output of a drive axis of the gyroscope, the at least one drive channel comprising: a drive channel analog-to-digital converter (ADC) that receives a drive signal from the drive channel and outputs a digitized drive signal; a drive channel in-phase demodulator that receives the digitized drive signal and generates an in-phase demodulated drive signal; at least one drive channel filter that receives the in-phase demodulated drive signal and outputs a filtered in-phase demodulated drive signal; and Phase-locked loop (PLL); a sensing channel configured to receive an output of a sensing axis of the gyroscope, the sensing channel comprising: a sense channel ADC that receives an analog rate signal from the sense channel and outputs a digitized rate signal; and A digital signal processor comprising: a sensing channel in-phase demodulator that receives the digitized rate signal and generates an in-phase demodulated rate signal; a sensing channel quadrature phase demodulator that receives the digitized rate signal and generates a quadrature phase demodulated rate signal; a first sensing channel filter that receives the in-phase demodulation rate signal and outputs a filtered in-phase demodulation rate signal; and a second sensing channel filter that receives the quadrature phase demodulation rate signal and outputs a filtered quadrature phase demodulation rate signal; and A digital subtraction circuit subtracts the filtered in-phase demodulated drive signal from the filtered in-phase demodulated rate signal to generate a sense axis output signal.

2. The system of claim 1, wherein the sense channel ADC and the drive channel ADC are implemented by delta-sigma modulators.

3. The system of claim 1, wherein the at least one drive channel filter, the first sense channel filter, and the second sense channel filter are implemented by decimation filters.

4. The system of claim 1, wherein the PLL comprises a PLL controller and an amplitude adjuster, and The PLL controller receives the filtered in-phase demodulated driving signal and outputs a clock control signal.

5. The system of claim 4, wherein the drive channel further include: A drive channel quadrature phase demodulator receives the digitized drive signal and generates a quadrature phase demodulated drive signal.

6. The system of claim 5, wherein the amplitude adjuster receives the quadrature phase demodulated drive signal and outputs a drive signal to the drive shaft.

7. The system of claim 1, wherein the filtered in-phase demodulated drive signal is multiplied by a scaling factor at a multiplier circuit prior to being provided to the digital subtraction circuit, the scaling factor being dependent on the quadrature-phase demodulated rate signal.

8. The system of claim 1, wherein the drive channel in-phase demodulator and the at least one drive channel filter are implemented by the PLL.

9. The system of claim 1, wherein the drive channel in-phase demodulator and the at least one drive channel filter are implemented by the digital signal processor.

10. A system for processing a signal from a gyroscope, wherein include: at least one drive channel configured to receive an output of a drive axis of the gyroscope, the at least one drive channel comprising: a drive channel analog-to-digital converter (ADC) that receives a drive signal from the drive channel and outputs a digitized drive signal; and a phase-locked loop (PLL) that receives the digitized drive signal from the drive channel ADC; and a sensing channel configured to receive an output of a sensing axis of the gyroscope, the sensing channel comprising: a sense channel ADC that receives an analog rate signal from the sense channel and outputs a digitized rate signal; and A digital signal processor is configured to receive the digitized rate signal from the sense channel ADC and the digitized drive signal from the drive channel ADC and to subtract the in-phase component of the digitized drive signal from the in-phase component of the digitized rate signal to generate a sense axis output signal.

11. The system of claim 10, wherein the PLL comprises a PLL controller and an amplitude adjuster, and The PLL controller receives the digitized driving signal from the driving channel ADC and outputs a clock control signal.

12. The system of claim 11, wherein the amplitude adjuster receives the digitized drive signal from the drive channel ADC and outputs the drive signal to the drive shaft.

Images