Circuits having standard cell architecture

Abstract

A circuit having a standard cell architecture that provides improved immunity to power supply droop, does not induce power supply droop on a continuous row power rail of the standard cells, and maintains standard cell environment compatibility. The circuit includes a first metal layer and a second metal layer formed at different distances above a substrate. At least one first standard cell drives a first timing signal and includes at least one transistor that receives power from a first power rail in the first metal layer. At least one second standard cell drives a second timing signal and includes at least one transistor that receives power from a second power rail in the second metal layer. The second power rail has a low peak noise level and a resistance that is lower than a resistance of the first metal layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority benefit of U.S. Provisional Patent Application No. 62 / 696,328, filed July 10, 2018, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The subject matter disclosed herein relates generally to techniques to reduce clock jitter in standard cell layouts resulting from instantaneous voltage drop (IVD) or dynamic voltage drop (DVD). BACKGROUND

[0004] As component sizes decrease in integrated circuits, the resistance of connections in the metal layers of the integrated circuits increases correspondingly, resulting in significant IVD / DVD for large drive strength cells. One aspect of particular concern relates to the distribution of global clocks, where large drive strength standard cells are used for efficient clock signal transmission over long distances.

[0005] If the power and ground connections of a large clock cell are the same as the metal power net of surrounding standard cell logic gates, the surrounding logic gates can experience any IVD / DVD induced in the power net by the clock driver, and vice versa. SUMMARY

[0006] Example embodiments provide a circuit having a standard cell architecture, where the circuit can include a first metal layer, a second metal layer, at least one first standard cell, and at least one second standard cell. The first metal layer can be formed a first distance above a substrate. The second metal layer can be formed a second distance above the substrate, where the second distance can be different than the first distance. The at least one first standard cell can drive a first timing signal, where the at least one first standard cell can include at least one transistor that receives power from a first power rail in the first metal layer. The at least one second standard cell can drive a second timing signal, and the at least one second standard cell can include at least one transistor that receives power from a second power rail in the second metal layer. In one embodiment, the second power rail in the second metal layer can include a noise level of less than about 20 millivolts peak. In another embodiment, the first metal layer can include a first resistance and the second metal layer can include a second resistance that is less than the first resistance. In one embodiment, the second distance can be greater than the first distance.

[0007] Another example embodiment provides a circuit having a standard cell architecture, where the circuit can include a first metal layer, a second metal layer, at least one first clock driver, and at least one second clock driver. The first metal layer can be formed a first distance above a substrate, and the second metal layer can be formed a second distance above the substrate, where the second distance can be different than the first distance.

[0008] The at least one first clock driver can be formed from a first standard cell that drives a first timing signal, and where the at least one first clock driver can include at least one transistor that receives power from a first power rail in the first metal layer.

[0009] The at least one second clock driver can be formed from a second standard cell that drives a second timing signal, and where the at least one second clock driver can include at least one transistor that receives power from a second power rail in the second metal layer. In one embodiment, the second power rail in the second metal layer can include a noise level of less than about 20 millivolts peak. In another embodiment, the first metal layer can include a first resistance and the second metal layer can include a second resistance that is less than the first resistance.

[0010] In one embodiment, the second distance can be greater than the first distance.

[0011] Still another example embodiment provides a circuit having a standard cell architecture, where the circuit can include a first metal layer, a second metal layer, at least one first standard cell, and at least one second standard cell. The first metal layer can be formed a first distance above a substrate, and where the first metal layer can include a first resistance. The second metal layer can be formed a second distance above the substrate, where the second distance can be different than the first distance, where the second metal layer can include a second resistance that is less than the first resistance, and where the second metal layer can include a noise level of less than 50 millivolts peak.

[0012] The at least one first standard cell can drive a first timing signal, and where the at least one first standard cell can include at least one transistor that receives power from a first power rail in the first metal layer. The at least one second standard cell can drive a second timing signal, and where the at least one second standard cell can include at least one transistor that receives power from a second power rail in the second metal layer.

[0013] In one embodiment, the second metal layer can further include a noise level of less than about 20 millivolts peak. In one embodiment, the second distance can be greater than the first distance. BRIEF DESCRIPTION OF DRAWINGS

[0014] In the following detailed description, aspects of the subject matter disclosed herein will be described with reference to the examples illustrated in the drawings, wherein:

[0015] Figure 1 An example circuit whose timing can be improved by the subject matter disclosed herein is depicted.

[0016] Figure 2A A cross-sectional view of a typical power connection to a clock driver of a standard cell layer is depicted.

[0017] Figure 2B A cross-sectional view of a power connection to a clock driver of a standard cell layer according to the subject matter disclosed herein is depicted.

[0018] Figure 3A A plan view of a typical standard cell layout comprising clock drivers connected to a common power network is depicted.

[0019] Figure 3B A plan view of a standard cell layout comprising clock drivers connected to isolated and dedicated power rails and according to the subject matter disclosed herein is depicted.

[0020] BRIEF DESCRIPTION OF THE DRAWINGS

[0021] 100: circuit;

[0022] 101: transmitting flip-flop;

[0023] 102: capturing flip-flop;

[0024] 103: logic circuit;

[0025] 104: clock driver / CK L driver;

[0026] 105: clock driver / CK C driver;

[0027] 200, 250: standard cell layer;

[0028] 201, 251: substrate;

[0029] 202a-202d, 252a-252d: inter-insulation layer;

[0030] 203a-203d, 253a-253d: metal layer;

[0031] 204, 260: power connection;

[0032] 205, 255: via;

[0033] 261: via stack;

[0034] 265, 351, 352: power rail;

[0035] 270: power metal layer;

[0036] 300, 350: standard cell layout;

[0037] 301, 302: source / drain regions;

[0038] CK, CK C, CK L: clock signal;

[0039] T ck : period of clock;

[0040] t ck_uncertainty : time uncertainty;

[0041] t ckq : delay time;

[0042] t pd : propagation delay;

[0043] t setup : setup time. DETAILED DESCRIPTION

[0044] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. However, it will be understood by those skilled in the art that the disclosed aspects can be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the subject matter disclosed herein.

[0045] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" or "according to an embodiment" (or other phrases of similar meaning) in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In this regard, the term "exemplary" as used herein means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Additionally, depending on the context, singular terms can include their plural forms and plural terms can include their singular forms. It is also noted that the various figures (including the components of the figures) illustrated and discussed herein are not drawn to scale. Similarly, the various waveforms and timing charts illustrated are for illustrative purposes only. For example, the size of some elements can be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals can be repeated among the figures to indicate like elements. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly literal or restricted way unless expressly so defined herein.

[0046] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting of the claimed subject matter. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the terms "first," "second," and the like, do not imply any type of order, quantity, or importance, but are used to distinguish one element from another, unless otherwise indicated by the context. Also, in two or more figures, the same drawing reference numbers will be used for components that have the same or similar functionality in the individual figures. However, these usages are merely for convenience and ease of discussion; they do not imply that the construction or architecture of such components or units are identical in all embodiments, or that a particular embodiment is the only way to implement the teachings of particular embodiments disclosed herein.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0048] The subject matter disclosed herein provides a technique to reduce clock uncertainty. In one embodiment, a standard cell architecture is provided that has improved immunity to power supply droop, does not induce power supply droop on the continuous row power rail of the standard cell, and maintains standard cell environment compatibility. In one embodiment, an isolated and dedicated power rail is provided in a standard cell layout that is connected to a low noise, low resistance power plane via a via stack. The low noise, low resistance power plane can be positioned higher above the substrate than the continuous row power rail.

[0049] One embodiment provides a dedicated power and ground connection for a clock driver of a standard cell layout that can be isolated from the surrounding power grid, where the power node of the clock driver can be connected to a low resistance metal layer that has a lower noise level than the surrounding power grid connected to the continuous row power rail. In one embodiment, the low resistance metal layer can be positioned at a relatively higher layer from the substrate and can be connected to the power node of the clock driver via a via stack.

[0050] Figure 1An example circuit 100 that timing can be improved by the subject matter disclosed herein is depicted. The example circuit 100 includes a launch flop 101, a capture flop 102, and combinational logic circuit 103 between the launch flop 101 and the capture flop 102. A clock signal CK is input to a first clock driver 104 and a second clock driver 105. The first clock driver 104 outputs a CK L clock signal that is input to the launch flop 101. The second clock driver 105 outputs a CK C clock signal that is input to the capture flop 102.

[0051] It is generally desirable to implement higher clock frequencies in mobile applications. However, if the launch flop 101 has a relatively short clock-to-Q delay (t ckq ), the capture flop 102 has a reduced setup delay (t setup ), and the delay (t pd ) of the combinational logic circuit 103 is fixed, then it would be necessary to reduce the uncertainty associated with the CK L clock signal and the CK C clock signal to provide an improved (i.e., higher) clock frequency. The uncertainty associated with a clock signal (also commonly referred to as clock jitter) can result in an offset or uncertain arrival time of the clock (compared to the ideal causal point of the clock). Clock uncertainty and the resulting offset can result from many non-ideal factors such as, but not limited to, local random transistor variations, wiring variations, coupling or other noise, electromagnetic interference (EMI), and / or IVD / DVD conditions.

[0052] If the example circuit 100 in Figure 1 is an ideal circuit, then the CK C clock signal path and the CK L clock signal path would have the same clock driver, the same signal path wiring, and ideal connections to power, such that the CK C clock signal and the CK L clock signal would arrive at their destinations at the same time and have no clock jitter.

[0053] If, for example, the CK L clock signal arrives later at the launch flop 101 due to a local supply voltage drop (i.e., IVD / DVD) on the power supply of the CK L clock driver 104 (which the CK C clock driver 105 does not experience), then the frequency of the circuit 100 would be reduced due to the difference in the arrival times of the corresponding clock signals CK L and CK C at the flops 101 and 102.

[0054] The period T ck of the clock should be

[0055] T ck ≥ t ckq + tpd + t setup - t ck_uncertainty (1)

[0056] where t ckq is the clock-to-Q delay time of the launch flip-flop 101, t pd is the propagation delay through the combinational logic circuit 103, t setup is the setup time of the capture flip-flop 102, and t ck_uncertainty is the uncertainty caused by the IVD / DVD condition. Although t ck_uncertainty may be caused by other non-ideal factors, as previously described, the focus of the presently disclosed subject matter involves reducing the clock jitter caused by the IVD / DVD condition, and thus t ck_uncertainty refers to the time uncertainty caused by the IVD / DVD condition, as used herein.

[0057] In the worst case scenario, if the CK_L clock signal arrives at the launch flip-flop 101 earlier due to a local voltage rise on the CK_L driver 104, and if the CK_C clock signal arrives at the capture flip-flop 102 later due to a voltage drop (i.e., IVD / DVD) on the CK_C driver 105, then it is possible for the launch data to arrive in the fixed timing window of the capture flip-flop 102, which can result in a capture hold violation that causes a wafer failure.

[0058] Figure 2A A cross-sectional view depicting a typical power connection to a clock driver of a standard cell layer 200. The standard cell layer 200 can include a substrate 201, a plurality of interlevel dielectric layers 202a-d, and a plurality of metal layers 203a-d, which can be formed in the interlevel dielectric layers 202a-d, respectively. A power connection 204 to a power net in the metal layer 203a can be formed between clock drivers (not shown) in the substrate 201 via a via 205. Typically, the power connection 204 is a connection to a continuous power rail of the standard cell. The power net 204 can typically be between 70-130 mV peak noise, which can significantly affect t ck_uncertainty .

[0059] Figure 2BA cross-sectional view of power connections to a clock driver of a standard cell layer 250 according to the subject matter disclosed herein is depicted. The standard cell layer 250 can include a substrate 251, a plurality of inter-insulating layers 252a-d, and a plurality of metal layers 253a-d, which can be formed in the inter-insulating layers 252a-d, respectively. Power connections 260 to a dedicated and isolated power rail 265 can be formed between a clock driver (not shown) and a metal layer 253a in the substrate 251 via a via 255. The power connections 260 can also include a via stack 261 between the power rail 265 and a power metal layer 270. The power metal layer 270 can have a resistance that is less than the resistance of the metal layer 253a, which can be substantially equal to the resistance of the metal layer 253a. In one embodiment, the power metal layer 270 can have a peak noise level that is less than about 50 millivolts. In another embodiment, the power metal layer 270 can have a peak noise level that is less than about 20 millivolts. Although Figure 2B The power metal layer 270 depicted in FIG. 3 is depicted as being positioned four metal layers above the substrate 251, it should be understood that the power metal layer 270 can be positioned any distance above the substrate 251. Additionally, it should be understood that the power metal layer 270 can be positioned at any distance above the substrate 251. Figure 2B There can be components in the standard cell 250 of FIG. 2 that can include connections to a power grid, such as the power grid 204 of FIG. 1. That is, there can be components in the standard cell 250 of FIG. 2 that can benefit from low clock jitter. Figure 2A There can be components in the standard cell 250 of FIG. 2 that can include connections to a power grid, such as the power grid 204 of FIG. 1. That is, there can be components in the standard cell 250 of FIG. 2 that can benefit from low clock jitter. Figure 2A There can be components in the standard cell 250 of FIG. 2 that can include connections to a power grid, such as the power grid 204 of FIG. 1. That is, there can be components in the standard cell 250 of FIG. 2 that can benefit from low clock jitter. Figure 2B There can be components in the standard cell 250 of FIG. 2 that can include connections to a power grid, such as the power grid 204 of FIG. 1. That is, there can be components in the standard cell 250 of FIG. 2 that can benefit from low clock jitter.

[0060] Figure 3A A plan view of a typical standard cell layout 300 including a clock driver connected to a common power grid is depicted. The power grid includes a continuous VDD rail positioned at the top of the standard cell 300 and a continuous VSS rail positioned at the bottom of the standard cell 300. Figure 3A The source / drain regions of the clock driver include power connections to the common power grid, which are indicated at 301 and 302 in FIG. 3. Figure 3A Figure 3A

[0061] Figure 3B A plan view of a standard cell layout 350 including a clock driver connected to isolated and dedicated power rails 351 and 352 and according to the subject matter disclosed herein is depicted. The metal layers of the dedicated and isolated power rails 351 and 352 can have a resistance that is less than the resistance of the common power rail layer (i.e., the VDD and VSS rails of FIG. 3). The clock driver of the standard cell 350 can include power connections 360 to the dedicated and isolated power rails 351 and 352. The power connections 360 can also include a via stack 361 between the power rails 351 and 352 and a power metal layer 370. The power metal layer 370 can have a resistance that is less than the resistance of the metal layers of the dedicated and isolated power rails 351 and 352, which can be substantially equal to the resistance of the metal layers of the dedicated and isolated power rails 351 and 352. In one embodiment, the power metal layer 370 can have a peak noise level that is less than about 50 millivolts. In another embodiment, the power metal layer 370 can have a peak noise level that is less than about 20 millivolts. Although Figure 3A ​​The resistance of the dedicated and isolated power supply rail 351 and the power supply rail 352 layers (second resistance) is less than the resistance of the power grid layer (first resistance). In one embodiment, the dedicated and isolated power supply rail 351 and the power supply rail 352 layers can have a peak noise level of less than about 50 millivolts. In another embodiment, the dedicated and isolated power supply rail 351 and the power supply rail 352 layers can have a peak noise level of less than about 20 millivolts.

[0062] As those skilled in the art will appreciate, the novel concepts described herein can be modified and varied widely by applying the principles of the present teachings. Accordingly, the scope of the subject matter claimed should not be limited to any one of the particular exemplary teachings discussed above, but should be defined by the following claims.

Claims

1. A circuit having a standard cell architecture, the circuit comprising: a first metal layer formed a first distance above a substrate; a second metal layer formed a second distance above the substrate, the second distance being different than the first distance; at least one first standard cell driving a first timing signal, the at least one first standard cell including at least one transistor receiving power from a first power rail in the first metal layer; at least one second standard cell driving a second timing signal, and the at least one second standard cell including at least one transistor receiving power from a second power rail in the second metal layer; and a third power rail located a distance equal to the first distance above the substrate, the third power rail electrically connected to the second power rail via at least one via, and the at least one second standard cell connected to the second power rail via the third power rail, wherein the at least one transistor of the at least one second standard cell is connected to the second power rail by a via formed between the substrate and the first metal layer and a power connection formed between the first metal layer and the second metal layer, and wherein the power connection is a continuous power rail and a connection of stacked vias between the first metal layer and the second metal layer.

2. The circuit of claim 1, wherein the second power rail in the second metal layer includes a noise level of less than about 20 millivolts peak.

3. The circuit of claim 2, wherein the first metal layer includes a first resistance and the second metal layer includes a second resistance, the second resistance being less than the first resistance.

4. The circuit of claim 1, wherein the second distance is greater than the first distance.

5. The circuit of claim 4, wherein the first metal layer includes a first resistance and the second metal layer includes a second resistance, the second resistance being less than the first resistance.

6. The circuit of claim 5, wherein the second power rail in the second metal layer includes a noise level of less than about 20 millivolts peak.

7. The circuit of claim 6, wherein the at least one first standard cell includes a first clock driver and the at least one second standard cell includes a second clock driver.

8. A circuit having a standard cell architecture, the circuit comprising: a first metal layer formed a first distance above a substrate; a second metal layer formed a second distance above the substrate, the second distance being different than the first distance; at least one first clock driver formed from a first standard cell driving a first timing signal, the at least one first clock driver including at least one transistor receiving power from a first power rail in the first metal layer; at least one second clock driver formed from a second standard cell driving a second timing signal, and the at least one second clock driver including at least one transistor receiving power from a second power rail in the second metal layer; and a third power rail located a distance equal to the first distance above the substrate, the third power rail electrically connected to the second power rail via at least one via, and the at least one second standard cell connected to the second power rail via the third power rail, wherein the at least one transistor of the at least one second standard cell is connected to the second power rail by a via formed between the substrate and the first metal layer and a power connection formed between the first metal layer and the second metal layer, and wherein the power connection is a continuous power rail and a connection of stacked vias between the first metal layer and the second metal layer. a third power rail located a distance equal to the first distance above the substrate, the third power rail electrically connected to the second power rail via at least one via, and the at least one second clock driver connected to the second power rail via the third power rail, wherein at least one transistor of the second standard cell is connected to the second power rail by a via formed between the substrate and the first metal layer and a power connection formed between the first metal layer and the second metal layer, and wherein the power connection is a connection of a continuous power rail and stacked vias between the first metal layer and the second metal layer.

9. The circuit of claim 8, wherein the second power rail in the second metal layer comprises a noise level of less than about 20 millivolts peak.

10. The circuit of claim 9, wherein the first metal layer comprises a first resistance and the second metal layer comprises a second resistance, the second resistance being less than the first resistance.

11. The circuit of claim 8, wherein the second distance is greater than the first distance.

12. The circuit of claim 11, wherein the first metal layer comprises a first resistance and the second metal layer comprises a second resistance, the second resistance being less than the first resistance.

13. The circuit of claim 12, wherein the second power rail in the second metal layer comprises a noise level of less than about 20 millivolts peak.

14. A circuit having a standard cell architecture, the circuit comprising: a first metal layer formed a first distance above a substrate, the first metal layer comprising a first resistance; a second metal layer formed a second distance above the substrate, the second distance being different than the first distance, the second metal layer comprising a second resistance less than the first resistance and the second metal layer comprising a noise level of less than 50 millivolts peak; at least one first standard cell, the at least one first standard cell driving a first timing signal, the at least one first standard cell comprising at least one transistor receiving power from a first power rail in the first metal layer; at least one second standard cell, the at least one second standard cell driving a second timing signal, and the at least one second standard cell comprising at least one transistor receiving power from a second power rail in the second metal layer; and a third power rail located a distance equal to the first distance above the substrate, the third power rail electrically connected to the second power rail via at least one via, and the at least one second standard cell connected to the second power rail via the third power rail, wherein at least one transistor of the at least one second standard cell is connected to the second power rail by a via formed between the substrate and the first metal layer and a power connection formed between the first metal layer and the second metal layer, and wherein the power connection is a connection of a continuous power rail and stacked vias between the first metal layer and the second metal layer.

15. The circuit of claim 14, wherein the second metal layer further comprises a noise level of less than about 20 millivolts peak.

16. The circuit of claim 14, wherein the second distance is greater than the first distance.

17. The circuit of claim 16, wherein the at least one first standard cell comprises a first clock driver and the at least one second standard cell comprises a second clock driver.

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