Silicon carbide device and method for manufacturing the same

Abstract

The present invention provides a silicon carbide device and a method for manufacturing the same. An exemplary method includes patterning a first hard mold to form a patterned first hard mold, and using the patterned first hard mold to form a body region having a second conductivity type opposite to the first conductivity type. Patterning a second hard mold to form a patterned second hard mold, and using the patterned first hard mold and the patterned second hard mold to simultaneously form a contact region and a sink region having a second conductivity type. The present invention also discloses other exemplary methods and silicon carbide devices. The device and method according to the present invention simplify the process steps, achieve channel self-alignment, reduce the cell spacing of the device, and improve the performance and application of silicon carbide devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a silicon carbide device and a method for manufacturing the same. Background Art

[0002] Silicon carbide (SiC) is a broadband semiconductor material with a wide bandgap between 2.35eV and 3.28eV. SiC-based semiconductors are thermally, chemically, and mechanically stable and are suitable for applications requiring high power, high speed, and high temperature.

[0003] In the conventional method of manufacturing a silicon carbide device, such as a silicon carbide metal oxide semiconductor field effect transistor (MOSFET), a p-type body region is usually formed by ion implantation using a mask, and then a p-type body region is formed by a second mask. + The sinker region is then formed through a third mask. + Source region. The existing method is complex and requires multiple masks, and the parameters of each mask must be precisely designed. Therefore, the performance of the final device is easily negatively affected by the design itself and the drift of process parameters during the actual manufacturing process. Moreover, since precise alignment cannot be achieved, the asymmetry of the channels on both sides of the gate region often leads to an imbalance in the MOSFET current, which seriously affects the performance of the device. Moreover, the current cell pitch of a general silicon carbide metal oxide semiconductor field effect transistor (MOSFET) is between 7 microns (μm) and 12μm. Due to the above reasons, it is difficult to improve the performance of silicon carbide devices by reducing the cell pitch. Summary of the invention

[0004] In view of one or more of the above-mentioned shortcomings of the prior art, the present invention provides a silicon carbide device and a method for manufacturing the same.

[0005] According to one aspect of the present invention, a method for manufacturing a silicon carbide device is provided, wherein a substrate of the silicon carbide device has a first conductivity type, the method comprising patterning a first hard mask to form a patterned first hard mask, forming a body region having a second conductivity type opposite to the first conductivity type using the patterned first hard mask, and patterning a second hard mask to form a patterned second hard mask, and simultaneously forming a contact region and a sink region having the second conductivity type using the patterned first hard mask and the patterned second hard mask.

[0006] According to another aspect of the present invention, a method for manufacturing a silicon carbide device is provided. The method includes: providing a substrate having a first conductivity type; providing a first epitaxial layer of the first conductivity type on the substrate, the doping concentration of the first epitaxial layer being lower than the doping concentration of the substrate; providing a second epitaxial layer of the first conductivity type on the first epitaxial layer, the doping concentration of the second epitaxial layer being lower than the doping concentration of the first epitaxial layer. Depositing a first oxide layer as a first hard mask on the second epitaxial layer; patterning the first hard mask to form a patterned first hard mask; using the patterned first hard mask as a mask to perform a first ion implantation to form a body region having a second conductivity type opposite to the first conductivity type, the body region extending from the surface of the epitaxial layer toward the substrate; depositing a second oxide layer as a second hard mask on the surface of the patterned first hard mask and the body region; patterning the second hard mask to form a patterned second hard mask; and using the patterned first hard mask and the patterned second hard mask as masks to perform a second ion implantation to form a contact region and a sink region having a second conductivity type, the doping concentrations of the contact region and the sink region are both higher than the doping concentration of the body region.

[0007] According to another aspect of the present invention, a method for manufacturing a silicon carbide device is provided. The method comprises: providing a silicon carbide substrate of n-type conductivity; depositing a first silicon carbide epitaxial layer of n-type conductivity on the silicon carbide substrate, wherein the doping concentration of the first silicon carbide epitaxial layer is lower than the doping concentration of the silicon carbide substrate; depositing a second silicon carbide epitaxial layer of n-type conductivity on the first silicon carbide epitaxial layer, wherein the doping concentration of the second silicon carbide epitaxial layer is lower than the doping concentration of the first silicon carbide epitaxial layer; depositing plasma-enhanced tetraethyl orthosilicate (PETEOS) with a thickness ranging from 3 μm to 6 μm on the second silicon carbide epitaxial layer as a first hard mask; patterning the first hard mask to form a patterned first hard mask; and performing aluminum ionization using the patterned first hard mask. The invention relates to a method for manufacturing a silicon carbide device comprising: injecting aluminum ions into a conductive layer to form a body region of p-type conductivity; depositing a conformal dielectric film with a thickness ranging from 0.6 μm to 1.2 μm on the patterned first hard mask and on the surface of the body region as a second hard mask; patterning the second hard mask to form a patterned second hard mask; using the patterned first hard mask and the patterned second hard mask as masks to perform aluminum ion implantation to form a contact region and a sink region of p-type conductivity, wherein the doping concentrations of the contact region and the sink region are both higher than the doping concentration of the body region; and performing nitrogen ion implantation to form a source region of n-type conductivity through the patterned first hard mask and the patterned second hard mask as masks, so that the channel of the silicon carbide device is self-aligned.

[0008] According to another aspect of the present invention, a silicon carbide device is provided. The silicon carbide device comprises: an n-type silicon carbide substrate; a first silicon carbide epitaxial layer of n-type conductivity disposed on the silicon carbide substrate; a second silicon carbide epitaxial layer of n-type conductivity disposed on the first silicon carbide epitaxial layer; a body region of p-type conductivity disposed in the second silicon carbide epitaxial layer and extending from the surface of the second silicon carbide epitaxial layer toward the silicon carbide substrate; a contact region of p-type conductivity disposed in the body region and extending from the surface of the body region toward the silicon carbide substrate; a sink region of p-type conductivity, the sink region and the contact region are simultaneously formed by ion implantation using the same mask, and the doping concentrations of the sink region and the contact region are both higher than the doping concentration of the body region; a source region of n-type conductivity, the source region is disposed in the body region and extends from the surface of the body region toward the silicon carbide substrate, and in the body region, the contact region contacts and is sandwiched between two adjacent source regions.

[0009] The silicon carbide device and the manufacturing method thereof according to the embodiment of the present invention simplify the process steps, realize self-alignment, and improve the performance and application of the silicon carbide device. According to the embodiment of the present invention, a two-step hard mold process is developed to realize ion implantation through the same mask to form the contact area and the sink area at the same time. And by adjusting one or both of the energy of the ion implantation and the thickness of the hard mold, the junction depth, relative position, etc. of the contact area and the sink area can be adjusted very flexibly. In addition, according to the embodiment of the present invention, self-alignment of the channel region is realized, thereby avoiding performance defects such as device current asymmetry caused by gate misalignment, allowing a smaller cell spacing, thereby improving the performance of the silicon carbide device. The silicon carbide device according to the embodiment of the present invention also improves the switching speed of the device and is suitable for high-speed applications.

[0010] More embodiments and beneficial technical effects of the present invention will be described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The embodiments of the present invention will be described below by way of example with reference to the accompanying drawings:

[0012] Figure 1 shows a cross-sectional view of a silicon carbide device according to some embodiments of the present invention;

[0013] Figure 2A A method of forming a body region according to some embodiments of the present invention is shown;

[0014] Figure 2B shows a doping profile of a body region formed by five chain ion implantations according to some embodiments of the present invention;

[0015] Figure 3 A method of forming a second hard mask according to some embodiments of the present invention is shown;

[0016] Figure 4 A method of patterning a second hard mask according to some embodiments of the present invention is shown;

[0017] Figure 5A A method of forming contact regions and sink regions according to some embodiments of the present invention is shown;

[0018] Figure 5B shows doping profiles of a contact region, a body region, and a second epitaxial layer according to some embodiments of the present invention;

[0019] Figure 5C shows doping profiles of a body region, a sink region, and a second epitaxial layer according to some embodiments of the present invention;

[0020] Fig. 6A Methods for forming contact regions and sink regions according to other embodiments of the present invention are shown;

[0021] Figure 6B shows doping profiles of a contact region, a body region, and a second epitaxial layer according to some other embodiments of the present invention;

[0022] Figure 6C shows doping profiles of a body region, a sink region, and a second epitaxial layer according to some other embodiments of the present invention;

[0023] Figure 7 A method of forming a source region according to some embodiments of the present invention is shown;

[0024] Figure 8 A method of forming a gate region according to some embodiments of the present invention is shown;

[0025] Fig. 9 A method of forming an interlayer dielectric according to some embodiments of the present invention is shown;

[0026] Fig.10 A method of forming a metal contact according to some embodiments of the present invention is shown;

[0027] Fig.11 Methods of forming a top metal layer and a back metal layer according to some embodiments of the present invention are shown. DETAILED DESCRIPTION

[0028] The following will describe more fully with reference to the accompanying drawings a number of embodiments of the present invention. It will be appreciated by those skilled in the art that embodiments of the present invention will be described herein with reference to a number of cross-sectional views and other schematic diagrams as exemplary illustrations of idealized embodiments of the present invention. Thus, for example, variations in the illustrated shapes caused by manufacturing techniques and / or tolerances can be expected. Thus, embodiments of the present invention should not be interpreted as being limited to the specific shapes of the regions shown herein, but rather include shape deviations, such as those produced by manufacturing. For example, an implanted region shown as a rectangle generally has slightly rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from implanted to non-implanted regions. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the region shown in the figure is actually schematic, and its shape is not intended to represent the precise shape of the region of the device, and is not intended to limit the scope of the present invention. For various layers and regions, embodiments of the present invention are described with reference to specific polarity conductivity types. However, as will be appreciated by those skilled in the art, the polarity of the layers and regions may be reversed to provide devices of opposite polarity.

[0029] Figure 1 A cross-sectional view of a silicon carbide device according to some embodiments of the present invention is shown. For illustrative purposes only, in this particular embodiment, the silicon carbide device is a MOSFET. It should be understood by those skilled in the art that the inventive concept can be applied to other types of silicon carbide devices. It should also be understood by those skilled in the art that in actual manufacturing, a plurality of silicon carbide MOSFETs may be included on the produced chip, which are typically repeated in unit cells. Figure 1 Only some core elements of three SiC MOSFET cells are illustrated.

[0030] Figure 1 The silicon carbide device shown includes a silicon carbide substrate 100 of a first conductivity type, such as a 4-H silicon carbide substrate of n-type conductivity (also simply referred to as "n-type"). A first silicon carbide epitaxial layer 101 of a first conductivity type, such as an n-type thin buffer epitaxial layer, is provided on a first surface of the substrate 100. A second silicon carbide epitaxial layer 110 of a first conductivity type, such as an n-type top epitaxial layer, is formed on the first epitaxial layer 101. The doping concentrations of the substrate 100, the first epitaxial layer 101, and the second epitaxial layer 110 are sequentially reduced.

[0031] like Figure 1 As shown, the second epitaxial layer 110 includes a body region 111 of the second conductivity type, for example, a body region of p-type conductivity (also simply referred to as "p-type"). The body region 111 extends from the surface of the second epitaxial layer 110 toward the substrate 100. The body region 111 can serve as a well region.

[0032] like Figure 1As shown, the silicon carbide device also includes a contact region 112 and a sinker region 113 of the second conductivity type. As will be described in detail below, the contact region 112 and the sinker region 113 according to an embodiment of the present invention can be formed simultaneously by ion implantation using the same mask. In this particular embodiment, the conductivity types of the contact region 112 and the sinker region 113 are both p-type, and the doping concentrations are both higher than the doping concentration of the body region 111. The contact region 112 is disposed in the body region 111 and extends from the surface of the body region 111 toward the substrate 100. The sinker region 113 is buried in the second epitaxial layer 110 and overlaps with the edge of the body region 111, and the sinker region 113 is not connected to the contact region 112. The "edge" described here refers to the junction depth of the body region 111, that is, the position where the body region 111 forms a pn junction with the second epitaxial layer 110. In other embodiments, the sink region 113 is buried or disposed in the body region 111 and does not overlap with the edge of the body region 111, but is connected to the contact region 112. As one of many advantages, the sink region 113 can reduce the body resistance of the silicon carbide device and improve device performance such as switching speed, thus facilitating high-speed device applications.

[0033] like Figure 1 As shown, the silicon carbide device further includes a source region 114 of a first conductivity type, such as an n-type source region. The source region 114 is disposed in the body region 111 and extends downward from the surface of the body region 111. In the same body region 111, a contact region 112 contacts and is sandwiched between two adjacent source regions 114.

[0034] like Figure 1 The silicon carbide device shown also includes a gate oxide layer 120, a doped polysilicon layer 121, and an interlayer dielectric 122. The gate oxide layer 120 covers the surface of the second epitaxial layer 110, and the doped polysilicon layer 121 is disposed on the gate oxide layer 120 and is patterned so as to form a gate of the silicon carbide device with the gate oxide layer 120. The interlayer dielectric 122 covers the doped polysilicon layer 121 and contacts the gate oxide layer 120, and is used to isolate the gate of the silicon carbide device from the source metal. In addition, the silicide metal layer 125, the barrier metal layer 130, and the top metal layer 131 form a source contact. The back metal layer 140 is disposed on the second surface of the substrate 100 to form a drain contact.

[0035] Figure 1Three silicon carbide MOSFET devices are illustrated. According to some embodiments of the present invention, the spacing between adjacent devices can be in the range of 5μm to 7μm. The lateral width of the body region 111 is in the range of 4.3μm to 4.9μm. The lateral distance between adjacent body regions 111 in the second epitaxial layer 110 is in the range of 1.1μm to 1.7μm. The lateral widths of the sink region 113 and the source region 114 are both in the range of 1.3μm to 1.5μm. The lateral distance between two adjacent sink regions 113 in the body region 111 is in the range of 0.9μm to 1.1μm. The lateral distance between two adjacent source regions 114 in the body region 111 is in the range of 0.9μm to 1.1μm. The lateral width of the doped polysilicon layer 121 is in the range of 2.9μm to 3.5μm. The lateral distance between two adjacent doped polysilicon layers 121 is in the range of 2.5μm to 3.1μm.

[0036] In this particular embodiment, the spacing between adjacent devices is 6 μm. The lateral width of the body region 111 is 4.6 μm. The lateral distance between adjacent body regions 111 in the second epitaxial layer 110 is 1.4 μm. The lateral widths of the sink region 113 and the source region 114 are both 1.4 μm. The lateral distance between two adjacent sink regions 113 in the body region 111 is 1.0 μm. The lateral distance between two adjacent source regions 114 in the body region 111 is 1.0 μm. The lateral width of the doped polysilicon layer 121 is 3.2 μm. The lateral distance between two adjacent doped polysilicon layers 121 is 2.8 μm. The "lateral" described here refers to a direction that is parallel to the direction of the doped polysilicon layer 121. Figure 1 The direction is parallel to the paper plane and perpendicular to the direction from the second epitaxial layer 110 toward the substrate 100 .

[0037] The following combination Figure 2A-11 Methods for manufacturing silicon carbide devices according to some embodiments of the present invention are described. Figure 2A As shown, a substrate 100 is provided. In this particular embodiment, the substrate 100 is an n-type 4-H silicon carbide substrate with a thickness of about 350 micrometers (μm) and a resistivity in the range of 0.02Ω·cm to 0.03Ω·cm. An n-type silicon carbide first epitaxial layer 101 is deposited on the substrate 100 as a buffer epitaxial layer. The thickness of the first epitaxial layer 101 is about 0.5μm, and the doping concentration is 1E18cm -3 (i.e., 1×10 18 cm -3 ) to 2E18cm -3 A second n-type silicon carbide epitaxial layer 110 is deposited on the first epitaxial layer 101 as a top epitaxial layer. The second epitaxial layer 110 has a thickness in the range of 5 μm to 30 μm and a doping concentration in the range of 1E15 cm -3 To 2E16cm -3These thickness and doping concentration values ​​are only exemplary, and the thickness and doping concentration of the first epitaxial layer 101 and the second epitaxial layer 110 can be adjusted accordingly according to the rated voltage requirements of the silicon carbide device.

[0038] A first hard mask is provided on the second epitaxial layer 110. The first hard mask may be formed of a suitable oxide, such as a silane (SiH4)-based oxide or a tetraethyl orthosilicate (TEOS)-based oxide. The oxide as the first hard mask may be formed by a suitable process, including but not limited to low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), etc. In this particular embodiment, the first hard mask is formed by depositing plasma enhanced tetraethyl orthosilicate (PETEOS) as the first oxide layer. The thickness of the PETEOS layer ranges from 3 μm to 6 μm.

[0039] like Figure 2A As shown, the first hard mask is patterned to form a patterned first hard mask 150. In this particular embodiment, the PETEOS layer as the first hard mask is photolithographically and dry-etched to expose the surface of the second epitaxial layer 110 corresponding to the body region 111 as a window for ion implantation (i.e., first ion implantation). Thus, a body region 111 having a conductivity type opposite to that of the second epitaxial layer 110 is formed using the patterned first hard mask 150 as a mask. This can be achieved, for example, by performing an ion implantation 450 of aluminum at a temperature in the range of 400° C. to 600° C. The junction depth of the formed body region 111 is in the range of about 0.9 μm to 1.5 μm.

[0040] In some embodiments, the aluminum ion implantation 450 includes a series of implantation steps, such as 3 to 6 ion implantations, and the energy of each ion implantation can be different, such as in the range of 50keV to 950keV, and the ion implantation dose can be in the range of 1E12cm -2 To 1E13cm -2 Through such chained multiple ion implantations, the desired doping profile or distribution can be obtained.

[0041] Figure 2B The doping concentration profile or distribution of the body region 111 formed by chain ion implantation is illustrated. Figure 2BAs shown, the chain ion implantation of aluminum includes five ion implantations, and the doping concentration profiles formed each time are 111A, 111B, 111C, 111D, and 111E. Among them, 111E corresponds to an ion implantation with the largest ion implantation energy and thus the deepest implantation depth. The dopant implanted this time forms a pn junction with the second epitaxial layer 110 of the opposite conductivity type, which corresponds to the junction depth of the body region 111. The final doping concentration profile in the body region 111 is the superposition of the doping concentration profiles obtained by the five ion implantations. Depending on the parameters, along the direction toward the second epitaxial layer 110, as the position changes, the doping concentration profile can be linear or nonlinear. In some embodiments, in order to obtain a retrograde concentration distribution, the implantation dose used for the ion implantation with the shallowest implantation depth is the lowest, and the implantation dose used for the ion implantation with the deepest implantation depth is the highest.

[0042] like Figure 3 As shown, a second hard mask 151 is provided. The second hard mask 151 covers the patterned first hard mask 150 and the surface of the body region 111. The second hard mask 151 may be a conformal dielectric film so that the second hard mask 151 is formed at various locations (e.g., Figure 3 As shown in the figure, the sidewalls and corners of the patterned first hard mask 150 are all kept at approximately the same thickness. The conformal dielectric film can be an oxide film or an oxide layer. For example, the conformal dielectric film can include a SiH4-based oxide or a TEOS-based oxide. The conformal dielectric film can be formed by a suitable process, and the suitable process includes but is not limited to LPCVD, PECVD, HDPCVD, etc. In this particular embodiment, oxide is deposited as a second oxide layer by an LPCVD process to form a second hard mask 151. The thickness of the deposited second oxide layer is in the range of 0.6μm to 1.2μm. The second oxide layer remains conformal so that the second oxide layer is as shown in the figure. Figure 3 The sidewalls and corners of the patterned first hard mask 150 are shown to have substantially the same thickness. The second oxide layer may include, for example, a TEOS-based oxide such as PETEOS, a SiH4-based oxide, or the like.

[0043] Figure 4 The second hard mask 151 is patterned to form a patterned second hard mask 151A. The patterned second hard mask 151A includes a portion 152 that is not in contact with the patterned first hard mask 150 and a portion 153 that is in contact with a sidewall of the patterned first hard mask 150.

[0044] The second hard mask 151 may be patterned by a suitable process. In this particular embodiment, a layer of photoresist is provided on the second hard mask 151. The photolithography process leaves only a portion of the photoresist 160, which corresponds to the portion where the contact region 112 is to be formed later. The second hard mask not covered by the photoresist 160 is then etched (e.g., reactive ion etching) to expose the window 155. In this process, the ratio of chemical etching to ion bombardment can be adjusted by a process recipe of reactive ion etching, so that the thickness of the portion 153 of the sidewall second hard mask can be adjusted when removing the second oxide layer corresponding to the window 155. Adjusting the thickness of the portion 153 of the sidewall second hard mask can adjust the channel length of the silicon carbide device.

[0045] like Figure 5A As shown, the contact region 112 and the sink region 113 are formed using the patterned first mask 150 and the patterned second hard mask 151A as masks. In this particular embodiment, the contact region 112 and the sink region 113 are formed simultaneously using the aluminum ion implantation 460 (i.e., the second ion implantation). The thickness (or height) of the portion 152 of the second mask along the direction toward the substrate 100 is in the range of 0.9 μm to 1.2 μm. The aluminum ion implantation energy is in the range of 700 eV to 1000 eV, and the ion implantation dose is 1E14 cm -2 To 8E14cm -2 The ion implantation parameters of aluminum are designed so that aluminum ions can penetrate the portion 152 to form the contact region 112 on the surface of the body region 111. At the same time, aluminum ions are implanted through the window 155 to form the sink region 113. That is, one ion implantation process can simultaneously form the contact region 112 and the sink region 113. At the same time, the patterned first mask 150 and the portion 153 of the second mask prevent aluminum ions from being implanted into the second epitaxial layer 110.

[0046] By adjusting one or both of the aluminum ion implantation energy and the thickness of the second hard mask portion 152, the profiles of the contact region 112 and the sink region 113, such as the junction depth and the relative position, such as the distance, of the contact region 112 and the sink region 113 can be adjusted. Figure 5A As shown, the contact region 112 is near the upper surface of the body region 111, and the sink region 113 is near the lower surface of the body region 111. The contact region 112 is not connected to the sink region 113.

[0047] In some embodiments, p + The contact region 112, the p-type body region 111, and the n - The doping profile of the first epitaxial layer 110 is as follows Figure 5B As shown. p-type body region 111, p + Area 113, and n -The doping profile of the first epitaxial layer 110 is as follows Figure 5C shown.

[0048] In some embodiments, the junction depth of the contact region 112 is 0.2 μm to 0.5 μm, and the junction depth of the sink region 113 along the direction toward the substrate 100 ranges from 1 μm to 1.6 μm.

[0049] In actual device manufacturing, due to scattering effects during ion implantation, the width of the sink region 113 in the direction parallel to the substrate 100 may be slightly greater than the lateral width of the window 155. This also falls within the scope of the embodiments of the present invention.

[0050] Fig. 6A Another embodiment of forming the contact region 112 and the sink region 113 is shown. In this particular embodiment, the ion implantation energy of aluminum is in the range of 400 eV to 600 eV, and the ion implantation dose is 1E14 cm -2 To 8E14cm -2 The thickness of the portion 152 of the second mask along the direction toward the substrate 100 is in the range of 0.6 μm to 0.9 μm. The parameters of the aluminum ion implantation are designed so that the aluminum ions can penetrate the portion 152 and form the contact region 112 on the surface of the body region 111. At the same time, the aluminum ions are implanted through the window 155 to form the sink region 113. Figure 5A Different from the ones shown, Fig. 6A The contact region 112 is shown to be directly connected to the sink region 113 .

[0051] In some embodiments, p + The contact region 112, the p-type body region 111, and the n - The doping profile of the second epitaxial layer 110 is as follows: Figure 6B As shown, the p-type body region 111, p + Area 113, and n - The doping profile of the second epitaxial layer 110 is as follows: Figure 6C shown.

[0052] In some embodiments, the junction depth of the contact region 112 is 0.4 μm to 0.6 μm, and the junction depth of the sink region 113 along the direction toward the substrate 100 ranges from 0.8 μm to 1.4 μm.

[0053] Figure 7 The steps of forming the source region according to the embodiment of the present invention are illustrated. Figure 7 As shown, the patterned first mask 150 and the patterned second mask 151A are used as masks to perform ion implantation, such as nitrogen ion implantation, to form a source region 114 of the first conductivity type, such as n + In this particular embodiment, the source region 114 extends from the surface of the body region 111 toward the substrate 100 and has a doping concentration of 2E19 cm-3 To 1E20cm -3 Since the lateral distance between the source region 114 and the body region 111 depends on the thickness of the portion 153 of the second hard mask, the method according to the embodiment of the present invention can achieve channel self-alignment, thereby avoiding gate misalignment during device manufacturing, thereby greatly improving device performance, such as current symmetry.

[0054] In addition, according to the embodiment of the present invention, only two hard molds are needed as masks to form the body region, contact region, sink region, and source region. And the parameters of the contact region and sink region, such as junction depth and relative position, can be adjusted by adjusting the parameters such as the thickness of the hard mold and the energy of ion implantation. The process is very simple and flexible. At the same time, the device performance degradation caused by the process parameter drift in the actual manufacturing process is also reduced.

[0055] See also Figure 8 By way of example, the patterned first hard mask 150 and the patterned second hard mask 151A are removed by a wet oxide clean process. An oxide layer 120 is grown on the second epitaxial layer 110. This can be achieved by one or more thermal oxidation or deposition steps. In one embodiment, the oxide layer 120 is generated by thermal oxidation to a thickness range of 20nm to 80nm, followed by a post-oxidation annealing using nitrous oxide (N2O) or nitric oxide (NO) to passivate or eliminate defects between the silicon carbide and oxide interface.

[0056] By way of example, an in-situ doped polysilicon layer is deposited on the oxide layer 120 by chemical vapor deposition. The thickness of the polysilicon layer is in the range of 300nm to 700nm. The polysilicon layer is patterned by photolithography and reactive ion etching processes, and the patterned polysilicon layer 121 defines the gate region of the silicon carbide device.

[0057] See also Fig. 9 By way of example, an interlayer dielectric 122 having a thickness ranging from 1.2 μm to 2.0 μm is formed by depositing PETEOS. The interlayer dielectric 122 covers the exposed portion of the patterned polysilicon layer 121 and the oxide layer 120. The interlayer dielectric 122 is subjected to a densification process, for example, the densification process may be a thermal degradation process at a temperature ranging from 800° C. to 900° C. Then, a photoresist layer 170 is provided on the interlayer dielectric 122. The photoresist layer 170 is processed by a photolithography process to form a window 172.

[0058] like Fig.10As shown, the interlayer dielectric 122 and the oxide layer 120 exposed through the window 172 are removed by reactive ion etching. Then, a contact metal is deposited through the window 172, for example, titanium or nickel is deposited on the surface of the second epitaxial layer 110 and in contact with the contact region 112. In one embodiment, nickel with a thickness ranging from 50nm to 300nm is deposited as the contact metal by a sputtering process. Subsequently, the contact metal is rapidly thermally annealed at a temperature ranging from 500°C to 900°C to form a nickel silicide metal layer 125. The nickel that has not formed nickel silicide is removed by chemical etching.

[0059] Reference Fig.11 , in such Fig.10 Titanium / titanium nitride (Ti / TiN) is deposited on the surface as a barrier metal layer 130. Aluminum with a thickness ranging from 2 μm to 5 μm is then formed thereon as a top metal layer 131. A back metal layer 140 is formed on one side of the substrate 100 opposite to the top metal layer 131. The back metal layer 140 can be used as a metal lead-out portion of a drain.

[0060] Figure 8-11 The corresponding steps are described with specific embodiments. It will be appreciated by those skilled in the art that these specific embodiments are merely illustrative and not intended to limit the present invention. For example, although the interlayer dielectric 122 is described as being made of PETEOS, it will be appreciated by those skilled in the art that the interlayer dielectric 122 may be other suitable oxides that can perform similar functions.

[0061] Unless otherwise limited, exemplary implementations of the present invention are illustrated in the non-limiting embodiments. Based on the above disclosed embodiments, various modifications and improvements that can be thought of by those skilled in the art all fall within the scope of the embodiments of the present invention.

Claims

1. A method for manufacturing a silicon carbide device, wherein a substrate of the silicon carbide device has a first conductivity type, the method comprising: patterning the first hard mask to form a patterned first hard mask, and using the patterned first hard mask to form a body region having a second conductivity type opposite to the first conductivity type; as well as Patterning the second hard mask to form a patterned second hard mask, the patterned second hard mask comprising a first portion contacting a sidewall of the patterned first hard mask and a second portion corresponding to a contact area to be formed later, a window being formed between the first portion and the second portion; Simultaneously forming a contact region and a sink region having a second conductivity type using the patterned first hard mask and the patterned second hard mask; Among them, the ion implantation parameters are designed so that ions can penetrate the second part, forming the contact area on the surface of the body region, and at the same time forming the sink area through the window; the doping concentrations of the contact area and the sink area are both higher than the doping concentration of the body region; the contact area contacts and is sandwiched between two adjacent source regions, and the sink area is arranged in the body region or overlaps with the edge of the body region.

2. The method according to claim 1, further comprising: Forming the first hard mask by depositing plasma enhanced tetraethyl orthosilicate (PETEOS); as well as The second hard mask is formed by depositing a conformal dielectric film on the patterned first hard mask and on the surface of the body region.

3. The method according to claim 1, further comprising: The relative position of the contact region and the sink region, and the junction depth and doping concentration of one or both of the contact region and the sink region are adjusted by adjusting one or both of ion implantation energy and the thickness of the second hard mask.

4. The method according to any one of claims 1 to 3, further comprising: Ion implantation is performed using the patterned first hard mask and the patterned second hard mask to form a source region with a first conductivity type. 5 . The method according to claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.

6. A method for manufacturing a silicon carbide device, comprising: providing a substrate having a first conductivity type; Providing a first epitaxial layer of a first conductivity type on the substrate, wherein the doping concentration of the first epitaxial layer is lower than the doping concentration of the substrate; Providing a second epitaxial layer of the first conductivity type on the first epitaxial layer, wherein the doping concentration of the second epitaxial layer is lower than the doping concentration of the first epitaxial layer; depositing a first oxide layer on the second epitaxial layer as a first hard mask; patterning the first hardmask to form a patterned first hardmask; Performing a first ion implantation using the patterned first hard mask as a mask to form a body region having a second conductivity type opposite to the first conductivity type, wherein the body region extends from the surface of the epitaxial layer toward the substrate; depositing a second oxide layer as a second hard mask on the surface of the patterned first hard mask and the body region; patterning the second hardmask to form a patterned second hardmask; The patterned second hard mask comprises a first portion contacting a sidewall of the patterned first hard mask and a second portion corresponding to a contact area to be formed later, wherein a window is formed between the first portion and the second portion; Performing a second ion implantation using the patterned first hard mask and the patterned second hard mask as masks to form a contact region and a sink region having a second conductivity type, wherein the ion implantation parameters are designed so that ions can penetrate the second portion to form the contact region on the surface of the body region, and at the same time, form the sink region through the window; The doping concentrations of the contact region and the sink region are both higher than the doping concentration of the body region; the contact region contacts and is sandwiched between two adjacent source regions, and the sink region is arranged in the body region or overlaps with the edge of the body region.

7. The method according to claim 6, further comprising: The contact region is disconnected from the sink region by adjusting one or both of the implantation energy of the second ion implantation and the thickness of the second hard mask.

8. The method according to claim 6, further comprising: The contact region is connected to the sink region by adjusting one or both of the implantation energy of the second ion implantation and the thickness of the second hard mask.

9. The method according to any one of claims 6 to 8, wherein depositing a first oxide layer as a first hard mask comprises: Plasma enhanced tetraethyl orthosilicate (PETEOS) is deposited on the second epitaxial layer as the first oxide layer, and the thickness of the first oxide layer is in a range of 3 μm to 6 μm.

10. The method of claim 9, wherein forming the body region comprises: The first ion implantation is performed at a temperature ranging from 400° C. to 600° C., so that a junction depth of the formed body region is in a range from 0.9 μm to 1.5 μm.

11. The method according to claim 10, wherein the first ion implantation is aluminum ion implantation, and the number of ion implantations is 3 to 6, the ion implantation energy is in the range of 50 eV to 950 eV, and the ion implantation dose is 1E12 cm -2 To 1E13cm -2 scope.

12. The method according to any one of claims 6 to 8, wherein depositing a second oxide layer as a second hard mask comprises: A conformal dielectric film is deposited on the patterned first hard mask and on the surface of the body region as the second oxide layer, and the thickness of the second oxide layer is in a range of 0.6 μm to 1.2 μm.

13. The method according to claim 12, patterning the second hard mask comprises: The channel length of the silicon carbide device is adjusted by adjusting the thickness of a portion of the sidewall second hard mask, wherein the portion of the sidewall second hard mask is a portion of the second hard mask that contacts the sidewall of the patterned first hard mask.

14. The method according to claim 12, wherein the second ion implantation comprises: Ion implantation is performed by aluminum ions, the ion implantation temperature is in the range of 400°C to 600°C, the ion implantation energy is in the range of 700eV to 1000eV, and the ion implantation dose is 1E14cm -2 To 8E14cm -2 scope.

15. The method according to any one of claims 6 to 8, further comprising: Using the patterned first hard mask and the patterned second hard mask as masks, nitrogen ion implantation is performed to form a source region of the first conductivity type, wherein the doping concentration of the source region is 2E19cm -3 To 1E20cm -3 scope.

16. A method for manufacturing a silicon carbide device, comprising: Providing a silicon carbide substrate having an n-type conductivity; Depositing a first silicon carbide epitaxial layer of n-type conductivity on the silicon carbide substrate, wherein the doping concentration of the first silicon carbide epitaxial layer is lower than the doping concentration of the silicon carbide substrate; Depositing a second silicon carbide epitaxial layer of n-type conductivity on the first silicon carbide epitaxial layer, wherein the doping concentration of the second silicon carbide epitaxial layer is lower than the doping concentration of the first silicon carbide epitaxial layer; Depositing plasma enhanced tetraethyl orthosilicate (PETEOS) with a thickness ranging from 3 μm to 6 μm on the second silicon carbide epitaxial layer as a first hard mask; patterning the first hardmask to form a patterned first hardmask; Using the patterned first hard mask to perform aluminum ion implantation to form a body region with a p-type conductivity; depositing a conformal dielectric film having a thickness ranging from 0.6 μm to 1.2 μm as a second hard mask on the patterned first hard mask and on the surface of the body region; patterning the second hardmask to form a patterned second hardmask; The patterned second hard mask comprises a first portion contacting a sidewall of the patterned first hard mask and a second portion corresponding to a contact area to be formed later, wherein a window is formed between the first portion and the second portion; Using the patterned first hard mask and the patterned second hard mask as masks, aluminum ion implantation is performed to form a contact region and a sink region of p-type conductivity, wherein the ion implantation parameters are designed so that ions can penetrate the second portion to form the contact region on the surface of the body region, and at the same time, form the sink region through the window; the doping concentrations of the contact region and the sink region are both higher than the doping concentration of the body region; and Using the patterned first hard mask and the patterned second hard mask as masks, nitrogen ion implantation is performed to form a source region of n-type conductivity, so that the channel of the silicon carbide device is self-aligned; The contact region contacts and is sandwiched between two adjacent source regions, and the sink region is arranged in the body region or overlaps with an edge of the body region.

17. The method of claim 16, wherein the conformal dielectric film comprises one of a SiH4-based oxide and a TEOS-based oxide.

18. A silicon carbide device, manufactured by the method of claim 16, comprising: A silicon carbide substrate having an n-type conductivity; A first epitaxial layer of silicon carbide with an n-type conductivity type disposed on the silicon carbide substrate; A second silicon carbide epitaxial layer of n-type conductivity disposed on the first silicon carbide epitaxial layer; A body region of p-type conductivity, disposed in the second silicon carbide epitaxial layer and extending from a surface of the second silicon carbide epitaxial layer toward the silicon carbide substrate; a contact region of p-type conductivity, the contact region being arranged in the body region and extending from a surface of the body region toward the silicon carbide substrate; A sink region of p-type conductivity, wherein the sink region is buried in the second silicon carbide epitaxial layer, and the doping concentrations of the sink region and the contact region are both higher than the doping concentration of the body region; A source region of n-type conductivity is disposed in the body region and extends from a surface of the body region toward the silicon carbide substrate. In the body region, the contact region contacts and is sandwiched between two adjacent source regions.

19. The silicon carbide device according to claim 18, wherein: The spacing between adjacent SiC devices is in the range of 5μm to 7μm.

20. The silicon carbide device according to claim 18 or 19, wherein a junction depth of the body region is in the range of 0.9 μm to 1.5 μm, a junction depth of the contact region is in the range of 0.2 μm to 0.5 μm, and a range of the sink region along a direction toward the silicon carbide substrate is 1 μm to 1.6 μm.

21. The silicon carbide device according to claim 18 or 19, wherein a junction depth of the body region is in a range of 0.9 μm to 1.5 μm, a junction depth of the contact region is in a range of 0.4 μm to 0.6 μm, and a range of the sink region along a direction toward the silicon carbide substrate is 0.8 μm to 1.4 μm.

22. A silicon carbide device according to claim 18 or 19, wherein the lateral width of the body region is in the range of 4.3 μm to 4.9 μm, the lateral distance between adjacent body regions in the second epitaxial layer is in the range of 1.1 μm to 1.7 μm, the lateral width of the sink region and the lateral width of the source region are both in the range of 1.3 μm to 1.5 μm, and the lateral distance between two adjacent sink regions in the body region and the lateral distance between two adjacent source regions in the body region are both in the range of 0.9 μm to 1.1 μm.

23. The silicon carbide device according to claim 18, wherein: The sink region is connected to the contact region.

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