Switching regulator, power supply circuit, and method of operating a switching regulator

Abstract

Provided are a switching regulator configured to generate an output voltage based on an input voltage, a power supply circuit configured to generate a power supply voltage based on the input voltage, and a method for operating the switching regulator. The switching regulator includes: an inductor; and a capacitor circuit configured to generate an output voltage by charging an inductor current passing through the inductor from the input voltage, provide a first capacitor as a load capacitor based on the output voltage being a first level or a second level, and provide a second capacitor smaller than the first capacitor as a load capacitor based on the output voltage being between the first level and the second level.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0085380 filed on July 23, 2018, in the Korean Intellectual Property Office, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Methods and apparatus consistent with example embodiments relate to power supply voltage generation, and more particularly, to a switching regulator that dynamically changes an output voltage and a power supply circuit including the switching regulator. Background Art

[0004] A power supply voltage may be generated to provide power to an electronic component. The power supply voltage may be required to have reduced noise and a level required to operate the electronic component. In addition, the level of the power supply voltage provided to the electronic component may be changed to reduce the power consumption of the electronic component. For example, in the case of a digital circuit that processes a digital signal, a low-level power supply voltage may be provided when relatively low performance is required, and a high-level power supply voltage may be provided when relatively high performance is required. Therefore, a circuit that generates a power supply voltage may be required to generate a power supply voltage that can quickly change levels and has reduced noise. Summary of the invention

[0005] Example embodiments provide a switching regulator that can generate a power supply voltage that can be quickly changed to a desired level and has reduced noise, and a power supply circuit including the switching regulator.

[0006] According to an aspect of an example embodiment, a switching regulator is provided, the switching regulator being configured to generate an output voltage based on an input voltage, and comprising: an inductor; and a capacitor circuit, the capacitor circuit being configured to generate the output voltage by being charged with an inductor current passing through the inductor from the input voltage, providing a first capacitance as a load capacitance based on the output voltage being a first level or a second level, and providing a second capacitance smaller than the first capacitance as the load capacitance based on the output voltage being between the first level and the second level.

[0007] According to an aspect of another example embodiment, a switching regulator is provided, which is configured to generate an output voltage based on an input voltage and includes: an inductor; and a capacitor circuit, which is configured to provide a load capacitance, generate the output voltage by charging an inductor current passing through the inductor from the input voltage, and quickly change the load capacitance from a first capacitance to a second capacitance smaller than the first capacitance and gradually change the load capacitance from the second capacitance to the first capacitance based on a control signal.

[0008] According to an aspect of another example embodiment, a power supply circuit is provided, which is configured to generate a power supply voltage based on an input voltage and includes: a first voltage regulator, which is configured to generate a first output voltage based on the input voltage and a reference voltage; a switch, which is configured to change a load capacitance between a ground voltage and the first output voltage based on a control signal; and a power controller, which is configured to: generate the reference voltage, thereby controlling the first voltage regulator to change the first output voltage according to a load condition; and generate the control signal to control the switch, thereby maintaining the load capacitance at a first capacitance based on the first output voltage being constant, and maintaining the load capacitance at a second capacitance smaller than the first capacitance based on the first output voltage being variable.

[0009] According to an aspect of an example embodiment, a method of operating a switching regulator is provided, the switching regulator being configured to generate an output voltage based on an input voltage. The method includes: maintaining a first capacitor as a load capacitor based on the output voltage being a first level; maintaining the load capacitor as a second capacitor smaller than the first capacitor based on the output voltage changing from the first level to a second level; and maintaining the load capacitor as the first capacitor based on the output voltage being the second level.

[0010] According to an aspect of an example embodiment, a switching regulator is provided, the switching regulator being configured to provide an output voltage based on an input voltage, the switching regulator comprising: a capacitor circuit configured to provide a first capacitance based on a control signal indicating a constant output voltage, and to provide a second capacitance based on a control signal indicating a varying output voltage; and a controller configured to generate the control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram illustrating a switching regulator according to an example embodiment;

[0013] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 A graph of an example of operation of a switching regulator with respect to time;

[0014] Figure 3A , 3B and 3C illustrate an example of a switching regulator according to an example embodiment;

[0015] Figure 4 is a diagram showing a method according to an example embodiment Figure 1 A circuit diagram of an example of a capacitor circuit;

[0016] Figure 5 is a diagram showing a method according to an example embodiment Figure 1 A graph of an example of time-lapse operation of a switching regulator;

[0017] Fig. 6A , 6B and 6C illustrate examples of variable capacitors according to example embodiments;

[0018] Figure 7 is a block diagram illustrating a power supply circuit according to an example embodiment;

[0019] Figure 8 is a diagram showing a method according to an example embodiment Figure 7 A circuit diagram of an example of a power supply circuit;

[0020] Fig. 9 is a diagram showing a method according to an example embodiment Figure 8 A graph of an example of operation of a power supply circuit based on a time lapse;

[0021] Fig.10 is a circuit diagram showing an example of a power supply circuit according to an example embodiment;

[0022] Fig.11 is a flow chart illustrating a method of operating a switching regulator according to an example embodiment;

[0023] Fig.12 is a flow chart illustrating a method of operating a switching regulator according to an example embodiment;

[0024] Fig.13 is a diagram illustrating a system according to an example embodiment; and

[0025] Fig.14 is a block diagram illustrating a wireless communication device according to an example embodiment. DETAILED DESCRIPTION

[0026] Figure 1 is a block diagram showing a switching regulator 10 according to an example embodiment. The switching regulator 10 may be based on a reference voltage V REF and input voltage V IN Generates output voltage V OUT , and the output voltage V OUT Can be used as a supply voltage for other electronic components. Figure 1As shown, the switching regulator 10 may include an inductor L, a switching circuit 11, a switch controller 12, and a capacitor circuit 13. In some example embodiments, the components included in the switching regulator 10 may be included in a semiconductor package. In some example embodiments, the switching regulator 10 may include a printed circuit board on which the components are mounted.

[0027] The switching regulator 10 can generate an output voltage V OUT For example, the switch circuit 11 of the switching regulator 10 can turn on / off the switch based on the switch control signal C_SW provided from the switch controller 12, bypassing the inductor L to switch the inductor current I L In this specification, on may refer to a state in which both ends of a switch are electrically connected, and off may refer to a state in which both ends of a switch are electrically disconnected. Figure 3A , Figure 3B and Figure 3C As described above, a DC-DC converter as an example of a switching regulator 10 can be configured to receive an input voltage V IN Generates output voltage V OUT , input voltage V IN is a DC voltage, and the output voltage V OUT is a DC voltage. Hereinafter, the example embodiments will be described mainly with reference to a DC-DC converter as the switching regulator 10. However, it should be understood that the example embodiments may be applied to other types of switching regulators 10, such as those having an input voltage V IN It is an AC-DC converter for alternating current (AC) voltage.

[0028] The switch circuit 11 may receive a switch control signal C_SW from the switch controller 12 and may include at least one switch that is turned on and off based on the switch control signal C_SW. The switch circuit 11 may control the input voltage V IN The inductor current I flowing through the inductor L L For example, the switch circuit 11 can respond to the switch control signal C_SW to change the inductor current I L The capacitor circuit 13 is provided to charge the capacitor included in the capacitor circuit 13, and at the same time it can block the inductor current I in response to the switch control signal C_SW. L is supplied to the capacitor circuit 13 to prevent overcharging of the capacitor included in the capacitor circuit 13. In addition, when there is an output voltage V received from the switching regulator 10 OUT When the load is L At least a portion of the Figure 3A , 3B3C and the like describe examples of the switch circuit 11.

[0029] The switch controller 12 can be based on the reference voltage V REF and output voltage V OUT Generates a switch control signal C_SW. For example, the switch controller 12 may include two or more resistors, and may generate an output voltage V divided by the two or more resistors. OUT The switch controller 12 can use the feedback voltage and the reference voltage V REF The feedback voltage is compared with the reference voltage V REF Therefore, the output voltage V OUT The level can be determined by the reference voltage V REF The level is determined, and the output voltage V OUT The level can be changed by changing the reference voltage V REF to change the level.

[0030] The capacitor circuit 13 may include at least one capacitor, and at least one of the at least one capacitor may pass a capacitor current I C Charging or discharging. For example, when the inductor current I L At least a portion of the capacitor current I C When at least one capacitor of the capacitor circuit 13 can be charged, so that the capacitor current I C On the other hand, when the capacitor current I C The current flows to the ground voltage (or ground) through the switch circuit 11 or flows to the receiving output voltage V OUT The load makes the capacitor current I C When is negative, at least one capacitor of the capacitor circuit 13 can be discharged. Figure 1 As shown, the capacitor circuit 13 can output the voltage V OUT Provide a load capacitor C between the ground voltage L .

[0031] The output voltage V generated by the switching regulator 10 OUT It can be used as a power supply voltage to provide power to electronic components, and such electronic components can be referred to as the load of the switching regulator 10. For example, the output voltage V OUT The load capacitance C may be provided to a digital circuit configured to process a digital signal, an analog circuit configured to process an analog signal, and / or a radio frequency (RF) circuit configured to process a radio frequency (RF) signal. L It can be determined according to various requirements. For example, the output voltage V OUTTo prevent malfunction of the load with reduced noise, and in particular, to reduce ripple caused by the switching operation of the switching regulator 10, a load capacitor C may be required. L has a large value to reduce the output voltage V OUT On the other hand, the output voltage V OUT level to reduce the power consumption of the load. For example, the switching regulator 10 can be configured to output a low level output voltage V OUT , and provides a high level output voltage V when the load requires high performance or high power consumption OUT Therefore, in order to quickly and dynamically change the output voltage V OUT The level may require a load capacitor C L According to an exemplary embodiment, as shown below, Figure 2 and Figure 5 As described above, the switching regulator 10 can provide an output voltage V with a fast changing level and reduced noise. OUT .

[0032] The capacitor circuit 13 may receive a capacitor control signal C_CL and may provide a load capacitance C that varies according to the capacitor control signal C_CL. L For example, when the output voltage V OUT When the level of is kept constant, the capacitor circuit 13 can provide a relatively large load capacitance C in response to the capacitor control signal C_CL. L , while the output voltage V OUT When the level of changes, the capacitor circuit 13 can also provide a relatively low load capacitance C in response to the capacitor control signal C_CL. L Therefore, the output voltage V OUT It is possible to have a level that changes rapidly dynamically and with reduced noise. In this specification, the capacitor control signal C_CL for controlling the capacitor circuit 13 may be referred to as a control signal.

[0033] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 FIG. 1 is a graph of an example of operation of the switching regulator 10 based on the passage of time. Figure 2 shows the time-lapse of the Figure 1 The output voltage V OUT and load capacitance C L . Figure 2 The dashed line in FIG. 1 shows the output voltage V based on the comparative example. OUT and load capacitance C L , in this comparative example, the load capacitance C L With a capacitance C fixed by a capacitor L0In the following, reference will be made to Figure 1 describe Figure 2 .

[0034] refer to Figure 2 The capacitor circuit 13 can be based on the capacitor control signal C_CL at a relatively high first capacitance C L1 and a relatively low second capacitance C L2 Switching between load capacitors C L On the other hand, according to the comparative example, the load capacitance CL will maintain the same capacitance as the first capacitance C L1 and the second capacitor C L2 The fixed capacitor C L0 Consistent.

[0035] From time t20 to time t21, the output voltage V OUT Can be maintained at the first level V 1 For example, when receiving the output voltage V OUT The load may require low performance and / or low power consumption, so the output voltage V OUT can be maintained at a relatively low first level V 1 The capacitor circuit 13 can provide a first capacitor C in response to the capacitor control signal C_CL. L1 As the load capacitance C L In contrast, the load capacitance C according to the comparative example L is greater than the first capacitor C L1 Small fixed capacitor C L0 Therefore, if Figure 2 As shown, the switching regulator 10 can generate an output voltage V having a reduced ripple compared to the comparative example from time t20 to time t21. OUT With repeated charging and discharging, the capacitor current I C Can oscillate with a constant mean value.

[0036] From time t21 to time t22, the output voltage V OUT From the first level V 1 Dynamically changes to the second level V 2 . Output voltage V OUT The first level V 1 Lower than the second level V 2 For example, when receiving the output voltage V OUT The load may require high performance and / or high power consumption, thus increasing the output voltage V OUT The capacitor circuit 13 can provide a second capacitor C in response to the capacitor control signal C_CL. L2 As the load capacitance C L In contrast, the load capacitance C according to the comparative exampleL is greater than the second capacitor C L2 Large fixed capacitor C L0 In addition, if Figure 2 As shown, the switching regulator 10 can generate a second level V at a relatively early point (ie, time t22). 2 The output voltage V OUT , while the switching regulator 10 according to the comparative example can generate a voltage having a second level V at a relatively delayed time point (ie, time t23). 2 The output voltage V OUT In addition, due to the second capacitor C L2 Smaller than the fixed capacitance C of the comparative example L0 , so compared with the comparative example, the capacitor current I C The inductor current I can have a smaller peak value, so the peak current amplitude through the switch circuit 11 and the inductor L can be reduced. L The peak value of , therefore, the operational reliability of the switching regulator 10 can be improved. In addition, the size of the switching circuit 11 and the inductor L can be reduced.

[0037] From time t22 to time t24, the output voltage V OUT Can be maintained at the second level V 2 The capacitor circuit 13 can provide a first capacitor C in response to the capacitor control signal C_CL. L1 As the load capacitance C L In contrast, the load capacitance C according to the comparative example L is greater than the first capacitor C L1 Small fixed capacitor C L0 Therefore, if Figure 2 As shown, similarly to the period from time t20 to time t21, the switching regulator 10 can generate an output voltage V having a reduced ripple compared to the comparative example during the period from time t22 to time t23. OUT With repeated charging and discharging, the capacitor current I C Can oscillate with a constant mean value.

[0038] From time t24 to time t25, the output voltage V OUT From the second level V 2 Dynamically changes to the first level V 1 For example, it may be necessary to receive an output voltage V OUT The load is low in performance and / or power consumption, so the output voltage V OUT The capacitor circuit 13 can provide a second capacitor C in response to the capacitor control signal C_CL. L2 As the load capacitance CL , while the load capacitance C according to the comparative example L is greater than the second capacitor C L2 Large fixed capacitor C L0 Therefore, if Figure 2 As shown, the switching regulator 10 generates a first level V at a relatively early time point t25. 1 The output voltage V OUT , while the output voltage V according to the comparative example OUT At a relatively delayed time (ie, at time t26), the first level V 1 .

[0039] From time t25, the output voltage V OUT Can be maintained at the first level V 1 The capacitor circuit 13 can provide a first capacitor C in response to the capacitor control signal C_CL. L1 As the load capacitance C L , while the load capacitance C according to the comparative example L It is a fixed capacitor C that is smaller than the first capacitor L0 Therefore, similar to the period from time t20 to time t21, the switching regulator 10 can generate an output voltage V having a reduced ripple starting from time t25, as compared with the comparative example. OUT With repeated charging and discharging, the capacitor current I C Can oscillate with a constant mean value.

[0040] although Figure 2 The output voltage V OUT is shown as having two different levels (i.e., a first level V 1 and the second level V 2 ), but in some example embodiments, the output voltage V OUT can be selectively controlled to three or more different levels. Figure 2 In the example, the load capacitance C L is shown as having two different capacitances (i.e., a first capacitance C L1 and the second capacitor C L2 ), but in some example embodiments, the capacitor circuit 13 may be based on the output voltage V OUT The level provides a load capacitance C having one of three or more different values. L .

[0041] Figure 3A , Figure 3B and Figure 3C An example of a switching regulator according to an example embodiment is shown. Specifically, Figure 3A , Figure 3B and Figure 3C As examples of DC-DC converters, a buck converter 30a, a boost converter 30b, and a buck-boost converter 30c are shown. Figure 3A , Figure 3B and Figure 3C Redundant content in the description.

[0042] refer to Figure 3A , the buck converter 30a can be used as a step-down converter and generate a voltage level lower than the input voltage V IN The level of low output voltage V OUT .like Figure 3A As shown, the buck converter 30a may include an inductor L, a switch circuit 31a, a switch controller 32a, and a capacitor circuit 33a. The switch controller 32a may be based on a reference voltage V REF and output voltage V OUT Generates a switch control signal C_SW and provides the switch control signal C_SW to the switch circuit 31a. REF When the level of the reference voltage V REF The level and level change of the output voltage V OUT Generate a switch control signal C_SW. The switch circuit 31a may include a switch connected in series at an input voltage V IN In some example embodiments, the switch circuit 31a may turn on the two switches mutually exclusively in response to the switch control signal C_SW. The capacitor circuit 33a may be configured to output the voltage V OUT A load capacitance C is provided between the ground voltage and the capacitor control signal C_CL. L .

[0043] refer to Figure 3B , the boost converter 30b can be used as a step-up converter and generate a voltage higher than the input voltage V IN The level high output voltage V OUT .like Figure 3B As shown, the boost converter 30b may include an inductor L, a switch circuit 31b, a switch controller 32b, and a capacitor circuit 33b. The switch controller 32b may be based on a reference voltage V REF and output voltage V OUT Generates a switch control signal C_SW and provides the switch control signal C_SW to the switch circuit 31b. REF When the level of V changes, the switch controller 32b can change the reference voltage V REF level and changes the output voltage VOUT The switch circuit 31b may include two switches to electrically connect one end of the inductor L to the output voltage V OUT and ground voltage. In some example embodiments, the switch circuit 31b may turn on two switches in response to the switch control signal C_SW in a mutually exclusive manner. The capacitor circuit 33b may output the voltage V OUT A load capacitance C is provided between the ground voltage and the capacitor control signal C_CL. L .

[0044] refer to Figure 3C , the buck-boost converter 30c can generate a voltage higher than the input voltage V IN The level high or low output voltage V OUT , and may include an inductor L, a switch circuit 31c, a switch controller 32c, and a capacitor circuit 33c. The switch controller 32c may generate a switch control signal C_SW so that the buck-boost converter 30c is based on the output voltage V OUT The level as Figure 3A The buck converter 30a or Figure 3B For example, when the output voltage V OUT The level is lower than the input voltage V IN When the level is , the switch controller 32c can generate the switch control signal C_SW so that the buck-boost converter 30c uses the switch included in the switch circuit 31c to have the same Figure 3A On the other hand, when the output voltage V OUT The level is higher than the input voltage V IN When the level is , the switch controller 32c can generate the switch control signal C_SW so that the buck-boost converter 30c uses the switch included in the switch circuit 31c to have the same Figure 3B The switch controller 32c can be based on the reference voltage V REF and output voltage V OUT A switch control signal C_SW is generated.

[0045] The switch circuit 31c may include a switch connected in series with the input voltage V IN and ground voltage, and electrically connects one end of the inductor L to the output voltage V OUT The capacitor circuit 33c can output the voltage V OUT A load capacitance C is provided between the ground voltage and the capacitor control signal C_CL. L .

[0046] Figure 4 is a diagram showing a method according to an example embodiment Figure 1 The circuit diagram of an example of the capacitor circuit 13 is shown in FIG. Figure 1 Said, Figure 4 The capacitor circuit 40 can output the voltage V OUT A load capacitance C is provided between the ground voltage and the capacitor control signal C_CL. L .like Figure 4 As shown, the capacitor circuit 40 may include a first capacitor C1 having a fixed capacitance and a variable capacitor 41 connected in parallel with the first capacitor C1. Figure 1 and Figure 2 describe Figure 4 .

[0047] The variable capacitor 41 may include a second capacitor C2 and a switch SW connected in series to each other, and the switch SW may be turned on and off according to the capacitor control signal C_CL. In some example embodiments, the switch SW may remain turned on while the output voltage V OUT remains at a constant level, and the switch SW can remain open while the output voltage V OUT When the switch SW is turned on, the first capacitor C1 and the second capacitor C2 may be electrically connected in parallel, and the capacitor circuit 40 may provide a load capacitance C corresponding to the sum of the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2. L On the other hand, when the switch SW is turned off, the capacitor circuit 40 can provide a load capacitance C corresponding to the capacitance of the first capacitor C1. L For example, as referenced above Figure 2 As described above, when the capacitor circuit 40 is capable of providing any one of two different load capacitances (ie, the first capacitance C L1 Or the second capacitor C L2 ), the first capacitor C1 may have a second capacitance C L2 , and the second capacitor C2 may have a L1 and the second capacitor C L2 The difference between L1 -C L2 The corresponding capacitance.

[0048] In some example embodiments, the capacitor circuit 40 may quickly reduce the load capacitance C in response to the capacitor control signal C_CL. L From the first capacitor C L1 Change to the second capacitor C L2 , and the load capacitance C L The second capacitor C L2 Gradually change to the first capacitor C L1That is, the capacitor circuit 40 can be OUT The level of the capacitor C is reduced rapidly at the time when it starts to change. L , and at the output voltage V OUT The level of the load changes completely when the load capacitance C is gradually increased. L Therefore, not only can the output voltage V OUT level, and can suppress the load capacitance C L The output voltage V OUT To this end, in some example embodiments, the switch SW included in the variable capacitor 41 may operate differently in each of turning on and off in response to the capacitor control signal C_CL. Fig. 6A , Figure 6B and Figure 6C An example of the variable capacitor 41 is described.

[0049] Figure 5 is a diagram showing a method according to an example embodiment Figure 1 FIG. 1 is a graph showing an example of the operation of the switching regulator 10 based on the passage of time. Specifically, Figure 5 The switching regulator 10 includes Figure 4 An example of a capacitor circuit 40 is shown. Figure 5 Shows Figure 4 The switch SW in the circuit has an on-resistance R based on the time lapse ON and capacitor current I C As mentioned above Figure 4 As stated, Figure 5 In the example, the load capacitance C L can decrease rapidly and increase gradually. Figure 1 and Figure 4 describe Figure 5 , and will be Figure 5 The description of Figure 2 Overlapping descriptions.

[0050] From time t50 to time t51, the output voltage V OUT Can be maintained at the first level V 1 The capacitor circuit 40 can provide a first capacitor C in response to the capacitor control signal C_CL. L1 As the load capacitance C L In order to provide the capacitance of the second capacitor C2 as the load capacitance C L The switch SW may be in an on state and may have a relatively small first resistance value R 1 In some example embodiments, the first resistance value R 1 Can be approximately zero. Figure 2As described above, due to the relatively large first capacitor C L1 , output voltage V OUT The ripple at can be reduced.

[0051] From time t51 to time t52, the output voltage V OUT From the first level V 1 Dynamically changes to the second level V 2 The capacitor circuit 40 may respond to the capacitor control signal C_CL at time t51 to reduce the load capacitance C L From the first capacitor C L1 Quickly change to the second capacitor C L2 and the load capacitance C L Keep the second capacitor C L2 Until time t52. At time t51, in order to L By excluding the capacitance of the second capacitor C2, the switch SW can be turned off. Figure 5 As shown, the on-resistance R of the switch SW ON The first resistance value R 1 Rapidly changes to a relatively large second resistance value R 2 and can be maintained at the second resistance value R 2 Until time t52. In some example embodiments, the second resistance value R 2 can be approximately infinite. Therefore, as mentioned above Figure 2 As described above, due to the relatively small second capacitor C L2 The output voltage V OUT may have a second level V at an earlier time point (ie, time t52). 2 .like Figure 5 As shown in FIG. 1 , from time t51 to time t52, due to the increase in output voltage V OUT The level of the capacitor circuit 40 can be provided with a capacitor current I for charging the capacitor circuit 40. C .

[0052] At time t52, the output voltage V OUT Can reach the second level V 2 , and the capacitor circuit 40 can respond to the capacitor control signal C_CL and start to gradually reduce the load capacitance C L From the second capacitor C L2 Change to the first capacitor C L1 The capacitor circuit 40 can gradually change the load capacitance C L , until the load capacitance C L Reaching the first capacitance C L1 time t53. Figure 5 The load capacitance C is shown inL The load capacitance C increases linearly from time t52 to time t53, but in some example embodiments, the load capacitance C L It may increase nonlinearly from time t52 to time t53.

[0053] In order to set the load capacitance C L From the second capacitor C L2 Gradually change to the first capacitor C L1 , the switch SW can gradually change from the OFF state to the ON state, that is, the on-resistance R ON The second resistor value R 2 Gradually changes to the first resistance value R 1 In addition, due to the second capacitor C L2 Gradually increases to the first capacitance C L1 The load capacitance C L And from the first level V 1 The second level V 2 The output voltage V OUT , so a capacitor current I can be generated for charging the variable capacitor 41 of the capacitor circuit 40 C In some example embodiments, Figure 5 As shown, from time t52 to time t53, the capacitor current I C Can have a constant amplitude I CHG .

[0054] From time t53 to time t54, the output voltage V OUT Can be maintained at the second level V 2 The capacitor circuit 40 can provide a second capacitor C in response to the capacitor control signal C_CL. L2 As the load capacitance C L In order to provide the capacitance of the second capacitor C2 as the load capacitance C L The switch SW may be in an on state and may have a relatively small first resistance value R 1 . Similar to the period from time t50 to time t51, due to the relatively large first capacitor C L1 , so the output voltage V OUT The ripple at can be reduced.

[0055] From time t54 to time t55, the output voltage V OUT From the second level V 2 Dynamically changes to the first level V 1 The capacitor circuit 40 may respond to the capacitor control signal C_CL at time t54 to reduce the load capacitance C L From the first capacitor C L1Quickly change to the second capacitor C L2 and the second capacitor C L2 Keep the load capacitance C L Until time t55. At time t54, the on-resistance R of the switch SW ON The first resistance value R 1 Quickly change to the second resistance value R 2 and can be maintained at the second resistance value R 2 Until time t55. Therefore, due to the relatively small second capacitor C L2 , so the output voltage V OUT may have the first level V at an earlier time point (ie, at time t55) 1 .like Figure 5 As shown, from time t54 to time t55, due to the reduced output voltage V OUT The level of the capacitor current I can be provided to the capacitor circuit 40 for discharging the capacitor circuit 40. C .

[0056] At time t55, the output voltage V OUT Can reach the first level V 1 , and the capacitor circuit 40 can start to convert the load capacitor C in response to the capacitor control signal C_CL L From the second capacitor C L2 Gradually change to the first capacitor C L1 The capacitor circuit 40 can gradually change the load capacitance C L , until the load capacitance C L Reaching the first capacitance C L1 In some example embodiments, the load capacitance C L can increase linearly, and in other example embodiments, the load capacitance C L The on-resistance R of the switch SW can be increased nonlinearly. ON The second resistor value R 2 Gradually changes to the first resistance value R 1 In addition, due to the second capacitor C L2 Gradually increases to the first capacitance C L1 The load capacitance C L and from the second level V 2 The first level V 1 The output voltage V OUT , so a capacitor current I can be generated for discharging the variable capacitor 41 of the capacitor circuit 40 C In some example embodiments, Figure 5 As shown, from time t55 to time t56, the capacitor current IC Can have a constant amplitude I DIS .

[0057] From time t56, the output voltage V OUT Can be maintained at the first level V 1 The capacitor circuit 40 can provide a first capacitor C in response to the capacitor control signal C_CL. L1 As the load capacitance C L , and the switching regulator 10 can provide an output voltage V with reduced ripple OUT .

[0058] Fig. 6A , Figure 6B and Figure 6C is a diagram showing an example of a variable capacitor according to an example embodiment. Figure 4 Said, Fig. 6A , Figure 6B and Figure 6C The variable capacitors 60a, 60b and 60c can each have a variable capacitance based on the capacitor control signal C_CL. Figure 5 In some example embodiments, Fig. 6A , Figure 6B and Figure 6C The variable capacitors 60a, 60b and 60c can be arranged to be connected from the load capacitance C L The capacitance of the second capacitor C2 is quickly excluded from the load capacitor C2, and the operation can be such that the capacitance of the second capacitor C2 is gradually added to the load capacitance C L .

[0059] refer to Fig. 6A , the variable capacitor 60a may include a second capacitor C2, a current source CS1, a single-pole double-throw (SPDT) switch SW1, and a first transistor T1. The first transistor T1 may include an NMOS transistor, the drain of which is connected to the second capacitor C2, the source of which is applied with a ground voltage, and the gate of which is connected to the SPDT switch SW1. The current source CS1 may generate a current I G , and the SPDT switch SW1 may connect the gate of the first transistor T1 to the current source CS1 or to the ground node based on the capacitor control signal C_CL.

[0060] For a reduced load capacitance C L (For example, the second capacitor C L2 ), the SPDT switch SW1 can connect the gate of the first transistor T1 to the ground node in response to, for example, a high-level capacitor control signal C_CL. In addition, the first transistor T1 can be turned off, so that the load capacitor C LOn the other hand, for the increased load capacitance C L (For example, the first capacitor C L1 ), the SPDT switch SW1 can couple the gate of the first transistor T1 to the current source CS1 in response to, for example, a low-level capacitor control signal C_CL. In addition, the gate voltage of the first transistor T1 can be increased by the current I G The capacitance of the second capacitor C2 can be gradually added to the load capacitance C L The rate at which the capacitance of the variable capacitor 60a increases in response to the low-level capacitor control signal C_CL may be determined by the current of the current source CS1 and the parasitic capacitance of the gate of the first transistor T1, and in some example embodiments, the variable capacitor 60a may further include a capacitor coupled between the gate of the first transistor T1 and a ground node.

[0061] refer to Figure 6B , the variable capacitor 60b may include a second capacitor C2, a current source CS2, and a plurality of transistors (e.g., second to fourth transistors T2 to T4). The second transistor T2 may include a drain connected to the second capacitor C2, a source to which a ground voltage is applied, and a gate connected to the third transistor T3 and the fourth transistor T4. The current source CS2 may generate a reference current I REF , and the third transistor T3 and the second transistor T2 can form a current mirror while the fourth transistor T4 is turned off. In addition, the current I flowing through the drain and source of the second transistor T2 X The reference current I REF And the size ratio of the third transistor T3 to the second transistor T2 is determined.

[0062] The fourth transistor T4 can respond to the load capacitance C L (For example, the second capacitor C L2 ) of the capacitor control signal C_CL of the high level, the ground voltage is applied to the gate of the second transistor T2. Therefore, the second transistor T2 can be turned off, so that the load capacitor C L The capacitance of the second capacitor C2 is excluded. On the other hand, the fourth transistor T4 can respond to the load capacitance C L (For example, the first capacitor C L1 ) is turned off by the low-level capacitor control signal C_CL. Therefore, the gate voltages of the second transistor T2 and the third transistor T3 can gradually increase, so the capacitance of the second capacitor C2 can be increased by drawing a current I from the second capacitor C2. X And gradually add the load capacitance C L .

[0063] refer to Figure 6C , the variable capacitor 60c may include a second capacitor C2 and a variable resistor VR connected in series with each other. The variable resistor VR may provide a variable resistance value between the second capacitor C2 and the ground potential based on the capacitor control signal C_CL. For example, the variable resistor VR may be a reduced load capacitor C L (For example, the second capacitor C L2 ) provides a relatively large resistance value (e.g., approximately infinite), while the variable resistor VR can provide ... L (For example, the first capacitor C L1 ) provides a relatively small resistance value (e.g., approximately zero).

[0064] In some example embodiments, the variable resistor VR may be responsive to the capacitor control signal C_CL to rapidly decrease the load capacitance C L Provides a rapidly increasing resistance value and a gradually increasing load capacitance C L Provide a gradually decreasing resistance value. For example, the variable resistor VR may include a plurality of sub-circuits, each of which includes a resistor and an NMOS transistor connected in series with each other, and the plurality of sub-circuits may be connected in parallel between the second capacitor C2 and the ground node. The capacitor control signal C_CL may include a plurality of bits provided to each sub-circuit. The capacitor control signal C_CL may change rapidly so that all bits have a low level due to the rapidly increasing resistance, and the capacitor control signal C_CL may change sequentially until all bits have a high level due to the gradually decreasing resistance value.

[0065] Figure 7 is a block diagram showing a power supply circuit 70 according to an example embodiment. Figure 7 As shown, the power supply circuit 70 can be powered from an input voltage V IN Generates output voltage V OUT , and may receive a setting signal SET. In some example embodiments, Figure 7 As shown, a reference voltage V may be generated within the power supply circuit 70 (eg, by a power controller 73). REF and the envelope voltage V ENV In other example embodiments, the reference voltage V may be received from outside the power supply circuit 70. REF and the envelope voltage V ENV The power supply circuit 70 may include a second capacitor C2, a switch SW, a first voltage regulator 71, a second voltage regulator 72, a power controller 73, and a mode switch 74.

[0066] The first voltage regulator 71 can be based on the reference voltage V REFFrom the input voltage V IN Generates a first output voltage V OUT1 For example, the first voltage regulator 71 may be a reference Figure 3A , Figure 3B and Figure 3C The DC-DC converter shown, and the first output voltage V OUT1 The level can be based on the reference voltage V REF The switch SW can be based on the capacitor control signal C_CL at the first output voltage V OUT1 and ground voltage to change the load capacitance C L . Similar to Figure 4 When the switch SW is turned on in response to the capacitor control signal C_CL, the second capacitor C2 can be connected to the load capacitor C L When the switch SW is turned off in response to the first control signal C_CL, the second capacitor C2 can be connected to the load capacitor C L Excluded.

[0067] The second voltage regulator 72 can be based on the envelope voltage V ENV From the input voltage V IN Generates the second output voltage V OUT2 For example, the second voltage regulator 72 may include a reference Figure 3A , Figure 3B and Figure 3C The DC-DC converter shown may also include an envelope voltage V ENV Adjust the second output voltage V OUT2 The envelope voltage V ENV can be a signal whose magnitude depends on the power consumption required at the load, and the envelope voltage V ENV The size of can, for example, follow the envelope of the swing output signal of the load. Therefore, the second output voltage V OUT2 The size of can correspond to the required power dissipation in the load. Figure 7 As shown, in some example embodiments, the second voltage regulator 72 may receive the first output voltage V from the first voltage regulator 71. OUT1 , and at least some components included in the second voltage regulator 72 can be derived from the first output voltage V OUT1 The following will refer to Figure 8 and Fig.10 An example of the first voltage regulator 71 and the second voltage regulator 72 is described.

[0068] The mode switch 74 may output a first output voltage V based on a mode control signal C_MD provided from the power controller 73. OUT1 and the second output voltage V OUT2One of the output voltages V OUT For example, the mode control signal C_MD may indicate an average power tracking (APT) mode or an envelope tracking (ET) mode, and the mode switch 74 may output the first output voltage V in response to the mode control signal C_MD indicating the average power tracking mode. OUT1 As the output voltage V OUT , and the mode switch 74 can output a second output voltage V in response to the mode control signal C_MD indicating the envelope tracking mode. OUT2 As the output voltage V OUT In some example embodiments, the mode switch 74 may include at least one power switch, and the power switch may include a power transistor capable of supporting a large current.

[0069] The power controller 73 may receive a setting signal SET from the power supply circuit 70 to generate a plurality of control signals C_CL, C_MD and C_EN based on the setting signal SET. For example, the setting signal SET may include information indicating an average power tracking mode or an envelope tracking mode, and may also include information indicating a dynamic change of the first output voltage V OUT1 In some example embodiments, the power controller 73 may also generate a reference voltage V REF and / or envelope voltage V ENV .

[0070] In some example embodiments, when the setting signal SET indicates the average power tracking mode, the power controller 73 may provide a deactivated enable signal C_EN to the second voltage regulator 72, and may provide a mode control signal C_MD to the mode switch 74 so that the first output voltage V OUT1 is output as the output voltage V OUT The second voltage regulator 72 may be disabled in response to the deactivated enable signal C_EN. For example, the disabled second voltage regulator 72 may be powered off. On the other hand, when the setting signal SET indicates the envelope tracking mode, the power controller 73 may provide the activated enable signal C_EN to the second voltage regulator 72 and may provide the mode control signal C_MD to the mode switch 74 so that the second output voltage V OUT2 is output as the output voltage V OUT The second voltage regulator 72 can respond to the activated enable signal C_EN based on the envelope voltage V ENV From the input voltage V IN Generates the second output voltage V OUT2 .

[0071] In some example embodiments, the power controller 73 may provide a capacitor control signal C_CL to the switch SW when the setting signal SET indicates that the first output voltage V OUT1 When the level of the capacitor C2 changes, the capacitor control signal C_CL turns off the switch SW. Therefore, the second capacitor C2 may not affect the load capacitance C of the first voltage regulator 71. L has contributed, and the load capacitance C L In addition, the power controller 73 can provide a capacitor control signal C_CL to the switch SW, and when the first output voltage V OUT1 When the capacitor control signal C_CL has changed to the required level, the switch SW is turned on. Therefore, the first output voltage V OUT1 Can quickly change to a different level with reduced ripple while maintaining a constant level.

[0072] Figure 8 is a diagram showing a method according to an example embodiment Figure 7 A circuit diagram of an example of a power supply circuit 70, Fig. 9 is a diagram showing a method according to an example embodiment Figure 8 Graph of an example of the operation of the power supply circuit 80. Specifically, Figure 8 Shows Figure 7 An example of a first voltage regulator 71, a second voltage regulator 72 and a mode switch 74, Fig. 9 Shows the time-lapse Figure 8 The first output voltage V OUT1 , the second output voltage V OUT2 , output voltage V OUT and load capacitance C L .

[0073] refer to Figure 8 The power supply circuit 80 may include a second capacitor C2, a switch SW, a first voltage regulator 81, a second voltage regulator 82, and a mode switch 84. The first voltage regulator 81 may be based on a reference voltage V REF Generates a first output voltage V OUT1 , the second voltage regulator 82 can be based on the envelope voltage V ENV Generates the second output voltage V OUT2 .exist Figure 8 In the example of FIG. 1 , the first voltage regulator 81 and the second voltage regulator 82 are shown as including a buck converter, but in some example embodiments, the first voltage regulator 81 and / or the second voltage regulator 82 may include a boost converter and / or a buck-boost converter.

[0074] The first voltage regulator 81 may include a first inductor L1, a first capacitor C1, a first switch circuit 81_1, and a first switch controller 81_2. The first switch controller 81_2 may be based on a reference voltage V REF and the first output voltage V OUT1 The first switch control signal C_SW1 is generated, and the first switch circuit 81_1 can respond to the first switch control signal C_SW1 from the input voltage V IN The first capacitor C1 can provide a load capacitance C of the first voltage regulator 81. L As mentioned above Figure 4 , Figure 7 As described in the examples above, the second capacitor C2 and the switch SW can change the load capacitance C of the first voltage regulator 81 based on the capacitor control signal C_CL. L .

[0075] The second voltage regulator 82 may include a second inductor L2, a second switch circuit 82_1, and a second switch controller 82_2, and may also include a third capacitor C3 and an amplifier 82_3. Similar to the first voltage regulator 81, the second inductor L2, the second switch circuit 82_1, and the second switch controller 82_2 in the second voltage regulator 82 may be used as a buck converter, and the second voltage regulator 82 may be responsible for the second output voltage V OUT2 In addition, the second switch controller 82_2 may receive the current flowing through the third capacitor C3 as feedback, and may generate a second switch control signal C_SW2 based on the feedback. Unlike the first switch controller 81_2 of the first voltage regulator 81, the second output voltage V OUT2 As feedback, the current flowing through the third capacitor C3 is used as feedback in the second switch controller 82_2 of the second voltage regulator 82. The second switch controller 82_2 may receive the enable signal C_EN and may perform normal operation in response to the activated enable signal C_EN, while in some example embodiments, the second switch controller 82_2 may be powered off in response to the inactivated control signal C_EN.

[0076] The amplifier 82_3 can receive the first output voltage V OUT1 power, and may include a circuit for receiving an envelope voltage V ENV The non-inverting input is used to receive the second output voltage V OUT2 The output signal of the amplifier 82_3 can be reflected to the second output voltage V through the third capacitor C3. OUT2, the third capacitor C3 can be called an AC coupling capacitor. Therefore, the amplifier 82_3 and the third capacitor C3 can be responsible for the second output voltage V OUT2 The second switch controller 82_2 may receive the enable signal C_EN and may perform a normal operation in response to the activated enable signal C_EN, while in some example embodiments, the second switch controller 82_2 may be powered off in response to the inactivated control signal C_EN.

[0077] The mode switch 84 can selectively connect the output node of the first voltage regulator 81 to the output node of the power supply circuit 80 based on the mode control signal C_MD. For example, the mode switch 84 can be turned on in response to the mode control signal C_MD indicating the average power tracking mode to output the first output voltage V OUT1 As the output voltage V OUT , and the mode switch 84 can be turned off in response to the mode control signal C_MD indicating the envelope tracking mode to connect the output node of the first voltage regulator 81 to the output node V of the power supply circuit 80. OUT If the power is disconnected. Figure 8 As shown, the output voltage V OUT can be connected with the second output voltage V OUT2 However, by disabling the second voltage regulator 82 in the average power tracking mode, the output voltage V OUT The first output voltage V OUT1 Sure.

[0078] refer to Fig. 9 , from time t90 to time t93, the power supply circuit 80 can be set to the average power tracking mode. Therefore, the output voltage V OUT Can be compared with the first output voltage V OUT1 In the average power tracking mode, the first voltage regulator 81 can dynamically change the first output voltage V OUT1 level (V11→V12→V13), and can be at the first output voltage V OUT1 The level of the capacitor C is reduced while the L For example, at time t91, the load capacitance C L From the first capacitor C L1 Reduced to the second capacitor C L2 , and the load capacitance C L The first output voltage V OUT1 The voltage level of the second capacitor C is maintained while changing (V11→V12). L2 In some example embodiments, the load capacitance C L From the first capacitor C L1 Rapidly decrease to the second capacitance C L2and from the second capacitor C L2 Gradually increases to the first capacitance C L1 Similarly, the load capacitance C L can be reduced at time t92 and time t93. Therefore, as described above, the first output voltage V OUT1 The level can change quickly, and when the first output voltage V OUT1 The level remains constant, the first output voltage V OUT1 The noise (eg, ripple) can be reduced.

[0079] From time t93, the power supply circuit 80 can be set to the envelope tracking mode. Therefore, the output voltage V OUT (ie, the second output voltage V OUT2 ) can be determined by the second voltage regulator 82. Figure 8 As described, some components of the second voltage regulator 82 (such as the amplifier 82_3) can be obtained from the first output voltage V provided by the first voltage regulator 81. OUT1 receives power, and the first output voltage V OUT1 The level of the second output voltage V OUT2 The level of V14→V15→V16 changes dynamically. Therefore, similar to the average power tracking mode, at the first output voltage V OUT1 At the same time as the level of the load capacitor C L can be reduced. For example, Fig. 9 As shown, at time t92, time t94 and time t95, the load capacitance C L can be reduced to the second capacitor C L2 .

[0080] Fig.10 1 is a circuit diagram showing an example of a power supply circuit 100 according to an example embodiment. Fig.10 The power supply circuit 100 and Figure 8 The power supply circuit 80 of the embodiment of the present invention can omit the second capacitor C2 for changing the load capacitance CL of the first voltage regulator 110. Fig.10 The description of Figure 8 The descriptions overlap the descriptions.

[0081] refer to Fig.10 , the power supply circuit 100 may include a switch SW, a first voltage regulator 110, a second voltage regulator 120, and a mode switch 140. The first voltage regulator 110 may be based on a reference voltage V REF Generates a first output voltage V OUT1, and may further include a first inductor L1, a first capacitor C1, a first switch circuit 111, and a first switch controller 112. The first switch controller 112 may be based on a reference voltage V REF and the first output voltage V OUT1 The second voltage regulator 120 can generate a first switch control signal C_SW1 based on the envelope voltage V ENV Generates the second output voltage V OUT2 , and may further include a second inductor L2, a second switch circuit 121, a second switch controller 122, a third capacitor C3, and an amplifier 123. The second switch controller 122 may generate a second switch control signal C_SW2 based on a current flowing into the third capacitor C3.

[0082] Similar to Figure 8 The switch SW, Fig.10 The switch SW can be based on the capacitor control signal C_CL between the ground voltage and the first output voltage V OUT1 The load capacitance C of the first voltage regulator 110 is changed between L Specifically, in Fig.10 In the embodiment, the switch SW can be switched by adding the capacitance of the third capacitor C3 (which is the AC coupling capacitor of the second voltage regulator 120) to the load capacitance C L Or exclude the third capacitor C3 to change the load capacitance C L For example, in the average power tracking mode, the mode switch 140 may electrically couple the output node of the first voltage regulator 110 to the output node of the second voltage regulator 120 based on the mode control signal C_MD. Therefore, one end of the third capacitor C3 may be electrically connected to the output node of the first voltage regulator 110. In addition, in the average power tracking mode, the amplifier 123 may have a floating output due to the inactivated enable signal C_EN. Therefore, in the average power tracking mode, the third capacitor C3 may perform the same Figure 8 The switch SW has the same function as the second capacitor C2 in FIG. 1 , and the load capacitance C can be changed by turning on / off based on the capacitor control signal C_CL. L In some example embodiments, the switch SW may be turned off in response to the capacitor control signal C_CL in the envelope tracking mode.

[0083] Fig.11 is a flow chart illustrating a method of operating a switching regulator according to an example embodiment. Fig.11 The method can be Figure 1 The switching regulator 10 performs Fig.11 As shown, the operating method of the switching regulator may include step S10, step S30 and step S50. Figure 1 and Figure 2 describe Fig.11 .

[0084] Step S10 may include steps S11 and S12, and in some example embodiments, steps S11 and S12 may be performed in parallel. In step S11, outputting a first level V 1 The output voltage V OUT For example, the switching regulator 10 can be based on the reference voltage V REF The level generates the first level V 1 The output voltage V OUT In step S12, the load capacitance C L Keep the first capacitor C L1 For example, the capacitor circuit 13 can respond to the capacitor control signal C_CL to change the load capacitor C L Maintained at a ratio of the second capacitor C L2 The first large capacitor C L1 , so the output voltage V OUT noise.

[0085] Step S30 may include steps S31 and S32, and in some example embodiments, steps S31 and S32 may be performed in parallel. In step S31, the output voltage V OUT From the first level V 1 Change to the second level V 2 For example, the switching regulator 10 may respond to the reference voltage V REF The level change of the output voltage V OUT From the first level V 1 Change to the second level V 2 , so the output voltage V OUT From the first level V 1 To the second level V 2 In step S32, the second capacitor C L2 Keep the load capacitance C L For example, the capacitor circuit 13 can respond to the capacitor control signal C_CL to change the load capacitor C L Maintained at a ratio of the first capacitor C L1 The small second capacitor C L2 , so the output voltage V OUT From the first level V 1 Quickly change to the second level V 2 .

[0086] Step S50 may include steps S51 and S52, and in some example embodiments, steps S51 and S52 may be performed in parallel. In step S51, outputting the second level V 2 The output voltage V OUT For example, the switching regulator 10 can be based on the reference voltage V REF The level generates the second level V 2 The output voltage V OUT In step S52, the load capacitance C L Keep the first capacitor C L1 For example, the capacitor circuit 13 can respond to the capacitor control signal C_CL to change the load capacitor C L Maintained at a ratio of the second capacitor C L2 The first large capacitor C L1 , so the output voltage V OUT noise.

[0087] Fig.12 is a flow chart illustrating an operating method of a switching regulator according to an example embodiment. Fig.11 Compared with the method Fig.12 Steps S20 and S40 may also be included. For example, Fig.12 The method can be Figure 1 The switching regulator 10 performs, hereinafter, reference will be made to Figure 1 and 5 describe Fig.12 .

[0088] exist Fig.11 After step S10, step S20 may be performed, and a rapid reduction of the load capacitance C may be performed in step S20. L For example, in step S12 (included in step S10), the load capacitance C L Can be maintained at the first capacitor C L1 , and in step S32 (included in step S30), the load capacitance C L Can be maintained at the second capacitor C L2 Therefore, in step S20, the load capacitance C L From the first capacitor C L1 Rapidly decrease to the second capacitance C L2 , so the output voltage V OUT The level can be reduced due to the rapid reduction of the load capacitance C L Then, step S30 may be performed.

[0089] After step S30, step S40 may be performed, and gradually increasing the load capacitance C may be performed in step S40.L For example, in step S32 (included in step S30), the load capacitance C L Keep the second capacitor C L2 , and in step S52 (included in step S50), the load capacitance C L Can be maintained as the first capacitor C L1 Therefore, in step S40, the load capacitance C L The second capacitor C L2 Gradually increases to the first capacitance C L1 , so when the first level V 1 To the second level V 2 When the change is completed, the output voltage V OUT Can stably have a second level V 2 .

[0090] Fig.13 1 is a diagram showing a system 130 according to an example embodiment. In some example embodiments, the system 130 may be a semiconductor integrated circuit, such as a system on a chip (SoC), or may include a printed circuit board and a package mounted thereon. Fig.13 As shown, the system 130 may include first to fourth functional blocks 131 to 134 and a power management integrated circuit (PMIC) 135 .

[0091] The first to fourth functional blocks 131 to 134 may operate based on power provided by the first to fourth power supply voltages VDD1 to VDD4 outputted from the PMIC 135. For example, at least one of the first to fourth functional blocks 131 to 134 may be a digital circuit for processing digital signals (e.g., an application processor (AP)), or may be an analog circuit for processing analog signals (e.g., an amplifier). In addition, at least one of the first to fourth functional blocks 131 to 134 may also be a circuit for processing mixed signals, such as an analog-to-digital converter (ADC). Although the system 130 is Fig.13 1 is shown as including four functional blocks, but in some example embodiments, system 130 may include less than four functional blocks, five functional blocks, or more than five functional blocks.

[0092] PMIC 135 can be powered from an input voltage V INA first power supply voltage VDD1 to a fourth power supply voltage VDD4 are generated, and the level of at least one of the first power supply voltage VDD1 to the fourth power supply voltage VDD4 can be changed based on the voltage control signal C_V. At least one of the first functional block 131 to the fourth functional block 134 can receive a power supply voltage whose level changes dynamically based on the required performance and power consumption. For example, the first functional block 131 can be an image processor that processes image data. Although the first functional block 131 can receive a low level of the first power supply voltage VDD1 while processing a photo including a single image, when the first functional block 131 processes a moving image including a series of images, the first functional block can receive a higher level of the first power supply voltage VDD1.

[0093] The PMIC 135 may receive a voltage control signal C_V corresponding to the performance and power consumption required in the first functional block 131, and the PMIC 135 may increase or decrease the level of the first power supply voltage VDD1 based on the voltage control signal C_V. In this way, the method of dynamically changing the power supply voltage level of the functional block may be referred to as dynamic voltage scaling (DVS). The PMIC 135 may include the switching regulator described above with reference to the accompanying drawings, so that the first power supply voltage VDD1 may have reduced noise when maintaining a constant level, and the level of the first power supply voltage VDD1 may change rapidly. In some example embodiments, the first functional block 131 may stop operating when the level of the first power supply voltage VDD1 changes, and may resume operating after the level of the first power supply voltage VDD1 changes. In addition, when the level of the first power supply voltage VDD1 changes rapidly, the execution time of the operation of the first functional block 131 may be shortened, and therefore, the system 130 may provide improved performance. In addition, since the noise of the first power supply voltage VDD1 is reduced, the operational reliability of the first functional block 131 and the system 130 may be improved.

[0094] Fig.14 is a block diagram illustrating a wireless communication device 200 according to an example embodiment. Specifically, Fig.14 A user equipment (UE) (or terminal) is shown to be powered by a battery 250. In some example embodiments, the wireless communication device 200 may be included in a wireless communication system using a cellular network such as 5G, LTE, or may be included in a wireless local area network (WLAN) or any other wireless communication system. In the wireless communication device 200, a switching regulator according to an example embodiment may be used to provide variable power to the power amplifier 216. Fig.14 As shown, the wireless communication device 200 may include a transceiver 210 , a baseband processor 220 , an antenna 230 , a power circuit 240 , and a battery 250 .

[0095] The transceiver 210 may include an antenna interface circuit 211, an input circuit 212, a low noise amplifier (LNA) 213, a receiving circuit 214, a transmitting circuit 215, a power amplifier (PA) 216, and an output circuit 217. The antenna interface circuit 211 may couple a transmitter or a receiver with the antenna 230 according to a transmit mode or a receive mode. In some example embodiments, the input circuit 212 may include a matching circuit or a filter, the low noise amplifier 213 may amplify an output signal of the input circuit 212, and the receiving circuit 214 may include a mixer for down-conversion. In some example embodiments, the transmitting circuit 215 may include a mixer for up-conversion, the power amplifier 216 may amplify an output signal of the transmitting circuit 215, and the output circuit 217 may include a matching circuit or a filter.

[0096] The baseband processor 220 may transmit and receive baseband signals using the transceiver 210, and may perform modulation / demodulation, encoding / decoding, etc. In some example embodiments, the baseband processor 220 may be referred to as a modem. The baseband processor 220 may generate a setting signal SET for setting an average power tracking mode or an envelope tracking mode, and may generate a setting signal SET for changing the output voltage V OUT The level of the setting signal SET.

[0097] The power supply circuit 240 can receive an input voltage V from the battery 250. IN , and can generate an output voltage V that provides power to the power amplifier 216 OUT The power supply circuit 240 may include the switching regulator described above with reference to the accompanying drawings, and may change the load capacitance C based on the setting signal SET. L , to achieve an output voltage V OUT Rapid level changes and stable levels.

[0098] As described above, example embodiments have been disclosed in the drawings and the specification. Although example embodiments have been described herein with reference to specific terms, it should be understood that they are only used for the purpose of describing the technical concept, and are not used to limit the scope of the present disclosure defined in the claims. Therefore, those skilled in the art will understand that various modifications can be made without departing from the scope of the present disclosure. Therefore, the true scope of protection should be determined by the technical concept of the attached claims.

Claims

1. A switching regulator configured to generate an output voltage based on an input voltage, the switching regulator include: Inductors; as well as a capacitor circuit configured to generate the output voltage by being charged with an inductor current passing through the inductor from the input voltage, provide a first capacitance as a load capacitance based on whether the output voltage is a first level or a second level, and provide a second capacitance smaller than the first capacitance as the load capacitance based on whether the output voltage is between the first level and the second level, Wherein, the capacitor circuit comprises: a first capacitor configured to provide a fixed capacitance between a ground voltage and the output voltage; and a variable capacitor connected in parallel with the first capacitor between the ground voltage and the output voltage, wherein the fixed capacitance of the first capacitor is the second capacitance, Wherein, the variable capacitor comprises: a second capacitor having a capacitance corresponding to a difference between the first capacitance and the second capacitance; and A switch is coupled in series with the second capacitor, the switch being configured to electrically disconnect the second capacitor from the ground voltage based on a control signal.

2. The switching regulator according to claim 1, in, The capacitor circuit is configured to gradually change the load capacitance from the second capacitance to the first capacitance within a specific period starting from a time point when the output voltage reaches the second level from the first level.

3. The switching regulator according to claim 2, in, The capacitor circuit is configured to be charged or discharged by a current of a constant magnitude during the specific period.

4. The switching regulator according to claim 1, in, The capacitor circuit is configured to quickly change the load capacitance from the first capacitance to the second capacitance at a time point based on when the output voltage starts to change from the first level to the second level.

5. The switching regulator according to claim 1, in, The switch includes a transistor connected between the second capacitor and the ground voltage, a control terminal of the transistor being configured to receive the control signal.

6. The switching regulator according to claim 1, in, The switch includes a current source configured to draw current from the second capacitor based on the control signal.

7. The switching regulator according to claim 1, in, The switch includes a resistance circuit between the second capacitor and the ground voltage, the resistance circuit being configured to provide a variable resistance value based on the control signal.

8. The switching regulator according to claim 1, in, The capacitor circuit is configured to provide the second capacitance based on the output voltage changing from the second level to the first level.

9. The switching regulator according to claim 8, in, The capacitor circuit is configured to gradually change the load capacitance from the second capacitance to the first capacitance within a specific period starting from a time point when the output voltage reaches the first level from the second level.

10. The switching regulator according to claim 8, in, The capacitor circuit is configured to quickly change the load capacitance from the first capacitance to the second capacitance based on the output voltage starting to change from the second level to the first level.

11. The switching regulator according to claim 1, wherein the switching regulator further comprises: include: a switching circuit configured to selectively provide the inductor current to the capacitor circuit; as well as A switch controller is configured to control the switch circuit based on a reference voltage and the output voltage.

12. A switching regulator configured to generate an output voltage based on an input voltage, the switching regulator include: Inductors; as well as a capacitor circuit configured to provide a load capacitance, generate the output voltage by being charged with an inductor current passing through the inductor from the input voltage, and quickly change the load capacitance from a first capacitance to a second capacitance smaller than the first capacitance and gradually change the load capacitance from the second capacitance to the first capacitance based on the output voltage, The capacitor circuit is further configured to provide the first capacitance as the load capacitance based on whether the output voltage is at a first level or a second level, and to provide the second capacitance based on whether the output voltage is between the first level and the second level.

13. A power supply circuit configured to generate a power supply voltage based on an input voltage, the power supply circuit include: a first voltage regulator configured to generate a first output voltage based on the input voltage and a reference voltage; a switch configured to change a load capacitance between a ground voltage and the first output voltage based on a control signal; as well as A power controller, wherein the power controller is configured to: generate the reference voltage to control the first voltage regulator to change the first output voltage according to the load condition; and generate the control signal to control the switch to maintain the load capacitance at a first capacitance based on the first output voltage being constant, and maintain the load capacitance at a second capacitance that is smaller than the first capacitance based on the first output voltage being variable.

14. The power supply circuit according to claim 13, wherein the power supply circuit further comprises: include: a second voltage regulator configured to generate a second output voltage based on the input voltage and the envelope voltage, The power controller is configured to disable the second voltage regulator in an average power tracking mode and enable the second voltage regulator in an envelope tracking mode.

15. The power supply circuit according to claim 14, further comprising a mode switch connected to the first voltage regulator and the second voltage regulator, in, The power controller is configured to control the mode switch to output the first output voltage as the power supply voltage in the average power tracking mode and to output the second output voltage as the power supply voltage in the envelope tracking mode.

16. The power supply circuit according to claim 14, in, The second voltage regulator comprises: an amplifier configured to amplify a difference between the envelope voltage and the second output voltage; and an AC coupling capacitor coupled to an output terminal of the amplifier, The switch is connected to one end of the AC coupling capacitor and is configured to add the capacitance of the AC coupling capacitor to the load capacitance or remove the capacitance of the AC coupling capacitor from the load capacitance based on the control signal.

17. The power supply circuit according to claim 16, in, The amplifier is powered based on the first output voltage in the envelope tracking mode.

18. The power supply circuit according to claim 16, in, The switch is configured to quickly change the load capacitance from the first capacitance to the second capacitance and gradually change the load capacitance from the second capacitance to the first capacitance based on the control signal.

19. A switching regulator configured to provide an output voltage based on an input voltage, the switching regulator include: a capacitor circuit configured to provide a first capacitance based on a control signal indicating a constant output voltage and to provide a second capacitance based on a control signal indicating a varying output voltage; as well as a controller configured to generate the control signal, Wherein, the capacitor circuit comprises: a first capacitor configured to provide a fixed capacitance between a ground voltage and the output voltage; and a variable capacitor connected in parallel with the first capacitor between the ground voltage and the output voltage, wherein the fixed capacitance of the first capacitor is the second capacitance, Wherein, the variable capacitor comprises: a second capacitor having a capacitance corresponding to a difference between the first capacitance and the second capacitance; and A switch is coupled in series with the second capacitor, the switch being configured to electrically disconnect the second capacitor from the ground voltage based on the control signal.

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