Semiconductor memory module including nonvolatile memory device

Abstract

The present disclosure relates to a semiconductor memory module including a nonvolatile memory device. The semiconductor memory module includes: a data buffer that exchanges a first data signal with an external device; a nonvolatile memory device that is connected to the data buffer through a data line, respectively; and a controller that is connected to the data line. The controller receives an address, a command, and a control signal from the external device, and according to the address, the command, and the control signal, the controller controls the data buffer through a first control line and controls the nonvolatile memory device through a second control line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2018-0090797 filed on August 3, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the inventive concepts disclosed herein relate to semiconductor devices, and more particularly, to semiconductor memory modules including nonvolatile memory devices. Background Art

[0004] The computing system includes a processor, a main memory, and an auxiliary memory. The auxiliary memory can store data of an operating system installed on the computing system, data of an application, or data generated by the operating system or application. The auxiliary memory includes a hard disk drive, a solid-state drive, etc., and is accessed by the processor through a specific bus such as a peripheral component express interconnect (PCIe) bus.

[0005] The main memory is used to temporarily store data used by the processor among the data stored in the auxiliary memory. Typically, the main memory includes a memory that supports high-speed random access, such as synchronous dynamic random access memory (SDRAM). The main memory is manufactured to operate in accordance with standards such as dual in-line memory modules (DIMMs), registered DIMMs (RDIMMs), and load-reduced DIMMs (LRDIMMs).

[0006] The main memory manufactured in accordance with the standard is implemented in the form of a semiconductor memory package attached to a printed circuit board. The main memory manufactured in accordance with the standard is implemented to be attached to a computing system or can be easily removed from the computing system. For this reason, the main memory is called a "semiconductor memory module".

[0007] Nowadays, a main memory has been developed that has a large storage capacity while having a relatively low cost compared to SDRAM, has an operating speed close to that of SDRAM, and stores data in a non-volatile manner. Such a main memory includes a non-volatile memory device such as a phase change RAM (PRAM), a resistive RAM (RRAM), a magnetic RAM (MRAM), a ferroelectric RAM (FRAM), or a flash memory, and is referred to as a "storage class memory" (SCM).

[0008] Existing computing systems have been manufactured using main memory manufactured according to standards such as DIMM, RDIMM, and LRDIMM. Therefore, storage class memory is being developed to be consistent with standards such as DIMM, RDIMM, and LRDIMM so that storage class memory can be applied to existing computing systems without additional cost.

[0009] However, the standard of the existing main memory is determined in consideration of the operating characteristics of SDRAM and is inconsistent with the operating characteristics of the nonvolatile memory device. Therefore, a semiconductor memory module that includes a nonvolatile memory device and is consistent with the standard of the main memory is required. Summary of the invention

[0010] Embodiments of the inventive concept provide a semiconductor memory module having reduced cost and reduced noise while complying with the standards of a main memory.

[0011] According to an exemplary embodiment, a semiconductor memory module includes: a data buffer that exchanges a first data signal with an external device outside the semiconductor memory module; a nonvolatile memory device that is connected to the data buffer through a data line, respectively; and an internal memory module controller that is connected to the data line. The controller receives an address, a command, and a control signal from the external device; and according to the address, the command, and the control signal, the controller controls the data buffer through a first control line and controls the nonvolatile memory device through a second control line.

[0012] According to an exemplary embodiment that may include the above-described embodiments, a semiconductor memory module includes: a data buffer that exchanges data signals with an external device outside the semiconductor memory module; a first nonvolatile memory device that is connected to the data buffer through a data line, respectively; a second nonvolatile memory device that is connected to the data buffer through the data line, respectively; and a controller that is connected to the data line. The controller receives an address, a command, and a control signal from the external device, and according to the address, the command, and the control signal, the first nonvolatile memory device communicates with the controller and the data buffer through the data line, and the second nonvolatile memory device communicates directly with the data buffer through the data line.

[0013] According to an exemplary embodiment that may include the above-described embodiments, a semiconductor memory module includes: a data buffer that exchanges data signals with an external device outside the semiconductor memory module; a nonvolatile memory device that is connected to the data buffer through a data line, respectively; and a controller that is connected to the data line. The data line includes a first line extending from one side of the controller, a second line extending from the first line toward the data buffer, and a third line extending from the first line toward the nonvolatile memory device. The controller receives an address, a command, and a control signal from the external device, and according to the address, the command, and the control signal, the controller controls the data buffer through a first control line and controls the nonvolatile memory device through a second control line. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects and features of the present inventive concept will become apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the attached drawings.

[0015] Figure 1 is a block diagram illustrating a semiconductor memory module according to a first embodiment of the inventive concept.

[0016] Figure 2 is a flowchart illustrating an operating method of a semiconductor memory module according to some embodiments of the inventive concept.

[0017] Figure 3 is a diagram illustrating an example of adjusting an external selection signal and an internal selection signal.

[0018] Figure 4 is a flowchart illustrating an example of writing data from a memory controller to first to ninth nonvolatile memory devices through a controller.

[0019] Figure 5 is a diagram illustrating an example of transmitting a data signal from a memory controller to a controller.

[0020] Figure 6 is an example of Figure 5 The data signal is then further transmitted from the memory controller to a diagram of an example of a controller.

[0021] Figure 7 is an example of Figure 6 A diagram of an example in which the controller writes the data stored in the buffer to the first nonvolatile memory device when a flush condition is then satisfied.

[0022] Figure 8is a flowchart illustrating an example in which a memory controller reads data from a semiconductor memory module.

[0023] Fig. 9 is an example of Figure 7 A diagram of an example in which a memory controller then reads a data signal stored in a buffer.

[0024] Fig.10 is an example of Fig. 9 A diagram of an example in which a memory controller then reads a data signal that is not stored in a buffer.

[0025] Fig.11 is a flowchart illustrating an example of a controller managing a buffer.

[0026] Fig.12 is a flow chart illustrating an example in which the controller arbitrates communications through the first to ninth data lines.

[0027] Fig.13 is a diagram illustrating an example in which a memory controller directly accesses a first nonvolatile memory device through a first data line.

[0028] Fig.14 is a block diagram illustrating a semiconductor memory module according to a second embodiment of the inventive concept.

[0029] Fig.15 is a block diagram illustrating a semiconductor memory module according to a third embodiment of the inventive concept.

[0030] Fig.16 is a block diagram illustrating a semiconductor memory module according to a fourth embodiment of the inventive concept.

[0031] Fig.17 and Fig.18 is a diagram illustrating an example of adjusting an external selection signal and an internal selection signal.

[0032] Fig.19 is a block diagram illustrating a semiconductor memory module according to a fifth embodiment of the inventive concept. DETAILED DESCRIPTION

[0033] Figure 1 is a block diagram illustrating a semiconductor memory module 100 according to a first embodiment of the inventive concept. Figure 1, the semiconductor memory module 100 includes a controller 110, nonvolatile memory devices (NVM) 121 to 129, and data buffers (DB) 131 to 139. The controller 110, the nonvolatile memory devices 121 to 129, and the data buffers 131 to 139 may be implemented by different semiconductor packages, and these semiconductor packages may be mounted on a printed circuit board 101 to form the memory module 100. Each semiconductor package may include one or more semiconductor chips mounted on a package substrate and covered with a molding layer.

[0034] The controller 110 may receive an external address ADDRe, an external command CMDe, an external clock signal CKe, and an external selection signal Se from the external memory controller 10. The external address ADDRe may be received in the form of an address signal set, and the external command CMDe may be received in the form of a command signal set. The signals received by the controller 110 from the memory controller 10 are not limited to the above signals. The controller 110 may receive various signals (e.g., control signals) from the memory controller 10. The memory controller 10 may be outside the memory module 100, for example, as part of a host device, and not mounted on the printed circuit board 101. The controller 110 may be included in the memory module 100 as a part of the memory module 100, and may therefore be referred to herein as an internal memory module controller inside the memory module 100 (as opposed to an external memory controller such as the memory controller 10).

[0035] The controller 110 may be connected to the first to ninth nonvolatile memory devices 121 to 129 and the first to ninth data buffers 131 to 139 through the first to ninth data lines 141 to 149. For example, each of the first to ninth data lines 141 to 149 may include two or more (e.g., 8) lines transmitting the internal data signal DQi and at least one (e.g., 2) line transmitting the internal data strobe signal DQSi. Therefore, in some cases, each of the first to ninth data lines 141 to 149 may be referred to as a data line group.

[0036] The controller 110 may receive the internal data signal DQi and the internal data strobe signal DQSi from the first to ninth nonvolatile memory devices 121 to 129 or the first to ninth data buffers 131 to 139 through the first to ninth data lines 141 to 149. The controller 110 may latch the level of the internal data signal DQi in synchronization with the transition timing of the internal data strobe signal DQSi.

[0037] The controller 110 may transmit the internal data signal DQi and the internal data strobe signal DQSi to the first to ninth nonvolatile memory devices 121 to 129 or the first to ninth data buffers 131 to 139 through the first to ninth data lines 141 to 149. The controller 110 may generate the internal data strobe signal DQSi from the external clock signal CKe, and may adjust the level of the internal data signal DQi in synchronization with the transition timing of the internal data strobe signal DQSi.

[0038] The controller 110 may send an internal address ADDRi, an internal command CMDi, an internal clock signal CKi, and an internal selection signal Si to the first non-volatile memory device 121 to the ninth non-volatile memory device 129 through the first control lines 151 and 152 in response to an external address ADDRe, an external command CMDe, an external clock signal CKe, and an external selection signal Se. The internal address ADDRi may be sent in the form of an address signal set, and the internal command CMDi may be sent in the form of a command signal set. It should be noted that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. Unless otherwise indicated by the context, these terms are only used to distinguish one element, component, region, or part from another element, component, region, or part, for example, as a naming convention. Therefore, a first element, component, region, or part discussed in one part of the specification below may be referred to as a second element, component, region, or part in another part of the specification or in the claims without departing from the teachings of the present invention. In addition, in some cases, even if a term “first”, “second”, etc. is not used to describe a certain term in the specification, it can still be referred to as “first” or “second” in the claims in order to distinguish the claimed elements from each other.

[0039] The signals transmitted by the controller 110 to the first to ninth nonvolatile memory devices 121 to 129 are not limited to the above-mentioned signals. The controller 110 may transmit various signals (e.g., control signals) including the internal selection signal Si to the first to ninth nonvolatile memory devices 121 to 129. The signals transmitted by the controller 110 to the first to ninth nonvolatile memory devices 121 to 129 may be the same as or similar to the signals received by the controller 110 from the memory controller 10.

[0040] The controller 110 may allow the first to ninth nonvolatile memory devices 121 to 129 to receive and write the internal data signals DQi transmitted through the first to ninth data lines 141 to 149 by using the internal command CMDi and the internal selection signal Si. The controller 110 may specify the location of a storage space in which each of the first to ninth nonvolatile memory devices 121 to 129 stores the internal data signals DQi by using the internal address ADDRi.

[0041] In addition, by using the internal command CMDi and the internal selection signal Si, the controller 110 may allow the first to ninth nonvolatile memory devices 121 to 129 to read the stored data and transmit the read data as the internal data signal Dqi through the first to ninth data lines 141 to 149. The controller 110 may specify the location of the storage space from which data is to be read by each of the first to ninth nonvolatile memory devices 121 to 129 by using the internal address ADDRi.

[0042] The controller 110 may control the first to ninth data buffers 131 to 139 in response to the external command CMDe and the external selection signal Se. The controller 110 may send a common buffering command BCOM to the first to ninth data buffers 131 to 139 through the second control lines 161 and 162. The buffering command BCOM may be implemented by a combination of buffering command signals.

[0043] The first to ninth nonvolatile memory devices 121 to 129 may receive and write the internal data signal DQi from the first to ninth data lines 141 to 149 in response to the internal command CMDi, the internal address ADDRi, and the internal selection signal Si. Each data buffer 131 in the first to ninth nonvolatile memory devices 121 to 129 may latch the level of the internal data signal DQi in synchronization with the transition timing of the internal data strobe signal DQSi.

[0044] The first to ninth nonvolatile memory devices 121 to 129 may read data written therein in response to an internal command CMDi, an internal address ADDRi, and an internal selection signal Si, and may transmit the read data to the first to ninth data lines 141 to 149 as internal data signals DQi.

[0045] Each of the first to ninth nonvolatile memory devices 121 to 129 may generate an internal data strobe signal DQSi from the internal clock signal CKi, and may adjust a level of the internal data signal DQi in synchronization with a transition timing of the internal data strobe signal DQSi.

[0046] The first to ninth data buffers 131 to 139 may operate in response to a buffering command BCOM. When the buffering command BCOM indicates a read operation, the first to ninth data buffers 131 to 139 may transmit internal data signals DQi and internal data strobe signals DQSi transmitted through the first to ninth data lines 141 to 149 as external data signals DQe and external data strobe signals DQSe to the memory controller 10.

[0047] When the buffering command BCOM indicates a write operation, the first to ninth data buffers 131 to 139 may send the external data signal DQe and the external data select signal DQSe transmitted from the memory controller 10 to the first to ninth data lines 141 to 149 as the internal data signal DQi and the internal data select signal DQSi.

[0048] like Figure 1 As shown in , the controller 110 , the first to ninth nonvolatile memory devices 121 to 129 , and the first to ninth data buffers 131 to 139 may be commonly connected to the first to ninth data lines 141 to 149 .

[0049] In this case, compared with the case where the connection between the first to ninth nonvolatile memory devices 121 to 129 and the controller 110 and the connection between the first to ninth data buffers 131 to 139 and the controller 110 are realized by using different data lines, the number of wirings required for the semiconductor memory module 100 and the complexity of the wiring arrangement can be reduced. Therefore, the manufacturing cost of the semiconductor memory module 100 is reduced.

[0050] In addition, compared with the case where the connection between the first to ninth nonvolatile memory devices 121 to 129 and the controller 110 and the connection between the first to ninth data buffers 131 to 139 and the controller 110 are implemented by using different data lines, the distance between the wirings is increased, and thus the interference between the wirings is reduced. Therefore, the noise generated due to the interference at the semiconductor memory module 100 is reduced.

[0051] The controller 110 may include a physical block (PHY) 111 that supports common communication with the first to ninth nonvolatile memory devices 121 to 129 and the first to ninth data buffers 131 to 139 through the first to ninth data lines 141 to 149 (e.g., through the same set of switches, drivers, and other circuits of the physical block 111). The physical block 111 may exchange internal data signals DQi and internal data strobe signals DQSi with the first to ninth data lines 141 to 149.

[0052] The physical block 111 may transmit or receive the internal data signal DQi and the internal data strobe signal DQSi in the same manner when communicating with the first to ninth nonvolatile memory devices 121 to 129 and when communicating with the first to ninth data buffers 131 to 139 .

[0053] The physical block 111 may receive an external address ADDRe, an external command CMDe, an external clock signal CKe, and an external selection signal Se from the memory controller 10. The physical block 111 may generate an internal address ADDRi, an internal command CMDi, an internal clock signal CKi, and an internal selection signal Si from the external address ADDRe, the external command CMDe, the external clock signal CKe, and the external selection signal Se.

[0054] When all storage spaces of the first to ninth nonvolatile memory devices 121 to 129 are configured to be accessed by the memory controller 10 , the physical block 111 may directly output the external address ADDRe as the internal address ADDRi through the first control lines 151 and 152 .

[0055] When some storage space of the first to ninth nonvolatile memory devices 121 to 129 is accessed by the memory controller 10 and the remaining storage space is used as a meta region of the semiconductor memory module 100, the physical block 111 can convert the external address ADDRe into the internal address ADDRi, and the internal address ADDRi can be output through the first control lines 151 and 152.

[0056] The physical block 111 may directly transmit the external command CMDe transmitted from the memory controller 10 as the internal command CMDi through the first control lines 151 and 152. The physical block 111 may directly transmit the external clock signal CKe as the internal clock signal Cki through the first control lines 151 and 152.

[0057] The physical block 111 may directly transmit the external selection signal Se as the internal selection signal Si through the first control lines 151 and 152, or may convert the external selection signal Se into the internal selection signal Si and may transmit the internal selection signal Si through the first control lines 151 and 152. The physical block 111 may transmit the buffering command BCOM to the first to ninth data buffers 131 to 139 through the second control lines 161 and 162. The physical block 111 may include an interface (e.g., an interface circuit) of the controller 110, and may include, for example, various switches and drivers for routing communications between the memory controller 10, the controller 110, the nonvolatile memory devices 121 to 129, and the data buffers 131-139.

[0058] Since the controller 110, the first to ninth nonvolatile memory devices 121 to 129, and the first to ninth data buffers 131 to 139 commonly use the first to ninth data lines 141 to 149, arbitration is required as to whether any of the first entity (e.g., the controller 110), the second entity (e.g., the first to ninth nonvolatile memory devices 121 to 129), and the third entity (e.g., the first to ninth data buffers 131 to 139) performs communication.

[0059] For example, if a third entity performs communication when the first entity and the second entity perform communication, a conflict may occur. The controller 110 may perform arbitration to prevent the conflict from occurring. When performing arbitration, the timing at which the physical block 111 receives the external address ADDRe, the external command CMDe, the external clock signal CKe, and the external selection signal Se from the memory controller 10 may be different from the timing at which the physical block 111 sends the internal address ADDRi, the internal command CMDi, the internal clock signal CKi, and the internal selection signal Si to the first to ninth nonvolatile memory devices 121 to 129.

[0060] In the case where the controller 110 uses different wirings when communicating with the first to ninth nonvolatile memory devices 121 to 129 and when communicating with the first to ninth data buffers 131 to 139, different physical blocks corresponding to the different wirings may be required. Figure 1 As illustrated, in the case where one physical block 111 is provided in the controller 110, the complexity and manufacturing cost of the controller 110 are reduced. Therefore, the complexity and manufacturing cost of the semiconductor memory module 100 are reduced.

[0061] The controller 110 may further include a buffer 112. The controller 110 may store the internal data signal DQi transmitted from the first to ninth nonvolatile memory devices 121 to 129 in the buffer 112. The controller 110 may read the data stored in the buffer 112, and may transmit the read data to the first to ninth data buffers 131 to 139 as the internal data signal DQi.

[0062] Similarly, the controller 110 may store the internal data signals DQi transmitted from the first to ninth data buffers 131 to 139 in the buffer 112. The controller 110 may read the data stored in the buffer 112, and may transmit the read data as the internal data signals DQi to the first to ninth nonvolatile memory devices 121 to 129.

[0063] The controller 110 may store information about the external address ADDRe, the external command CMDe, and the external selection signal Se received from the memory controller 10 in the buffer 112. The controller 110 may generate the internal address ADDRi, the internal command CMDi, and the internal selection signal Si based on the information stored in the buffer 112.

[0064] Figure 2 1 is a flowchart illustrating an operating method of the semiconductor memory module 100 according to an embodiment of the inventive concept. Figure 1 and Figure 2 In operation S110, the controller 110 may receive an internal data signal DQi from an external device (eg, a memory controller 10) through first to ninth data buffers 131 to 139 and common first to ninth data lines 141 to 149 (hereinafter referred to as “common data lines”).

[0065] In operation S120 , the controller 110 may transmit the internal data signal DQi to the first to ninth nonvolatile memory devices 121 to 129 through the common data lines 141 to 149 .

[0066] In operation S130 , the controller 110 may receive the internal data signals DQi from the first to ninth nonvolatile memory devices 121 to 129 through the common data lines 141 to 149 .

[0067] In operation S140 , the controller 110 may transmit the internal data signal DQi to an external device (eg, the memory controller 10 ) through the common data lines 141 to 149 and the first to ninth data buffers 131 to 139 .

[0068] Figure 3 is a diagram illustrating an example of adjusting the external selection signal Se and the internal selection signal Si. Figure 1 and Figure 3 , the external selection signal Se may include a first external selection signal Se1 and a second external selection signal Se2. The first external selection signal Se1 may be activated (e.g., to a low level) by the memory controller 10 so as to enable or configure the memory controller 10 to access the first to ninth nonvolatile memory devices 121 to 129 through the controller 110.

[0069] The second external selection signal Se2 can be activated by the memory controller 10 (e.g., to a low level) to enable the memory controller 10 or set the memory controller 10 to access the first to ninth nonvolatile memory devices 121 to 129 without passing through the controller 110 (e.g., bypassing the controller 110).

[0070] The internal selection signal Si may include a first internal selection signal Si1 and a second internal selection signal Si2. The first internal selection signal Si1 may be activated (eg, to a low level) by the controller 110 to enable or configure the controller 110 to access the first to ninth nonvolatile memory devices 121 to 129.

[0071] The second internal selection signal Si2 may be activated (e.g., to a low level) by the controller 110 so as to cause or configure the controller 110 to limit communication with the first to ninth nonvolatile memory devices 121 to 129. In one embodiment, the second internal selection signal Si2 may be omitted. Communication with the first to ninth nonvolatile memory devices 121 to 129 may be limited by deactivating the first internal selection signal Si1 (e.g., to a high level) instead of by the second internal selection signal Si2.

[0072] In the first part or the first time period, the memory controller 10 and the controller 110 may communicate with each other through the first to ninth data buffers 131 to 139 and the first to ninth data lines 141 to 149. For example, communication between the memory controller 10 and the controller 110 may be established to allow the memory controller 10 to write data to or read data from the first to ninth nonvolatile memory devices 121 to 129 through the controller 110.

[0073] In the example of a write operation, the memory controller 10 may send an external address ADDRe and an external command CMDe indicating a write operation to the controller 110. In addition, the memory controller 10 may activate a first external selection signal Se1 for providing a notification that the first to ninth nonvolatile memory devices 121 to 129 are targets of the write operation. The memory controller 10 may deactivate a second external selection signal Se2 for providing a notification that a write operation is performed by the controller 110.

[0074] When the external command CMDe indicates a write operation, the controller 110 may send a write command WR as a buffer command BCOM to the first to ninth data buffers 131 to 139. The controller 110 may receive write data from the memory controller 10 through the first to ninth data buffers 131 to 139 and the first to ninth data lines 141 to 149 in the form of internal data signals DQi.

[0075] In order to prevent the first to ninth nonvolatile memory devices 121 to 129 from colliding at the first to ninth data lines 141 to 149, the controller 110 may deactivate the first internal selection signal Si1 and may activate the second internal selection signal Si2. In an example of a read operation, the memory controller 10 may send an external address ADDRe and an external command CMDe indicating a read operation to the controller 110. The memory controller 10 may activate the first external selection signal Se1 and may deactivate the second external selection signal Se2.

[0076] When the external command CMDe indicates a read operation, the controller 110 may send a read command RD as a buffer command BCOM to the first to ninth data buffers 131 to 139. In one embodiment, the data requested by the memory controller 10 may have been stored in the buffer 112 of the controller 110.

[0077] The controller 110 may transmit the requested data to the memory controller 10 in the form of the internal data signal DQi through the first to ninth data lines 141 to 149 and the first to ninth data buffers 131 to 139. To prevent a conflict, the controller 110 may deactivate the first internal selection signal Si1 and may activate the second internal selection signal Si2.

[0078] In the first section, the first to ninth data buffers 131 to 139 may exchange internal data signals DQi with the controller 110 through the first to ninth data lines 141 to 149. The first to ninth nonvolatile memory devices 121 to 129 may ignore the internal data signals DQi transmitted through the first to ninth data lines 141 to 149 (e.g., based on the first and second internal selection signals Si1 and Si2 in response to the first and second external selection signals Se1 and Se2) and may not transmit any signals to the first to ninth data lines 141 to 149.

[0079] In the second portion or the second period, the controller 110 and the first to ninth nonvolatile memory devices 121 to 129 may communicate with each other through the first to ninth data lines 141 to 149 .

[0080] For example, when data stored in the buffer 112 is written to the first to ninth nonvolatile memory devices 121 to 129 through the memory controller 10, or when data requested by the memory controller 10 is read from the first to ninth nonvolatile memory devices 121 to 129, communication can be performed between the controller 110 and the first to ninth nonvolatile memory devices 121 to 129.

[0081] The second part is associated with the communication performed within the semiconductor memory module 100 and is not associated with the memory controller 10. Therefore, the first external selection signal Se1 and the second external selection signal Se2 may be in a deactivated state (e.g., a high level). The controller 110 may send an internal address ADDRi and an internal command CMDi indicating a read or write operation to the first to ninth nonvolatile memory devices 121 to 129.

[0082] In order to provide a notification that the first nonvolatile memory device 121 to the ninth nonvolatile memory device 129 are communication targets, the controller 110 may activate the first internal selection signal Si1 (to a low level) and may deactivate the second internal selection signal Si2 (to a high level). Since the first data buffer 131 to the ninth data buffer 139 are not associated with the second part, the controller 110 may not send the buffering command BCOM.

[0083] The controller 110 may transmit or receive data to or from the first to ninth nonvolatile memory devices 121 to 129 through the first to ninth data lines 141 to 149 in the form of internal data signals DQi.

[0084] In the second part, the first to ninth nonvolatile memory devices 121 to 129 may exchange internal data signals DQi with the controller 110 through the first to ninth data lines 141 to 149. The first to ninth data buffers 131 to 139 may ignore (e.g., based on the buffering command BCOM in response to the first and second external selection signals Se1 and Se2) the internal data signals DQi transmitted through the first to ninth data lines 141 to 149 and may not transmit any signal to the first to ninth data lines 141 to 149.

[0085] In the third section, the memory controller 10 and the first to ninth nonvolatile memory devices 121 to 129 may communicate with each other through the first to ninth data buffers 131 to 139 and the first to ninth data lines 141 to 149 .

[0086] For example, communication may be performed between the memory controller 10 and the first to ninth nonvolatile memory devices 121 to 129 so that the memory controller 10 or the memory controller 10 is configured to directly write data to the first to ninth nonvolatile memory devices 121 to 129, or so that the memory controller 10 or the memory controller 10 is configured to directly read data from the first to ninth nonvolatile memory devices 121 to 129.

[0087] The memory controller 10 may send an external address ADDRe and an external command CMDe indicating a write or read operation to the controller 110. The controller 110 may convert the external address ADDRe and the external command CMDe into an internal address ADDRi and an internal command CMDi and send the internal address ADDRi and the internal command CMDi to the first to ninth nonvolatile memory devices 121 to 129, or may send the external address ADDRe and the external command CMDe as the internal address ADDRi and the internal command CMDi to the first to ninth nonvolatile memory devices 121 to 129 without conversion.

[0088] In addition, the memory controller 10 may activate the first external selection signal Se1 (to a low level) to provide a notification that the first to ninth nonvolatile memory devices 121 to 129 are access targets. The memory controller 10 may activate the second external selection signal Se2 (to a low level) to provide a notification that access is performed without passing through the controller 110.

[0089] According to the external command CMDe, the controller 110 may send a write command WR or a read command RD as a buffer command BCOM to the first to ninth data buffers 131 to 139. The first to ninth nonvolatile memory devices 121 to 129 may exchange data with the memory controller 10 through the first to ninth data lines 141 to 149 in the form of internal data signals DQi.

[0090] In order to prevent conflicts from occurring at the first data lines 141 to the ninth data lines 149, the controller 110 may ignore (for example, based on the first external selection signal Se1 and the second external selection signal Se2) the internal data signals DQi transmitted through the first data lines 141 to the ninth data lines 149, and may not send any signals to the first data lines 141 to the ninth data lines 149.

[0091] In the third section, the first to ninth data buffers 131 to 139 may exchange internal data signals DQi with the first to ninth nonvolatile memory devices 121 to 129 through the first to ninth data lines 141 to 149. The controller 110 may ignore the internal data signals DQi transmitted through the first to ninth data lines 141 to 149 and may not transmit any signal to the first to ninth data lines 141 to 149.

[0092] In some embodiments, the memory controller 10 may be prohibited from directly accessing the first to ninth nonvolatile memory devices 121 to 129 without going through the controller 110. In this case, the second external selection signal Se2 may be omitted.

[0093] Figure 4 1 is a flowchart illustrating an example of writing data from the memory controller 10 to the first to ninth nonvolatile memory devices 121 to 129 through the controller 110. Figure 1 and Figure 4 , in operation S210 , the controller 110 may receive an address ADDR, a command CMD, and a data signal DQ from the memory controller 10 .

[0094] For example, the controller 110 receives an external address ADDRe, an external command CMDe, and an external selection signal Se from the memory controller 10. The first to ninth data buffers 131 to 139 may transmit the external data signal DQe received from the memory controller 10 to the controller 110 as the internal data signal Dqi.

[0095] In operation S220, the controller 110 stores the external address ADDRe and the external command CMDe (e.g., a write command) received from the memory controller 10 and the internal data signal DQi received through the first to ninth data buffers 131 to 139 in the buffer 112. For example, the controller 110 may store the external address ADDRe and the external command CMDe or information about the external address ADDRe and the external command CMDe in the buffer 112.

[0096] The controller 110 may complete the first operation according to the external command CMDe (write command in operation S210) of the memory controller 10 by storing the external address ADDRe, the external command CMDe, and the internal data signal DQi (operation S220). The controller 110 may perform a second operation (e.g., a flush operation) of storing the internal data signal DQi stored in the buffer 112 in the first to ninth nonvolatile memory devices 121 to 129 without intervention of the memory controller 10. For example, the controller 110 may support a write-back operation.

[0097] In operation S230, the controller 110 determines whether a dump-clearing condition is satisfied. For example, the dump-clearing condition may be satisfied when a dump-clearing command as an external command CMDe is received from the memory controller 10. For another example, the dump-clearing condition may be satisfied when an idle time during which the memory controller 10 does not access the semiconductor memory module 100 is not less than a threshold value.

[0098] When the dump-clearing condition is not satisfied, the dump-clearing operation is not performed, and the process is terminated. When the dump-clearing condition is satisfied, operation S240 is performed. In operation S240, the controller 110 sends the internal address ADDRi, the internal command CMDi, the internal data signal DQi, and the internal selection signal Si stored in the buffer 112 to the first to ninth nonvolatile memory devices 121 to 129.

[0099] In operation S250, the first to ninth nonvolatile memory devices 121 to 129 perform a write operation according to the internal address ADDRi, the internal command CMDi, the internal data signal DQi, and the internal selection signal Si from the controller 110. Therefore, the data requested to be written by the memory controller 10 can be finally written to the first to ninth nonvolatile memory devices 121 to 129.

[0100] As described above, the controller 110 may refer to the flush condition to prevent the communication between the memory controller 10 and the controller 110 from conflicting with the communication between the controller 110 and the first to ninth nonvolatile memory devices 121 to 129 .

[0101] Figure 5 is a diagram illustrating an example of transmitting a data signal DQ from the memory controller 10 to the controller 110. In one embodiment, the remaining components except the memory controller 10, the controller 110, and the first nonvolatile memory device 121 are omitted. The second to ninth nonvolatile memory devices 122 to 129 may operate simultaneously with the first nonvolatile memory device 121. The external data signal DQe and the internal data signal DQi may be commonly referenced as the data signal DQ.

[0102] Reference Figure 5 In operation S311, the memory controller 10 may send an external address ADDRe and an external command CMDe to the controller 110, and may Figure 3 The external selection signal Se is controlled as in the first part of the external command CMDe. The external command CMDe may be a write command. In operation S312, the memory controller 10 may send a data signal DQ to the controller 110 through the first data line 141. The controller 110 may receive the external address ADDRe, the external command CMDe, the external selection signal Se, and the data signal DQ by using the physical block 111.

[0103] In operation S313, the controller 110 may store the external address ADDRe and the data signal DQ received from the memory controller 10 as the first data entity DQ_ET1 in the first area 113 of the buffer 112. In operation S314, the controller 110 may store the first write pointer W_PTR1 pointing to the first data entity DQ_ET1 in the second area 114 of the buffer 112.

[0104] The first write pointer W_PTR1 may include information indicating that a write operation is performed or information about the location of the first region 113 where the first data entity DQ_ET1 is stored. For example, the first write pointer W_PTR1 may be used as a dirty flag indicating that any data entity stored in the first region 113 may be written to the first to ninth nonvolatile memory devices 121 to 129.

[0105] Figure 6 is an example of Figure 5 The data signal DQ is then further transmitted from the memory controller 10 to the controller 110. Figure 6 In operation S315, the memory controller 10 may send an external address ADDRe and an external command CMDe (eg, a write command) to the controller 110, and may be like Figure 3 The external selection signal Se is controlled as in the first part.

[0106] In operation S316, the memory controller 10 may transmit the data signal DQ to the controller 110 through the first data line 141. In operation S317, the controller 110 may store the external address ADDRe and the data signal DQ received from the memory controller 10 as the second data entity DQ_ET2 in the first area 113. In operation S318, the controller 110 may store the second write pointer W_PTR2 pointing to the second data entity DQ_ET2 in the second area 114.

[0107] In one embodiment, when the external address ADDRe of the second data entity DQ_ET2 is the same as the external address ADDRe of the first data entity DQ_ET1, the controller 110 may replace the first data entity DQ_ET1 with the second data entity DQ_ET2. Also, the controller 110 may replace the first write pointer W_PTR1 with the second write pointer W_PTR2.

[0108] Figure 7 is an example of Figure 6 A diagram of an example in which the controller 110 writes the data stored in the buffer 112 to the first nonvolatile memory device 121 when the flush condition is satisfied. Figure 7 , in operation S321 , the controller 110 reads the oldest first write pointer W_PTR1 from the write pointers stored in the second area 114 of the buffer 112 .

[0109] In operation S322, the controller 110 reads the first data entity DQ_ET1 according to the first write pointer W_PTR1 thus read. The controller 110 may generate an internal address ADDRi from an external address ADDRe of the first data entity DQ_ET1. The controller 110 may generate an internal command CMDi (eg, a write command) from the first write pointer W_PTR1.

[0110] In operation S323, the controller 110 transmits an internal address ADDRi and an internal command CMDi to the first nonvolatile memory device 121 through the first data line 141 by using the physical block 111, and may be like Figure 3 The controller 110 transmits the data signal DQ to the first nonvolatile memory device 121 through the first data line 141 by using the physical block 111 in operation S324 .

[0111] Similarly, in operation S325, the controller 110 reads the second write pointer W_PTR2 from the second area 114; in operation S326, the controller 110 reads the second data entity DQ_ET2 from the first area 113. In operation S327, the controller 110 sends the internal address ADDRi and the internal command CMDi to the first nonvolatile memory device 121 through the first data line 141 by using the physical block 111, which can be like Figure 3 The internal selection signal Si is controlled as in the second part of the embodiment, and the data signal DQ is transmitted in operation S328.

[0112] The first nonvolatile memory device 121 may write the data signal DQ of the first data entity DQ_ET1 according to operation S323 , and may write the data signal DQ of the second data entity DQ_ET2 according to operation S327 .

[0113] In one embodiment, the controller 110 may remove the corresponding write pointer of the second region 114 after writing the data signal DQ of the specific data entity to the first nonvolatile memory device 121. The controller 110 may write the data signal DQ of the specific data entity to the first nonvolatile memory device 121, and then may keep the specific data entity in the first region 113 or may remove the specific data entity from the first region 113.

[0114] Figure 8 1 is a flowchart illustrating an example in which the memory controller 10 reads data from the semiconductor memory module 100. Figure 1 and Figure 8 , in operation S410 , the controller 110 receives an external address ADDRe, an external command CMDe (eg, a read command), and an activated external selection signal Se from the memory controller 10 .

[0115] In operation S420, the controller 110 determines whether a data signal DQ corresponding to the external address ADDRe exists in the buffer 112. In the case where the data signal DQ corresponding to the external address ADDRe exists in the buffer 112, in operation S480, the controller 110 transmits the data signal DQ stored in the buffer 112 to the memory controller 10. Then, the read process may be terminated.

[0116] In the case where the data signal DQ corresponding to the external address ADDRe does not exist in the buffer 112, operation S430 is performed. In operation S430, the controller 110 may notify the memory controller 10 that a backup read operation is required. For example, the controller 110 may notify the memory controller 10 that a backup read operation is required by activating an error signal, deactivating a ready signal, or outputting a dummy data signal with an error.

[0117] The backup read operation may indicate a read operation of reading data requested by the memory controller 10 from the first to ninth nonvolatile memory devices 121 to 129 and storing the read data to the buffer 112 of the controller 110 .

[0118] In operation S440 , the controller 110 transmits an internal address ADDRi corresponding to an external address ADDRe, an internal command CMDi (eg, a read command), and an activated internal selection signal Si to the first to ninth nonvolatile memory devices 121 to 129 .

[0119] In operation S450 , the controller 110 receives data signals DQ corresponding to the internal addresses ADDRi from the first to ninth nonvolatile memory devices 121 to 129 and may store the received data signals DQ to the buffer 112 .

[0120] In operation S460, the controller 110 notifies the memory controller 10 that the backup read operation is completed. For example, the controller 110 may notify the memory controller 10 that the backup read operation is completed by deactivating an error signal, activating a ready signal, or stopping outputting a dummy data signal having an error.

[0121] In operation S470, the controller 110 receives an external address ADDRe, an external command CMDe, and an activated external selection signal Se from the memory controller 10. Operation S470 may correspond to a retry of operation S410. Therefore, the information received in operation S470 may be the same as the information received in operation S410. In operation S480, the controller 110 may transmit the data signal DQ stored in the buffer 112 to the memory controller 10. Thereafter, the read process may be terminated.

[0122] In one embodiment, in response to the notification of operation S430, the memory controller 10 may periodically repeat operation S470 (or operation S410) of requesting a read operation from the controller 110. By repeating operation S430, the controller 110 may provide a notification that the data is not ready. In this case, operation S460 may be omitted. When the controller 110 does not perform the notification of operation S430, the memory controller 10 may successfully read data from the semiconductor memory module 100 through operation S480.

[0123] As described above, the controller 110 may inform the memory controller 10 that a backup read operation is required to prevent communication between the memory controller 10 and the controller 110 from conflicting with communication between the controller 110 and the first to ninth nonvolatile memory devices 121 to 129 .

[0124] Fig. 9 is an example of Figure 7 The memory controller 10 then reads the data signal DQ stored in the buffer 112. Fig. 9 In operation S511, the memory controller 10 sends an external address ADDRe and an external command CMDe (eg, a read command) to the controller 110, and may be like Figure 3 The external selection signal Se is controlled as in the first part.

[0125] In response to the external command CMDe, the controller 110 determines whether a data entity corresponding to the external address ADDRe exists in the first area 113 of the buffer 112. For example, the external address ADDRe received from the memory controller 10 may coincide with the external address ADDRe of the second data entity DQ_ET2.

[0126] In operation S512, the controller 110 reads the data signal DQ of the second data entity DQ_ET2 stored in the first area 113. In operation S513, the controller 110 transmits the data signal DQ read from the first area 113 to the memory controller 10 through the first data line 141.

[0127] Fig.10 is an example of Fig. 9 The memory controller 10 then reads the data signal DQ that is not stored in the buffer 112. Fig.10 In operation S514, the memory controller 10 may send an external address ADDRe and an external command CMDe (eg, a read command) to the controller 110, and may be like Figure 3 The external selection signal Se is controlled as in the first part.

[0128] The controller 110 may determine that a data entity corresponding to the external address ADDRe received from the memory controller 10 is not stored in the buffer 112. The controller 110 may inform the memory controller 10 that a backup read operation is required.

[0129] In operation S515, the controller 110 sends an internal address ADDRi, an internal command CMDi (eg, a read command), and a first nonvolatile memory device 121. Figure 3 The first nonvolatile memory device 121 may read data according to the internal address ADDRi, the internal command CMDi, and the activated internal selection signal Si.

[0130] In operation S516, the first nonvolatile memory device 121 transmits the read data as a data signal DQ to the controller 110 through the first data line 141. In operation S517, the controller 110 stores the external address ADDRe received from the memory controller 10 and the data signal DQ received from the first nonvolatile memory device 121 as a third data entity DQ_ET3 to the first area 113 of the buffer 112.

[0131] When the third data entity DQ_ET3 is stored in the first area 113, the controller 110 may notify the memory controller 10 that the backup read operation is completed. When the backup read operation is completed, in operation S518, the memory controller 10 sends an external address ADDRe and an external command CMDe to the controller 110, and may Figure 3 The external selection signal Se is controlled as in the first part.

[0132] In operation S519, the controller 110 reads the data signal DQ of the third data entity DQ_ET3 of the first area 113. In operation S520, the controller 110 transmits the data signal DQ read from the first area 113 to the memory controller 10 through the first data line 141.

[0133] Fig.11 is a flowchart illustrating an example of a method in which the controller 110 manages the buffer 112. Figure 1 and Fig.11 , in operation S610 , the controller 110 monitors the storage capacity of the buffer 112 .

[0134] In operation S620, the controller 110 determines whether the free storage capacity of the buffer 112 is less than the threshold value according to the monitoring result. If the free storage capacity of the buffer 112 is not less than the threshold value, the process is terminated. If the free storage capacity of the buffer 112 is less than the threshold value, operation S630 is performed.

[0135] In operation S630, the controller 110 may discard the least recently used (LRU) data signal DQ among the data signals DQ stored in the buffer 112. For example, the controller 110 may discard the clean data signal DQ that does not need to be written to the first to ninth nonvolatile memory devices 121 to 129.

[0136] As another example, the controller 110 may write the dirty data signal DQ that should be written into the first to ninth nonvolatile memory devices 121 to 129 into the first to ninth nonvolatile memory devices 121 to 129 (refer to Figure 7 ), and the corresponding data signal DQ can be discarded.

[0137] For example, the controller 110 may be configured to discard the oldest used data signal DQ first or to discard the clean data signal DQ first. The priority of data that the controller 110 may discard may be set by the memory controller 10 .

[0138] Fig.12 1 is a flowchart illustrating an example in which the controller 110 arbitrates communication through the first to ninth data lines 141 to 149. Figure 1 and 12 In operation S710, the controller 110 receives an external command CMDe or an external selection signal Se from the memory controller 10. For example, the arbitration method according to an embodiment of the inventive concept may be triggered by the external command CMDe or the external selection signal Se.

[0139] In operation S720, the controller 110 determines whether communication with the first to ninth nonvolatile memory devices 121 to 129 is being performed (e.g., to be performed). When the controller 110 is not communicating with the first to ninth nonvolatile memory devices 121 to 129, the controller 110 may perform access associated with the external command CMDe (refer to Figure 5 , Figure 6 , Fig. 9 , Fig.10 or Fig.13 ). Afterwards, terminate the process.

[0140] If the controller 110 is communicating with the first to ninth nonvolatile memory devices 121 to 129, in operation S740, the controller 110 may transmit (e.g., activate) a stop signal to the first to ninth nonvolatile memory devices 121 to 129. According to the stop signal, the first to ninth nonvolatile memory devices 121 to 129 may stop exchanging the internal data signals DQi with the first to ninth data lines 141 to 149. Then, the controller 110 may perform access associated with the external command CMDe.

[0141] In operation S750, after performing the access associated with the external command CMDe, the controller 110 may retry the operation stopped by the stop signal. For example, the controller 110 may request the first to ninth nonvolatile memory devices 121 to 129 to resume the stopped operation. For another example, the controller 110 may request to restart the stopped operation from the beginning again through the internal address ADDRi, the internal command CMDi, and the internal selection signal Si.

[0142] Fig.131 is a diagram illustrating an example in which the memory controller 10 directly accesses the first nonvolatile memory device 121 through the first data line 141. Fig.13 In operation S811, the memory controller 10 sends an external address ADDRe and an external command CMDe (eg, a write command) to the controller 110, and may be like Figure 3 The external selection signal Se is controlled like the third part.

[0143] The physical block 111 of the controller 110 may generate an internal address ADDRi and an internal command CMDi from an external address ADDRe and an external command CMDe. In operation S812, the controller 110 transmits the internal address ADDRi, the internal command CMDi and the external command CMDe to the first nonvolatile memory device 121. Figure 3 In operation S813, the memory controller 10 directly transmits the data signal DQ to the first nonvolatile memory device 121 through the first data line 141 (eg, without the data passing through the controller 110). For example, the data signal DQ may pass through the data buffer 131 without being stored in the controller.

[0144] In operation S814, the memory controller 10 sends an external address ADDRe and an external command CMDe (eg, a read command) to the controller 110, and may Figure 3 The physical block 111 of the controller 110 may generate an internal address ADDRi and an internal command CMDi from an external address ADDRe and an external command CMDe.

[0145] In operation S815, the controller 110 sends an internal address ADDRi, an internal command CMDi, and a first nonvolatile memory device 121. Figure 3 In operation S816, the memory controller 10 receives the data signal DQ directly from the first nonvolatile memory device 121 through the first data line 141 (eg, without data passing through the controller 110).

[0146] Fig.14 1 is a block diagram illustrating a semiconductor memory module 100_1 according to a second embodiment of the inventive concept. Components of the semiconductor memory module 100_1 are similar to those of the first to ninth data lines 141a to 149a. Figure 1 Therefore, additional description will be omitted to avoid redundancy.

[0147] Reference Fig.14, the first to ninth data lines 141a to 149a may include first lines extending from opposite sides of the controller 110, second lines connecting the first lines and the first to ninth nonvolatile memory devices 121 to 129, and third lines connecting the first lines and the first to ninth data buffers 131 to 139. The second lines and the third lines may be implemented as reference lines. Figure 1 The first line may have the same length regardless of the position of the first node connected to the second line or the position of the second node connected to the third line.

[0148] The loads of the first to ninth data lines 141a to 149a from the controller 110 may become balanced. The loads of the first to ninth data lines 141a to 149a from the first nonvolatile memory device 121 to the ninth nonvolatile memory device 129 may become balanced. Moreover, the loads of the first to ninth data lines 141a to 149a from the first data buffer 131 to the ninth data buffer 139 may become balanced. Therefore, the transmission timing of the internal data signal DQi may be balanced. Therefore, hysteresis may be prevented.

[0149] Fig.15 1 is a block diagram illustrating a semiconductor memory module 100_2 according to a third embodiment of the inventive concept. Components of the semiconductor memory module 100_2 are similar to those of the first to ninth data lines 141 b to 149 b. Figure 1 Therefore, additional description will be omitted to avoid redundancy.

[0150] Reference Fig.15 , the first lines of the first to ninth data lines 141b to 149b may have different lengths. The positions of the first node and the second node may be adjusted to make the loads of the first to ninth data lines 141b to 149b more similar. For example, the data line 141b or 149b may be formed by connecting the second line of the nonvolatile memory device 121 or 129 farthest from the controller 110 and the third line of the data buffer 135 or 136 closest to the controller 110 to one first line.

[0151] The data line 142 b or 148 b may be formed by connecting the second line of the nonvolatile memory device 122 or 128 second farthest from the controller 110 and the third line of the data buffer 134 or 137 second closest to the controller 110 with another first line.

[0152] The data line 145 b or 146 b may be formed by connecting the second line of the nonvolatile memory device 125 or 126 closest to the controller 110 and the third line of the data buffer 131 or 139 farthest from the controller 110 with another first line.

[0153] Fig.16 1 is a block diagram illustrating a semiconductor memory module 100_3 according to a fourth embodiment of the inventive concept. Figure 1 Compared to the semiconductor memory module 100 of FIG. 1 , the semiconductor memory module 100_3 includes the first nonvolatile memory devices 121a to the ninth nonvolatile memory devices 129a of the first rank and the first nonvolatile memory devices 121b to the ninth nonvolatile memory devices 129b of the second rank. Note that although the data lines 141-149 are shown, data lines 141-149 may be used instead. Fig.14 or Fig.15 The changed data line structure.

[0154] The controller 110 may transmit internal addresses ADDRi, internal commands CMDi, and internal selection signals Si to the first to ninth nonvolatile memory devices 121a to 129a in the first rank and the first to ninth nonvolatile memory devices 121b to 129b in the second rank through first control lines 151 and 152 .

[0155] The first nonvolatile memory devices 121a and 121b may be commonly connected to a first data line 141. The second nonvolatile memory devices 122a and 122b may be commonly connected to a second data line 142. Likewise, a particular nonvolatile memory in the first rank may be commonly connected to one data line along with a corresponding nonvolatile memory device in the second rank.

[0156] Fig.17 and Fig.18 is a diagram illustrating an example of adjusting the external selection signal Se and the internal selection signal Si. Figures 16 to 18 , the external selection signal Se may include first to third external selection signals Se1 to Se3. The first external selection signal Se1 may be activated (to a low level) by the memory controller 10 to enable or configure the memory controller 10 to access the first to ninth nonvolatile memory devices 121a to 129a in the first rank through the controller 110.

[0157] The second external selection signal Se2 may be activated (to a low level) by the memory controller 10 so that the memory controller 10 or the memory controller 10 is configured to access the first to ninth nonvolatile memory devices 121 b to 129 b in the second rank through the controller 110. The third external selection signal Se3 may be activated (to a low level) by the memory controller 10 so that the memory controller 10 or the memory controller 10 is configured to access the first to ninth nonvolatile memory devices 121 a to 129 a in the first rank or the first to ninth nonvolatile memory devices 121 b to 129 b in the second rank without passing through the controller 110 (e.g., bypassing the controller 110).

[0158] The internal selection signal Si may include first to third internal selection signals Si1 to Si3. The first internal selection signal Si1 may be activated (to a low level) by the controller 110 to enable or configure the controller 110 to access the first to ninth nonvolatile memory devices 121a to 129a in the first rank.

[0159] The second internal selection signal Si2 may be activated (to a low level) by the controller 110 so as to cause the controller 110 or to configure the controller 110 to access the first to ninth nonvolatile memory devices 121b to 129b in the second rank. The third internal selection signal Si3 may be activated by the controller 110 so as to cause the controller 110 or to configure the controller 110 to prohibit communication of the first to ninth nonvolatile memory devices 121a to 129a in the first rank and communication of the first to ninth nonvolatile memory devices 121b to 129b in the second rank.

[0160] In the first section, the memory controller 10 and the controller 110 may communicate with each other through the first to ninth data buffers 131 to 139 and the first to ninth data lines 141 to 149. In the first section, the memory controller 10 may provide a notification that the first to ninth nonvolatile memory devices 121a to 129a in the first rank are access targets by activating the first external selection signal Se1. Information on the activation of the first external selection signal Se1 may be stored in the buffer 112.

[0161] The controller 110 may transmit the write command WR or the read command RD as the buffer command BCOM. The controller 110 may disable communication of the nonvolatile memory devices 121a to 129a and 121b to 129b by activating the third internal selection signal Si3.

[0162] In the second part, the controller 110 and the first to ninth nonvolatile memory devices 121a to 129a in the first rank may communicate with each other through the first to ninth data lines 141 to 149. According to activation information of the first external selection signal Se1 stored in the buffer 112, the controller 110 may activate the first internal selection signal Si1 to communicate with the first to ninth nonvolatile memory devices 121a to 129a in the first rank.

[0163] In the third section, the memory controller 10 and the first to ninth nonvolatile memory devices 121 a to 129 a in the first rank may communicate with each other through the first to ninth data buffers 131 to 139 and the first to ninth data lines 141 to 149 .

[0164] The memory controller 10 may activate the first external selection signal Se1 and the third external selection signal Se3 to provide notification that the memory controller 10 directly accesses the first to ninth nonvolatile memory devices 121a to 129a in the first rank. The controller 110 may send a write command WR or a read command RD as a buffer command BCOM.

[0165] In the fourth section, the memory controller 10 and the controller 110 may communicate with each other through the first to ninth data buffers 131 to 139 and the first to ninth data lines 141 to 149. In the fourth section, the memory controller 10 may activate the second external selection signal Se2 to provide notification that the first to ninth nonvolatile memory devices 121b to 129b in the second rank are access targets. Information on the activation of the second external selection signal Se2 may be stored in the buffer 112.

[0166] The controller 110 may transmit the write command WR or the read command RD as the buffer command BCOM. The controller 110 may disable communication of the nonvolatile memory devices 121a to 129a and 121b to 129b by activating the third internal selection signal Si3.

[0167] In the fifth section, the controller 110 and the first to ninth nonvolatile memory devices 121 b to 129 b in the second rank may communicate with each other through the first to ninth data lines 141 to 149. According to activation information of the second external selection signal Se2 stored in the buffer 112, the controller 110 may activate the second internal selection signal Si2 to communicate with the first to ninth nonvolatile memory devices 121 b to 129 b in the second rank.

[0168] In the sixth section, the memory controller 10 and the first to ninth nonvolatile memory devices 121 b to 129 b in the second rank may communicate with each other through the first to ninth data buffers 131 to 139 and the first to ninth data lines 141 to 149 .

[0169] The memory controller 10 may activate the second external selection signal Se2 and the third external selection signal Se3 to provide notification that the first to ninth nonvolatile memory devices 121b to 129b in the second rank are direct access targets. The controller 110 may transmit a write command WR or a read command RD as a buffer command BCOM.

[0170] Fig.19 is a block diagram illustrating a semiconductor memory module 100_4 according to a fifth embodiment of the inventive concept. Fig.16 Compared to the semiconductor memory module 100_3, the memory controller 10 includes a first error correction block 11, in which the first error correction code ECC1 is included. The controller 110 may include a second error correction block 115, in which the second error correction code ECC2 is included. Note that although the data lines 141-149 are shown, data lines 141-149 may be used instead. Fig.14 or Fig.15 The changed data line structure.

[0171] In order to prevent conflicts between the first error correction block 11 of the memory controller 10 and the second error correction block 115 of the controller 110, the memory controller 10 can be configured to pass through the buffer 112 of the controller 110 when accessing the first non-volatile memory device 121a to the ninth non-volatile memory device 129a in the first row and bypass the buffer 112 of the controller 110 when accessing the first non-volatile memory device 121b to the ninth non-volatile memory device 129b in the second row.

[0172] For example, when the memory controller 10 writes data to the first to ninth nonvolatile memory devices 121a to 129a in the first rank, the first error correction block 115 may generate a first error correction parity bit (e.g., may perform error correction coding), and the second error correction block 115 may generate a second error correction parity bit (e.g., may perform error correction coding). The first error correction parity bit and the second error correction parity bit may be written to the first to ninth nonvolatile memory devices 121a to 129a together with the data.

[0173] When the memory controller 10 reads data from the first to ninth nonvolatile memory devices 121a to 129a, the second error correction block 115 may correct errors by using the second error correction parity bits (e.g., error correction decoding may be performed), and the first error correction block 11 may correct errors by using the first error correction parity bits (e.g., error correction decoding may be performed).

[0174] When the memory controller 10 writes data to the first to ninth nonvolatile memory devices 121b to 129b in the second rank, the first error correction block 11 may generate first error correction parity bits. The first error correction parity bits may be written to the first to ninth nonvolatile memory devices 121b to 129b together with the data.

[0175] When the memory controller 10 reads data from the first to ninth nonvolatile memory devices 121 b to 129 b , the first error correction block 11 may correct errors by using the first error correction parity bits.

[0176] According to various aspects of the inventive concept, a nonvolatile memory device, a data buffer, and a controller communicate with each other through a common data line. Therefore, a semiconductor memory module having reduced cost and reduced noise while complying with the standard of a main memory is provided.

[0177] While the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

1. A semiconductor memory module, comprising: a data buffer configured to exchange a first data signal with an external device outside the semiconductor memory module; a nonvolatile memory device directly connected to the data buffer via a data line; and an internal memory module controller connected to the data line, Wherein, the internal memory module controller is further configured as: receiving address, command and control signals from the external device; and According to the address, the command, and the control signal, the data buffer is controlled through a first control line and the nonvolatile memory device is controlled through a second control line.

2. The semiconductor memory module according to claim 1, wherein: According to the command and the control signal, the internal memory module controller selects one of the following states: a first state of receiving a second data signal from the data line, a second state of sending a third data signal to the data line, and a third state of ignoring a fourth data signal sent through the data line.

3. The semiconductor memory module according to claim 1, wherein: Under control of the internal memory module controller, the data buffer has a first state receiving a second data signal from the data line, a second state sending a third data signal to the data line, and a third state ignoring a fourth data signal sent through the data line.

4. The semiconductor memory module according to claim 1, wherein: Under control of the internal memory module controller, the nonvolatile memory device has a first state of receiving a second data signal from the data line, a second state of sending a third data signal to the data line, and a third state of ignoring a fourth data signal sent through the data line.

5. The semiconductor memory module according to claim 1, wherein: In the case where the internal memory module controller receives the address, the command or the control signal from the external device when the internal memory module controller communicates with the nonvolatile memory device through the data line or is about to communicate with the nonvolatile memory device through the data line, the internal memory module controller stops or cancels the communication with the nonvolatile memory device by deactivating a first internal selection signal based on the control signal or activating a second internal selection signal based on the control signal.

6. The semiconductor memory module according to claim 1, wherein: The internal memory module controller includes an interface circuit connected to the data line, and The internal memory module controller is further configured to use the interface circuit to communicate with the data buffer and with the non-volatile memory device.

7. The semiconductor memory module according to claim 1, wherein: The internal memory module controller includes a buffer memory, and Wherein, the internal memory module controller is further configured as: storing a second data signal received from the data buffer or the nonvolatile memory device through the data line in the buffer memory; and The second data signal stored in the buffer memory is transmitted as a third data signal to the nonvolatile memory device or the data buffer through the data line.

8. The semiconductor memory module according to claim 7, wherein: The second data signal to be sent from the data buffer to the nonvolatile memory device through the data line and the third data signal to be sent from the nonvolatile memory device to the data buffer through the data line bypass the buffer memory of the internal memory module controller depending on the command and the control signal.

9. The semiconductor memory module according to claim 7, wherein: The internal memory module controller is further configured to discard a fourth data signal previously stored in the buffer memory when a free storage capacity of the buffer memory is less than a threshold value.

10. The semiconductor memory module according to claim 1, wherein: The control signal includes a first control signal, and Wherein, the internal memory module controller is further configured such that: When the first control signal is in an active state, the internal memory module controller controls the nonvolatile memory device so that the nonvolatile memory device ignores a second data signal transmitted through the data line and the internal memory module controller receives or transmits the second data signal through the data line.

11. The semiconductor memory module according to claim 10, wherein: The control signal also includes a second control signal, and Wherein, the internal memory module controller is further configured such that: When the first control signal is in an active state and the second control signal is in an active state, the internal memory module controller controls the nonvolatile memory device so that the nonvolatile memory device exchanges a fourth data signal with the data line and the internal memory module controller ignores the fourth data signal sent through the data line.

12. The semiconductor memory module according to claim 10, wherein: The internal memory module controller is further configured to, when the first control signal is in a deactivated state, deactivate the data buffer and exchange a fourth data signal with the nonvolatile memory device through the data line.

13. The semiconductor memory module according to claim 1, wherein: The control signal includes a first control signal and a second control signal, and The internal memory module controller is further configured to receive a second data signal from the data buffer through the data line or send a third data signal to the data buffer through the data line when one of the first control signal and the second control signal is in an activated state.

14. The semiconductor memory module according to claim 13, wherein: The control signal further includes a third control signal, and Wherein, the internal memory module controller is further configured to control a first non-volatile memory device among the non-volatile memory devices so that the first non-volatile memory device exchanges a fourth data signal with the data line, control a second non-volatile memory device among the non-volatile memory devices so that the second non-volatile memory device ignores the fourth data signal sent through the data line, and ignores the fourth data signal sent through the data line based on the first control signal being in an activated state and the third control signal being in an activated state.

15. The semiconductor memory module according to claim 13, wherein: The internal memory module controller is further configured to deactivate the data buffer and exchange a fourth data signal with a first nonvolatile memory device or a second nonvolatile memory device among the nonvolatile memory devices through the data line based on the first control signal and the second control signal being in a deactivated state.

16. A semiconductor memory module, comprising: a data buffer configured to exchange a data signal with an external device outside the semiconductor memory module; a first nonvolatile memory device, the first nonvolatile memory device being directly connected to the data buffer via a data line; a second nonvolatile memory device, the second nonvolatile memory device being directly connected to the data buffer via the data line; as well as A controller connected to the data line, wherein the controller is configured to receive address, command and control signals from the external device, and Wherein, depending on the address, the command and the control signal, the first non-volatile memory device is configured to communicate with the controller and the data buffer through the data line, and the second non-volatile memory device is configured to communicate directly with the data buffer through the data line.

17. The semiconductor memory module according to claim 16, wherein: The controller includes an error correction block, and Wherein, the controller is further configured as: performing error correction encoding on data to be written into the first nonvolatile memory device through the data line; and Error correction decoding is performed on data read from the first nonvolatile memory device through the data line.

18. A semiconductor memory module, comprising: a data buffer configured to exchange a data signal with an external device outside the semiconductor memory module; a non-volatile memory device connected to the data buffer via a data line; as well as a controller connected to the data line, Wherein, the data line includes: a first line extending from a side of the controller; a second line extending from the first line toward the data buffer; and a third line extending from the first line toward the nonvolatile memory device, Wherein, the controller is further configured as: receiving address, command and control signals from the external device; and According to the address, the command, and the control signal, the data buffer is controlled through a first control line, and the nonvolatile memory device is controlled through a second control line.

19. The semiconductor memory module according to claim 18, wherein: Regardless of a position of a first node at which the first line is connected to the second line or a position of a second node at which the first line is connected to the third line, the first lines have the same length as each other.

20. The semiconductor memory module according to claim 18, wherein One of the first lines is connected to a first nonvolatile memory device farthest from the controller among the nonvolatile memory devices and to a first data buffer closest to the controller among the data buffers, and Another of the first lines is connected to a second nonvolatile memory device that is closest to the controller among the nonvolatile memory devices and is connected to a second data buffer that is farthest from the controller among the data buffers.

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