Anti-aging device

Abstract

A device is provided that includes: a stack of transistors of the same conductivity type, the stack including a first transistor and a second transistor, the first transistor and the second transistor being coupled in series and having a common node; and a feedback transistor of the same conductivity type coupled to the common node and to a gate terminal of the first transistor in the stack.

Description

[0001] Priority requirements

[0002] This application claims priority to U.S. Patent Application No. 15 / 650,271, filed July 14, 2017, entitled “AGING TOLERANT APPARATUS,” which is incorporated herein by reference in its entirety. Background Technology

[0003] Compared to transistors developed in planar technologies, complementary metal-oxide-semiconductor (CMOS) transistors developed in FinFET (Fin Field-Effect Transistor) technology typically suffer from enhanced aging degradation. Digital circuit performance deteriorates due to aging in two ways: (1) functional degradation, which occurs when the aging circuit ceases operation or deteriorates significantly during its lifetime; and (2) device failure, which occurs when excessive aging triggers irreversible dielectric breakdown in the transistor, leading to transient circuit failure. Since aging is exponentially related to voltage, digital circuits age when transistors are exposed to voltages exceeding the operating limits of CMOS devices. One type of digital circuit topology where internal nodes are exposed to voltages exceeding the device target limits is a stacked transistor configuration. Attached Figure Description

[0004] The embodiments of this disclosure will be more fully understood through the following detailed description and the accompanying drawings of various embodiments of this disclosure. However, the detailed description and the accompanying drawings should not be construed as limiting this disclosure to the specific embodiments, but are for illustration and understanding only.

[0005] Figure 1A The stacked circuit configuration is shown.

[0006] Figure 1B The diagram illustrates the stack circuit configuration when one of the transistors in the stack is turned off, which can lead to excessive aging and failure of that transistor.

[0007] Figure 2 A stacked circuit configuration with anti-aging devices is shown according to some embodiments of the present disclosure.

[0008] Figure 3 An “N” stacked circuit configuration with anti-aging devices is shown according to some embodiments of the present disclosure.

[0009] Figure 4A The diagram shows a NAND logic gate circuit that has suffered aging failure.

[0010] Figure 4B NAND logic gate circuits with anti-aging devices are shown according to some embodiments of the present disclosure.

[0011] Figure 5 A comparison of some embodiments according to this disclosure is shown. Figure 4A A set of graphs showing the transient behavior of -B NAND logic gates.

[0012] Figure 6 A comparison of some embodiments according to this disclosure over many years is shown. Figure 4A A set of graphs showing the transient behavior of -B NAND logic gates.

[0013] Figure 7 A graph illustrating the relationship between frequency degradation and service life of a ring oscillator (RO) according to some embodiments is shown.

[0014] Figure 8 An illustration according to some embodiments is shown. Figure 1A and Figure 2 The curve of the deterioration of the drive current of transistor MN2.

[0015] Figure 9 Anti-aging NOR logic gate circuits according to some embodiments of the present disclosure are shown.

[0016] Figure 10 An anti-aging selection circuit according to some embodiments of the present disclosure is shown.

[0017] Figure 11 An anti-aging multiplexer circuit according to some embodiments of the present disclosure is shown.

[0018] Figure 12 A smart device or computer system or SoC (System-on-a-Chip) with anti-aging devices is shown according to some embodiments of the present disclosure. Detailed Implementation

[0019] Some embodiments describe an anti-aging circuit that clamps a high-impedance node to a well-defined fixed voltage. Some embodiments apply the anti-aging circuit technique to "N" stacked transistors, and the technique is also applicable to all digital circuits using stacked n-type and p-type devices. Some embodiments ensure that if the signal at an intermediate node in the transistor stack is affected by noise and / or coupling, there is an alternative charge / discharge path to clamp the voltage at that node to a specified voltage.

[0020] Numerous technical advantages exist in the various embodiments. For example, some embodiments of anti-aging circuitry or apparatus prevent the device operating voltage from exceeding the process-specified voltage for a stacked n-type transistor and / or p-type transistor configuration by clamping all affected internal nodes to a specified voltage level. Some embodiments of anti-aging circuitry or apparatus avoid excessive degradation of transistors, digital circuitry, and circuit failure. In some embodiments, for a ring oscillator (RO) circuit using transistor stacks, frequency degradation with anti-aging circuitry can be significantly lower than frequency degradation without it.

[0021] For example, the frequency degradation of a RO without anti-aging circuitry might be 45% over 10 years, while with anti-aging circuitry, it might be 14% over 10 years. In another example, the reduction in drive current for the RO can be much lower than without anti-aging circuitry. For example, for a stacked RO, the drive current reduction after 10 years might be 80% without anti-aging circuitry, while for the same period, the drive current reduction with anti-aging circuitry is 28%. Other technical effects will be apparent from the various embodiments and figures.

[0022] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. However, it will be apparent to those skilled in the art that embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present disclosure.

[0023] Note that in the corresponding figures of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more component signal paths and / or have arrows at one or more ends to indicate the main flow of information. Such indications are not intended to be limiting. Rather, these lines are used in conjunction with one or more exemplary embodiments to facilitate easier understanding of the circuit or logic unit. Any represented signal may actually include one or more signals that can propagate in either direction and can be implemented using any suitable type of signaling scheme, as indicated by design needs or preferences.

[0024] Throughout this specification and in the claims, the term "connection" refers to a direct connection, such as an electrical, mechanical, or magnetic connection between connected objects without any intermediate means. The term "coupling" refers to a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between connected objects, or an indirect connection via one or more passive or active intermediate means. The terms "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a," "an," and "the" include the plural forms. The meaning of "in" includes both "in" and "on."

[0025] The term "scaling" typically refers to converting a design (schematic and layout) from one process technology to another, resulting in a reduction in layout area. "Scaling" also typically refers to reducing the size of layouts and devices within the same technology node. Furthermore, "scaling" can refer to adjusting (e.g., slowing down or speeding up, i.e., reducing or amplifying, respectively) a signal frequency relative to another parameter (e.g., power supply level). The terms "substantially," "close to," "approximately," "near," and "about" typically refer to within + / - 10% of a target value.

[0026] Unless otherwise specified, the use of ordinal adjectives such as “first,” “second,” and “third” to describe common objects merely indicates that different instances of the same object are being referenced, and is not intended to imply that the objects described in this way must be in a given order in time, space, sequence, or any other way.

[0027] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” mean (A), (B) or (A and B). For the purposes of this disclosure, the phrases “A, B and / or C” mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0028] The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “above,” “below,” etc. (if any) used in the specification and claims are for descriptive purposes only and are not necessarily used to describe permanent relative positions. For the purposes of this disclosure, the terms “spin” and “magnetic moment” are used equivalently. More strictly, the direction of spin is opposite to the direction of the magnetic moment, and the particle has a negative charge (e.g., in the case of an electron).

[0029] For the purposes of this embodiment, the transistors in the various circuits and logic blocks described herein are metal-oxide-semiconductor (MOS) transistors or derivatives thereof, wherein a MOS transistor includes a drain terminal, a source terminal, a gate terminal, and a body terminal. Transistors and / or MOS transistor derivatives also include tri-gate transistors and FinFET transistors, fully enclosed gate cylindrical transistors, tunnel FETs (TFETs), square wire or rectangular stripe transistors, ferroelectric FETs (FeFETs), or other devices that implement transistor functions, such as carbon nanotubes or spintronic devices. The symmetrical source and drain terminals of a MOSFET are identical and can be used interchangeably herein. On the other hand, a TFET device has asymmetrical source and drain terminals. Those skilled in the art will understand that other transistors, such as bipolar junction transistors (BJT PNP / NPN), BiCMOS, CMOS, etc., can be used without departing from the scope of this disclosure.

[0030] Because aging is exponentially related to voltage, digital circuits will age when transistors are exposed to voltages exceeding the operating limits of CMOS devices. One type of digital circuit topology that exposes internal nodes to voltages exceeding the device's target limits is a stacked transistor configuration.

[0031] Figure 1A A stacked circuit configuration 100 is shown. Configuration 100 is widely used in circuits such as logic circuits, I / O (input / output) interfaces, DC-DC converters, power amplifiers, etc. The stacked circuit configuration 100 includes two stacked n-type transistors, referred to as transistors MN1 and MN2. Here, n-type transistors are shown in a stacked configuration; however, the aging problem also applies to stacked p-type transistors. To avoid excessive aging of the devices, the voltage between the terminals of the two transistors (e.g., between gate and source, or between drain and source) is limited to a maximum voltage V. max Typically, V max =1.1V DD,nom Used as a constraint, where V DD,nom This is the nominal supply voltage of the corresponding device.

[0032] Figure 1B The diagram illustrates a stacked circuit configuration 120 when one transistor in the stack is turned off, which can lead to excessive aging and failure of that transistor. Special attention should be paid to the drain-source voltage Vd of the upper transistor MN2 during the design of the stacked topology. DS,2 When transistor MN2 is turned off, for example, when the gate-source voltage V of transistor MN2 is... GS,2 The threshold voltage V of transistor MN2 is less than or equal to th (For example, V) GS,2 <V thWhen node "Y" is a high-impedance node (e.g., a floating node) susceptible to arbitrary coupling or noise, therefore V DS,2 It will become higher than V max (For example, V) DS,2 >V max Here, the term "V" max The voltage is as follows: If a voltage higher than this is applied for a certain period of time, the transistor at the process node will be damaged. Excessive voltage exceeding the operating limit will cause the device to degrade due to aging, thereby causing transistor MN2 to fail and potentially limiting circuit function.

[0033] As FinFET geometries shrink to 14nm, 10nm, or 7nm, the device geometry becomes more susceptible to aging than planar transistors. Even moderate operating voltages exceeding the operating voltages specified by the process node can cause standard circuit topologies to fail. Similar issues may arise for some externally small geometry processes, whether planar or silicon-on-insulator (SOI) technologies. One solution to overcome aging is to reduce the supply voltage to provide more operating voltage margin. However, reducing the supply voltage limits circuit operation and restricts circuit drive capability, leading to timing violations on the integrated circuit (IC) chip. Various embodiments provide an anti-aging circuitry technique that mitigates aging on smaller process geometries.

[0034] Figure 2 A stacked circuit configuration 200 with anti-aging devices is shown according to some embodiments of the present disclosure. It should be noted that... Figure 2 Elements having the same reference numerals (or names) as those in any other figure may operate or function in any manner similar to, but not limited to, those described. Here, the stacked circuit configuration 200 includes a first n-type transistor MN2 coupled in series with a second n-type transistor MN1, such that node “Y” is a common node. In some embodiments, the anti-aging device includes a feedback transistor MNfb of the same conductivity type (e.g., n-type) coupled to the common node “Y” and the gate terminal of the first transistor MN2 in the stack. In some embodiments, the gate terminal of the feedback transistor MNfb is coupled to the first transistor MN2 in the stack. In some embodiments, the gate terminals of the first transistor MN2 and the second transistor MN1 may be controlled by two separate control nodes “G2” and “G1”, respectively. In some embodiments, the size of the feedback transistor MNfb is smaller than the size of one of the first or second transistors. For example, the width of the feedback transistor MNfb is 75% of the width of the first transistor MN2 or the second transistor MN1. In some embodiments, the size of the feedback transistor may also be larger than the size of the stacked transistors.

[0035] In some embodiments, the anti-aging circuitry maintains the internal nodes of the stacked circuit topology within a specified operating voltage range. In some embodiments, the feedback transistor MNfb is coupled between nodes "G2" and "Y", and its gate is coupled to node "X". In some embodiments, the feedback transistor MNfb will V DS,2 Limit to below V max The value of is determined, thus preventing excessive degradation and failure of transistor MN2. Two operating scenarios of the circuit are described here.

[0036] In the first case, transistor MN2 is off (e.g., V). GS,2 <V th ), and V DS,2 >V max It is possible. In this case, once V DS,2 Start exceeding V th Then, transistor MNfb will turn on. According to some embodiments, transistor MNfb now provides an additional charge / discharge path for node "Y". This can raise the voltage at node "Y" to the voltage at the gate of transistor MN2, thereby reducing V. DS,2 =V X -V Y Limit it to below V max The value of .

[0037] In the second case, transistor MN2 is turned on (e.g., V). GS,2 >V th ), and V DS,2 >V max It's impossible. In this situation, V DS,2 =V GS,P =0, meaning that transistor MNfb is turned off and will not further affect the function of the entire circuit.

[0038] Figure 3 An "N" stacked circuit configuration 300 with anti-aging devices is shown according to some embodiments of the present disclosure. It should be noted that... Figure 3 Elements having the same reference numerals (or names) as those in any other figure may operate or function in any manner similar to that described, but are not limited thereto. The “N” stacked circuit configuration 300 includes “N” transistors MN1 to MNN coupled in series. In some embodiments, a feedback transistor is associated with each transistor in the stack. Here, as shown, the “N” feedback transistors MNfb1 to MNfbN are shown coupled to an internal node. For example, the gate of the feedback transistor MNfbN is coupled to node “N-1”, its drain is coupled to gate GN, and its source is coupled to node “N”.

[0039] Figure 4AA NAND logic gate 400 suffering from aging failure is shown. The NAND logic gate 400 includes p-type transistors MP1 and MP2 and n-type transistors MN1 and MN2 coupled together as shown, such that transistors MP1 and MN2 are controlled by node "A" providing signal "A", and transistors MP2 and MN1 are controlled by node "B" providing signal "B". For example, the NAND gate 400 can be part of a ring oscillator (RO) designed for industrial applications requiring a lifespan in the range of 5 to 10 years. Here, the stacking of transistors MN2 and MN1 is similar to... Figure 1A The stack shown in -B is subjected to the same problem.

[0040] The NAND logic gate 400 depicts the schematic of a single NAND RO stage, which is state-of-the-art. In state-of-the-art solutions, transistor MN2 may operate beyond the device voltage limit, leading to excessive aging of the entire RO.

[0041] Figure 4B A NAND logic gate circuit 420 with anti-aging devices is shown according to some embodiments of the present disclosure. It should be noted that... Figure 4B Elements that have the same reference numerals (or names) as those in any other accompanying drawing may operate or function in any manner similar to, but not limited to, those described. As shown, NAND logic gate 420 includes an anti-aging device comprising a transistor MNfb coupled to nodes “Y” and “A” and controllable by node “X”. The behavior of transistor MNfb in NAND logic gate 420 is similar to… Figure 2 The transistor MNfb in it is the same.

[0042] Figure 5 A comparison of some embodiments according to this disclosure is shown. Figure 4A A set of graphs 500 showing the transient behavior of the -B NAND logic gate. It should be noted that... Figure 5 Elements that have the same reference numerals (or names) as those in any other accompanying drawing may operate or function in any manner similar to that described, but are not limited thereto. Graph 501 shows the input at nodes “A” and “B” over time. Graph 502 shows the input for… Figure 4A (existing NAND technology) and Figure 4B The output voltage at node "X" of the (robust NAND) is shown in Figure 503. Figure 4A (existing NAND technology) and Figure 4B The voltage at node "Y" of the (robust NAND) is shown in Figure 504. Figure 4A (existing NAND technology) and Figure 4B V of (robust NAND) transistor MN2 DS .

[0043] Considering the waveform of the existing technical solution, the following situation is observed: when the input signal changes from V... DD Switch to V SS This causes the output "X" to change from V. SS Transition to V DD At that time, the voltage at node "Y" drops to V. SS Below. In the example considered, the negative voltage is caused by a capacitive voltage divider, which is caused by the gate-source capacitance C of transistor MN2. GS The capacitance C at node "Y" Y form: Thus, as shown in curve 504, the drain-source voltage V of transistor MN2 DS More than V DD (V DS =V out -V Y >V DD It can be seen that V DS Exceeding the maximum voltage level (typically V) max =1.05*V DD –1.1*V DD This poses a high reliability risk to transistor MN2 for up to 50% of the time.

[0044] According to some embodiments, this situation in a stacked transistor configuration can be avoided when applying anti-aging devices. When the input is from V... DD Switch to V SS At that time, it caused the output node "X" to change from V. SS Transition to V DD At that time, the additional transistor MNfb is turned on. From Figure 5 The transient waveform shows that transistor MNfb charges node "Y" to V. SS This will change the V of transistor MN2. DS Restricted to V DD Note that, according to some embodiments, the waveform at the NAND gate output is completely unaffected (or negligible) by the anti-aging device.

[0045] Figure 6 A comparison of some embodiments according to this disclosure over many years is shown. Figure 4A A set of graphs showing the transient behavior of the -B NAND logic gate. Graph 601 illustrates... Figure 4A The transient behavior at the output node "X" of the NAND is shown in Figure 602. Figure 4B The transient behavior at the output node "X" of the NAND flash memory. Using existing technology solutions (such as...) Figure 4A As shown, the fall time increases significantly with use. For example, after 8 years (yrs), the increase in fall time is so large that the output no longer reaches a low level during one clock cycle (200MHz in this example), leading to logic output level errors (e.g., circuit failure). Conversely, with anti-aging devices, the degradation of the output fall time is significantly reduced. For example, even after 10 years of operation, a robust NAND gate functions normally with only a negligible increase in output fall time on the order of 1%.

[0046] Figure 7 A graph 700 is shown, according to some embodiments, illustrating the relationship between frequency degradation and service life of a ring oscillator (RO). Graph 700 compares... Figure 4A Existing technology design solutions and Figure 4B The relationship between RO frequency degradation due to transistor aging and time is presented in the proposed anti-aging circuit solution. In this example, the RO frequency using the existing technology solution degraded by 45% after 10 years, while the frequency degradation using the proposed solution was only 14% after 10 years.

[0047] Figure 8 An illustration according to some embodiments is shown. Figure 1A and Figure 2 The graph 800 shows the degradation of the drive current of transistor MN2. Here, the relationship between the reduction of the drive current of transistor MN2 in a single RO stage and time is plotted. In the technology used, the reduction of the drive current must be less than 50% to prevent breakdown of the corresponding transistor. Using existing technology solutions, this threshold limit is reached after about one year. Therefore, existing technology solutions cannot meet the needs of products requiring a service life of more than one year. In contrast, using anti-aging circuitry techniques from some embodiments, the maximum current degradation after 10 years is 28%, which still leaves sufficient margin for the 50% threshold limit. The performance and area impact of the anti-aging circuitry shown is negligible. According to some embodiments, in the case of NAND RO, adding anti-aging circuitry to existing technology solutions increases the active gate area by only 2.5%.

[0048] Table 1 summarizes and compares the performance of existing technical solutions with that of the proposed solution.

[0049] parameter Current solution Anti-aging solutions usage period 1 year More than 10 years Area impact 0 +2.5％ RO frequency deteriorates after 10 years 45％ Less than 14% The drive current decreases after 10 years 80％ 28％

[0050] The anti-aging circuits or devices of various embodiments are not limited to NAND circuits. For example, the anti-aging circuits or devices of various embodiments can also be implemented in other digital circuits having various stacks of n-type or p-type transistors.

[0051] Figure 9 An anti-aging NOR logic gate circuit 900 according to some embodiments of the present disclosure is shown. A conventional NOR logic gate circuit includes p-type transistors MP1 and MP2 and n-type transistors MN1 and MN2 coupled together as shown, having input nodes "A" and "B" and an output node OUTB. Here, the transistor stack is formed by the p-type transistors MP1 and MP2. (See reference...) Figure 4A As discussed in the NAND gate discussion, here, without feedback p-type transistor MPfb, the stacked transistors (here, transistor MP2) suffer from excessive aging (like... Figure 4A (The transistor MN2 in the reference is the same). Return to reference. Figure 9 To mitigate aging, in some embodiments, as shown in the figure, a feedback transistor MPbf coupled to transistors MP2, MP1, MN1, and MN2 is added.

[0052] In some embodiments, a feedback p-type transistor MPfb is provided, coupled to two n-type transistors (MN1 and MN2) of a NOR gate and two p-type transistors (MP1 and MP2) of the NOR gate. In some embodiments, the gate terminal of the feedback transistor MPfb is coupled to the drain terminals of the two n-type transistors MN1 and MN2 of the NOR gate. In some embodiments, the feedback transistor MPfb is coupled to the gate terminal of one of the two p-type transistors (e.g., transistor MP2). In some embodiments, the feedback transistor MPfb is a p-type transistor. In some embodiments, the gate terminal of the feedback transistor MPfb is coupled to the output node OUTB of the NOR gate. In some embodiments, the size of the feedback transistor MPfb is smaller than that of one of the two p-type transistors. For example, the feedback transistor MPfb may occupy only 2.5% of the total area of ​​the NOR gate 900 and may be 75% to 80% of the width of transistor MP2 or MP1.

[0053] Figure 10An anti-aging selection circuit 1000 according to some embodiments of the present disclosure is illustrated. In some embodiments, the anti-aging selection circuit 1000 includes p-type devices MP1, MP2, and MPfb (first feedback devices) coupled together as shown, and n-type transistors MN1, MN2, and MNfb (second feedback devices). Prior art selection circuits include transistors MP1, MP2, MN1, and MN2 without anti-aging devices (e.g., feedback transistors MPfb and MNfb). The selection circuit is designed to provide an inverted version of the signal at node "A" to the output node OUTB when the signal at node SEL is high and the signal at node SELB is low.

[0054] Reference Figure 10 Here, there are two stacks of the same conductivity type. The first stack consists of p-type transistors MP1 and MP2, where transistor MP1 is controlled by SELB (the inverted form of SEL), and transistor MP2 is controlled by node "A". The second stack consists of n-type transistors MN1 and MN2, where transistor MN1 is controlled by SEL, and transistor MN2 is controlled by node "A". Just like... Figure 1A Similar to the aging stress experienced by transistor MN2 in -B, transistors MP2 and MN2 in their respective stacks also face aging stress. To mitigate or reduce aging stress, as shown in the figure, a first feedback p-type transistor MPfb is coupled to transistors MP1 and MP2 and node OUTB, and a second feedback n-type transistor MNfb is coupled to transistors MN1 and MN2 and node OUTB.

[0055] Figure 11 An anti-aging multiplexer (MUX) circuit 1100 according to some embodiments of the present disclosure is shown. It should be noted that... Figure 11 Elements having the same reference numerals (or names) as elements in any other accompanying drawing may operate or function in any manner similar to that described, but are not limited thereto. The anti-aging multiplexer circuit 1100 includes... Figure 10 Two examples of the anti-aging selection circuit 1000 are provided, and therefore include four feedback devices, including p-type transistors MPfba and MPfbb and n-type transistors MNfba and MNfbb. In some embodiments, the MUX circuit 1100 includes p-type transistors MP1a, MP1b, MP2a and MP2b, MPfba and MPfbb, and n-type transistors MN1a, MN1b, MN2a, MN2b, MNfba and MNfbb coupled together as shown. Figure 10 Two instances of the anti-aging selection circuit 1000 are coupled together to share the output node OUTB, while swapping the selection input for one of the anti-aging selection circuits.

[0056] For example, transistor MP1b is controlled by the SEL node, transistor MP1a by the SELB node, transistor MN1a by the SEL node, and transistor MN1b by the SELB node. The two input nodes are nodes "A" and "B," which are selectively provided to the output node OUTB based on the logic levels of the signals on the selection nodes SEL and SELB (which are the inverted versions of SEL). In some embodiments, feedback devices MPfba, MPfbb, MNfba, and MNfbb provide anti-aging protection to transistors MP2a, MP2b, MN2a, and MN2b, respectively.

[0057] Figure 12 A smart device or computer system or SoC (System-on-a-Chip) with anti-aging devices is illustrated according to some embodiments of the present disclosure. It should be noted that... Figure 12 Elements that have the same reference numerals (or names) as elements in any other figure may operate or function in any manner similar to that described, but are not limited thereto.

[0058] Figure 12 A block diagram illustrating an embodiment of a mobile device that can use a planar interface connector is shown. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, mobile phone or smartphone, wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown in general, but not all components of this device are shown in computing device 1600.

[0059] In some embodiments, computing device 1600 includes a first processor 1610 with anti-aging devices according to some of the embodiments discussed. According to some embodiments, other modules of computing device 1600 may also include device 300 and anti-aging devices. Various embodiments of this disclosure may also include a network interface (e.g., a wireless interface) within 1670, enabling the incorporation of system embodiments into wireless devices (e.g., cellular phones or personal digital assistants).

[0060] In some embodiments, processor 1610 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing module. Processing operations performed by processor 1610 include the execution of an operating platform or operating system on which application and / or device functions are performed. Processing operations include operations related to I / O (input / output) of human users or other devices, operations related to power management, and / or operations related to connecting computing device 1600 to another device. Processing operations may also include operations related to audio I / O and / or display I / O.

[0061] In some embodiments, computing device 1600 includes an audio subsystem 1620, which represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components associated with providing audio functionality to the computing device. Audio functionality may include speaker and / or headphone outputs, and microphone inputs. Devices for such functionality may be integrated into or connected to computing device 1600. In one embodiment, a user interacts with computing device 1600 by providing audio commands, which are received and processed by processor 1610.

[0062] In some embodiments, computing device 1600 includes a display subsystem 1630. Display subsystem 1630 represents hardware (e.g., a display device) and software (e.g., a driver) components that provide visual and / or tactile displays for user interaction with computing device 1600. Display subsystem 1630 includes a display interface 1632, which includes a specific screen or hardware device for providing a display to a user. In one embodiment, display interface 1632 includes logic decoupled from processor 1610 for performing at least some display-related processing. In one embodiment, display subsystem 1630 includes a touchscreen (or touchpad) device that provides both output and input to a user.

[0063] In some embodiments, computing device 1600 includes an I / O controller 1640. The I / O controller 1640 represents hardware devices and software components related to user interaction. The I / O controller 1640 is operable to manage hardware that is part of an audio subsystem 1620 and / or a display subsystem 1630. Additionally, the I / O controller 1640 illustrates connection points for attaching additional devices to computing device 1600 through which the user can interact with the system. For example, devices that can be attached to computing device 1600 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or an I / O device used with a specific application (e.g., a card reader or other device).

[0064] As described above, the I / O controller 1640 can interact with the audio subsystem 1620 and / or the display subsystem 1630. For example, input via a microphone or other audio device can provide input or commands to one or more applications or functions of the computing device 1600. Additionally, audio output can be provided in place of or in addition to display output. In another example, if the display subsystem 1630 includes a touchscreen, the display device also acts as an input device, which can be managed at least partially by the I / O controller 1640. Additional buttons or switches may also be present on the computing device 1600 to provide I / O functionality managed by the I / O controller 1640.

[0065] In some embodiments, the I / O controller 1640 manages devices such as accelerometers, cameras, light sensors, or other environmental sensors, or other hardware that may be included in the computing device 1600. Input may be part of direct user interaction, as well as providing environmental input to the system to affect its operation (e.g., filtering noise, adjusting the display for brightness detection, applying a flash to the camera, or other features).

[0066] In some embodiments, computing device 1600 includes power management 1650, which manages battery power usage, battery charging, and features related to power-saving operation. Memory subsystem 1660 includes storage devices for storing information in computing device 1600. The memory may include non-volatile storage devices (whose state does not change if power to the storage device is interrupted) and / or volatile storage devices (whose state is indeterminate if power to the storage device is interrupted). Memory subsystem 1660 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of computing device 1600.

[0067] Elements of the embodiments are also provided as machine-readable media (e.g., memory 1660) for storing computer-executable instructions (e.g., instructions for implementing any other processes discussed herein). Machine-readable media (e.g., memory 1660) may include, but are not limited to, flash memory, optical disc, CD-ROM, DVD-ROM, RAM, EPROM, EEPROM, magnetic or optical cards, phase-change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of this disclosure can be downloaded as a computer program (e.g., BIOS) that can be transmitted via a communication link (e.g., modem or network connection) through data signals from a remote computer (e.g., server) to a requesting computer (e.g., client).

[0068] In some embodiments, computing device 1600 includes connectivity 1670. Connectivity 1670 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) that enable computing device 1600 to communicate with external devices. Computing device 1600 may be a standalone device (e.g., another computing device, a wireless access point, or a base station) and peripherals (e.g., headphones, printers, or other devices).

[0069] Connection 1670 can include various different types of connections. Generally speaking, computing device 1600 is shown to have cellular connection 1672 and wireless connection 1674. Cellular connection 1672 typically refers to a cellular network connection provided by a wireless operator, such as a cellular network connection provided via GSM (Global System for Mobile Communications) or its variants or derivatives, CDMA (Code Division Multiple Access) or its variants or derivatives, TDM (Time Division Multiplexing) or its variants or derivatives, or other cellular service standards. Wireless connection (or wireless interface) 1674 refers to a non-cellular wireless connection and may include personal area networks (e.g., Bluetooth, NFC, etc.), local area networks (e.g., Wi-Fi), and / or wide area networks (e.g., WiMax) or other wireless communications.

[0070] In some embodiments, computing device 1600 includes peripheral connectivity 1680. Peripheral connectivity 1680 includes hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) for peripheral connectivity. It should be understood that computing device 1600 can be a peripheral to other computing devices (“to” 1682) or have peripherals connected to it (“from” 1684). Computing device 1600 typically has a “dock” connector for connecting to other computing devices for purposes such as managing (e.g., downloading and / or uploading, changing, synchronizing) content on computing device 1600. Additionally, the dock connector may allow computing device 1600 to connect to certain peripherals that allow computing device 1600 to control content output to, for example, an audiovisual system or other system.

[0071] In addition to proprietary docking connectors or other proprietary connection hardware, computing device 1600 can also be peripherally connected 1680 via common connectors or standards-based connectors. Common types may include Universal Serial Bus (USB) connectors (which may include any of a number of different hardware interfaces), DisplayPort including Mini DisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0072] References to "embodiment," "one embodiment," "some embodiments," or "other embodiments" in the specification mean that a particular feature, structure, or characteristic described in connection with these embodiments is included in at least some, but not necessarily all, embodiments. Various appearances of "embodiment," "one embodiment," or "some embodiments" do not necessarily refer to the same embodiment. If the specification states that a component, feature, structure, or characteristic "may," "can," or "is capable of" being included, then that particular component, feature, structure, or characteristic does not need to be included. If the specification or claims refer to an element "a" or "one," this does not mean that only one element exists. If the specification or claims refer to an "additional" element, this does not exclude the existence of more than one additional element.

[0073] Furthermore, in one or more embodiments, specific features, structures, functions, or characteristics can be combined in any suitable manner. For example, a first embodiment can be combined with a second embodiment in any place where specific features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0074] Although this disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be apparent to those skilled in the art from the foregoing description. The embodiments of this disclosure are intended to cover all such alternatives, modifications, and variations falling within the broad scope of the appended claims.

[0075] Additionally, to simplify the illustrations and discussion and without obscuring the disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented figures. Furthermore, arrangements may be shown in block diagram form to avoid obscuring the disclosure, also because the details of implementing such block diagram arrangements largely depend on the platform in which the disclosure is implemented (i.e., such details should be within the view of someone skilled in the art). While specific details (e.g., circuits) are set forth to describe exemplary embodiments of the disclosure, it will be apparent to those skilled in the art that the disclosure can be practiced without these specific details or in variations thereof. Therefore, this description should be considered illustrative rather than restrictive.

[0076] The following examples relate to other embodiments. Details from the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented relative to a method or process.

[0077] Example 1. An apparatus comprising: a stack of transistors of the same conductivity type, the stack including a first transistor and a second transistor, the first transistor and the second transistor being coupled in series and having a common node; and a feedback transistor of the same conductivity type coupled to the common node and a gate terminal of the first transistor in the stack.

[0078] Example 2. The apparatus according to Example 1, wherein the feedback transistor includes a gate terminal coupled to a first transistor in the stack.

[0079] Example 3. The apparatus according to any one of the foregoing examples, wherein the gate terminal of the first transistor and the gate terminal of the second transistor are controlled by two separate control nodes.

[0080] Example 4. The apparatus according to any one of the foregoing examples, wherein the size of the feedback transistor is smaller than that of either the first transistor or the second transistor.

[0081] Example 5. An apparatus comprising: a NAND gate; and a feedback transistor coupled to two n-type transistors of the NAND gate and two p-type transistors of the NAND gate.

[0082] Example 6. The apparatus according to Example 5, wherein the gate terminal of the feedback transistor is coupled to the drain terminals of the two p-type transistors of the NAND gate.

[0083] Example 7. The apparatus according to Example 5, wherein the feedback transistor is coupled to the gate terminal of one of the two n-type transistors.

[0084] Example 8. The apparatus according to Example 5, wherein the feedback transistor is an n-type transistor.

[0085] Example 9. The apparatus according to any one of Examples 5-8, wherein the gate terminal of the feedback transistor is coupled to the output of the NAND gate.

[0086] Example 10. The apparatus according to any one of Examples 5-9, wherein the size of the feedback transistor is smaller than that of one of the two n-type transistors.

[0087] Example 11. An apparatus comprising: a NOR gate; and a feedback transistor, two n-type transistors coupled to the NOR gate and two p-type transistors coupled to the NOR gate.

[0088] Example 12. The apparatus according to Example 11, wherein the gate terminal of the feedback transistor is coupled to the drain terminals of the two n-type transistors of the NOR gate.

[0089] Example 13. The apparatus according to Example 11, wherein the feedback transistor is coupled to the gate terminal of one of the two p-type transistors.

[0090] Example 14. The apparatus according to Example 11, wherein the feedback transistor is a p-type transistor.

[0091] Example 15. The apparatus according to any one of Examples 11-15, wherein the gate terminal of the feedback transistor is coupled to the output of the NOR gate.

[0092] Example 16. The apparatus according to any one of Examples 11-15, wherein the size of the feedback transistor is smaller than that of one of the two p-type transistors.

[0093] Example 17. A system comprising: a memory; a processor coupled to the memory, the processor including means according to any one of Examples 1-4; and a wireless interface for allowing the processor to communicate with another device.

[0094] Example 18. A system comprising: a memory; a processor coupled to the memory, the processor including means according to any one of Examples 5-10; and a wireless interface for allowing the processor to communicate with another device.

[0095] Example 19. A system comprising: a memory; a processor coupled to the memory, the processor including means according to any one of Examples 11-16; and a wireless interface for allowing the processor to communicate with another device.

[0096] Example 20. An apparatus comprising: a module for clamping a high-impedance node in a transistor stack to a fixed voltage.

[0097] Example 21. The apparatus according to Example 20 includes a module for controlling the transistors in the stack via two separate control nodes.

[0098] Example 22. The apparatus according to Example 20, wherein the size of the clamping module is smaller than that of one of the transistors in the stack.

[0099] Example 23. A method comprising clamping a high-impedance node in a transistor stack to a fixed voltage.

[0100] Example 24. The method according to Example 23 includes controlling the transistors in the stack via two separate control nodes.

[0101] Example 25. The method according to Example 23, wherein the size of the transistor used for clamping is smaller than that of one of the transistors in the stack.

[0102] An abstract is provided to allow the reader to determine the nature and essence of the technical disclosure. It is understood at the time of submission that the abstract is not intended to limit the scope or meaning of the claims. The appended claims are thereby incorporated into the detailed description, wherein each claim represents a separate embodiment.

Claims

1. A device for anti-aging, the device comprising: A stack of transistors of the same conductivity type, the stack comprising a first transistor and a second transistor, the first transistor and the second transistor being coupled in series and having a common node; and Feedback transistors of the same conductivity type are coupled to the gate terminal of the common node and the first transistor in the stack. In this configuration, one of the source and drain terminals of the feedback transistor is coupled to the gate terminal of the first transistor, and the other of the source and drain terminals of the feedback transistor is coupled to the common node. The gate terminal of the feedback transistor is coupled to one of the source and drain terminals of the first transistor.

2. The apparatus according to claim 1, wherein, The gate terminals of the first transistor and the second transistor are controllable by two separate control nodes.

3. The apparatus according to any one of the preceding claims, wherein, The size of the feedback transistor is smaller than that of either the first transistor or the second transistor.

4. A NAND gate, comprising the means according to any one of claims 1-3, in, The stack of transistors of the same conductivity type includes two n-type transistors of the NAND gate. The NAND gate also includes two p-type transistors.

5. The NAND gate according to claim 4, wherein, The gate terminal of the feedback transistor is coupled to the drain terminals of the two p-type transistors of the NAND gate.

6. The NAND gate according to claim 4, wherein, The gate terminal of the feedback transistor is coupled to the output of the NAND gate.

7. A NOR gate, comprising the means according to any one of claims 1-3, in, A stack of transistors of the same conductivity type includes two p-type transistors of the NOR gate. The NOR gate also includes two n-type transistors.

8. The NOR gate according to claim 7, wherein, The gate terminal of the feedback transistor is coupled to the drain terminals of the two n-type transistors of the NOR gate.

9. The NOR gate according to claim 7, wherein, The gate terminal of the feedback transistor is coupled to the output of the NOR gate.

10. A system comprising: Memory; A processor coupled to the memory, the processor comprising the means according to any one of claims 1-3; and A wireless interface is provided to allow the processor to communicate with another device.

11. A system comprising: Memory; A processor coupled to the memory, the processor comprising NAND gates according to any one of claims 4-6; and A wireless interface is provided to allow the processor to communicate with another device.

12. A system comprising: Memory; A processor coupled to the memory, the processor comprising a NOR gate according to any one of claims 7-9; and A wireless interface is provided to allow the processor to communicate with another device.

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