Display device and driving method thereof

Abstract

A display device and a driving method thereof are provided. The display device includes a decoder. The decoder includes: a first switching control block configured to select at least two first interval endpoint values ​​from a plurality of gamma grayscale values ​​based on a predetermined high bit of input data; and a second switching control block configured to select a second interval endpoint value from the selected at least two first interval endpoint values ​​based on a predetermined low bit of the input data and output at least two channel values.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2018-0095171 filed on August 14, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety for all purposes by reference. Technical Field

[0003] The following description may relate to a display device, a decoder driving the display device, a display device including the decoder, and a driving method of the display device. Background Art

[0004] The source driver displays an image by converting a digital signal corresponding to image data desired to be displayed into an analog voltage and supplying the analog voltage to each pixel of the display panel.

[0005] Figure 1 An example of a display device is shown.

[0006] Reference Figure 1 The display panel may include a plurality of data lines, a plurality of gate lines, and a plurality of pixels formed at intersections of the respective data lines and the respective gate lines.

[0007] Each pixel (not shown) may include a transistor and a pixel capacity, and may input data by charging an analog voltage corresponding to a grayscale level of an image desired to be displayed in each pixel capacity.

[0008] Figure 2 is a block diagram of a source driver according to a comparative example, and Figure 3 is a data decoding table showing the operation of the source driver according to the comparative example.

[0009] Reference Figure 2 ,like Figure 2 As shown, the common source driver may include a main controller 11, at least one channel decoder 12-1 to 12-n and at least one channel amplifier 15-1 to 15-n. At least one channel decoder 12-1 to 12-n receives a grayscale voltage from a gamma block 40 and outputs a grayscale voltage SOUT corresponding to data (display data) input from the main controller.

[0010] When the data is n bits (where n is a natural number greater than or equal to 1), the gamma grayscale value input to the at least one channel decoder 121 to 12-n has a value obtained by dividing the difference between the ground voltage and the power supply voltage by 2. nFor example, if the display data is 6 bits, the gamma grayscale value is a value obtained by dividing the difference between the supply voltage and the ground voltage by 64 levels, and if the display data is 8 bits, the gamma grayscale value is a value obtained by dividing the difference between the supply voltage and the ground voltage by 256 levels.

[0011] In the current display device environment requiring high performance as well as high resolution, as the amount of data increases according to the high resolution, the gamma grayscale value increases. Figure 3 256 levels of gamma grayscale values ​​are shown when the data is 8 bits.

[0012] Figure 3 256 levels of gamma grayscale values ​​are shown when the data is 8 bits.

[0013] exist Figure 2 and Figure 3 In the comparative example, the decoder can be input so that each gamma line corresponds to each of the gamma grayscale values, and the decoder selects and outputs one of the multiple gamma grayscale values ​​according to the input data. That is, according to the comparative example, an increase in the amount of data according to the resolution means an increase in the gamma lines input to the decoder from the gamma block 40 as shown in the figure, and considering the design area and parasitic capacitance between each line, it is necessary to reduce the number of gamma lines. Summary of the invention

[0014] This Summary is provided to introduce selected concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0015] In general terms, a display device includes a decoder, which includes: a first switching control block, which is configured to select at least two first interval endpoint values ​​from a plurality of gamma grayscale values ​​based on predetermined high bits of input data; and a second switching control block, which is configured to select a second interval endpoint value from the selected at least two first interval endpoint values ​​based on predetermined low bits of the data and output the selected second interval endpoint value as at least two channel values.

[0016] When the gamma grayscale value is in the configuration interval, the second switching control block may include a non-interpolation control block configured to output the gamma grayscale value itself as at least two channel values ​​based on the input data.

[0017] The configuration interval may be one of a predetermined low grayscale interval, a medium grayscale interval, and a high grayscale interval.

[0018] The first switching control block may be configured to select at least two first interval endpoint values ​​from a plurality of gamma grayscale values ​​based on a first upper bit of the predetermined upper bits and a second upper bit of the predetermined upper bits.

[0019] The first switching control block may include: a NAND logic circuit, which is configured to output a first enable signal based on a first high bit and a second high bit; an inverter (NOT) circuit, which is configured to receive the first enable signal and output a second enable signal; and a selector, which is configured to select at least two first interval endpoint values ​​from the gamma grayscale level values ​​based on the first enable signal and the second enable signal.

[0020] The second switch control block may be configured to select two second interval endpoint values ​​based on the first lower bits, and combine and output the selected two second interval endpoint values ​​as at least two channel values ​​based on the second lower bits.

[0021] If the second low bit is the first condition, the second switching control block can select three first endpoint values ​​and one second endpoint value from the two second interval endpoint values ​​for combination and output; if the second low bit is the second condition, the second switching control block selects two first endpoint values ​​and two second endpoint values ​​from the two second interval endpoint values ​​for combination and output; if the second low bit is the third condition, the second switching control block selects three first endpoints and one second endpoint value from the two second interval endpoint values ​​for combination and output; and if the second low bit is the fourth condition, the second switching control block selects four second endpoint values ​​from the two second interval endpoint values ​​for combination and output.

[0022] The display device may further include: a source driver including an amplifier configured to average at least two channel values ​​and output a brightness value.

[0023] The amplifier may further include: a plurality of first amplifiers respectively configured to receive and amplify corresponding channel values; and a second amplifier configured to output a brightness value, wherein the brightness value may be obtained by adding and averaging output values ​​of the plurality of first amplifiers.

[0024] In general, a driving method for a display device is provided for outputting a channel value by receiving first data including multiple bits and second data including multiple level values, the method comprising: selecting multiple interval endpoint values ​​from the second data based on a predetermined number of high bits of the first data; and selecting at least two interval endpoint values ​​from the multiple interval endpoint values ​​based on a predetermined number of low bits of the first data and outputting them as channel values.

[0025] If the upper bits of the first data are a predetermined non-interpolation condition, the method may further include outputting a level value corresponding to the second data as the output channel value.

[0026] Selecting at least two interval endpoint values ​​and outputting them as channel values ​​may include: when the upper bits of the first data are the same, selecting the interval endpoint values ​​based on the first lower bits; and when the first lower bits are the same, combining and outputting the selected interval endpoint values ​​based on the changed second lower bits.

[0027] Two interval endpoint values ​​are selected to output four channel values, and combining the selected interval endpoint values ​​and outputting may further include: if the second lowest bit is the first condition, three first endpoint values ​​and three second endpoint values ​​are selected from the two interval endpoint values ​​to be combined and output; if the second lowest bit is the second condition, two first endpoint values ​​and two second endpoint values ​​are selected from the two interval endpoint values ​​to be combined and output; if the second lowest bit is the third condition, one first endpoint value and three second endpoint values ​​are selected from the two interval endpoint values ​​to be combined and output; and if the second lowest bit is the fourth condition, four second endpoint values ​​are selected from the two interval endpoint values ​​to be combined and output.

[0028] The interval endpoint value may be an output value corresponding to a value in which the upper bit and the first lower bit of the first data are the same and the second lower bits are all 1.

[0029] The method may further include averaging the channel values ​​to output a brightness value, wherein the first data is data input from the main controller, and the second data is a plurality of gamma grayscale values ​​input from the gamma block.

[0030] In general terms, a display device includes a decoder and a source driver, the decoder including: a non-interpolation control block, which is configured to output gamma grayscale values ​​of a predetermined interval among multiple gamma grayscale values ​​as channel values; a first switching control block, which is configured to select multiple interval endpoint values ​​among the remaining gamma grayscale values ​​based on predetermined high bits of data input from a main controller; and a second switching control block, which is configured to combine the selected multiple interval endpoint values ​​based on low bits of the data and output the combination of the multiple interval endpoint values ​​as multiple channel values, and wherein the source driver is configured to average the multiple channel values ​​and output the averaged value as a brightness value.

[0031] When a plurality of gamma grayscale values ​​are divided into a plurality of predetermined intervals, a maximum value among the gamma grayscale values ​​in each predetermined interval is set as an interval endpoint value.

[0032] The second switching control block is further configured to: if the number of low bits is n, then 2 of the selected interval endpoint value is nThe combined output is used as multiple channel values.

[0033] In general terms, a display device includes a decoder and a source driver, wherein the source driver is configured to average multiple channel values ​​and output the average value as a brightness value, wherein the decoder is configured to output the multiple channel values ​​by receiving N-bit data and multiple gamma grayscale values, and wherein the decoder includes: a rear switching control block, which is configured to combine two first interval endpoint values ​​based on the least significant two bits of the N-bit data to interpolate into the multiple channel values; an intermediate switching control block, which is configured to interpolate five second interval endpoint values ​​into the two first interval endpoint values ​​based on two middle bits before the least significant two bits in the N-bit data; and a front switching control block, which is configured to interpolate multiple gamma grayscale values ​​into five second interval endpoint values ​​based on four forward bits before the two middle bits in the N-bit data, wherein N is a natural number.

[0034] The data can be more than 8 bits, i.e., N>8, wherein the number of front switching control blocks is twice the number of remainder bits, wherein the remainder bits are at least two bits from the most significant bit to the previous bit of the four forward bits in the N-bit data, and wherein the decoder also includes a multiplexer, the multiplexer is configured to select any one of the multiple front switching control blocks based on the remainder bits, and output five second interval endpoint values ​​to the intermediate switching control block.

[0035] The decoder may further include a non-interpolation control block configured to output a gamma grayscale value of a predetermined interval among the plurality of gamma grayscale values ​​as the channel value.

[0036] In general terms, a display device includes a decoder, which includes: a front switching control block, which is configured to divide a plurality of gamma grayscale levels into a predetermined number of intervals based on the most significant four bits in 8-bit data, and output five interval endpoint values; a middle switching control block, which is configured to select and output two second interval endpoint values ​​from the five interval endpoint values; and a rear switching control block, which is configured to output a plurality of channel values ​​by combining the two second interval endpoint values.

[0037] Other features and aspects will be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is an example of a block diagram of a display device.

[0039] Figure 2 is an example of a block diagram of a source driver according to a comparative example.

[0040] Figure 3is a data decoding table showing the operation of the source driver according to the comparative example.

[0041] Figure 4 An example of a block diagram of a source driver according to one or more embodiments is shown.

[0042] Figure 5 is a data decoding table illustrating the operation of a source driver according to one or more embodiments.

[0043] Figure 6 is an example of a circuit diagram of a first switching control block according to one or more embodiments.

[0044] Figure 7 is an example of a block diagram of a second handover control block according to one or more embodiments.

[0045] Figure 8 is an example of a block diagram of a source driver according to one or more embodiments.

[0046] Fig. 9 is an example of a circuit diagram of a source driver according to one or more embodiments.

[0047] Fig.10 is an example of a circuit diagram of an amplification unit according to one or more embodiments.

[0048] Fig.11 is a graph illustrating output channel values ​​according to one or more embodiments.

[0049] Fig.12 is a graph illustrating output brightness values ​​according to one or more embodiments.

[0050] Like reference numerals refer to like elements throughout the drawings and detailed description. The drawings may not be to scale, and the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0051] The following detailed description is provided to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, after understanding the disclosure of the application, various changes, modifications and equivalents of the method, device and / or system described herein will be obvious. For example, the order of operations described herein is merely an example and is not limited to those set forth herein, but as will be apparent after understanding the disclosure of the application, it can be changed except for the operations that must occur in a specific order. Moreover, for greater clarity and brevity, the description of features known in the art may be omitted.

[0052] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided merely to illustrate some of the many possible ways to implement the methods, devices, and / or systems described herein, which will be apparent after understanding the disclosure of the present application.

[0053] Throughout the specification, when an element (e.g., a layer, a region, or a substrate) is described as being "on", "connected to", or "coupled to" another element, the element may be directly "on", "connected to", or "coupled to" another element, or one or more other elements may be present therebetween. In contrast, when an element is described as being "directly on", "directly connected to", or "directly coupled to" another element, there are no other elements present therebetween.

[0054] As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more of the associated listed items.

[0055] Although terms such as "first", "second", and "third" may be used herein to describe various components, parts, regions, layers, or portions, these components, parts, regions, layers, or portions are not limited by these terms. Instead, these terms are only used to distinguish one component, part, region, layer, or portion from another component, part, region, layer, or portion. Therefore, without departing from the teachings of the examples described herein, the first component, part, region, layer, or portion mentioned in the examples may also be referred to as the second component, part, region, layer, or portion.

[0056] As shown in the accompanying drawings, for ease of description, spatial relative terms such as "above", "above", "below", and "under" may be used herein to describe the relationship of one element to another element. In addition to the directions depicted in the drawings, such spatial relative terms are intended to cover different directions of the device in use or operation. For example, if the device in the drawings is turned over, an element described as "above" or "above" relative to another element will become "below" or "under" relative to the other element. Therefore, the term "above" includes both the upper direction and the lower direction according to the spatial direction of the device. The device can also be oriented in other ways (e.g., rotated 90 degrees or in other directions), and the spatial relative terms used in this article are interpreted accordingly.

[0057] The terms used herein are only used to describe various examples and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the articles "a", "an" and "the" are also intended to include plural forms. The terms "include", "comprise" and "have" specify the presence of the features, numbers, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, operations, components, elements and / or combinations thereof.

[0058] As will be apparent after understanding the disclosure of the present application, the features of the examples described herein can be combined in various ways. In addition, as will be apparent after understanding the disclosure of the present application, although the examples described herein have various configurations, other configurations are also feasible.

[0059] In the following disclosure, the word "a" in the singular may be used interchangeably with the term "at least one" and means one or more of the elements being described.

[0060] In the following disclosure, for ease of description, it is described that the display data is 8 bits and the gamma grayscale level value is 0 to 255, but the scope of the present disclosure is not limited to this, and it should be understood that depending on the resolution of the display device, the number of bits of the display data and the gamma grayscale level value can have different values.

[0061] In order to solve the above-mentioned problems, a display device including a decoder which reduces the number of gamma lines and thus reduces the size thereof and a driving method thereof are provided.

[0062] Figure 4 shows a block diagram of a source driver, and Figure 5 is an example of a data decoding table showing the operation of a source driver.

[0063] Reference Figure 4 , the source driver 10 includes a decoder 100 and an amplifier 500 .

[0064] The decoder 100 may receive display data (ie, first data) Data <n-1:0>and gamma input (i.e., second data), and can output at least two channel values. The channel value can be a gamma grayscale value in the second data corresponding to the input first data. In this article, it should be noted that, with respect to an example or implementation, for example, for what an example or implementation may include or implement, the use of the term "may" indicates that there is at least one example or implementation in which the feature is included or implemented, and all examples and implementations are not limited thereto.

[0065] The amplifier 500 averages the plurality of channel values ​​and outputs the average value as an output value. At this time, the output value may be a grayscale voltage value input to the display panel.

[0066] The decoder 100 includes a first switching control block 200 and a second switching control block 300 .

[0067] The first switching control block 200 selects at least two or more interval endpoint values ​​from a plurality of gamma grayscale values ​​based on a predetermined upper bit of the input data. That is, the first switching control block selects at least two interval endpoint values ​​from a plurality of gamma grayscale values ​​based on a first upper bit and a second upper bit of the predetermined upper bit.

[0068] Further references Figure 5 , assuming that the input data is 8 bits (ie n = 8, Data <n-1:0>The data is divided into 4 high bits D[7:4] and 4 low bits D[3:0]). The predetermined low bit can be divided into a first low bit D[3:2] and a second low bit D[1:0]. In this example, it is described that the input data is divided into two halves and is divided into high bits and low bits, but the example is not limited to this. According to another example, the data can be divided into high bits and low bits, and depending on the specific circuit implementation, the number of high bits / low bits may not be divided into two halves.

[0069] about Figure 5 The high bits D[7:4] in the source driver are all the same interval of '0001', and the output value of the source driver can have 16 gamma grayscale values ​​according to the change of the low bits D[3:0]. At this time, the number of intervals with the same first low bit is four, and each interval can have four values ​​according to the change of the second low bit. In the present disclosure, the intervals with the same high bit are referred to as the first unit interval, and the intervals with the same first low bit in the first unit interval are referred to as the second unit interval.

[0070] The interval endpoint value, which is a value corresponding to the maximum value of the second unit interval, is an output value corresponding to when all the second lowest bits are 1, and refers to Figure 5 , when D[7:0] is 00010011, the gamma grayscale value is B; when D[7:0] is 00010111, the gamma grayscale value is C; when D[7:0] is 00011011, the gamma grayscale value is D; and when D[7:0] is 00011111, the gamma grayscale value is E.

[0071] The first switching control block 200 selects five interval endpoint values ​​A, B, C, D, and E based on the high bit D[7:4]. At this time, the interval endpoint value A is the maximum value in the previous interval of the first unit interval, that is, the interval with the same high bit. In other words, A is the gamma grayscale value corresponding to the maximum value 1111 in the previous first unit interval, and its high bit is the same as 0000.

[0072] The second switching control block 300 selects at least two interval endpoint values ​​from the selected interval endpoint values ​​based on the predetermined low bits of the data, and outputs them as the channel value. That is, the second switching control block 300 selects at least two interval endpoint values ​​from the interval endpoint values ​​based on the first low bits D[3:2], and combines the interval endpoint values ​​based on the second low bits D[1:0] and outputs them as the channel value.

[0073] Described with reference to the illustrated example, the second switching control block 300 selects two interval endpoint values ​​(A and B, B and C, C and D, or D and E) from the five representative values ​​A, B, C, D, and E based on the first lower bit. For example, if D[7:2] is 000100, A and B can be selected as interval endpoint values, and the channel value can be output according to the second lower bit.

[0074] For example, if the second lowest bit is the first condition (00), one second interval endpoint value (B) and three first interval endpoint values ​​(A) are output as channel values. For example, if the second lowest bit is the second condition (01), two first interval endpoint values ​​(A) and two second interval endpoint values ​​(B) are output as channel values. For example, if the second lowest bit is the third condition (10), three second interval endpoint values ​​(B) and one first interval endpoint value (A) are output as channel values. For example, if the second lowest bit is the fourth condition (11), four second interval endpoint values ​​(B) are output as channel values.

[0075] The amplifier 500 receives a plurality of channel values, averages the channel values ​​and outputs them as a brightness value. In the above example, if the second lowest bit is the first condition (00), the brightness value is If the second lowest bit is the second condition (01), the brightness value is If the second lowest bit is the third condition (10), the brightness value is And if the second lowest bit is the fourth condition (11), the brightness value is

[0076] According to another example, the second switching control block may further include a non-interpolation control block.

[0077] The non-interpolation control block 400 may set an irrecoverable grayscale value, which is a value corresponding to a low grayscale value among gamma grayscale values, according to the resolution of the display device. Figure 4 and Figure 5 In the example of , the gamma grayscale value having 0 to 15 levels can be set to a non-interpolation range. However, the scope of the present disclosure is not limited thereto, and the gamma grayscale value can be set to a different range, for example, a predetermined low grayscale interval, a medium grayscale interval, or a high grayscale interval, depending on the resolution of the display device or the operating performance of the display device.

[0078] Therefore, since the decoder according to the example can select and decode the gamma grayscale value, the number of gamma lines can be reduced, and the size of the decoder itself including the pads connected to the gamma lines can be reduced. Moreover, the reduction in the number of gamma lines can reduce the influence of parasitic capacitance.

[0079] Figure 6 is a circuit diagram of a first switching control block according to an example of the present disclosure.

[0080] Reference Figure 6 , the first switching control block 200 includes a NAND logic circuit 210 , an inverter circuit 220 , and a plurality of selectors 230 .

[0081] The NAND logic circuit receives the first upper bits D[7:6] and the second upper bits D[5:4] and outputs a first enable signal EP.

[0082] The inverter circuit 220 inverts the first enable signal EP and generates a second enable signal EN.

[0083] The selection unit 230 may be a circuit that selects a representative value from a plurality of gamma lines, and may be implemented using a plurality of intervals, wherein a first unit interval and a second unit interval are the same except for an interval connected to the non-interpolation control block 400. Figure 6 In the embodiment, the selection units 231 to 235 may be included in the first unit interval, and if gamma grayscale values ​​having 0 to 15 levels are excluded when implementing 256-level gamma grayscale values, a total of 15×5=75 selectors are included.

[0084] Figure 7 is a block diagram of a second switching control block according to an example of the content of the present disclosure.

[0085] Reference Figure 7 , the second switching control block 300 may include a switching control block 350 and a non-interpolation control block 400, and may output the low gray value itself as a channel value with respect to data (Data[7:0]) corresponding to the low gray. Figure 5 , for example, if the gamma grayscale value is 0 and the data is 00000000, the non-interpolation control block 400 outputs the channel values ​​CH1, CH2, CH3, CH4 as 0, 0, 0, 0.

[0086] The switching control block 350 receives the interval endpoint values ​​(Go_A, Go_B, Go_C, Go_D, Go_E) from the first switching control block 200 and combines the interval endpoint values ​​according to predetermined lower bits D[3:0] to output channel values ​​(CH1 to CH4).

[0087] The switching control block 350 receives the first lower bits D[3:2] and selects two interval endpoint values ​​from the interval endpoint values. The non-interpolation control block 400 combines the interval endpoint values ​​selected based on the second lower bits D[1:0] to output a channel value.

[0088] For example, if the second lowest bit is the first condition (00), one second interval endpoint value (B) and three first interval endpoint values ​​(A) are output as channel values. For example, if the second lowest bit is the second condition (01), two first interval endpoint values ​​(A) and two second interval endpoint values ​​(B) are output as channel values. For example, if the second lowest bit is the third condition (10), three second interval endpoint values ​​(B) and one first interval endpoint value (A) are output as channel values. For example, if the second lowest bit is the fourth condition (11), four second interval endpoint values ​​(B) are output as channel values.

[0089] Figure 8 is an example of a source driver according to an example of the present disclosure. Figure 8 The implementation method is an example when the input data is 8 bits, and will refer to Figure 5 right Figure 8 The implementation method is described below.

[0090] Reference Figure 8 , the decoder includes a first switching control block 200, a second switching control block 351 and a third switching control block 352. Each switching control block may also be referred to as a front switching control block 200, a middle switching control block 351 and a rear switching control block 352.

[0091] The first switching control block 200 divides the plurality of gamma grayscale values ​​into four first intervals based on the most significant four bits in the 8-bit data, and each first interval has two first interval endpoint values ​​(AB or BC or CD or DE). For example, when Data[7:4]=0001, the first switching control block 200 outputs a total of five interval endpoint values ​​A, B, C, D and E to the second switching control block 351.

[0092] When five interval endpoint values ​​A, B, C, D and E are input, the second switching control block 351 outputs two second interval endpoint values. The two second interval endpoint values ​​are selected from any one of the plurality of first interval endpoint values ​​based on the two middle bits Data[3:2]. Figure 5 , when Data[3:2]=10, C and D become the second interval endpoint values ​​among the five interval endpoint values ​​A to E.

[0093] The third switching control block 352 outputs a plurality of channel values ​​by combining two second interval endpoint values. The number of channel values ​​may vary according to the number of second interval endpoint values. For example, if the number of second interval endpoint values ​​is M (M is a natural number), the number of channel values ​​may be a maximum of 2. M , but the number of channel values ​​can vary according to the design. Figure 5 In the example of , if D[1:0]=00, the channel value is output as three Cs and one D.

[0094] The decoder 100 may further include a non-interpolation control block 400 which does not perform interpolation corresponding to the first to third switching control blocks for a predetermined section.

[0095] Fig. 9 is a circuit diagram of a source driver according to an example of the present disclosure.

[0096] Fig. 9 Assume that the resolution of a display panel increases. Figure 8 It is described based on 256 gray levels and 8-bit data, but Fig. 9 Assume that the gamma grayscale value exceeds 256 grayscale levels and 8-bit data.

[0097] Fig. 9 The decoder 100 includes a plurality of first switching control blocks 200, a multiplexer 250, a second switching control block 351 and a third switching control block 352. Figure 8 overlap, so the detailed description will be omitted.

[0098] The third switching control block 352 combines the last two interval endpoint values ​​based on the least significant two bits Data[1:0] in the N-bit data, and outputs the result as a plurality of channel values. The second switching control block 352 outputs the five intermediate interval endpoint values ​​as the final two interval endpoint values ​​based on the two first data D[3:2], which are the two bits before the least significant bit in the N-bit data.

[0099] and Figure 8 Different, in Fig. 9 In the example of , a plurality of first switching control blocks 200 are included. When the data is greater than 8 bits (N>8), the number of first switching control blocks 200 becomes 2. (N-8) For example, when the data is 10 bits, the number of the first switching control blocks 200 included in the decoder 100 is four.

[0100] The multiplexer 250 selects any one of the plurality of first switching control blocks 200 and connects the selected multiplexer to the second switching control block 351. More specifically, referring to Figure 5 , if the data is 10 bits, then according to the number of examples of the most significant two bits (a total of 10 bits - 8 bits) of the bits D[9:8], the 8 bits D[7:0] starting from the least significant bit are repeated 4 times from [00010000] to [00011111]. In this case, an interval is selected according to D[9:8] and connected to the second switching control block 351.

[0101] If the data is 12 bits, then according to the most significant 4 bits (= a total of 12 bits - 8 bits), the interval where D[7:0] is from [00010000] to [00011111] is repeated a total of 16 times. In this example, the multiplexer can be implemented in two levels. More specifically, the first multiplexer can select any one of the first multiplexers corresponding to D[7:0] based on D[9:8], and connect the selected multiplexer to the second multiplexer. The second multiplexer selects any one of the four first multiplexers based on one D[11:10], and connects the selected multiplexer to the second switching control block 352.

[0102] The decoder 100 may further include a non-interpolation control block 400 which does not perform interpolation corresponding to the first to third switching control blocks for a predetermined grayscale interval.

[0103] Fig.10 is a circuit diagram of an amplifier according to an example of the present disclosure.

[0104] Amplifier 500 may include a plurality of amplifiers.

[0105] For example, Fig.10 As shown, the amplifier 500 can be implemented as a two-stage amplification device. When there are four channel values, it can include: a first amplifier 510 that receives and amplifies two channel values ​​and two feedback brightness values; and a second amplifier 550 that adds the output values ​​of the first amplifier to output an average brightness value.

[0106] The first amplifier 510 includes a plurality of individual unit amplifiers 511-514. The number of individual amplifiers including the first amplifier 510 may depend on the number of input channels in the amplifier 500. Four channel values ​​are applied to the positive input of each of the individual amplifiers 511-514, respectively. The feedback value of the source output (SOURCE_OUTPUT) is applied to the negative input of all individual amplifiers. The output of an individual amplifier may be connected to the output of an adjacent individual amplifier.

[0107] For example, the positive outputs of the first single amplifier 511 and the second single amplifier 512 may be connected to each other as a node N1. The negative outputs of the first single amplifier 511 and the second single amplifier 512 may be connected to each other as a node N2. The positive outputs of the third single amplifier 513 and the fourth single amplifier 514 may be connected to each other as a node N1. The negative outputs of the third single amplifier 513 and the fourth single amplifier 514 may be connected to each other as a node N2. The node N1 and the node N2 may respectively have the summed value of the multiple outputs of the single amplifier. The node N1 and the node N2 may be applied to the input of the second amplifier 550. The second amplifier 550 has two inputs N1, N2, and outputs SOURCE_OUTPUT as an average value.

[0108] In the above example, if the second lowest bit is the first condition (00), the channel values ​​CH1, CH2, CH3, CH4 are A, A, A, B and the brightness value SOURCE_OUTPUT is If the second lowest bit is the second condition (01), the channel values ​​CH1, CH2, CH3, CH4 are A, A, B, B and the brightness value SOURCE_OUTPUT is If the second lowest bit is the third condition (10), the channel values ​​CH1, CH2, CH3, CH4 are A, B, B, B and the brightness value SOURCE_OUTPUT is And if the second lowest bit is the fourth condition (11), the channel values ​​CH1, CH2, CH3, CH4 are B, B, B, B and the brightness value SOURCE_OUTPUT is

[0109] Fig.11 is a graph showing output of channel values ​​according to an example, and Fig.12 is a graph showing output of brightness values ​​according to another example.

[0110] Reference Fig.11 , for 256 levels of data, as shown in the figure, the grayscale value is output in each channel of the decoder according to the example. The curves of the output values ​​CH1, CH2, CH3, CH4 of each channel may be different because they are output by combining the interval endpoint values ​​as described above. However, it can be seen that if all channel values ​​are represented by the average value and the non-interpolated grayscale value, the gamma grayscale value (i.e., the full grayscale) can be fully restored, as shown in Fig.12 shown.

[0111] A decoder according to various examples may select and decode a gamma grayscale value, and the size and gamma line of the decoder itself may be reduced.

[0112] The decoder according to various examples may reduce the number of gamma lines so that the influence of parasitic capacitance may be reduced.

[0113] The source driver according to various examples may reduce a circuit area by reducing the size of a decoder, thereby making a driving circuit thinner and smaller while maintaining a high resolution of a display device.

[0114] Although the present disclosure includes specific examples, it is obvious after understanding the disclosure of the present application that various changes in form and detail can be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are considered to be descriptive only, not for the purpose of limitation. The description of the features or aspects in each example will be considered to be applicable to similar features or aspects in other examples. If the described techniques are performed in a different order, and / or if the components in the described systems, architectures, devices, or circuits are combined in different ways, and / or replaced or supplemented by other components or their equivalents, suitable results can be achieved. Therefore, the scope of the present disclosure is not limited by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents will be interpreted as included in the present disclosure.

Claims

1. A display device, comprising a decoder, wherein the decoder comprises: a first switching control block configured to select at least two interval endpoint values ​​from a plurality of gamma grayscale values ​​based on predetermined upper bits of input data, and output the at least two interval endpoint values; as well as A second switching control block is configured to select two interval endpoint values ​​from the outputted at least two interval endpoint values ​​based on predetermined lower bits of the input data, and output the selected two interval endpoint values ​​as at least two channel values.

2. The display device according to claim 1, wherein: When the gamma grayscale value is in a configuration interval, the second switching control block includes a non-interpolation control block configured to output the gamma grayscale value itself as the at least two channel values ​​based on the input data.

3. The display device according to claim 2, wherein: The configuration interval is one of a predetermined low grayscale interval, a medium grayscale interval, or a high grayscale interval.

4. The display device according to claim 1, wherein: The first switching control block is configured to select at least two interval endpoint values ​​from among the plurality of gamma grayscale values ​​based on a first upper bit of the predetermined upper bits and a second upper bit of the predetermined upper bits.

5. The display device according to claim 4, wherein: The first switching control block includes: a NAND logic circuit configured to output a first enable signal based on the first upper bit and the second upper bit; an inverter NOT circuit configured to receive the first enable signal and output a second enable signal; and A selector is configured to select at least two interval endpoint values ​​from the gamma grayscale values ​​based on the first enable signal and the second enable signal.

6. The display device according to claim 1, wherein: The second switching control block is configured to select two interval endpoint values ​​based on the first lower bits, and combine the selected two interval endpoint values ​​based on the second lower bits and output them as the at least two channel values.

7. The display device according to claim 6, wherein: If the second low bit is the first condition, the second switching control block selects three first endpoint values ​​and one second endpoint value; If the second low bit is a second condition, the second switching control block selects two first endpoint values ​​and two second endpoint values; If the second lower bit is a third condition, the second switching control block selects a first endpoint value and three second endpoint values; and If the second lower bit is a fourth condition, the second switching control block selects four second endpoint values.

8. The display device according to claim 1, wherein: The display device further includes: A source driver includes an amplifier configured to average the at least two channel values ​​and output a brightness value.

9. The display device according to claim 8, wherein: The amplifier further comprises: a plurality of first amplifiers respectively configured to receive and amplify at least two channel values; and a second amplifier configured to output the brightness value, The brightness value is obtained by adding and averaging the output values ​​of the plurality of first amplifiers.

10. A method for driving a display device, for outputting a channel value by receiving first data including a plurality of bits and second data including a plurality of gradation values, the method comprising: Selecting and outputting a plurality of interval endpoint values ​​from the second data based on a predetermined number of high bits of the first data; as well as Two interval endpoint values ​​are selected from the outputted plurality of interval endpoint values ​​based on a predetermined number of lower bits of the first data and are outputted as channel values.

11. The method according to claim 10, wherein: If the upper bits of the first data are a predetermined non-interpolation condition, the method further includes outputting a level value corresponding to the second data as a channel value.

12. The method according to claim 10, wherein: Selecting two interval endpoint values ​​as channel values ​​includes: When the upper bits of the first data are the same, selecting two interval endpoint values ​​based on the first lower bits; and When the first lower bits are the same, the selected two interval endpoint values ​​are combined based on the changed second lower bits.

13. The method according to claim 12, wherein: Two interval endpoint values ​​are selected to output four channel values, and Combining the selected two interval endpoint values ​​further comprises: If the second lower bit is the first condition, three first endpoint values ​​and one second endpoint value are selected from the two interval endpoint values ​​to be combined and output; If the second lower bit is the second condition, two first endpoint values ​​and two second endpoint values ​​are selected from the two interval endpoint values ​​to be combined and output; If the second lower bit is the third condition, selecting a first endpoint value and three second endpoint values ​​from the two interval endpoint values ​​to be combined and output; and If the second lower bit is the fourth condition, four second endpoint values ​​are selected from the two interval endpoint values ​​to be combined and output.

14. The method according to claim 12, wherein: The multiple interval endpoint values ​​are output values ​​corresponding to values ​​in which the upper bit of the first data and the first lower bit are the same and the second lower bits are all 1.

15. The method according to claim 10, further comprising: The channel values ​​are averaged to output a brightness value, and The first data is data input from a main controller, and the second data is a plurality of gamma grayscale values ​​input from a gamma block.

16. A display device comprising a decoder and a source driver, in, The decoder comprises: a non-interpolation control block configured to output gamma grayscale values ​​of a predetermined interval among gamma grayscale values ​​as a plurality of channel values; a first switching control block configured to select a plurality of interval endpoint values ​​among the remaining gamma grayscale values ​​based on a predetermined upper bit of data input from the main controller, and output the plurality of interval endpoint values; and a second switching control block configured to select two interval endpoint values ​​from the outputted plurality of interval endpoint values ​​based on the lower bits of the data and output the two plurality of interval endpoint values ​​as a plurality of channel values, and The source driver is configured to average the multiple channel values ​​and output the average value as the brightness value.

17. The display device according to claim 16, in, When the gamma grayscale value is divided into a plurality of predetermined intervals, a maximum value among the gamma grayscale values ​​in each predetermined interval is set as a plurality of interval endpoint values.

18. The display device according to claim 16, in, The second switching control block is further configured to: if the number of the lower bits is n, then 2 of the two selected interval endpoint values ​​are n The combined output is used as multiple channel values.

19. A display device comprising a decoder and a source driver, in, The source driver is configured to average a plurality of channel values ​​and output the average value as a brightness value, wherein the decoder is configured to output the plurality of channel values ​​by receiving N-bit data and a plurality of gamma grayscale values, and Wherein, the decoder comprises: a front switching control block configured to interpolate the plurality of gamma grayscale values ​​into five interval endpoint values ​​based on four forward bits preceding the two middle bits in the N-bit data, and output the five interval endpoint values, an intermediate switching control block configured to interpolate five interval endpoint values ​​into two interval endpoint values ​​based on two intermediate bits preceding the least significant two bits in the N-bit data, and a post-switching control block configured to combine two interval endpoint values ​​based on the least significant two bits of the N-bit data to interpolate into the plurality of channel values, Wherein, N is a natural number.

20. The display device according to claim 19, in, The data is more than 8 bits, that is, N>8, The number of the front switching control blocks is twice the number of the remaining bits. The remaining bits are at least two bits from the most significant bit to the previous bit of the four forward bits in the N-bit data, and The decoder further comprises a multiplexer configured to select any one of a plurality of front switching control blocks based on the remainder bits and output the five interval endpoint values ​​to the middle switching control block.

21. The display device according to claim 19, in, The decoder further includes a non-interpolation control block configured to output gamma grayscale values ​​of a predetermined interval among the plurality of gamma grayscale values ​​as a plurality of channel values.

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