Semiconductor chip and method of manufacturing the same

Abstract

This invention provides a semiconductor chip and a method for manufacturing the same. The semiconductor chip includes: a substrate; an interlayer insulating layer including a bottom interlayer insulating layer on the upper surface of the substrate and a top interlayer insulating layer on the bottom interlayer insulating layer; an etch stop layer located between the bottom and top interlayer insulating layers; a ground pad located on the interlayer insulating layer; and a through-hole connected to the ground pad via the substrate, the interlayer insulating layer, and the etch stop layer. The etch stop layer is isolated to prevent direct contact with the ground pad.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0104738, filed on September 3, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor chips and methods of manufacturing the same, and more specifically to semiconductor chips comprising through-silicon vias and methods of manufacturing the same. Background Technology

[0004] By actively developing three-dimensional semiconductor packages, each equipped with multiple semiconductor chips contained in a single semiconductor package, it is possible to develop technologies that ensure the reliability of interconnect structures by using silicon vias to form vertical electrical connections through a substrate or die. Summary of the Invention

[0005] The present invention provides a semiconductor chip for ensuring the reliability of a connection structure by using through-silicon vias.

[0006] The present invention provides a method for manufacturing a semiconductor chip, wherein the semiconductor chip ensures the reliability of the interconnect structure by using through-silicon vias.

[0007] The concept of the present invention is not limited to the foregoing, but those skilled in the art will clearly understand other exemplary embodiments not described herein based on the following description.

[0008] According to some example embodiments, a semiconductor chip may include: a substrate; an interlayer insulating layer including a bottom interlayer insulating layer on an upper surface of the substrate and a top interlayer insulating layer on the bottom interlayer insulating layer; an etch stop layer located between the bottom interlayer insulating layer and the top interlayer insulating layer; a grounding pad located on the interlayer insulating layer; and a through-hole connected to the grounding pad via the substrate, the interlayer insulating layer, and the etch stop layer. The etch stop layer may be isolated to prevent direct contact with the grounding pad.

[0009] According to some example embodiments, a semiconductor chip may include: a substrate; an interlayer insulating layer located on an upper surface of the substrate, the interlayer insulating layer surrounding a semiconductor device; an intermetallic insulating layer surrounding metal wiring and including a bottom intermetallic insulating layer on the interlayer insulating layer and a top intermetallic insulating layer on the bottom intermetallic insulating layer; an etch stop layer located between the bottom intermetallic insulating layer and the top intermetallic insulating layer; a ground pad located on the intermetallic insulating layer; a bump structure located on the ground pad; and a through-hole connected to the ground pad via the substrate, the interlayer insulating layer, the intermetallic insulating layer, and the etch stop layer. The etch stop layer may be isolated to prevent direct contact with the ground pad.

[0010] According to some example embodiments, a method of manufacturing a semiconductor chip may include: forming a semiconductor device on a first surface of a substrate; forming a bottom interlayer insulating layer on the first surface of the substrate such that the bottom interlayer insulating layer surrounds the semiconductor device; forming an etch stop layer on the bottom interlayer insulating layer; forming a top interlayer insulating layer on the etch stop layer; forming a ground pad on the top interlayer insulating layer such that the ground pad is isolated from direct contact with the etch stop layer; forming a preliminary through-hole extending from a second surface of the substrate opposite to the first surface of the substrate through the substrate to expose the etch stop layer; forming a via insulating layer on the inner wall of the preliminary through-hole to define the through-hole; widening the bottom of the through-hole to expose the ground pad; and forming a via filling the through-hole. Attached Figure Description

[0011] Exemplary embodiments of the invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a plan view illustrating a semiconductor chip according to some example embodiments.

[0013] Figure 2 It is shown Figure 1 A cross-sectional view of a portion of the main configuration area and a portion of the through-hole area.

[0014] Figure 3 yes Figure 2 A magnified view of region CX.

[0015] Figure 4 This is a cross-sectional view of a semiconductor chip according to some example embodiments.

[0016] Figure 5 This is a cross-sectional view of a semiconductor chip according to some example embodiments.

[0017] Figure 6 This is a cross-sectional view of a semiconductor chip according to some example embodiments.

[0018] Figure 7 It is shown Figure 1 A cross-sectional view of a portion of the main configuration area and a portion of the through-hole area.

[0019] Figure 8 yes Figure 7 A magnified view of region CX2.

[0020] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 as well as Figure 17 This is a cross-sectional view illustrating a method for manufacturing a semiconductor chip in process sequence according to some example embodiments.

[0021] Figure 18 This is a cross-sectional view showing the main configuration of a semiconductor package containing a semiconductor chip according to some example embodiments.

[0022] Figure 19 This is a plan view showing a semiconductor module containing a semiconductor chip according to some example embodiments.

[0023] Figure 20 This is a block diagram illustrating a system comprising a semiconductor chip according to some example embodiments.

[0024] Explanation of icon numbers

[0025] 100, 100A, 100B, 100C, 100D, 220, 1030: Semiconductor chips;

[0026] 110: Substrate;

[0027] 110F1: First surface;

[0028] 110F2: Second surface;

[0029] 120: Interlayer insulation layer;

[0030] 120B, 121B: Bottom interlayer insulation layer;

[0031] 120B_T, 120T_T, ESL_T: Thickness;

[0032] 120T, 121T: Top interlayer insulation layer;

[0033] 122: Semiconductor device;

[0034] 124: Wiring structure;

[0035] 130: Intermetallic insulation layer;

[0036] 130B: Insulation layer between bottom metals;

[0037] 130T: Top metal interlayer insulation layer;

[0038] 132: Multi-layer wiring structure;

[0039] 132W: Wiring layer;

[0040] 132P: Wiring via;

[0041] 134: Grounding pad;

[0042] 134B: Grounding pad barrier layer;

[0043] 134W: Grounding pad metal layer;

[0044] 134BU, 134WU, 156U, ESL_U: Top surface;

[0045] 142: First pad;

[0046] 144: Passivation layer;

[0047] 144H: Opening;

[0048] 146: Protrusion structure;

[0049] 146P: Column;

[0050] 146S: Solder layer;

[0051] 150, 222, 232: Through holes;

[0052] 150H: Through hole;

[0053] 150HP: Initial breakthrough of the hole;

[0054] 150S, 156S1, 156S2: sidewalls; 150T1: first width;

[0055] 150T2: Second width;

[0056] 152: Conductive plug;

[0057] 152L: Bottom;

[0058] 154: Conductive barrier layer;

[0059] 154S1: Part One;

[0060] 154S2: Part Two;

[0061] 156: Through-hole insulation layer;

[0062] 162: Second pad;

[0063] 172: Supporting substrate;

[0064] 174: Adhesive layer;

[0065] 200: Semiconductor packaging;

[0066] 210: Packaging substrate;

[0067] 212: Internal wiring of the substrate;

[0068] 214: Connecting terminal;

[0069] 216: Solder ball;

[0070] 230, 1020: Control chips;

[0071] 240: Sealing component;

[0072] 250: Connecting component;

[0073] 1000: Semiconductor module;

[0074] 1010: Module substrate;

[0075] 1050: Input / output terminals;

[0076] 1100: System;

[0077] 1110: Controller;

[0078] 1120: I / O device;

[0079] 1130: Memory;

[0080] 1140: Interface;

[0081] 1150: Bus;

[0082] CX, CX2: Region;

[0083] ESL: Etching stop layer;

[0084] ESL_C: Central part;

[0085] ESL_P: Peripheral portion;

[0086] ESL1: First etch stop layer;

[0087] ESL2: Second etch stop layer;

[0088] ESL_L: Layer surface, lower surface;

[0089] h1, h2: Height;

[0090] MCR: Main configuration area;

[0091] PR1: First peripheral circuit region;

[0092] PR2: Second peripheral circuit region;

[0093] TVR: Through-hole area. Detailed Implementation

[0094] The following description will be based on the accompanying drawings and will be a detailed description of exemplary embodiments.

[0095] Figure 1 This is a plan view showing a semiconductor chip 100 according to some example embodiments. Figure 2 It is shown Figure 1 A cross-sectional view of a portion of the main configuration area and a portion of the through-hole area. Figure 3 yes Figure 2 A magnified view of region CX.

[0096] See Figures 1 to 3 The semiconductor chip 100 may include a substrate 110, which includes multiple main configuration regions (MCRs) and multiple through-hole regions (TVRs).

[0097] Multiple memory cells can be placed in multiple main configuration regions (MCRs). A first peripheral circuit region (PR1) can be placed on one side of each of the multiple main configuration regions (MCRs), and a second peripheral circuit region (PR2) can be placed on the other side of each of the multiple main configuration regions (MCRs).

[0098] In some example embodiments, a row decoder connected to memory cells contained in multiple main configuration regions MCR may be placed in a first peripheral circuit region PR1, and a column decoder connected to memory cells contained in multiple main configuration regions MCR may be placed in a second peripheral circuit region PR2.

[0099] In other embodiments, additional driving elements for driving multiple memory cells, such as control logic units, sense amplifiers, and page buffers, may be additionally disposed in the first peripheral circuit region PR1 and the second peripheral circuit region PR2.

[0100] Multiple through-holes 150 passing through the substrate 110 can be disposed in the through-hole region TVR. Signals can be received from an external terminal via the through-holes 150, or the signals can be transmitted to an external terminal via the through-holes 150.

[0101] The arrangement of the main configuration region MCR, the first peripheral circuit region PR1, the second peripheral circuit region PR2, and the through-hole region TVR is shown in the figures, but modifications are possible and not limited thereto. In other embodiments, unlike the figures, the main configuration region MCR may be positioned at the center of the substrate 110, and the first peripheral circuit region PR1, the second peripheral circuit region PR2, and the through-hole region TVR may be arranged to one-dimensionally surround the main configuration region MCR.

[0102] Substrate 110 may include a first surface 110F1 and a second surface 110F2. Substrate 110 may include a semiconductor substrate, such as silicon (Si), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some example embodiments, substrate 110 may have a silicon-on-insulator (SOI) structure. For example, substrate 110 may include a buried oxide (BOX) layer. In some example embodiments, substrate 110 may include conductive regions (e.g., impurity-doped wells or impurity-doped structures). Similarly, substrate 110 may have various isolation structures, such as shallow trench isolation (STI) structures.

[0103] The first surface 110F1 of the substrate 110 may be referred to as the active surface. An interlayer insulating layer 120 may be disposed on the first surface 110F1 of the substrate 110. The interlayer insulating layer 120 may be disposed to surround a plurality of semiconductor devices 122 and wiring structures 124 respectively disposed on the substrate 110. The plurality of semiconductor devices 122 may each include a memory device or a logic device.

[0104] Memory devices can be volatile or non-volatile. Volatile memory devices may include, for example, volatile memory devices such as dynamic random access memory (DRAM), static random access memory (SRAM), or thyristor random access memory (TRAM), as well as volatile memory devices currently under development. Similarly, non-volatile memory devices may include, for example, non-volatile memory devices such as flash memory, magnetic random access memory (MRAM), spin-transfer torque MRAM (STT-MRAM), ferroelectric random access memory (FRAM), phase change random access memory (PRAM), or resistance random access memory (RRAM), as well as non-volatile memory devices currently under development.

[0105] The logic device may be implemented as, for example, a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, an audio codec, a video codec, an application processor, or a system-on-chip (SOC), but is not limited thereto.

[0106] Multiple semiconductor devices 122 are electrically connected to wiring structure 124 and may be surrounded by interlayer insulating layer 120. Interlayer insulating layer 120, the multiple semiconductor devices 122 surrounded by interlayer insulating layer 120, and wiring structure 124 may be referred to as a front-end-of-line (FEOL) structure, enabling... Figure 1 The semiconductor chip 100 illustrated herein includes a FEOL structure on the upper surface (110F1) of a substrate 110. As described herein, an interlayer insulating layer 120 may be part of the FEOL structure.

[0107] The interlayer insulating layer 120 may comprise a low-dielectric material having a dielectric constant lower than that of silicon oxide, silicon nitride, or silicon oxynitride. The low-dielectric material contained in the interlayer insulating layer 120 may be a material with a dielectric constant lower than that of silicon oxide and may have improved insulation properties, enabling the semiconductor chip 100 to be highly integrated and operate at high speeds.

[0108] In a semiconductor chip 100 according to some example embodiments, the position of the interlayer insulating layer 120 relative to the etch stop layer ESL may include a bottom interlayer insulating layer 120B disposed between the first surface 110F1 of the substrate 110 and the etch stop layer ESL, and a top interlayer insulating layer 120T disposed on the etch stop layer ESL. That is, the semiconductor chip 100 may be arranged in a stacked structure, wherein the etch stop layer ESL is disposed on the bottom interlayer insulating layer 120B, and the top interlayer insulating layer 120T is disposed on the etch stop layer ESL. In other words, in some example embodiments (including those illustrated in...), Figures 1 to 3 In the example embodiment, the first surface 110F1 of the substrate 110 may be referred to as the upper surface of the substrate 110, and the interlayer insulating layer 120 may be understood as including a bottom interlayer insulating layer 120B on the upper surface of the substrate 110 and a top interlayer insulating layer 120T on the bottom interlayer insulating layer 120B, wherein the etch stop layer ESL is located between the bottom interlayer insulating layer 120B and the top interlayer insulating layer 120T.

[0109] It should be understood that an element described as being "on" another element may be "above" or "below" the other element. Furthermore, it should be understood that an element described as being "on" another element may be "directly" on the other element such that the elements are in direct contact with each other, or an element may be "indirectly" on the other element such that the elements are isolated from each other by one or more insertion spaces and / or structures to prevent direct contact.

[0110] In some example embodiments, the bottom interlayer insulating layer 120B may be configured such that silicon oxide, such as phosphor silicate glass (PSG), boro-phosphor silicate glass (BPSG), undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), plasma-enhanced TEOS (PE-TEOS), and high-density plasma-chemical vapor deposition (HDP-CVD) oxides, are arranged on a single layer or in a stacked structure.

[0111] An etch stop layer (ESL) may be placed between the bottom interlayer insulating layer 120B and the top interlayer insulating layer 120T forming the interlayer insulating layer 120. Similarly, the etch stop layer (ESL) may be kept away from the ground pad 134 by at least the top interlayer insulating layer 120T ("isolated to avoid direct contact").

[0112] In some example embodiments, the thickness 120B_T of the bottom interlayer insulating layer 120B may be greater than the thickness ESL_T of the etch-stop layer ESL, and the thickness ESL_T of the etch-stop layer ESL may be substantially equal to or greater than the thickness 120T_T of the top interlayer insulating layer 120T. As described herein, a thickness “substantially” equal to another thickness is to be understood as equal to another thickness within manufacturing tolerances and / or material tolerances.

[0113] Generally, in the etching process that forms the through-hole 150H, some of the metal material contained in the ground pad 134 may be exposed due to the etching distribution of each of the central and peripheral portions of the substrate 110 and the thickness distribution of the interlayer insulating layer 120. Therefore, in the etching process that forms the through-hole 150H, the etch stop layer (ESL) can solve the problem of the upper surface of the ground pad 134 being exposed at undesired process stages due to over-etching.

[0114] The material contained in the etch stop layer ESL may have etch selectivity relative to the material contained in the bottom interlayer insulating layer 120B. For example, when the bottom interlayer insulating layer 120B contains silicon oxide, the etch stop layer ESL may contain silicon nitride.

[0115] As described above, since the etch stop layer ESL is located between the bottom interlayer insulating layer 120B and the top interlayer insulating layer 120T of the interlayer insulating layer 120, the etching process for forming the through hole 150H can include the process of exposing the etch stop layer ESL and the process of exposing the upper surface of the ground pad 134, thereby minimizing the degree to which the upper surface of the ground pad 134 is exposed in non-desired process stages due to the etch distribution.

[0116] An intermetallic insulating layer 130 may be disposed on an interlayer insulating layer 120, and the intermetallic insulating layer 130 may be disposed to surround a multilayer wiring structure 132 disposed on the interlayer insulating layer 120. The multilayer wiring structure 132 may include a plurality of wiring layers 132W and a plurality of wiring vias 132P. The multilayer wiring structure 132 may be simply referred to herein as "metallic wiring". In some example embodiments, the intermetallic insulating layer 130 may have a stacked structure of multiple insulating layers, and each of the plurality of insulating layers may be disposed to surround a portion of a corresponding wiring layer of the plurality of wiring layers 132W and a portion of a corresponding wiring via of the plurality of wiring vias 132P. The intermetallic insulating layer 130 and the multilayer wiring structure 132 surrounded by the intermetallic insulating layer 130 may be referred to as a back-end-of-line (BEOL) structure. Therefore, it should be understood that... Figure 1 The illustrated semiconductor chip 100 may include a BEOL structure on the FEOL structure of the semiconductor chip 100.

[0117] Such as at least Figures 1 to 3 As illustrated, ground pad 134 may be located on interlayer insulation layer 120, and at least a portion of ground pad 134 may be surrounded by intermetallic insulation layer 130. Ground pad 134 may be part of multilayer wiring structure 132 disposed in via region TVR.

[0118] The ground pad 134 may include a ground pad metal layer 134W and a ground pad barrier layer 134B. The ground pad barrier layer 134B may be disposed to surround the upper surface 134WU and side surfaces of the ground pad metal layer 134W.

[0119] In this document, the surface of the ground pad barrier layer 134B that is closer to the interlayer insulation layer 120 or the substrate 110 on the two surfaces of the ground pad barrier layer 134B that extends in the horizontal direction (X direction or Y direction) may be referred to as the upper surface 134BU of the ground pad barrier layer 134B.

[0120] Additionally, the surface of the ground pad metal layer 134W facing the interlayer insulation layer 120 and extending in the horizontal direction (X direction or Y direction) can be referred to as the upper surface 134WU of the ground pad metal layer 134W, and the surface opposite to the upper surface 134WU can be referred to as the lower surface of the ground pad metal layer 134W.

[0121] In some example embodiments, the ground pad metal layer 134W may comprise nickel (Ni), copper (Cu), aluminum (Al), gold (Au), tungsten (W), or combinations thereof, but is not limited thereto. The ground pad barrier layer 134B may comprise at least one material selected from: W, tungsten nitride (WN), tungsten carbide (WC), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), cobalt (Co), manganese (Mn), Ni, and nickel boride (NiB), but is not limited thereto.

[0122] A first pad 142 may be disposed on an intermetallic insulating layer 130, and a passivation layer 144 comprising an opening 144H exposing at least a portion of the upper surface of the first pad 142 may be disposed on the intermetallic insulating layer 130. The first pad 142 may comprise Al, Ni, Cu, or a combination thereof, and the passivation layer 144 may comprise polyimide or silicon nitride, but is not limited thereto.

[0123] A bump structure 146 comprising pillars 146P and a solder layer 146S can be disposed on a first pad 142. The bump structure 146 may comprise pillars 146P and a solder layer 146S, which are sequentially stacked on the first pad 142. In some example embodiments, pillars 146P may comprise Cu, Ni, or an alloy thereof, and solder layer 146S may comprise tin (Sn), silver (Ag), lead (Pb), Au, Cu, boron (B), or an alloy thereof. However, pillars 146P and solder layer 146S are not limited thereto.

[0124] As shown, the first pad 142 and the bump structure 146 can be placed in the through-hole region TVR, and optionally, the first pad 142 and the bump structure 146 can be additionally placed in the main configuration region MCR.

[0125] The via 150 can pass through (“extend”) the substrate 110 and the interlayer insulating layer 120 and can be electrically connected to the ground pad 134. The via 150 may include a conductive plug 152 and a conductive barrier layer 154.

[0126] A through-hole 150 can be disposed in a through-hole 150H that passes through the substrate 110 and the interlayer insulating layer 120. Therefore, and as at least Figure 2 As illustrated, the via 150 extends through the substrate 110, the interlayer insulating layer 120, and the etch stop layer ESL, thereby connecting the via 150 to the ground pad 134 via the substrate 110, the interlayer insulating layer 120, and the etch stop layer ESL. The via 150H extends vertically (Z-direction) from the second surface 110F2 of the substrate 110 to the first surface 110F1, and a conductive barrier layer 154 and a conductive plug 152 can be sequentially disposed on the inner wall of the via 150H.

[0127] The conductive plug 152 may extend from the second surface 110F2 via the first surface 110F1 of the substrate 110, and the bottom surface 152L of the conductive plug 152 may be disposed at a horizontal height below the bottom surface of the interlayer insulating layer 120. In other words, the bottom surface 152L of the conductive plug 152 may be disposed further away from the first surface 110F1 of the substrate 110 than the bottom surface of the interlayer insulating layer 120.

[0128] In some example embodiments, the conductive plug 152 may comprise Cu, copper-tin (CuSn), copper-magnesium (CuMg), copper-nickel (CuNi), copper-zinc (CuZn), copper-palladium (CuPd), copper-gold (CuAu), copper-rhenium (CuRe), copper-tungsten (CuW), W, or W alloys, but is not limited thereto.

[0129] The conductive barrier layer 154 may be disposed to surround the sidewalls and bottom surface 152L of the conductive plug 152. In some example embodiments, the conductive barrier layer 154 may comprise at least one material selected from, but is not limited to, W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB.

[0130] The via insulating layer 156 may surround a large portion of the sidewall of the conductive barrier layer 154, said large portion being a limited portion of the sidewall of the via 150. For example, such as at least Figure 3 As illustrated, the via insulating layer 156 may surround most of the sidewalls of the via 150, such that a first portion 154S1 of the sidewalls of the conductive barrier layer 154 providing a first portion of the sidewalls of the via 150 is covered by the via insulating layer 156, and a second portion 154S2 of the sidewalls of the conductive barrier layer 154 providing a second portion of the sidewalls of the via 150 is exposed by the via insulating layer 156. The via insulating layer 156 may act as an insulating spacer to prevent direct contact between the substrate 110 and the conductive material contained in the via 150. Similarly, the via insulating layer 156 may directly contact the etch-stop layer ESL and may be positioned away from (“isolated from direct contact”) the ground pad 134, such that the via insulating layer 156 does not directly contact the ground pad 134. As at least Figure 3 As illustrated, portions 154S1 and 154S2 may collectively include the sidewall 150S of the through-hole 150 that directly contacts the via insulating layer 156, the etch-stop layer ESL, the top interlayer insulating layer 120T, and the ground pad 134. Figures 2 to 3The diagram further illustrates that one sidewall 156S1 of the via insulating layer 156 can directly contact the via 150, and the other sidewall 156S2 of the via insulating layer 156 can directly contact the substrate 110 and the bottom interlayer insulating layer 120B. Additionally, the upper surface 156U of the via insulating layer 156, opposite the upper surface (110F1) of the substrate 110, can directly contact the surface ESL_L of the etch stop layer ESL.

[0131] The via insulating layer 156 may comprise silicon oxide, silicon nitride, silicon carbide, a polymer, or a combination thereof. In some example embodiments, a chemical vapor deposition (CVD) process may be used to form the via insulating layer 156. The thickness of the via insulating layer 156 may be from about 500 angstroms to about 3000 angstroms, but is not limited thereto.

[0132] Additionally, one sidewall of the via insulating layer 156 can directly contact the via 150, and the other sidewall of the via insulating layer 156 can directly contact the substrate 110 and the interlayer insulating layer 120. The upper surface of the via insulating layer 156 can have a structure that directly contacts the lower surface ESL_L of the etch-stop layer ESL. Figure 3 As illustrated, the lower surface ESL_L of the etch-stop layer ESL facing the upper surface (110F1) of the substrate 110 can directly contact the via insulating layer 156 and the bottom interlayer insulating layer 120B. For example... Figure 3 The diagram further shows that the upper surface ESL_U of the etch stop layer ESL, which is opposite to the upper surface (110F1) of the substrate 110, can directly contact the top interlayer insulating layer 120T and can not directly contact the via insulating layer 156 and the ground pad 134.

[0133] That is, regarding the through hole 150, the sidewall of the through hole 150 may have a structure that directly contacts the through hole insulating layer 156, the etch stop layer ESL, the top interlayer insulating layer 120T, and the ground pad 134.

[0134] The second surface 110F2 of the substrate 110 may be referred to as a passive surface. A second pad 162 connected to the through-hole 150 may be disposed on the second surface 110F2 of the substrate 110. The second pad 162 may contain Al, Ni, Cu or a combination thereof, but is not limited thereto.

[0135] As shown, the through-hole 150 can pass through the substrate 110 and the interlayer insulating layer 120, and can be electrically connected to the ground pad 134. To allow only the conductive barrier layer 154 to directly contact the ground pad metal layer 134W, a conductive plug 152 can be placed without directly contacting the ground pad metal layer 134W.

[0136] Although described below, the method of manufacturing a semiconductor chip 100 according to some example embodiments may use a via last method, which corresponds to the method of first forming a ground pad 134 and an intermetallic insulating layer 130 on a first surface 110F1 of a substrate 110 to form a via 150, and then forming the via 150.

[0137] Generally, the methods for forming the via 150 can include the pre-via method, the middle via method, and the post-via method. The pre-via method can refer to the method of forming the via 150 before forming the integrated circuit of the semiconductor device, the middle via method can refer to the method of forming the via 150 after forming the integrated circuit of the semiconductor device but before forming the wiring layer, and the post-via method can refer to the method of forming the via 150 after forming the wiring layer.

[0138] For example, in the post-via method, multiple semiconductor devices 122, wiring structures 124 and interlayer insulating layers 120 may be formed on the first surface 110F1 of the substrate 110, ground pads 134, multilayer wiring structures 132 and intermetallic insulating layers 130 may be formed on the interlayer insulating layer 120, and through-holes 150H may be formed from the second surface 110F2 of the substrate 110 through the substrate 110 and the interlayer insulating layer 120.

[0139] Specifically, in a method of manufacturing a semiconductor chip 100 according to some example embodiments, a preliminary through-hole 150HP (see [reference]) may first be formed extending through the substrate 110 into the interior of the interlayer insulating layer 120 and exposing the etch stop layer ESL. Figure 10 The through-hole insulating layer 156 can be formed in the initial through-hole 150HP (see...). Figure 10 On the inner wall of the through hole 150H, the bottom of the through hole 150H can be further enlarged until the upper surface 134WU of the grounding pad metal layer 134W is exposed, and the conductive barrier layer 154 can be formed on the inner wall of the through hole 150H.

[0140] In a semiconductor chip different from the semiconductor chip 100 according to some example embodiments, the etch stop layer (ESL) may be omitted, and the through-hole 150H may be formed in a single etch process. In this case, due to the etch distribution, a portion of the ground pad metal layer 134W may be etched during the formation of the through-hole 150H, and the metal material contained in the exposed ground pad metal layer 134W may remain in the through-hole 150H without being removed and may attach to the sidewalls of the through-hole 150H (e.g., substrate 110 or interlayer insulating layer 120). Therefore, substrate 110 or interlayer insulating layer 120 may be contaminated with metal material, and due to this, sufficient insulation properties of substrate 110 or interlayer insulating layer 120 may not be guaranteed.

[0141] On the other hand, in the semiconductor chip 100 according to some example embodiments, since the etch stop layer ESL is disposed between the bottom interlayer insulating layer 120B and the top interlayer insulating layer 120T of the interlayer insulating layer 120, the etching process for forming the through hole 150H may include a process for exposing the etch stop layer ESL and a process for exposing the upper surface of the ground pad 134.

[0142] Therefore, the extent to which the upper surface of the ground pad 134 is exposed in undesirable process stages due to etch distribution can be minimized. Similarly, after the process of exposing the etch-stop layer ESL, the via insulation layer 156 can be conformally formed on the sidewall of the initial through-hole 150HP (see...). Figure 10 The via insulating layer 156 can act as a protective layer on the surfaces of the substrate 110 and the interlayer insulating layer 120, and thus on the exposed etch stop layer ESL.

[0143] Therefore, in the process of exposing the upper surface of the ground pad 134, the metal material contained in the ground pad metal layer 134W can be prevented from directly adhering to the sidewall of the substrate 110 or the interlayer insulating layer 120, and thus, contamination of the metal material in the substrate 110 or the interlayer insulating layer 120 can be prevented, thereby enabling the semiconductor chip 100 to have good reliability.

[0144] Figure 4 This is a cross-sectional view of a semiconductor chip 100A according to some example embodiments and is corresponding to Figure 2 A magnified view of region CX.

[0145] The following describes the elements configured for semiconductor chip 100A, and the materials contained in each of the elements are substantially the same (e.g., the same within manufacturing and / or material tolerances) or similar to those described in the reference above. Figures 1 to 3 The given description. Therefore, for ease of description, the following text will mainly describe semiconductor chip 100A and semiconductor chip 100 (see... Figure 3 The difference between ).

[0146] See Figure 4 In a semiconductor chip 100A according to some example embodiments, the through-hole 150 and the ground pad 134 may each have a sidewall configuration with a certain slope.

[0147] The process of forming the through-hole 150H can begin from the second surface 110F2 of the substrate 110 and can be performed in the direction toward the ground pad 134. In terms of the characteristics of the anisotropic etching process for forming the through-hole 150H, the width of the through-hole 150H can gradually decrease toward the ground pad 134.

[0148] Therefore, the configuration of the through-hole 150 disposed in the through-hole 150H can be based on the configuration of the through-hole 150H. That is, the through-hole 150 can have a sidewall configuration in which a first width 150T1 that directly contacts a portion of the substrate 110 is wider than a second width 150T2 that directly contacts a portion of the ground pad 134. Therefore, and as Figure 4 As illustrated, at least a portion of the through-hole 150 may have a cross-sectional width that gradually and / or continuously narrows in a direction extending away from the second surface 110F2 (e.g., the bottom surface) of the substrate 110 along the longitudinal axis of at least a portion of the through-hole 150, and gradually and / or continuously narrows in proportion to the distance of the cross-section of the portion of the through-hole 150 from the second surface 110F2 (e.g., the bottom surface) of the substrate 110, such that in a portion of the through-hole 150, the width of a given cross-section of the through-hole 150 is proportional to the distance of the given cross-section from the second surface 110F2 (e.g., the bottom surface) of the substrate 110.

[0149] On the other hand, the process of forming the ground pad hole (not shown) can begin from the intermetallic insulating layer 130 corresponding to the direction opposite to the second surface 110F2 of the substrate 110, and can be performed in the direction toward the intermetallic insulating layer 120. In terms of the characteristics of the anisotropic etching process for forming the ground pad hole, the width of the ground pad hole can gradually decrease toward the intermetallic insulating layer 120.

[0150] Therefore, the configuration of the ground pad 134 disposed in the ground pad hole can be based on the configuration of the ground pad hole. That is, the ground pad 134 can have a sidewall configuration in which a second width 134T2, a portion spaced apart from the through hole 150, is wider than the first width 134T1, a portion directly contacting the through hole 150. Therefore, and as Figure 4 As illustrated, the ground pad 134 may have a cross-sectional width that gradually and / or continuously widens in a direction extending away from the second surface 110F2 (e.g., the bottom surface) of the substrate 110 along the longitudinal axis of the ground pad 134, wherein the longitudinal axis of the ground pad 134 may be the same as the longitudinal axis of the through-hole 150, and wherein the cross-sectional width of the ground pad 134 gradually and / or continuously widens in proportion to the distance of the cross-section of the ground pad 134 from the second surface 110F2 (e.g., the bottom surface) of the substrate 110, such that the width of a given cross-section of the ground pad 134 widens in proportion to the distance of the given cross-section from the second surface 110F2 (e.g., the bottom surface) of the substrate 110.

[0151] As described above, a method of manufacturing a semiconductor chip 100A according to some example embodiments may use a post-via method, wherein a ground pad 134 and an intermetallic insulating layer 130 are first formed on a first surface 110F1 of a substrate 110 to form a via 150, and then the via 150 is formed.

[0152] In this case, the direction of the etching process for etching the through-hole 150H relative to the substrate 110 may be different from the direction of the etching process for etching the ground pad hole. Therefore, as shown, at least a portion of the through-hole 150 may have an inverted trapezoidal shape, wherein its width gradually decreases away from the substrate 110, and the ground pad 134 may have a trapezoidal shape, wherein its width gradually increases away from the substrate 110.

[0153] Figure 5 This is a cross-sectional view of a semiconductor chip 100B according to some example embodiments and is corresponding to Figure 2 A magnified view of region CX.

[0154] The components of the semiconductor chip 100B described below, and the materials contained in each of the components, are substantially the same as those described in the reference above. Figures 1 to 3 The descriptions given are the same or similar. Therefore, for ease of description, the following text will mainly describe semiconductor chip 100B and semiconductor chip 100 (see...). Figure 3 The difference between ).

[0155] See Figure 5 In the semiconductor chip 100B according to some example embodiments, the material contained in the bottom interlayer insulating layer 121B may be different from the material contained in the top interlayer insulating layer 121T. In other words, the material composition of the bottom interlayer insulating layer 121B may be different from the material composition of the top interlayer insulating layer 121T.

[0156] Relative to the location of the etch stop layer ESL, the interlayer insulating layer 121 may include a bottom interlayer insulating layer 121B disposed between the first surface 110F1 of the substrate 110 and the etch stop layer ESL, and a top interlayer insulating layer 121T disposed on the etch stop layer ESL. That is, the semiconductor chip 100 can be arranged in a stacked structure, wherein the etch stop layer ESL is disposed on the bottom interlayer insulating layer 121B, and the top interlayer insulating layer 121T is disposed on the etch stop layer ESL.

[0157] The bottom interlayer insulating layer 121B can be disposed in a structure in which silicon oxide (such as PSG, BPSG, USG, TEOS, PE-TEOS, and HDP CVD oxide) is arranged on a single layer or in a stacked structure. The material contained in the etch stop layer ESL can be etch-selective relative to the material contained in the bottom interlayer insulating layer 121B (“the material”). For example, when the bottom interlayer insulating layer 121B contains silicon oxide, the etch stop layer ESL can contain silicon nitride.

[0158] In the semiconductor chip 100B according to some example embodiments, the etch rate of the material contained in the top interlayer insulating layer 121T, unlike the bottom interlayer insulating layer 121B, may be equal to or similar to the etch rate of the material contained in the etch stop layer ESL. That is, the material contained in the bottom interlayer insulating layer 121B (e.g., the material composition of the bottom interlayer insulating layer 121B) may be different from the material contained in the top interlayer insulating layer 121T (e.g., the material composition of the top interlayer insulating layer 121T).

[0159] Figure 6 This is a cross-sectional view of a semiconductor chip 100C according to some example embodiments and is corresponding to Figure 2 A magnified view of region CX.

[0160] The following describes the components that configure the semiconductor chip 100C, and the materials contained in each of the components are generally the same as those described in the above reference. Figures 1 to 3 The descriptions given are the same or similar. Therefore, for ease of description, the following text will mainly describe semiconductor chip 100C and semiconductor chip 100 (see...). Figure 3 The difference between ).

[0161] See Figure 6 According to some example embodiments, a semiconductor chip 100C may include an etch stop layer ESL, which includes a first etch stop layer ESL1 and a second etch stop layer ESL2.

[0162] In a semiconductor chip 100C according to some example embodiments, the interlayer insulating layer 120 may include a bottom interlayer insulating layer 120B that directly contacts the first etch-stop layer ESL1 and a top interlayer insulating layer 120T that directly contacts the second etch-stop layer ESL2, relative to the location of the etch-stop layer ESL. That is, the semiconductor chip 100C according to some example embodiments may be arranged in a stacked structure, wherein the first etch-stop layer ESL1 is disposed on the bottom interlayer insulating layer 120B, the second etch-stop layer ESL2 is disposed on the first etch-stop layer ESL1, and the top interlayer insulating layer 120T is disposed on the second etch-stop layer ESL2.

[0163] The etch-stop layer (ESL) can be configured as a multilayer structure in which a first etch-stop layer (ESL1) and a second etch-stop layer (ESL2) are stacked sequentially. The thickness of the first etch-stop layer (ESL1) may be equal to or different from the thickness of the second etch-stop layer (ESL2). In the figures, the etch-stop layer (ESL) is shown as comprising two stacked layers (e.g., a first etch-stop layer (ESL1) and a second etch-stop layer (ESL2), but is not limited thereto. In other embodiments, depending on the circumstances, the etch-stop layer (ESL) may comprise three or more layers.

[0164] Furthermore, the material composition of the first etch-stop layer ESL1 may differ from that of the second etch-stop layer ESL2. For example, the first etch-stop layer ESL1 may contain a material that is etch-selective relative to the material contained in the bottom interlayer insulating layer 120B, and the second etch-stop layer ESL2 may contain the same material as the bottom interlayer insulating layer 120B. Therefore, in some example embodiments (including...) Figure 6 As shown in the example embodiment, the etch stop layer ESL may comprise a stack of multiple different material layers (e.g., a first etch stop layer ESL1 and a second etch stop layer ESL2).

[0165] In this way, the first etch stop layer ESL1 and the second etch stop layer ESL2 may contain different materials (e.g., different material compositions), the materials being based on the relative relationship between the bottom interlayer insulating layer 120B and the top interlayer insulating layer 120T to facilitate etching processes on the through hole 150H.

[0166] Figure 7 It is shown Figure 1 A cross-sectional view of a portion of the main configuration area MCR and a portion of the through-hole area TVR. Figure 8 yes Figure 7 A magnified view of region CX2.

[0167] The components of the semiconductor chip 100D described below, and the materials contained in each of the components, are substantially the same as those described in the reference above. Figures 1 to 3 The descriptions given are the same or similar. Therefore, for ease of description, the following text will mainly describe semiconductor chip 100D and semiconductor chip 100 (see...). Figure 3 The difference between ).

[0168] See Figure 7 and Figure 8 In a semiconductor chip 100D according to some example embodiments, a through-hole 150 may be provided through the substrate 110, the interlayer insulating layer 120, and the intermetallic insulating layer 130. Therefore, and as at least... Figures 7 to 8As illustrated, the via 150 extends through the substrate 110, the interlayer insulating layer 120, the intermetallic insulating layer 130, and the etch stop layer ESL, such that the via 150 is connected to the first pad 142 via the substrate 110, the interlayer insulating layer 120, the intermetallic insulating layer 130, and the etch stop layer ESL, wherein the etch stop layer ESL is isolated to prevent direct contact with the first pad 142.

[0169] Such as at least Figure 8 As shown in the figure, the via insulating layer 156 can directly contact the substrate 110, the interlayer insulating layer 120, the bottom intermetallic insulating layer 130B and the etch stop layer ESL, and the via insulating layer 156 can not directly contact the top intermetallic insulating layer 130T and the first pad 142.

[0170] Such as at least Figure 8 The diagram further illustrates that the lower surface ESL_L of the etch-stop layer ESL facing the upper surface (110F1) of the substrate 110 can directly contact the via insulating layer 156 and the bottom intermetallic insulating layer 130B, and the upper surface ESL_U of the etch-stop layer ESL opposite to the upper surface (110F1) of the substrate 110 can directly contact the top intermetallic insulating layer 130T but may not directly contact the via insulating layer 156 and the first pad 142. It should be understood that components described herein that do not directly contact another component may be isolated to prevent direct contact with another component.

[0171] The through-hole 150 may include a first outer wall portion surrounded by a substrate 110, a second outer wall portion surrounded by an interlayer insulating layer 120, and a third outer wall portion surrounded by an intermetallic insulating layer 130.

[0172] The through-hole 150 provides electrical contact with the first pad 142 located on the intermetallic insulating layer 130. That is, it corresponds to the semiconductor chip 100 (see...). Figure 3 A portion of the ground pad 134 can be a first pad 142 in the semiconductor chip 100D. To electrically connect the via 150 to the multilayer wiring structure 132, the first pad 142 can extend from the intermetallic insulating layer 130. For example... Figure 7 As illustrated, a portion of the multilayer wiring structure 132 extends through the etch-stop layer ESL and directly contacts the first pad 142.

[0173] In a semiconductor chip 100D according to some example embodiments, an intermetallic insulating layer 130 may include a bottom intermetallic insulating layer 130B disposed between an interlayer insulating layer 120 and an etch-stop layer ESL, and a top intermetallic insulating layer 130T disposed on the etch-stop layer ESL. That is, the semiconductor chip 100D according to some example embodiments may be configured in a stacked structure, wherein the etch-stop layer ESL is disposed on the bottom intermetallic insulating layer 130B and the top intermetallic insulating layer 130T is disposed on the etch-stop layer ESL. Alternatively, the intermetallic insulating layer 130 may include a bottom intermetallic insulating layer 130B on the interlayer insulating layer 120 and a top intermetallic insulating layer 130T on the bottom intermetallic insulating layer 130B, wherein the etch-stop layer ESL is located between the bottom intermetallic insulating layer 130B and the top intermetallic insulating layer 130T.

[0174] It should be understood that the semiconductor chip 100D may include a FEOL structure on the upper surface (110F1) of the substrate 110 and a BEOL structure on the FEOL structure, wherein the interlayer insulating layer 120 is part of the FEOL structure, and each of the multilayer wiring structure 132 and the intermetallic insulating layer 130 is part of the BEOL structure.

[0175] An etch stop layer (ESL) can be disposed between the bottom intermetallic insulating layer 130B and the top intermetallic insulating layer 130T. Similarly, the etch stop layer (ESL) can be disposed away from the first pad 142 via the top intermetallic insulating layer 130T. In some example embodiments (including those illustrated in at least...), Figures 7 to 8 In the example embodiment, the etch stop layer ESL can be part of the BEOL structure.

[0176] Generally, in the etching process for forming the through-hole 150H, some of the metal material contained in the first pad 142 may be exposed due to the etching distribution of each of the central and peripheral portions of the substrate 110, the thickness distribution of the interlayer insulating layer 120, and the thickness distribution of the intermetallic insulating layer 130. Therefore, in the etching process for forming the through-hole 150H, the etch stop layer (ESL) can solve the problem of the upper surface of the first pad 142 being exposed in undesirable process stages due to over-etching.

[0177] The material contained in the etch stop layer ESL can be etch-selective relative to the material contained in the bottom intermetallic insulating layer 130B. For example, when the bottom intermetallic insulating layer 130B contains silicon oxide, the etch stop layer ESL can contain silicon nitride.

[0178] As described above, since the etch stop layer ESL is disposed between the bottom intermetallic insulating layer 130B and the top intermetallic insulating layer 130T of the intermetallic insulating layer 130, the etching process for forming the through hole 150H may include a process for exposing the etch stop layer ESL and a process for exposing the upper surface of the first pad 142, thereby minimizing the extent to which the upper surface of the first pad 142 is exposed in non-desired process stages due to the etch distribution.

[0179] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 as well as Figure 17 This is a cross-sectional view illustrating a method for manufacturing a semiconductor chip in process sequence according to some example embodiments.

[0180] In detail, Figure 9 , Figure 10 , Figure 12 , Figure 13 , Figure 15 , Figure 16 as well as Figure 17 It is shown Figure 1 A cross-sectional view of a portion of the main configuration area MCR and a portion of the through-hole area TVR. Figure 11 yes Figure 10 A magnified view of region CX, and Figure 14 yes Figure 13 A magnified view of region CX.

[0181] See Figure 9 Multiple semiconductor devices 122 and wiring structures 124 may be formed on a first surface 110F1 of substrate 110, and an interlayer insulating layer 120 covering (“enclosing”) the multiple semiconductor devices 122 and wiring structures 124 may be formed on the first surface 110F1 of substrate 110, such that a bottom interlayer insulating layer 120B is formed on the first surface 110F1 of substrate 110 and surrounds the semiconductor devices 122, an etch stop layer ESL is formed on the bottom interlayer insulating layer 120B, and a top interlayer insulating layer 120T is formed on the etch stop layer ESL.

[0182] An etch stop layer (ESL) may be disposed between a bottom interlayer insulating layer 120B and a top interlayer insulating layer 120T of interlayer insulating layer 120. The interlayer insulating layers 120 may be arranged in a stacked structure, wherein the etch stop layer ESL is disposed on the bottom interlayer insulating layer 120B and the top interlayer insulating layer 120T is disposed on the etch stop layer ESL. The material contained in the etch stop layer ESL (“Material”) may have etch selectivity relative to the material contained in the bottom interlayer insulating layer 120B (“Material”). For example, when the bottom interlayer insulating layer 120B contains silicon oxide, the etch stop layer ESL may contain silicon nitride. In some example embodiments, the formation of the etch stop layer ESL may include forming a first etch stop layer ESL1 on the bottom interlayer insulating layer 120B and forming a second etch stop layer ESL2 on the first etch stop layer ESL1, wherein the second etch stop layer ESL2 contains a material composition different from that of the first etch stop layer ESL1.

[0183] Ground pad 134, multilayer wiring structure 132, and intermetallic insulating layer 130 covering ground pad 134 and multilayer wiring structure 132 can be formed on interlayer insulating layer 120, so that ground pad 134 is isolated from direct contact with etch stop layer ESL.

[0184] In some example embodiments, the process of forming the ground pad 134 and the multilayer wiring structure 132 may include a damascene process. For example, an intermetallic insulating layer 130 may be formed on the interlayer insulating layer 120, and by patterning the intermetallic insulating layer 130, wiring holes (not shown) may be formed in the main configuration region MCR and ground pad holes (not shown) may be formed in the via region TVR. Subsequently, the ground pad 134 may be formed in the ground pad hole, and the wiring layer 132W may be formed in the wiring hole. For example, for forming the ground pad barrier layer 134B (see... Figure 3 The first layer and the metal layer 134W used to form the ground pad (see) Figure 3 The second layer can be sequentially formed in the ground pad hole, and then the intermetallic insulating layer 130 is exposed by planarizing the upper portion of each of the first and second layers, and the ground pad barrier layer 134B (see Figure 3 ) and grounding pad metal layer 134W (see Figure 3 It can be left in the grounding pad hole.

[0185] In some example embodiments, the ground pad barrier layer 134B can be formed via physical vapor deposition (PVD) or CVD processes using W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB (see [link to example embodiment]). Figure 3The grounding pad metal layer 134W can be formed by electroplating using Ni, Cu, Al, Au, W, or combinations thereof (see...). Figure 3 For example, in the 134W metal layer of the ground pad (see...) Figure 3 In the process, a Cu-containing seed layer (not shown) can be formed on the ground pad barrier layer 134B (see...). Figure 3 On top of the seed layer, a Cu layer can be formed by electroplating.

[0186] Subsequently, by repeating a process similar to that used to form the ground pad 134, a multilayer wiring structure 132, including wiring vias 132P and wiring layers 132W, can be formed on the ground pad 134.

[0187] Subsequently, a conductive layer (not shown) may be formed on the intermetallic insulating layer 130, and a first pad 142 may be formed by patterning the conductive layer. The first pad 142 may be formed using Al, Ni, Cu, or a combination thereof.

[0188] Subsequently, a passivation layer 144 exposing a portion of the first pad 142 may be formed on the intermetallic insulating layer 130. The passivation layer 144 may be formed using polyimide or silicon nitride.

[0189] The bump structure 146 is electrically connected to the first pad 142 exposed via the passivation layer 144, thereby forming the bump structure 146 on the first pad 142. For example, the bump structure 146 may have a structure comprising pillars 146P and a solder layer 146S. The pillars 146P can be formed by electroplating using Cu, Ni, or alloys thereof. The solder layer 146S can be formed by sequentially performing electroplating and reflow processes using Sn, Ag, Pb, Au, Cu, B, or alloys thereof. The formation of the bump structure 146 can be referenced below at least... Figures 15 to 17 Further details are provided after the through hole 150 is formed.

[0190] See Figure 10 and Figure 11 The support substrate 172 can be attached to the bump structure 146 and the passivation layer 144. The support substrate 172 can be attached to the bump structure 146 and the passivation layer 144 via the adhesive layer 174. Subsequently, a portion corresponding to a certain thickness can be removed from the second surface 110F2 of the substrate 110 by performing a polishing process on the second surface 110F2 of the substrate 110.

[0191] A mask pattern (not shown) may be formed on the second surface 110F2 of the substrate 110, and the substrate 110 may be etched to form a preliminary through-hole 150HP by using the mask pattern as an etch mask. The preliminary through-hole 150HP may extend (“extend”) the substrate 110 from the second surface 110F2 of the substrate 110 opposite to the first surface 110F1 of the substrate 110 to expose the etch stop layer ESL.

[0192] The exposed surface of the etch-stop layer (ESL) can have a configuration where the central portion protrudes beyond the peripheral portion. In other words, and as at least... Figure 11 As illustrated, forming the initial through-hole 150HP allows the height h1 of the central portion ESL_C of the exposed surface of the etch-stop layer ESL to be greater than the height h2 of the peripheral portion ESL_P of the exposed surface of the etch-stop layer ESL. This configuration can occur for two reasons. In the first reason, during the etching process of etching the initial through-hole 150HP, negative charges can accumulate on the exposed sidewalls of the interlayer insulating layer 120, and the negative charges exert an attraction on the etch cations generated in the etching process, allowing the peripheral portion of the etch-stop layer ESL adjacent to the sidewalls of the interlayer insulating layer 120 to be etched relatively more. In the second reason, as the sidewalls of the interlayer insulating layer 120 are etched to a certain slope, the linearity of the etch cations can be relatively weakened, and therefore, the peripheral portion of the etch-stop layer ESL can be etched relatively more.

[0193] In the relatively small remaining peripheral portion of the etch-stop layer ESL, the etching process can be performed on the initial through-hole 150HP to avoid exposing the top interlayer insulating layer 120T.

[0194] In some example embodiments, the initial through-hole 150HP can be made via an isotropic etching process or a laser drilling process. Due to the etch stop layer ESL, the initial through-hole 150HP may not completely penetrate the interlayer insulation layer 120, and therefore, the upper surface of the ground pad 134 may be covered by the top interlayer insulation layer 120T and the etch stop layer ESL without being exposed by the initial through-hole 150HP.

[0195] The preliminary through-hole 150HP can be formed to have various widths, depths, and shapes. In some example embodiments, as shown in the figures, the preliminary through-hole 150HP can be formed to have sidewalls perpendicular to the first surface 110F1 of the substrate 110. In other embodiments, during the process of forming the preliminary through-hole 150HP, the sidewalls of the preliminary through-hole 150HP can be etched to have a certain slope, and therefore, the upper width of the preliminary through-hole 150HP can be set to be greater than the lower width of the preliminary through-hole 150HP, thereby creating the above-referenced... Figure 4The semiconductor chip 100A is described.

[0196] It can form an initial through-hole of 150HP that exposes the etch-stop layer ESL, and then remove the mask pattern.

[0197] See Figure 12 Conformal coverage of the initial through-hole 150HP (see...) Figure 11 The via insulating layer 156 of the sidewall and the exposed surface of the etch stop layer ESL can be formed on the second surface 110F2 of the substrate 110 and the inner wall 150HS of the preliminary through hole 150HP, thereby defining the through hole 150H.

[0198] The through-hole insulating layer 156 may comprise silicon oxide, silicon nitride, silicon carbide, a polymer, or a combination thereof. In some example embodiments, a CVD process may be used to form the through-hole insulating layer 156. For example, the through-hole insulating layer 156 may comprise silicon oxide formed by a low-temperature CVD process. The thickness of the through-hole insulating layer 156 may be from about 500 angstroms to about 3000 angstroms.

[0199] The via insulating layer 156 can be formed to cover the entire exposed surface of the etch-stop layer ESL. That is, the upper surface of the ground pad 134 can be covered by the top interlayer insulating layer 120T, the etch-stop layer ESL, and the via insulating layer 156, without being exposed by the through-hole 150H. In other words, and as at least... Figure 12 As illustrated, the via insulating layer 156 may be formed by conformally forming the via insulating layer 156 on the sidewalls of the substrate 110, the sidewalls of the bottom interlayer insulating layer 120B, and the exposed surface of the etch stop layer ESL.

[0200] See Figure 13 and Figure 14 The through-hole 150H can be extended downwards by removing the bottom through-hole insulating layer 156, the etch stop layer ESL, the top interlayer insulating layer 120T, and the ground pad barrier layer 134B, thus exposing the upper surface 134WU of the ground pad metal layer 134W. In other words, and as... Figures 13 to 14 As shown in the illustration, the bottom of the through hole 150H can be enlarged to expose the grounding pad 134.

[0201] Such as at least Figures 13 to 14 As illustrated, the enlargement of the bottom of the through-hole 150H may include etching the exposed surface of the through-hole insulating layer 156 to expose the etch stop layer ESL, etching the exposed surface of the etch stop layer ESL to expose the top interlayer insulating layer 120T, and etching the exposed surface of the top interlayer insulating layer 120T to expose the ground pad 134.

[0202] The ground pad metal layer 134W can be stopped during the etching process of etching through-hole 150H, and therefore, the upper surface 134WU of the ground pad metal layer 134W surrounded by the ground pad barrier layer 134B can be exposed by the through-hole 150H.

[0203] In other words, the material layer exposed by the through-hole 150H may include a via insulating layer 156, an etch-stop layer ESL, a top interlayer insulating layer 120T, a ground pad barrier layer 134B, and a ground pad metal layer 134W. In this document, the via insulating layer 156, the etch-stop layer ESL, and the top interlayer insulating layer 120T may each contain insulating material, and the ground pad barrier layer 134B and the ground pad metal layer 134W may each contain conductive material.

[0204] See Figure 15 The conductive barrier layer 154 can be formed on the inner wall of the through hole 150H. The conductive barrier layer 154 can be formed by using W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni or NiB via PVD process, electroplating process or electroless electroplating process.

[0205] The conductive barrier layer 154 may be conformally formed to cover the via insulating layer 156, etch stop layer ESL, top interlayer insulating layer 120T, and ground pad barrier layer 134B, each exposed on the sidewall of the via 150H. Similarly, the conductive barrier layer 154 may be conformally formed to cover the ground pad metal layer 134W on the bottom of the via 150H.

[0206] See Figure 16 A conductive plug 152 filling the interior of the through-hole 150H can be formed on the conductive barrier layer 154. The conductive plug 152 can be formed by electroplating using Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W or W alloy.

[0207] For example, to form the conductive plug 152, a metal seed layer (not shown) may be formed on the surface of the conductive barrier layer 154, and then a metal layer filling the through-hole 150H may be formed on the conductive barrier layer 154 by electroplating using the metal seed layer. The metal seed layer may comprise Cu, Cu alloy, Co, Ni, Ru, Co / Cu, or Ru / Cu, and a PVD process for forming the metal seed layer may be used. The electroplating process may be performed at a temperature of about 10°C to about 65°C. In some example embodiments, the electroplating process may be performed at room temperature. Depending on the circumstances, after forming the conductive plug 152, an annealing process may be performed on the material obtained by forming the conductive plug 152 at a temperature of about 150°C to about 450°C.

[0208] See Figure 17 By performing a chemical mechanical polishing (CMP) process on the resulting material containing the conductive plug 152, the second surface 110F2 of the substrate 110 is exposed, and the conductive plug 152 and the conductive barrier layer 154 can remain only in the internal portion of the through-hole 150H. Therefore, a through-hole 150 filling the through-hole 150H can be formed.

[0209] See again Figure 2 A conductive layer (not shown) may be formed on the second surface 110F2 of the substrate 110, and by patterning the conductive layer, a second pad 162 electrically connected to the through hole 150 may be formed.

[0210] In the method of manufacturing the semiconductor chip 100 described above, by forming an etch stop layer ESL between the bottom interlayer insulating layer 120B and the top interlayer insulating layer 120T of the interlayer insulating layer 120, the etching process for etching the through-hole 150H may include a process for exposing the etch stop layer ESL and a process for exposing the upper surface of the ground pad 134, thereby minimizing the extent to which the upper surface of the ground pad 134 is exposed in undesired process stages due to etch distribution. Similarly, after the process of exposing the etch stop layer ESL, a via insulating layer 156 may be conformally formed on the sidewalls of the through-hole 150H and the exposed etch stop layer ESL, and thus, the via insulating layer 156 may act as a protective layer covering the surfaces of the substrate 110 and each of the interlayer insulating layers 120. Therefore, in the process of exposing the upper surface of the ground pad 134, the metal material contained in the ground pad metal layer 134W can be prevented from directly adhering to the sidewall of the substrate 110 or the interlayer insulating layer 120, and thus, contamination of the metal material in the substrate 110 or the interlayer insulating layer 120 can be prevented, thereby enabling the semiconductor chip 100 to have good reliability.

[0211] Figure 18 This is a cross-sectional view showing the main configuration of a semiconductor package 200 containing a semiconductor chip according to some example embodiments.

[0212] See Figure 18 Semiconductor package 200 may include a plurality of semiconductor chips 220 sequentially stacked on package substrate 210.

[0213] The control chip 230 can be connected to multiple semiconductor chips 220. The stacked structure of the multiple semiconductor chips 220 and the control chip 230 can be sealed on the packaging substrate 210 by a sealing member 240, such as a thermosetting resin. In the figures, an example of six semiconductor chips 220 stacked vertically is shown, but the number of semiconductor chips 220 and the stacking orientation are not limited thereto. Depending on the situation, the number of semiconductor chips 220 may be increased or decreased. Multiple semiconductor chips 220 may be arranged horizontally on the packaging substrate 210, or may be arranged in a mounting connection structure combining vertical and horizontal mounting. In some example embodiments, the control chip 230 may be omitted.

[0214] The packaging substrate 210 may be a flexible printed circuit board, a rigid printed circuit board, or a combination thereof. The packaging substrate 210 may include internal substrate wiring 212 and connection terminals 214. The connection terminals 214 may be disposed on one surface of the packaging substrate 210. Solder balls 216 may be disposed on the other surface of the packaging substrate 210. The connection terminals 214 may be electrically connected to the solder balls 216 via the internal substrate wiring 212. In some example embodiments, the solder balls 216 may be replaced by conductive bumps or a lead grid array (LGA).

[0215] Multiple semiconductor chips 220 may each include a through-hole 222, and a control chip 230 may include a through-hole 232. The through-holes 222 and 232 can be electrically connected to connection terminals 214 of the package substrate 210 via connection members 250 (such as bumps). In some example embodiments, the through-hole 232 in the control chip 230 may be omitted.

[0216] At least one of the plurality of semiconductor chips 220 may include the above reference. Figures 1 to 8 The semiconductor chip 100 and semiconductor chips 100A to 100D are described. Similarly, at least one of the plurality of semiconductor chips 220 can be manufactured according to the above reference. Figures 9 to 17 The methods described are for manufacturing semiconductor chips according to some example embodiments.

[0217] Figure 19 This is a plan view showing a semiconductor module 1000 containing semiconductor chips according to some example embodiments.

[0218] See Figure 19 The semiconductor module 1000 may include a module substrate 1010, a control chip 1020 mounted on the module substrate 1010, and a plurality of semiconductor chips 1030 mounted on the module substrate 1010.

[0219] Multiple input / output (I / O) terminals 1050, capable of being inserted into sockets on the motherboard, can be disposed on one side of the module substrate 1010. At least one of the multiple semiconductor chips 1030 may include the above-mentioned reference. Figures 1 to 8 The semiconductor chip 100 and semiconductor chips 100A to 100D are described. Similarly, at least one of a plurality of semiconductor chips 1030 can be manufactured according to the above reference. Figures 9 to 17 The methods described are for manufacturing semiconductor chips according to some example embodiments.

[0220] Figure 20 This is a block diagram illustrating a system 1100 comprising a semiconductor chip according to some example embodiments.

[0221] See Figure 20 The system 1100 may include a controller 1110, an I / O device 1120, a memory 1130, an interface 1140, and a bus 1150.

[0222] System 1100 may be a mobile system or a system for transmitting or receiving information. In some embodiments, the mobile system may be a portable computer, a web tablet, a mobile phone, a digital music player, or a memory card.

[0223] The controller 1110 can control the execution program in the system 1100 and can be configured to have a microprocessor, digital signal processor, microcontroller, or similar device.

[0224] I / O device 1120 can be used to input data to or output data from system 1100. System 1100 can be connected to external devices (such as personal computers (PCs) or networks) and can exchange data with external devices by using I / O device 1120. I / O device 1120 can be, for example, a touchpad, keyboard, or display.

[0225] Memory 1130 may store data used for the operation of controller 1110, or may store data obtained by controller 1110 after processing. Memory 1130 may contain the data referenced above. Figures 1 to 8 The semiconductor chip 100 and semiconductor chip 100A to semiconductor chip 100D are described. Similarly, they can be manufactured according to the above reference. Figures 9 to 17The methods described in some example embodiments of semiconductor chip manufacturing of memory 1130.

[0226] Interface 1140 can be a data transmission path between system 1100 and external devices. Controller 1110, I / O device 1120, memory 1130 and interface 1140 can be interconnected via bus 1150.

[0227] While the inventive concept has been shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor chip, comprising: Substrate; Interlayer insulation layer, including A bottom interlayer insulating layer is located on the upper surface of the substrate, and A top interlayer insulation layer is located on top of the bottom interlayer insulation layer; An etch stop layer is located between the bottom interlayer insulating layer and the top interlayer insulating layer; A ground pad is located on the interlayer insulation layer. The ground pad includes a ground pad metal layer and a ground pad barrier layer. The ground pad barrier layer surrounds the upper surface and the side surface of the ground pad metal layer. The ground pad barrier layer is at least partially located between the ground pad metal layer and the top interlayer insulation layer. as well as A through-hole is connected to the ground pad via the substrate, the interlayer insulating layer, and the etch stop layer. The etch stop layer is isolated to prevent direct contact with the ground pad. The through-hole extends throughout the entire through-hole, which exposes the ground pad barrier layer, the upper surface of the ground pad metal layer, and the inner sidewall of the ground pad metal layer. The through-hole extends through the ground pad barrier layer and directly contacts the ground pad metal layer, and the sidewall of the through-hole directly contacts the inner sidewall of the ground pad metal layer.

2. The semiconductor chip according to claim 1, further comprising: A through-hole insulating layer, surrounding a limited portion of the sidewall of the through-hole. The via insulating layer directly contacts the etch stop layer but not directly contacts the ground pad.

3. The semiconductor chip according to claim 2, wherein the sidewall of the through-hole directly contacts the through-hole insulating layer, the etch stop layer, the top interlayer insulating layer, and the ground pad.

4. The semiconductor chip according to claim 2, wherein The lower surface of the etch stop layer facing the upper surface of the substrate directly contacts the via insulating layer and the bottom interlayer insulating layer, and The upper surface of the etch stop layer, which is opposite to the upper surface of the substrate, directly contacts the top interlayer insulating layer but does not directly contact the via insulating layer or the ground pad.

5. The semiconductor chip according to claim 4, wherein One sidewall of the through-hole insulation layer directly contacts the through-hole. The other sidewall of the via insulating layer directly contacts the substrate and the bottom interlayer insulating layer, and The upper surface of the via insulating layer, which is opposite to the upper surface of the substrate, directly contacts the lower surface of the etch stop layer.

6. The semiconductor chip of claim 1, wherein the material of the etch stop layer has etch selectivity relative to the material of the bottom interlayer insulating layer.

7. The semiconductor chip according to claim 1, wherein... The thickness of the bottom interlayer insulating layer is greater than the thickness of the etch stop layer, and The thickness of the etch stop layer is equal to or greater than the thickness of the top interlayer insulating layer.

8. The semiconductor chip according to claim 1, wherein In a direction extending away from the bottom surface of the substrate along the longitudinal axis of the through-hole, the cross-sectional width of at least a portion of the through-hole gradually narrows proportionally to the distance of the cross-section of said portion of the through-hole from the bottom surface of the substrate, and In a direction extending away from the bottom surface of the substrate along the longitudinal axis of the through hole, the cross-sectional width of the ground pad gradually increases in proportion to the distance of the cross-section of the ground pad from the bottom surface of the substrate.

9. The semiconductor chip according to claim 1, wherein the material composition of the bottom interlayer insulating layer is different from the material composition of the top interlayer insulating layer.

10. The semiconductor chip of claim 1, wherein the etch stop layer comprises a stack of multiple layers of different materials.

11. A semiconductor chip, comprising: Substrate; An interlayer insulating layer is located on the upper surface of the substrate, and the interlayer insulating layer surrounds the semiconductor device; Intermetallic insulation layer, surrounding the metallic wiring and comprising: A bottom intermetallic insulating layer is located on the interlayer insulating layer; as well as A top intermetallic insulating layer is located on the bottom intermetallic insulating layer; An etching stop layer is located between the bottom intermetallic insulating layer and the top intermetallic insulating layer; A grounding pad is located on the intermetallic insulating layer. The grounding pad includes a grounding pad metal layer and a grounding pad barrier layer. The grounding pad barrier layer surrounds the upper surface and the side surface of the grounding pad metal layer. The grounding pad barrier layer is at least partially located between the grounding pad metal layer and the intermetallic insulating layer. A bump structure is located on the grounding pad; as well as A through-hole is connected to the ground pad via the substrate, the interlayer insulating layer, the intermetallic insulating layer, and the etch stop layer. The etch stop layer is isolated to prevent direct contact with the ground pad. The through-hole extends throughout the entire through-hole, which exposes the ground pad barrier layer, the upper surface of the ground pad metal layer, and the inner sidewall of the ground pad metal layer. The through-hole extends through the ground pad barrier layer and directly contacts the ground pad metal layer, and the sidewall of the through-hole directly contacts the inner sidewall of the ground pad metal layer.

12. The semiconductor chip according to claim 11, further comprising: A through-hole insulating layer, surrounding a limited portion of the sidewall of the through-hole. in The via insulating layer directly contacts the substrate, the interlayer insulating layer, the bottom intermetallic insulating layer, and the etch stop layer. The through-hole insulation layer does not directly contact the top intermetallic insulation layer or the grounding pad.

13. The semiconductor chip according to claim 12, wherein The lower surface of the etch stop layer facing the upper surface of the substrate directly contacts the via insulating layer and the bottom intermetallic insulating layer, and The upper surface of the etch stop layer, which is opposite to the upper surface of the substrate, directly contacts the top intermetallic insulating layer but does not directly contact the via insulating layer or the ground pad.

14. The semiconductor chip according to claim 11, further comprising: The front-end process structure is located on the upper surface of the substrate; and The downstream process structure is located on top of the upstream process structure. in The interlayer insulation layer is part of the front-end process structure, and Each of the metal wiring and the intermetallic insulation layer is part of the downstream process structure.

15. The semiconductor chip according to claim 14, wherein The etch stop layer is part of the subsequent process structure, and A portion of the metal wiring extends through the etch-stop layer and directly contacts the ground pad.

16. A method for manufacturing a semiconductor chip, the method comprising: A semiconductor device is formed on the first surface of the substrate; A bottom interlayer insulating layer is formed on a first surface of the substrate such that the bottom interlayer insulating layer surrounds the semiconductor device; An etch stop layer is formed on the bottom interlayer insulating layer; A top interlayer insulating layer is formed on the etch stop layer; A ground pad is formed on the top interlayer insulating layer, such that the ground pad is isolated from direct contact with the etch stop layer. The ground pad includes a ground pad metal layer and a ground pad barrier layer. The ground pad barrier layer surrounds the upper surface and the side surface of the ground pad metal layer. The ground pad barrier layer is at least partially located between the ground pad metal layer and the top interlayer insulating layer. A preliminary through-hole is formed, the preliminary through-hole extending through the substrate from a second surface of the substrate opposite to a first surface of the substrate to expose the etch stop layer; An insulating layer is formed on the inner wall of the initial through hole to define the through hole; Enlarge the bottom of the through hole to expose the ground pad barrier layer, the upper surface of the ground pad metal layer, and the inner wall of the ground pad metal layer; as well as A through hole is formed to fill the through hole, such that the through hole extends through the ground pad barrier layer and directly contacts the ground pad metal layer, and the sidewall of the through hole directly contacts the inner sidewall of the ground pad metal layer.

17. The method of manufacturing a semiconductor chip according to claim 16, wherein forming the via insulating layer comprises conformally forming the via insulating layer on the sidewalls of the substrate, the sidewalls of the bottom interlayer insulating layer, and the exposed surface of the etch stop layer.

18. The method of manufacturing a semiconductor chip according to claim 16, wherein enlarging the bottom of the through-hole includes Etch the exposed surface of the via insulating layer to expose the etch stop layer; Etch the exposed surface of the etch stop layer to expose the top interlayer insulating layer; as well as The exposed surface of the top interlayer insulation layer is etched to expose the ground pad barrier layer, the upper surface of the ground pad metal layer, and the inner sidewall of the ground pad metal layer.

19. The method of manufacturing a semiconductor chip according to claim 18, wherein the material of the etch stop layer has etch selectivity relative to the material of the bottom interlayer insulating layer.

20. The method of manufacturing a semiconductor chip according to claim 16, wherein the initial through-hole is formed such that the height of the central portion of the exposed surface of the etch stop layer is greater than the height of the peripheral portion of the exposed surface of the etch stop layer.

21. The method for manufacturing a semiconductor chip according to claim 16, wherein... The thickness of the bottom interlayer insulating layer is greater than the thickness of the etch stop layer, and The thickness of the etch stop layer is equal to or greater than the thickness of the top interlayer insulating layer.

22. The method for manufacturing a semiconductor chip according to claim 16, wherein... In a direction extending away from the bottom surface of the substrate along the longitudinal axis of the through-hole, the cross-sectional width of at least a portion of the through-hole gradually narrows proportionally to the distance of the cross-section of said portion of the through-hole from the bottom surface of the substrate, and In a direction extending away from the bottom surface of the substrate along the longitudinal axis of the through hole, the cross-sectional width of the ground pad gradually increases in proportion to the distance of the cross-section of the ground pad from the bottom surface of the substrate.

23. The method of manufacturing a semiconductor chip according to claim 16, wherein the material composition of the bottom interlayer insulating layer is different from the material composition of the top interlayer insulating layer.

24. The method of manufacturing a semiconductor chip according to claim 16, wherein forming the etch stop layer comprises: A first etch stop layer is formed on the bottom interlayer insulating layer; and A second etch stop layer is formed on the first etch stop layer, the second etch stop layer comprising a material composition different from that of the first etch stop layer.

25. The method for manufacturing a semiconductor chip according to claim 16, further comprising: After forming the through hole, a bump structure is then formed on the ground pad.

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