Semiconductor device and method for forming the same

Abstract

The present invention provides a semiconductor device and a method for forming the same. After two gate structures are formed in a substrate, ion implantation is performed in the substrate below a drain region using an ion implantation method to form a threshold adjustment region between the two gate structures. The threshold voltage of the transistor can be changed by adjusting the doping concentration of the threshold adjustment region without affecting the performance of the semiconductor device. Moreover, forming the threshold adjustment region only below the drain region can also avoid mutual influence between adjacent active regions.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] Dynamic random access memory (DRAM) usually uses buried-gate transistors. During the manufacturing process of DRAM, the threshold voltage of the transistor is usually fixed and cannot be adjusted arbitrarily or requires very complex process technology to adjust. This limits the possibility of changing the threshold voltage of the transistor in the back-end process. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor device and a method for forming the same, which can conveniently and effectively adjust the threshold voltage of a DRAM transistor.

[0004] In order to achieve the above object, the present invention provides a semiconductor device, comprising:

[0005] A substrate, wherein two source regions and a drain region located between the two source regions are formed in the substrate;

[0006] two gate structures formed in the substrate between the source region and the drain region to form two transistors; and,

[0007] A threshold adjustment region is located in the substrate below the drain region, and the threshold voltage of the transistor is changed by adjusting the doping concentration of the threshold adjustment region.

[0008] Optionally, a trench isolation structure is further formed in the substrate, and the trench isolation structure defines a plurality of active regions, and two source regions and one drain region are formed in each of the active regions.

[0009] Optionally, the drain region and the source region extend from the surface of the substrate to a first depth position within the substrate, and the gate structure extends from the surface of the substrate to a second depth position within the substrate, and the second depth position is further sunken than the first depth position, so that the area from the source region to the drain region along the side wall and bottom wall of the gate structure constitutes the channel region of the transistor, and the threshold adjustment region is located between the first depth position and the second depth position of the substrate to adjust the concentration of the substrate between the first depth position and the second depth position.

[0010] Optionally, side boundaries of the threshold adjustment region extend to side walls of the gate structure.

[0011] Optionally, a well region is further formed in the substrate, and the threshold adjustment region is located in the well region.

[0012] Optionally, when the transistor is an N-type transistor, the threshold adjustment region is N-type doped to cause a threshold voltage of the transistor to shift negatively.

[0013] Optionally, the conductive ions doped in the threshold adjustment region include boron ions.

[0014] Optionally, the doping concentration of the threshold adjustment region is positively correlated with the threshold voltage of the transistor.

[0015] Optionally, the concentration of the conductive ions doped in the threshold adjustment region is between 5E13 atoms / cm 2 ~1E14atoms / cm 2 .

[0016] The present invention provides a method for forming a semiconductor device, comprising:

[0017] Providing a substrate, wherein two source regions and a drain region located between the two source regions are formed in the substrate;

[0018] forming two gate structures in the substrate between the source region and the drain region to form two transistors; and,

[0019] A first ion implantation process is performed to implant ions into the substrate below the drain region to form a threshold adjustment region, and the threshold voltage of the transistor is changed by adjusting the doping concentration of the threshold adjustment region.

[0020] Optionally, the ion implantation energy of the first ion implantation process is between 20 keV and 50 keV.

[0021] Optionally, before performing the first ion implantation process, the method for forming a semiconductor device further includes:

[0022] forming a mask layer on the substrate, wherein an opening corresponding to the drain region is formed in the mask layer;

[0023] Furthermore, after forming the threshold adjustment region, the method for forming the semiconductor device further includes:

[0024] A bit line contact is formed in the opening.

[0025] Optionally, after forming the mask layer and before performing the first ion implantation process, the method for forming the semiconductor device further includes:

[0026] A second ion implantation process is performed to implant conductive ions of the same conductive type into the drain region.

[0027] Optionally, the ion implantation energy of the second ion implantation process is between 10keV and 15keV, and the ion implantation concentration of the second ion implantation process is between 3E13atoms / cm 2 ~6E13atoms / cm 2 .

[0028] In the semiconductor device and the method for forming the same provided by the present invention, after two gate structures are formed in the substrate, ion implantation is performed in the substrate below the drain region using an ion implantation method to form a threshold adjustment region between the two gate structures. The threshold voltage of the transistor can be changed by adjusting the doping concentration of the threshold adjustment region without affecting the performance of the semiconductor device. Moreover, forming the threshold adjustment region only below the drain region can also avoid mutual influence between adjacent active regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A flow chart of a method for forming a semiconductor device provided by an embodiment of the present invention;

[0030] Figure 2-Figure 4 A schematic cross-sectional view of a semiconductor structure formed by a method for forming a semiconductor device provided by an embodiment of the present invention;

[0031] In the figure, the reference numerals are:

[0032] 1-substrate; 11-well region; 12-deep N-well; 111-source region; 112-drain region; 113-threshold adjustment region;

[0033] 2-Gate structure;

[0034] 3-mask layer; 31-opening;

[0035] 4-bit line contact. DETAILED DESCRIPTION

[0036] The inventors found that the threshold voltage of the transistor is closely related to the doping concentration of the substrate, so the threshold voltage of the transistor can be changed by adjusting the doping concentration of the substrate. Through further research, it was found that for a semiconductor device with two transistors with a common drain region in the same active region, the source regions of the two transistors are close to the trench isolation structure. If ion implantation is performed in the substrate at the bottom of the source region, it is equivalent to reducing the resistance of the substrate. The electrons between one active region may enter the adjacent active region, causing the two adjacent active regions to affect each other, resulting in a decrease in the overall performance of the semiconductor device.

[0037] Based on this, the present invention provides a semiconductor device and a method for forming the same. After two gate structures are formed in a substrate, an ion implantation method is used to perform ion implantation in the substrate below the drain region to form a threshold adjustment region between the two gate structures. The threshold voltage of the transistor can be changed by adjusting the doping concentration of the threshold adjustment region without affecting the performance of the semiconductor device. Moreover, forming the threshold adjustment region only below the drain region can also avoid mutual influence between adjacent active regions.

[0038] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0039] Figure 4 A schematic diagram of a semiconductor device provided in this embodiment, such as Figure 4 As shown, the semiconductor device includes: a substrate 1, in which two source regions 111 and a drain region 112 located between the two source regions 111 are formed; two gate structures 2 are formed in the substrate 1 between the source regions 111 and the drain regions 112 to constitute two transistors; and a threshold adjustment region 113 is located in the substrate 1 below the drain region 112, and the threshold voltage of the transistor is changed by adjusting the doping concentration of the threshold adjustment region 113.

[0040] For details, please continue to refer to Figure 4 A trench isolation structure and a plurality of active areas are formed in the substrate 1, wherein the trench isolation structure isolates adjacent active areas, each of the active areas includes two source areas 111 and a drain area 112, two gate trenches are formed in the substrate 1 of the active area, the gate trenches are formed in the substrate 1 and are located between the source areas 111 and the drain areas 112, a gate structure 2 is formed in one of the gate trenches, wherein the gate structure 2 includes a gate dielectric layer and a gate conductive layer, the gate dielectric layer covers the bottom wall and the side wall of the gate trench, and the gate conductive layer fills the gate trench.

[0041] Further, the gate structures 2 are all located between the source region 111 and the drain region 112 to form a transistor. It can be understood that two transistors in the same active region use one of the adjacent source regions 111 respectively and share the drain region 112. The drain region 112 and the source region 111 extend from the surface of the substrate 1 to the inside of the substrate 1 to a first depth position respectively, and the gate structure extends from the surface of the substrate to the inside of the substrate 1 to a second depth position. Optionally, the threshold adjustment region 113 is located below the drain region 112 and between the two gate structures 2. Moreover, the second depth position is further sunken than the first depth position, so that the bottom of the gate structure 2 is further sunken into the source region 111 and the drain region 112 to form the channel region of the transistor, that is, the region from the source region 111 to the drain region 112 along the trench sidewalls and the trench bottom wall of the gate trench. The threshold adjustment region 113 adjusts the doping concentration of the portion of the substrate between the two gate structures 2 at the first depth position to the second depth position, or it can also be understood that the threshold adjustment region 113 changes the doping concentration of a portion of the channel region, thereby changing the threshold voltage of the transistor. However, because the threshold adjustment region 113 is only located below the drain region 112 and is far away from the trench isolation structure, it will not affect the isolation effect of the trench isolation structure.

[0042] Optionally, the side boundaries of the threshold adjustment region 113 extend to the side walls of the gate structure 2, and the surface and bottom surface of the threshold adjustment region 113 may be respectively at the first depth position and the second depth position, or both may be located between the first depth position and the second depth position, or as Figure 4 As described above, the surface of the threshold adjustment area 113 is located at the first depth position, and the bottom surface is located between the first depth position and the second depth position, and the present invention will not cite examples one by one.

[0043] Furthermore, a well region 11 is formed in the substrate 1. In this embodiment, the well region 11 is a P well. The threshold adjustment region 113 is formed in the well region 11. The ion doping concentration in the well region 11 is lower than the ion doping concentration in the source region 111 and the drain region 112. Furthermore, the doping type of the well region 11 can be determined according to the type of transistor formed. For example, when the transistor is a P-type transistor, the well region 11 can be doped with phosphorus ions (P) accordingly; when the transistor is an N-type transistor, the well region 11 can be doped with boron ions (B) accordingly. A deep well region for isolation is also formed in the substrate 1. In this embodiment, the deep well region is a deep N well 12. The deep N well 12 is formed below the well region 11 to isolate the transistor, prevent external factors from interfering with the transistor, or prevent different active regions from interfering with each other, and also prevent the transistor from interfering with other external devices.

[0044] Optionally, in this embodiment, the transistor is an N-type transistor, and the threshold adjustment region 113 is N-type doped, that is, the conductive ions doped in the threshold adjustment region 113 are N-type ions (such as phosphorus ions) to make the threshold voltage of the transistor positively drift. In addition, the doping concentration of the threshold adjustment region 113 is positively correlated with the magnitude of the threshold voltage of the transistor, that is, when the doping concentration of the threshold adjustment region 113 increases, the threshold voltage of the transistor also increases, and conversely, when the doping concentration of the threshold adjustment region 113 decreases, the threshold voltage of the transistor also decreases. In this embodiment, the concentration of the doped conductive ions in the threshold adjustment region 113 is between 5E13atoms / cm2 and 1E14atoms / cm2.

[0045] Based on this, Figure 1 As shown, the present invention also provides a method for forming a semiconductor device, comprising:

[0046] S1: providing a substrate, wherein two source regions and a drain region located between the two source regions are formed in the substrate;

[0047] S2: forming two gate structures in the substrate between the source region and the drain region to form two transistors; and,

[0048] S3: performing a first ion implantation process to implant ions into the substrate below the drain region to form a threshold adjustment region, and adjusting the doping concentration of the threshold adjustment region to change the threshold voltage of the transistor.

[0049] For details, please refer to Figure 2, providing the substrate 1, wherein a plurality of active regions are formed in the substrate 1, wherein the active regions include two source regions 111 and a drain region 112, wherein the drain region 112 is located between the two source regions 111, and then forming two gate structures 2 in the substrate 1 between each of the source regions 111 and the drain region 112, respectively, to form two transistors.

[0050] Then as Figure 2 As shown, a mask layer 3 is formed on the surface of the substrate 1, the mask layer 3 covers the substrate 1, and an opening 31 corresponding to the drain region 112 is formed in the mask layer 3, that is, the drain region 112 is below the opening 31. Optionally, the material of the mask layer 3 in this embodiment is photoresist.

[0051] Next, see Figure 3 , using the mask layer 3 as a mask, performing a second ion implantation process to implant conductive ions of the same conductive type into the drain region 112, so as to increase the doping concentration of the drain region 112, thereby reducing the contact resistance on the surface of the drain region 112, and improving the conduction capability of the semiconductor device. Further, the ion implantation energy of the second ion implantation process is between 10keV and 15keV, and the ion implantation concentration of the second ion implantation is between 3E13atoms / cm2 and 6E13atoms / cm2.

[0052] Furthermore, the mask layer 3 is used as a mask to perform a first ion implantation process to implant ions in the substrate 1 below the drain region 112 to form the threshold adjustment region 113. The position of the threshold adjustment region 113 in the substrate 1 depends on the ion implantation energy of the first ion implantation process. If the ion implantation energy of the first ion implantation process is high, the threshold adjustment region 113 is deeper. Conversely, if the ion implantation energy of the first ion implantation process is low, the threshold adjustment region 113 is shallower. Moreover, since the opening 31 of the mask layer 3 only corresponds to the drain region 112, the threshold adjustment region 113 is located between the two gate structures 2. It can be understood that since the threshold adjustment region 113 is formed below the drain region 112, the ion implantation energy of the first ion implantation process is greater than the ion implantation energy of the second ion implantation process. In this embodiment, the ion implantation energy of the first ion implantation process is between 20keV and 50keV, and the concentration of the conductive ions doped in the threshold adjustment region 113 is between 5E13atoms / cm 2 ~1E14atoms / cm 2 .

[0053] See next Figure 3-Figure 4After forming the threshold adjustment region 113, a bit line contact 4 can be formed in the opening 31. The specific process is: forming a doped polysilicon layer on the substrate 1, the doped polysilicon layer covers the substrate 1 and fills the opening 31, grinding to remove the doped polysilicon layer on the surface of the substrate 1, and retaining the doped polysilicon layer in the opening 31 to form the bit line contact 4 on the substrate 1. The bit line contact 4 is used to connect with the bit line, that is, the mask layer 3 is directly used for forming the bit line contact, and no additional new mask layer is needed, which saves the photomask.

[0054] In summary, in the semiconductor device and the method for forming the same provided in the embodiments of the present invention, after two gate structures are formed in the substrate, ion implantation is performed in the substrate below the drain region using an ion implantation method to form a threshold adjustment region between the two gate structures. The threshold voltage of the transistor can be changed by adjusting the doping concentration of the threshold adjustment region without affecting the performance of the semiconductor device, and mutual influence between adjacent active regions can also be avoided.

[0055] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A substrate, wherein two source regions and a drain region located between the two source regions are formed in the substrate; two gate structures formed in the substrate between the source region and the drain region to form two transistors; as well as, A threshold adjustment region, located in the substrate below the drain region, and the threshold voltage of the transistor is changed by adjusting the doping concentration of the threshold adjustment region; The drain region and the source region extend from the surface of the substrate to a first depth position in the substrate, the gate structure extends from the surface of the substrate to a second depth position in the substrate, the second depth position is further sunken than the first depth position, so that the region from the source region to the drain region along the sidewall and bottom wall of the gate structure constitutes a channel region of the transistor, and the threshold adjustment region is located between the first depth position and the second depth position of the substrate to adjust the concentration of the substrate between the first depth position and the second depth position; When the transistor is an N-type transistor, the threshold adjustment region is P-type doped to make the threshold voltage of the transistor shift positively.

2. The semiconductor device according to claim 1, wherein A trench isolation structure is also formed in the substrate, and the trench isolation structure defines a plurality of active regions, and two source regions and one drain region are formed in each of the active regions.

3. The semiconductor device according to claim 1, wherein The side boundaries of the threshold adjustment region extend to the side walls of the gate structure.

4. The semiconductor device according to claim 1, wherein A well region is also formed in the substrate, and the threshold adjustment region is located in the well region.

5. The semiconductor device according to claim 1, wherein: The conductive ions doped into the threshold adjustment region include boron ions.

6. The semiconductor device according to claim 1, wherein: The doping concentration of the threshold adjustment region is positively correlated with the threshold voltage of the transistor.

7. The semiconductor device according to claim 6, wherein: The concentration of the conductive ions doped in the threshold adjustment region is between 5E13 atoms / cm2 and 1E14 atoms / cm2.

8. A method for forming a semiconductor device, characterized in that: include: Providing a substrate, wherein two source regions and a drain region located between the two source regions are formed in the substrate; forming two gate structures in the substrate between the source region and the drain region to form two transistors; as well as, Performing a first ion implantation process to implant ions into the substrate below the drain region to form a threshold adjustment region, and adjusting the doping concentration of the threshold adjustment region to change the threshold voltage of the transistor; The drain region and the source region extend from the surface of the substrate to a first depth position in the substrate, the gate structure extends from the surface of the substrate to a second depth position in the substrate, the second depth position is further sunken than the first depth position, so that the region from the source region to the drain region along the sidewall and bottom wall of the gate structure constitutes a channel region of the transistor, and the threshold adjustment region is located between the first depth position and the second depth position of the substrate to adjust the concentration of the substrate between the first depth position and the second depth position; When the transistor is an N-type transistor, the threshold adjustment region is P-type doped to make the threshold voltage of the transistor shift positively.

9. The method for forming a semiconductor device according to claim 8, wherein: The ion implantation energy of the first ion implantation process is between 20 keV and 50 keV.

10. The method for forming a semiconductor device according to claim 8, wherein: Before performing the first ion implantation process, the method for forming a semiconductor device further includes: forming a mask layer on the substrate, wherein an opening corresponding to the drain region is formed in the mask layer; Furthermore, after forming the threshold adjustment region, the method for forming the semiconductor device further includes: A bit line contact is formed in the opening.

11. The method for forming a semiconductor device according to claim 10, wherein: After forming the mask layer and before performing the first ion implantation process, the method for forming the semiconductor device further includes: A second ion implantation process is performed to implant conductive ions of the same conductive type into the drain region.

12. The method for forming a semiconductor device according to claim 11, wherein: The ion implantation energy of the second ion implantation process is between 10 keV and 15 keV, and the ion implantation concentration of the second ion implantation process is between 3E13 atoms / cm2 and 6E13 atoms / cm2.

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