A variable symbol sampling rate raised cosine filter based on FPGA

Abstract

The present invention relates to a variable symbol sampling rate raised cosine filter based on FPGA, comprising L+1 high-speed sampling modules and L address calculation modules, and satisfying N=KL, wherein K is the number of sampling points for each symbol, L represents that the filter cut-off time length is L symbols, and the number of filter coefficients is N+1; the L+1 high-speed sampling modules are sequentially delayed by one clock cycle for sampling, the output ends of the high-speed sampling modules are each connected to a multiplier, the output ends of the multipliers are connected to an adder, the adder performs addition operation on L+1 parallel input signals, and is used to output a raised cosine filter signal; and also comprises L ROM memories, the ROM memories are used to store raised cosine filter coefficients h(n), n=0,1,2...N-1, and each ROM memory is connected to an address calculation module, which is used to calculate the address of the subsequent ROM memory. This scheme can adapt to a variable symbol sampling rate, and the consumed FPGA multiplier resources do not change with the symbol sampling rate.

Description

Technical Field

[0001] The invention relates to the field of filters, and in particular to a variable sign sampling rate raised cosine filter based on FPGA. Background Art

[0002] In modern communication systems, in order to reduce the impact of inter-symbol interference, make the transmitted signal more suitable for channel transmission, and improve the transmission quality of the communication system, a raised cosine (or square root raised cosine) filter is usually used as a pulse shaping filter. The unit impulse response of the transmitter raised cosine filter is:

[0003]

[0004] Where R is the roll-off factor, t is the time, and T is the symbol period.

[0005] When implementing the raised cosine filter, FPGA hardware can be used. Since the symbol rate is different from the output rate of the raised cosine filter, it is necessary to first upsample and digitize formula (1) and then use the filter structure to implement it. The implementation structure is as follows: Figure 1 As shown in the figure, D represents a delay of one clock unit in the FPGA. represents the multiplier, and h(N) represents the coefficient of the raised cosine filter. The transmission code element is converted into a modulated signal through the modulation module. The high-rate sampling module samples the modulated signal at a high multiple to match the sampling rate of the raised cosine filter. Finally, the raised cosine filter completes the shaping of the pulse signal. The raised cosine filter is implemented by multiplication and accumulation like other filters (such as FIR filters).

[0006] The above-mentioned raised cosine filter structure is the same as the general filter block structure, which is mainly completed by multiplication and accumulation, but the filter structure is fixed and cannot adapt to the changing symbol sampling rate. When the input signal code rate changes and the output signal rate remains unchanged, that is, when the symbol sampling rate changes, the number of coefficients of the raised cosine filter in one code period also needs to change, and when the number of coefficients is large, many FPGA clock delay units need to be consumed. Summary of the invention

[0007] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a variable symbol sampling rate raised cosine filter based on FPGA, which can adapt to variable symbol sampling rate and consume FPGA multiplier resources that do not change with the symbol sampling rate.

[0008] The objective of the present invention is achieved through the following technical solutions:

[0009] A variable symbol sampling rate raised cosine filter based on FPGA, comprising L+1 high-speed sampling modules and L address calculation modules, and satisfying N=KL, wherein K is the number of sampling points for each symbol, L indicates that the filter cutoff time length is L symbols, and the number of filter coefficients is N+1;

[0010] L+1 high-speed sampling modules are sequentially delayed by one clock cycle for sampling, the output ends of the L+1 high-speed sampling modules are respectively connected to the input end of a multiplier, the output ends of the L+1 multipliers are connected to the same adder, and the adder performs an addition operation on the L+1 parallel input signals to output a raised cosine filter signal;

[0011] It also includes L ROM memories, the ROM memories are used to store raised cosine filter coefficients h(n), n=0, 1, 2...N-1, and each ROM memory is connected to an address calculation module for calculating the address of a subsequent ROM memory;

[0012] The output end of the ROM memory is respectively connected to the input end of the 1st to Lth multipliers for inputting the raised cosine filter coefficients, and the L+1th multiplier directly inputs the last coefficient h(N) of the raised cosine filter.

[0013] Furthermore, the high-speed sampling module is composed of a counter, a comparator, and a selector;

[0014] The output end of the counter is connected to the reference end of the comparator, and the output end of the comparator is connected to the input end of the selector. The counter output is compared with the K value. When they are equal, the output is 1, otherwise the output is 0. This signal serves as the rst signal of the counter to reset the counter, and also as the selection signal of the selector. When it is 0, 0 is selected as the output, and when it is 1, the input signal is selected as the output.

[0015] Furthermore, the address calculation module is composed of a second counter, a second comparator, a second selector, and a multiplier;

[0016] The second counter output terminal is connected to the reference input terminal of the second comparator, and the second comparator output terminal is connected to the multiplier input terminal;

[0017] The second selector output terminal is connected to a multiplier input terminal, and the multiplier is used to output a raised cosine filter coefficient;

[0018] When K=Km, the selector outputs Mm, where Mm=Kmax / Km.

[0019] Furthermore, the raised cosine filter coefficients h(n), n=0, 1, 2...N-1, a total of N coefficients are equally divided into L parts and stored in L ROM memories respectively, each ROM stores Kmax=Lcm(K1, K2, K3...) coefficients, Lcm represents the least common multiple, K1, K2, K3... represent various possible values ​​of K.

[0020] Furthermore, the value of L is 4-8. Theoretically, the larger the value of L is, the better the effect of the filter is, but more resources are consumed.

[0021] The beneficial effect of the present invention is that, compared with the prior art, the present invention divides the sampled signal into L+1 for sampling, and then multiplies them with the raised cosine filter coefficients respectively. Compared with the traditional method of sampling with one sampling unit and then passing through N+1 delay devices in sequence, the sampling speed in the present solution is faster. At the same time, since multiple sampling points are provided, it can adapt to different symbol sampling rates, is easy to implement on FPGA hardware, and consumes fixed FPGA multiplication resources, which will not change with different symbol sampling rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A structure for realizing a prior art raised cosine filter;

[0023] Figure 2 The filter structure circuit of the present invention;

[0024] Figure 3 Implement the structural diagram for the high-rate sampling module;

[0025] Figure 4 Implement the structure diagram for the address calculation module. DETAILED DESCRIPTION

[0026] The technical solution of the present invention is further described in detail below in conjunction with specific embodiments, but the protection scope of the present invention is not limited to the following.

[0027] like Figure 2As shown, a variable symbol sampling rate raised cosine filter based on FPGA includes L+1 high-speed sampling modules S101 and L address calculation modules S201, and satisfies N=KL, where K is the number of sampling points for each symbol, L indicates that the filter cutoff time length is L symbols, and the value of L is 4-8. The number of filter coefficients is N+1; L+1 high-speed sampling modules S101 are sequentially delayed by one clock cycle for sampling, the output ends of the L+1 high-speed sampling modules S101 are respectively connected to the input ends of a multiplier, the output ends of the L+1 multipliers are connected to the same adder, the adder adds L+1 parallel input signals, and is used to output a raised cosine filter signal; it also includes L ROM memories, the ROM memories are used to store raised cosine filter coefficients h(n), n=0,1,2...N-1, each ROM memory is connected to an address calculation module S201, and is used to calculate the address of the subsequent ROM memory; the output ends of the ROM memories are respectively connected to the input ends of the 1st to Lth multipliers, and are used to input the raised cosine filter coefficients, and the L+1th multiplier directly inputs the last coefficient h(N) of the raised cosine filter.

[0028] like Figure 3 As shown, the high-speed sampling module S101 is composed of a counter, a comparator, and a selector;

[0029] The output of the counter is connected to the reference terminal of the comparator, and the output of the comparator is connected to the input terminal of the selector. The output of the counter is compared with the K value. When they are equal, the output is 1, otherwise the output is 0. This signal serves as the rst signal of the counter to reset the counter. It also serves as the selection signal of the selector. When it is 0, 0 output is selected, and when it is 1, the input signal is selected as the output.

[0030] like Figure 4 As shown, the address calculation module S201 is composed of a second counter, a second comparator, a second selector, and a multiplier;

[0031] The second counter output terminal is connected to the reference input terminal of the second comparator, and the second comparator output terminal is connected to the multiplier input terminal;

[0032] The second selector output terminal is connected to the multiplier input terminal, and the multiplier is used to output the raised cosine filter coefficient;

[0033] When K=Km, the selector outputs Mm, where Mm=Kmax / Km, m takes values ​​of 1, 2, 3, etc., i.e. Km can be represented by K1, K2, K3, etc. The raised cosine filter coefficients h(n), n=0, 1, 2, etc., N coefficients are evenly divided into L parts and stored in L ROM memories, each ROM stores Kmax=Lcm(K1, K2, K3, etc.), Lcm represents the least common multiple, K1, K2, K3, etc. represent various possible values ​​of K.

[0034] To further specify this embodiment, let L=8. Figure 2 In the figure, D1, D2, D3, D4, D5, D6, D7, D8, and D9 represent delays of 1, 2, 3, 4, 5, 6, 7, 8, and 9 clock cycles respectively. Represents a multiplier. Module S101 is a high-rate sampling module for sampling to match the sampling rate of subsequent modules; module S201 is an address calculation module, which is used to calculate the address of the subsequent ROM memory. ROM0, ROM1, ROM2, ROM3, ROM4, ROM5, ROM6, and ROM7 are used to store the coefficients of the raised cosine filter. As mentioned above, the number of the raised cosine filter coefficients is N+1, represented by h(n), n=0,1,2...N-1, and the last coefficient is h(N), which does not require memory and is placed in Figure 2 In the last signal, the remaining N coefficients are evenly divided into L parts and stored in ROM0, ROM1, ROM2, ROM3, ROM4, ROM5, ROM6, ROM7 respectively. Each ROM stores Kmax=Lcm(K1, K2, K3...) coefficients. Lcm represents the least common multiple, and K1, K2, K3... represent various possible values ​​of K. The adder adds the L+1 parallel input signals and finally outputs the raised cosine filter result. Compared with the prior art, the sampling rate of the high-speed sampling module S101 in this solution is increased by K times. Figure 3 As shown, Figure 3 The output of the counter is compared with the K value. When they are equal, the output is 1, otherwise the output is 0. This signal serves as the rst signal of the counter to reset the counter. It also serves as the selection signal of the selector. When it is 0, 0 is selected as output, and when it is 1, the input signal is selected as output.

[0035] Figure 4 In the counter part, Figure 3 The corresponding parts are the same, and the function of the selector is that when K=Km, the selector outputs Mm, wherein Mm=Kmax / Km.

[0036] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.

Claims

1. A variable symbol sampling rate raised cosine filter based on FPGA, characterized in that: It includes L+1 high-speed sampling modules (S101) and L address calculation modules (S201), and satisfies N=KL, where K is the number of sampling points for each symbol, L indicates that the filter cutoff time length is L symbols, and the number of filter coefficients is N+1; L+1 high-speed sampling modules (S101) are sequentially delayed by one clock cycle for sampling, the output ends of the L+1 high-speed sampling modules (S101) are respectively connected to the input end of a multiplier, the output ends of the L+1 multipliers are connected to the same adder, and the adder performs an addition operation on the L+1 parallel input signals to output a raised cosine filter signal; It also includes L ROM memories, the ROM memories are used to store raised cosine filter coefficients h(n), n=0, 1, 2...N-1, each ROM memory is connected to an address calculation module (S201) for calculating the address of the subsequent ROM memory; The output end of the ROM memory is connected to the input end of the 1st to Lth multipliers respectively, for inputting the raised cosine filter coefficients, and the L+1th multiplier directly inputs the last coefficient h(N) of the raised cosine filter; The high-speed sampling module (S101) is composed of a counter, a comparator, and a selector; The output end of the counter is connected to the reference end of the comparator, and the output end of the comparator is connected to the input end of the selector. The counter output is compared with the K value. When they are equal, the output is 1, otherwise the output is 0. This signal is used as the rst signal of the counter to reset the counter, and also as the selection signal of the selector. When it is 0, 0 is selected as the output, and when it is 1, the input signal is selected as the output; The address calculation module (S201) is composed of a second counter, a second comparator, a second selector, and a multiplier; The second counter output terminal is connected to the reference input terminal of the second comparator, and the second comparator output terminal is connected to the multiplier input terminal; The second selector output terminal is connected to a multiplier input terminal, and the multiplier is used to output a raised cosine filter coefficient; When K=Km, the selector outputs Mm, where Mm=Kmax / Km; The raised cosine filter coefficients h(n), n=0, 1, 2...N-1, a total of N coefficients are evenly divided into L parts and stored in L ROM memories respectively, each ROM stores Kmax=Lcm (K1, K2, K3...) coefficients, Lcm represents the least common multiple, K1, K2, K3... represent various possible values ​​of K.

2. The variable sign sampling rate raised cosine filter based on FPGA according to claim 1, characterized in that: The value of L is 4-8.

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