Display Devices

Abstract

A display device is provided. The display device includes: a base layer on which a display area and a non-display area arranged to surround the display area are defined; a circuit layer arranged on the base layer and including a plurality of insulating layers; a pixel layer arranged in the display area and including a plurality of organic light emitting diodes; an encapsulation layer arranged on the pixel layer to cover the pixel layer; and a protruding member arranged between the circuit layer and the encapsulation layer in the non-display area. A bank coupling hole is defined in the circuit layer in the non-display area, and the bank coupling hole is defined to pass through at least the uppermost insulating layer of the insulating layer and overlap the protruding member in a plane.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2018-0109965, filed on September 14, 2018, the contents of which are hereby incorporated by reference in their entirety. Technical Field

[0002] The present disclosure herein relates to a display device, and more particularly, to a display device having improved durability. Background Art

[0003] Generally, a display device includes a display unit disposed on a substrate. In such a display device, at least a portion of the display device may be bent so that visibility at various angles may be improved or a surface area of ​​a non-display region may be reduced. Summary of the invention

[0004] In a process of manufacturing a conventional flexible display device, defects may occur or the life of the display device may be shortened, so that the manufacturing cost may increase.

[0005] The present disclosure provides a display device having improved durability.

[0006] An embodiment of the invention provides a display device, the display device comprising: a base layer, on which a display area and a non-display area surrounding the display area are defined; a circuit layer, disposed on the base layer and comprising a plurality of insulating layers; a pixel layer, disposed in the display area and comprising a plurality of organic light emitting diodes; an encapsulation layer, disposed on the pixel layer to cover the pixel layer; and a protruding member, disposed between the circuit layer and the encapsulation layer in the non-display area. In such an embodiment, a bank coupling hole is defined in the circuit layer in the non-display area, and the bank coupling hole is defined to pass through at least the uppermost insulating layer of the insulating layers and overlap the protruding member in a plane.

[0007] In an embodiment, the protrusion member may be provided in plurality, and the protrusion member may include: a dam provided to surround the display area; and a bank provided on an outer side of the dam in the first direction, and the bank coupling hole may overlap the bank in a plane.

[0008] In an embodiment, the circuit layer may further include: a barrier layer disposed on the base layer; a plurality of thin film transistors disposed on the barrier layer; and a plurality of conductive patterns disposed on the barrier layer in the non-display area. In such an embodiment, the plurality of insulating layers may include: a plurality of intermediate insulating layers disposed on the barrier layer; and an upper insulating layer disposed on the intermediate insulating layer to cover the thin film transistors and the conductive patterns.

[0009] In an embodiment, a bank coupling hole may be defined through the upper insulating layer to expose a portion of the intermediate insulating layer, and the bank and the intermediate insulating layer may be coupled to each other through the bank coupling hole.

[0010] In an embodiment, the package bonding hole may be defined to pass through at least the upper insulating layer in the non-display area, and the package bonding hole may be defined between the bank and the dam on a plane.

[0011] In an embodiment, a package bonding hole may be defined through the upper insulating layer and the middle insulating layer, and the package layer and the barrier layer may be bonded to each other through the package bonding hole.

[0012] In an embodiment, a bank coupling hole may be defined through the upper insulating layer, the intermediate insulating layer, and the barrier layer, and the bank and the base layer may be coupled to each other through the bank coupling hole.

[0013] In an embodiment, the bank coupling hole may not overlap the conductive pattern in plane and may be insulated from the conductive pattern.

[0014] In an embodiment, the circuit layer may include a dam coupling hole defined to pass through at least the upper insulating layer in the non-display area, and the dam coupling hole may overlap the dam in a plane.

[0015] In an embodiment, the dam coupling hole may overlap at least a portion of the conductive pattern in a plane and may be insulated from the conductive pattern.

[0016] In an embodiment, a dam coupling hole may be defined through the upper insulating layer and the intermediate insulating layer, and the dam and the barrier layer may be coupled to each other through the dam coupling hole.

[0017] In an embodiment, the dam coupling hole may not overlap the conductive pattern in plane and may be insulated from the conductive pattern.

[0018] In an embodiment, the dam may be provided in plurality, and the dam may include: a first dam having a frame shape surrounding the display area in a plane; and a second dam having a frame shape surrounding the first dam in a plane, and at least one of the first dam and the second dam may overlap with the conductive pattern.

[0019] In an embodiment, the non-display area may include a bending area that is bent on a plane with respect to a bending axis that is perpendicular to the first direction.

[0020] In an embodiment, a distance between the display area and the bending area in the first direction may be about 400 micrometers (μm) or less.

[0021] In an embodiment, the bank coupling hole may have a first direction width of about 5 μm or more and about 200 μm or less.

[0022] In an embodiment, the bank combining hole may be provided in plural.

[0023] In an embodiment, the bank may have a first-direction width greater than a first-direction width of the dam.

[0024] In an embodiment of the invention, a display device includes: a base layer on which a display area and a non-display area surrounding the display area are defined; a circuit layer disposed on the base layer; a display layer disposed on the circuit layer; and a plurality of protruding members disposed on the circuit layer in the non-display area. In such an embodiment, the circuit layer includes: a plurality of insulating layers, wherein a coupling hole is defined to pass through at least one uppermost insulating layer of the insulating layers in the non-display area; and a plurality of conductive patterns disposed between the insulating layers, and at least one of the protruding members is filled in the coupling hole.

[0025] In an embodiment of the invention, a display device includes a display panel, on which a display area for displaying an image and a non-display area surrounding the display area are defined, wherein at least a portion of the non-display area is curved. In such an embodiment, the display panel includes: a base layer, a circuit layer, which is disposed on the base layer and includes a plurality of insulating layers; a pixel layer, which is disposed in the display area; an encapsulation layer, which is disposed on the pixel layer to cover the pixel layer; and a dam, which is disposed between the circuit layer and the encapsulation layer in the non-display area, and a dam coupling hole is defined in the circuit layer in a partial area disposed adjacent to the curved area in the non-display area, wherein the dam coupling hole is defined to pass through at least the upper insulating layer of the insulating layer, and a lower portion of the dam is filled in the dam coupling hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] These and / or other features of the invention will become apparent and more readily understood through the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a perspective view showing a display device according to an embodiment of the invention;

[0028] Figure 2 It shows that Figure 1 A perspective view showing a state in which a portion of the display device is bent;

[0029] Figure 3 It is shown Figure 2 a cross-sectional view of a cross section of a display device in;

[0030] Figure 4 It is shown Figure 3 A cross-sectional view of a display panel in FIG.

[0031] Figure 5 is a plan view showing a display panel according to an embodiment of the invention;

[0032] Figure 6 is an equivalent circuit diagram showing a pixel according to an embodiment of the invention;

[0033] Figure 7 is a plan view showing a display panel according to an embodiment of the invention;

[0034] Figure 8 is along Figure 7 A cross-sectional view taken along line II”;

[0035] Fig. 9 is along Figure 7 A cross-sectional view taken along line I'-I"';

[0036] Fig.10 is along Figure 7 A cross-sectional view taken along line II-II';

[0037] Fig.11 is a cross-sectional view showing a display panel according to an alternative embodiment of the invention;

[0038] Fig.12 is a cross-sectional view showing a display panel according to another alternative embodiment of the invention;

[0039] Fig.13 is a cross-sectional view showing a display panel according to another alternative embodiment of the invention; and

[0040] Fig.14 is a cross-sectional view showing a display panel according to another alternative embodiment of the invention. DETAILED DESCRIPTION

[0041] The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the invention may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. The same reference numerals represent the same elements throughout.

[0042] In the present specification, it will be understood that when an element such as a region, layer or section is referred to as being “on” another element, the element can be directly on the other element or intervening elements may also be present.

[0043] In the drawings, the thickness, proportion, and size of components are exaggerated for clarity of illustration.

[0044] The terms used here are only for the purpose of describing specific embodiments, and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "one (kind / person)" and "the (described)" are intended to include plural forms including "at least one (kind / person)". "Or (or)" means "and / or". "At least A and B" means "A and / or B". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that the term "include" and its variations and / or "comprising" and its variations are used in this specification to illustrate the existence of stated features, regions, wholes, steps, operations, elements and / or components, but does not exclude the existence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or their groups.

[0045] It will be understood that, although the first and second terms are used here to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one component from other components. For example, a first element that is referred to as a first element in one embodiment may be referred to as a second element in another embodiment. Unless otherwise indicated, a term in the singular may include a plural form.

[0046] In addition, for ease of description, spatial relative terms such as "below", "lower", "above", and "upper" may be used here to describe the relationship between one element and / or feature and another element and / or feature as shown in the drawings. These terms are relative concepts and are described with respect to the directions indicated in the drawings.

[0047] As used herein, “about” or “approximately” is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and errors associated with measurement of the particular quantity (i.e., limitations of the measurement system).

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art. Terms defined in general dictionaries should be interpreted as having the same meaning as in the context of the relevant technology, and unless clearly defined in the description, terms should not be interpreted ideally or excessively as having a formal meaning.

[0049] Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. As such, variations in the shapes of the diagrams, such as those caused by manufacturing techniques and / or tolerances, will be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions as shown here, but will include deviations in shape, such as those caused by manufacturing. For example, a region shown or described as being flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and the shapes of these regions are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims.

[0050] Hereinafter, embodiments of the invention will be described in detail with reference to the accompanying drawings.

[0051] Figure 1 is a perspective view showing a display device DD according to an embodiment of the invention, Figure 2 It shows that Figure 1 A perspective view of a state in which a portion of the display device DD is bent.

[0052] Figure 3 It is shown Figure 2 sectional view of a display device DD in FIG. Figure 3 is a schematic diagram showing a stacking relationship between functional panels and / or functional units constituting the display device DD.

[0053] Reference Figures 1 to 3 , an embodiment of the display device DD according to the invention may have a rectangular shape having a long side in a first direction DR1 and a short side in a second direction DR2 perpendicular to the first direction DR1. Here, for the convenience of description, the shape of one embodiment of the display device DD is described. However, the embodiment of the invention is not limited to the shape of the above-mentioned display device DD.

[0054] The display device DD can display an image IM through its display surface IS. The display surface IS is parallel to a surface defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface IS (ie, the thickness direction of the display device DD) is defined as a third direction DR3.

[0055] Hereinafter, the front surface (or top surface) and the rear surface (or bottom surface) of each member or unit are distinguished by the third direction DR3. However, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 may be relative concepts and thus may be converted relative to each other.

[0056] The display surface IS includes a display area DA on which an image IM is displayed and a non-display area NDA disposed adjacent to the display area DA. The display area DA is defined in a central area of ​​the display device DD. The non-display area NDA may be an area on which the image IM is not displayed. The non-display area NDA is defined to surround the display area DA on the display surface IS. Figure 1 and Figure 2 , an icon image is shown as one exemplary embodiment of the image IM displayed in the display area DA.

[0057] The display device DD includes a display module DM and a circuit board DC. The display module DM displays an image IM. In such an embodiment, a display surface IS may be defined on a top surface of the display module DM.

[0058] A plurality of areas NBA1, BA and NBA2 arranged on a plane in a first direction DR1 may be defined on the display module DM. Here, "on a plane" means when viewed from a plan view in a third direction DR. Each of the plurality of areas NBA1, BA and NBA2 may be defined differently according to an operation type of the display module DM.

[0059] In an embodiment, Figure 1 As shown in FIG. 1 , a first area NBA1, a second area NBA2, and a third area BA disposed between the first area NBA1 and the second area NBA2 are defined on a plane on the display module DM. The first area NBA1 includes a display area DA and partially overlaps a non-display area NDA. The first area NBA1 is not curved or is substantially flat.

[0060] The second area NBA2 is defined at one side of the display module DM in the first direction DR1 (or defined by one side of the display module DM in the first direction DR1). Here, when one side is in one direction, the extension direction of the one side is perpendicular to the direction. The second area NBA2 partially overlaps another part of the non-display area NDA. The second area NBA2 is not bent or is substantially flat. The second area NBA2 may be connected to a circuit board DC which will be described in detail later.

[0061] The third area BA is an area bent relative to a bending axis BX parallel to the second direction DR2. The third area BA basically forms a certain curvature. Hereinafter, the first area NBA1, the second area NBA2, and the third area BA may be referred to as a first non-bending area NBA1, a second non-bending area NBA2, and a bending area BA, respectively.

[0062] In an embodiment, Figure 2As shown in , when the bending area BA of the display module DM is bent, a portion of the display module DM corresponding to the second non-bending area NBA2 may be disposed below a portion of the display module DM corresponding to the first non-bending area NBA1. In such an embodiment, the second non-bending area NBA2 may overlap a portion of the first non-bending area NBA1 on a plane.

[0063] The first non-bending area NBA1 may have a first direction width different from the first direction width of the second non-bending area NBA2. Here, "direction width" means "width measured in the direction". In an embodiment, the first non-bending area NBA1 may have a first direction width greater than the first direction width of the second non-bending area NBA2. Therefore, when the display module DM is bent, the second non-bending area NBA2 is not visible because it overlaps with the first non-bending area NBA1 on a plane.

[0064] In an embodiment, Figure 3 As shown in FIG. 1 , the display module DM includes a display panel DP including a plurality of display elements (not shown), an input sensing layer ISU, an anti-reflection (or anti-reflection) layer RPP, and a protection member (or layer) PF.

[0065] The input sensing layer ISU is disposed on the display panel DP. The input sensing layer ISU completely overlaps with the display area DA. In one embodiment, for example, the input sensing layer ISU may overlap with the first non-bending area NBA1.

[0066] The input sensing layer ISU may detect an external input (eg, a touch) provided to the display device DD.

[0067] In one embodiment, for example, the input sensing layer ISU may detect external input inputted through a part of the user's body (e.g., fingertips). However, embodiments of the invention are not limited to methods of inputting external inputs. Alternatively, the external input may be inputted through methods such as optical, contact, or magnetic methods.

[0068] Although not shown in the drawings, the input sensing layer ISU may include a plurality of input sensing electrodes (not shown) that detect external inputs.

[0069] The input sensing layer ISU may detect external input by various methods. In one embodiment, for example, the input sensing layer ISU may be driven in a method such as a capacitance method, a resistance film method, or a coordinate recognition method.

[0070] The anti-reflection layer RPP is disposed on the input sensing layer ISU. The anti-reflection layer RPP completely overlaps with the display area DA on a plane. In one embodiment, for example, the anti-reflection layer RPP may overlap with the first non-bending area NBA1.

[0071] The anti-reflection layer RPP prevents external light incident from the outside into the display device DD from being reflected by the display module DM, thereby preventing the reflected light from being seen by the user. Although not shown, the anti-reflection layer RPP may include a polarization layer (not shown) and a phase retardation layer (not shown).

[0072] The polarizing layer has a transmission axis and an absorption axis perpendicular to the transmission axis. One of the components of external light incident into the polarizing layer is absorbed or reflected by the absorption axis and is not transmitted through the transmission axis, and a component perpendicular to the one of the components of external light incident into the polarizing layer is transmitted through the transmission axis. That is, the polarizing layer selectively polarizes external light.

[0073] In such an embodiment, the polarizing layer may include or be made of a polymer resin elongated in a specific direction. However, embodiments of the present invention are not limited to such polarizing layers. In an alternative embodiment of the invention, the polarizing layer may be a wire grid polarizer.

[0074] The phase retarder layer can be arranged below the polarization layer. The phase retarder layer has optical anisotropy. Therefore, the phase retarder layer can delay the phase of one component of the incident light. That is, the phase retarder layer is used to change the polarization state of the light. In one embodiment, for example, the phase retarder layer can delay one component of the incident light by about λ / 4. In such an embodiment, the phase retarder layer can be a quarter-wavelength film. Therefore, when the phase of one component of the light passing through the phase retarder layer is delayed, the light can be converted from a linear polarization state to a circular polarization state or from a circular polarization state to a linear polarization state.

[0075] According to such an embodiment, although external light incident into the display device DD from the outside is reflected by the display module DM, since the polarization state is changed by the phase retardation layer, the external light is absorbed or reflected by the polarization layer. Therefore, the external light reflected by the display module DM is not seen from the outside of the display device DD.

[0076] Although the anti-reflection layer RPP may be disposed above the display panel DP as described above, embodiments of the invention are not limited thereto. In an alternative embodiment, for example, the anti-reflection layer RPP may be disposed inside the display panel DP.

[0077] In another alternative embodiment of the invention, the input sensing layer ISU and the anti-reflection layer RPP may be omitted.

[0078] Although not shown in the drawings, the display module DM may further include a plurality of adhesive members (not shown) disposed between the input sensing layer ISU and the anti-reflection layer RPP or between the display panel DP and the input sensing layer ISU to couple the input sensing layer ISU and the anti-reflection layer RPP to each other or to couple the display panel DP and the input sensing layer ISU to each other.

[0079] In an embodiment, Figure 3 As shown in , the protection member PF is disposed on the bottom surface of the display panel DP. The protection member PF overlaps the first non-bending area NBA1 and the second non-bending area NBA2. The protection member PF may include a first protection member PF and a second protection member PF separated or spaced apart from each other. The first protection member PF and the second protection member PF overlap the first non-bending area NBA1 and the second non-bending area NBA2, respectively, and face each other in a bent state of the display module DM.

[0080] The circuit board DC is connected to one side of the display module DM in the first direction DR1. In an embodiment, the circuit board DC is connected to the second non-bending area NBA2 of the display module DM. Figure 1 As shown in , the circuit board DC may include a flexible film CB and a driving circuit DV.

[0081] The flexible film CB is connected to the second non-bending area NBA2 of the display module DM. The flexible film CB may be electrically connected to the display module DM through an adhesive member (not shown). The adhesive member may include a transparent adhesive or an anisotropic conductive film.

[0082] The driving circuit DV may be disposed or mounted on the flexible film CB. The driving circuit DV is electrically connected to the flexible film CB through a circuit line (not shown) of the flexible film CB. The flexible film CB may electrically connect the driving circuit DV to the display panel DP, and the driving circuit DV may generate an electrical signal to be provided to the display panel DP or process an electrical signal provided from the display panel DP.

[0083] In an embodiment, although not shown in the drawings, the display device DD may further include a window (not shown). The window may be disposed above the anti-reflection layer RPP. The window defines the front surface of the display device DD and protects the anti-reflection layer RPP, the input sensing layer ISU, and the display panel DP. In an embodiment, for example, the window may include a glass substrate, a sapphire substrate, or a plastic film. The window may have a multi-layer or single-layer structure. In an embodiment, for example, the window may have a stacked structure in which a plurality of plastic films are bonded or stacked to each other by an adhesive or a stacked structure in which a glass substrate and a plastic film are bonded to each other by an adhesive.

[0084] Figure 4 It is shown Figure 3A cross-sectional view of the display panel DP in FIG. Figure 4 A cross section defined by the first direction DR1 and the third direction DR3 is shown. Figure 4 is a schematic diagram showing a stacking relationship between functional panels and / or functional units constituting the display device DD.

[0085] Combination Figure 3 Reference Figure 4 , an embodiment of the display panel DP may be an organic light emitting display panel. In such an embodiment, the display element included in the display panel DP may be an organic light emitting diode OLED.

[0086] In an embodiment, Figure 4 As shown in FIG. 1 , the display panel DP includes a base layer BL, a circuit layer CL and a display layer DPL.

[0087] The base layer BL defines the rear surface of the display panel DP. The base layer BL includes or contains an insulating material. The base layer BL may include a metal substrate, a glass substrate, a plastic substrate, or an insulating film.

[0088] The circuit layer CL is disposed on the base layer BL. The circuit layer CL may include a circuit for driving a plurality of organic light emitting diodes OLED (refer to Figure 6 and Figure 8 ) of multiple thin film transistors (not shown), multiple signal lines (not shown) and multiple insulating layers (not shown).

[0089] The display layer DPL is disposed on the circuit layer CL. The display layer DPL is disposed in the first non-bending area NBA1. The display layer DPL includes a pixel layer ELL and an encapsulation layer TFE.

[0090] The pixel layer ELL includes a plurality of organic light emitting diodes OLED (refer to Figure 6 and Figure 8 ), organic light emitting diode OLED (refer to Figure 6 and Figure 8 ) of the pixel defining layer 40 (refer to Figure 8 ) and the protective layer 50 (refer to Figure 8 ). An organic light-emitting diode OLED of the pixel layer ELL (refer to Figure 6 and Figure 8 ) and the circuit layer CL connected to the one organic light emitting diode OLED (reference Figure 6 and Figure 8 ) can define a pixel PX (refer to Figure 5 and Figure 6 In such an embodiment, the display panel DP includes a plurality of pixels PX (refer to Figure 5 and Figure 6 ).

[0091] The encapsulation layer TFE is disposed on the pixel layer ELL to cover the pixel layer ELL. The encapsulation layer TFE seals the pixel layer ELL. The encapsulation layer TFE may include a plurality of stacked organic layers and / or inorganic layers. Optionally, the encapsulation layer TFE may be a planarization layer that provides a flat surface for the layer below it or planarizes the top surface of the pixel layer ELL. However, embodiments of the invention are not limited thereto. Optionally, the encapsulation layer TFE may have various types of structures.

[0092] Will refer to later Figures 8 to 10 The circuit layer CL and the display layer DPL are described in more detail.

[0093] Figure 5 is a plan view showing a display panel DP according to an embodiment of the invention. Figure 5 is a diagram showing a state in which the above-described circuit layer CL and pixel layer ELL are provided on the base layer BL.

[0094] Reference Figure 5 As described above, the embodiment of the display panel DP includes the display area DA and the non-display area NDA on a plane. The non-display area NDA is defined along the edge of the display area DA to surround the display area DA.

[0095] In an embodiment, the non-display area NDA includes a first non-display area NDA1 and a second non-display area NDA2. The first non-display area NDA1 surrounds the display area DA. The conductive patterns CP1 and CP2 to be described later may be disposed in the first non-display area NDA1. In such an embodiment, the first non-display area NDA1 and the display area DA may completely overlap with the first non-bending area NBA1.

[0096] The second non-display area NDA2 is disposed adjacent to one side of the first non-display area NDA1 in the first direction DR1 and includes a line area NDA-CL and a panel pad area NDA-PDA.

[0097] The line area NDA-CL overlaps the bending area BA. In an embodiment, the line area NDA-CL may be as follows Figure 5 The line area NDA-CL shown in FIG. 1 is the same as the bending area BA, but the embodiments of the invention are not limited thereto. Optionally, the line area NDA-CL may be larger than the bending area BA on the display panel DP.

[0098] The panel pad area NDA-PDA is disposed on one side of the second non-display area NDA2 in the first direction DR1. The panel pad area NDA-PDA overlaps the second non-bending area NBA2.

[0099] On a plane, the display panel DP includes a plurality of conductive patterns CP1 and CP2 , a plurality of signal lines DL, GL, PL, SL1 , and SL2 , a plurality of panel pads DP-PD, and a plurality of pixels PX.

[0100] The pixels PX are arranged in the display area DA. Each pixel PX includes an organic light emitting diode and a pixel driving circuit connected to the organic light emitting diode. The signal lines DL, GL, PL, SL1 and SL2, a plurality of conductive patterns CP1 and CP2, a plurality of panel pads DP-PD, and the pixel driving circuit may be arranged Figure 4 In the circuit layer CL.

[0101] The signal lines DL, GL, PL, SL1 and SL2 are disposed in the entire areas DA and NDA of the display panel DP and include a scan line GL, a data line DL, a power line PL, a first signal line SL1 and a second signal line SL2.

[0102] Each scan line GL is connected to a corresponding pixel PX among the pixels PX, and each data line DL is connected to a corresponding pixel PX among the pixels PX. A power line PL is connected to each pixel PX. A first signal line SL1 is connected to a second conductive pattern CP2, and a second signal line SL2 is connected to a first conductive pattern CP1.

[0103] The conductive patterns CP1 and CP2 are disposed in the first non-display area NDA1. The conductive patterns CP1 and CP2 include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 and the second conductive pattern CP2 are insulated from each other. In an embodiment, the first conductive pattern CP1 and the second conductive pattern CP2 are spaced apart from each other in the first non-display area NDA. Figure 5 As shown in , but the embodiments of the present invention are not limited thereto. Optionally, the first conductive pattern CP1 and the second conductive pattern CP2 may be disposed on different layers from each other. In such an embodiment, the first conductive pattern CP1 and the second conductive pattern CP2 may overlap each other on a plane.

[0104] The first conductive pattern CP1 may be connected to the power line PL extending from the display area DA. The power line PL may be connected to one first conductive pattern CP1 and respectively provide the pixels PX with the first power supply voltage ELVDD (refer to Figure 6 ).

[0105] The second conductive pattern CP2 is connected to the organic light emitting diode OLED to provide a second power signal. The second conductive pattern CP2 may provide the pixels PX with second power voltages ELVSS (refer to Figure 6 ).

[0106] A plurality of panel pads DP-PD are arranged in the panel pad area NDA-PDA. The plurality of panel pads DP-PD include a first signal pad PD1, a second signal pad PD2 and a plurality of display signal pads DPD. The first signal pad PD1 is connected to a first signal line SL1. The second signal pad PD2 is connected to a second signal line SL2. The display signal pads DPD are respectively connected to corresponding data lines DL.

[0107] In such an embodiment, the signal lines DL, GL and PL connected to the pixel PX constitute most of the signal lines DL, GL, PL, SL1 and SL2. The signal lines DL, GL and PL connected to the pixel PX are connected to the transistors T1 and T2 of the pixel PX (refer to Figure 6 ). The signal lines DL, GL, and PL connected to the pixel PX may have a single-layer or multi-layer structure and may have a single body or be divided into two or more parts. The two or more parts may be disposed on layers different from each other and may be connected to each other through a contact hole defined or extended through an insulating layer disposed between the two or more parts.

[0108] exist Figure 5 , a circuit board DC electrically connected to a display panel DP is shown. The flexible board CB of the circuit board DC may include a board pad DC-PD electrically connected to the display panel DP. In an embodiment, the board pad DC-PD is disposed in a board pad area DC-PDA defined on the flexible board CB. Although not shown, the flexible board CB may further include a signal line (not shown) connecting the board pad DC-PD to the drive circuit DV.

[0109] Figure 6 is an equivalent circuit diagram showing a pixel PX according to an embodiment of the invention. Figure 6 , a pixel PX and a corresponding scan line GL, a corresponding data line DL, and a power line PL connected to the pixel PX are shown. However, the embodiments of the invention are not limited to Figure 6 The configuration of the pixel PX in FIG. 4 may be modified in various ways.

[0110] Reference Figure 6 , the organic light emitting diode OLED may be a front light emitting element or a rear light emitting element. The pixel PX includes a pixel driving circuit for driving the organic light emitting diode OLED. The pixel PX includes a first transistor T1 (or a switching transistor), a second transistor T2 (or a driving transistor), and a capacitor Cst. A first power supply voltage ELVDD is provided to the second transistor T2, and a second power supply voltage ELVSS is provided to the organic light emitting diode OLED. The second power supply voltage ELVSS may be less than the first power supply voltage ELVDD.

[0111] The first transistor T1 outputs a data signal applied to the data line DL in response to a scan signal applied to the scan line GL. The capacitor Cst charges a voltage corresponding to the data signal received from the first transistor T1. The second transistor T2 is connected to the organic light emitting diode OLED. The second transistor T2 controls a driving current flowing through the organic light emitting diode OLED corresponding to the charge stored in the capacitor Cst.

[0112] although Figure 6 An embodiment of an equivalent circuit is shown in FIG. 1 , but the embodiments of the invention are not limited thereto. Optionally, the pixel PX may further include three or more transistors and a plurality of capacitors. The second transistor T2 may be connected between the power line PL and the organic light emitting diode OLED.

[0113] Figure 7 is a plan view showing a display panel DP according to an embodiment of the invention. Figure 7 A state in which the encapsulation layer TFE is provided on the base layer BL is shown.

[0114] Combination Figure 6 Reference Figure 7 , the embodiment of the display panel DP further includes a plurality of protruding members DAM1, DAM2 and BNK. The protruding members DAM1, DAM2 and BNK are disposed on the outside of the display area DA, that is, in the first non-display area NDA1. The protruding members DAM1, DAM2 and BNK are disposed to surround the display area DA.

[0115] The plurality of protruding members DAM1 , DAM2 , and BNK include a first dam DAM1 , a second dam DAM2 , and a bank BNK.

[0116] The first dam DAM1 has a frame shape surrounding the display area DA in a plane. The second dam DAM2 is disposed on the outer side of the first dam DAM1 in a plane. In such an embodiment, the first dam DAM1 is disposed relatively closer to the display area DA than the second dam DAM2. The second dam DAM2 has a frame shape surrounding the first dam DAM1. The first dam DAM1 and the second dam DAM2 may prevent an organic monomer (an organic monomer is applied to form an organic layer (e.g., Figure 8 The OL in the figure overflows from the display area DA to the outside.

[0117] In an embodiment, each of the first dam DAM1 and the second dam DAM2 has a Figure 7 , but the embodiments of the invention are not limited thereto. Alternatively, each of the first dam DAM1 and the second dam DAM2 may surround only at least one side of the display area DA.

[0118] The bank BNK is disposed on the outer side of the second dam DAM2. In an embodiment, the bank BNK is disposed at one side of the second dam DAM2 in the first direction DR1. The bank BNK serves as a spacer that prevents a mask used during a process of manufacturing the display panel DP and the input sensing layer ISU from contacting components of the display panel DP and components of the input sensing layer ISU. In such an embodiment, the bank BNK may have a certain width in the first direction DR1 that is greater than a width of each of the first dam DAM1 and the second dam DAM2.

[0119] In an embodiment, Figure 7 As shown in FIG. 1 , the bank BNK is disposed only on one side of the first non-display area NDA1 in the first direction DR1 , but the embodiments of the invention are not limited thereto. Alternatively, the bank BNK may be disposed on at least two edge portions of four edge portions defining the first non-display area NDA1 .

[0120] According to an embodiment of the invention, at least a portion of one of the protruding members BNK, DAM1, and DAM2 may overlap the conductive patterns CP1 and CP2. Figures 8 to 10 In the embodiment, at least a portion of the first dam DAM1 overlaps the first conductive pattern CP1 in plane.

[0121] Although not shown, an embodiment of the display panel DP may further include a crack dam (not shown) disposed in the first non-display area NDA1. The crack dam (not shown) may be disposed on the outer side of the second dam DAM2. In one embodiment, for example, the crack dam (not shown) may be disposed on the outer side of the second dam DAM2 in the second direction DR2, and may have a shape extending in the first direction DR1 on a plane. When an external stimulus is applied, the crack dam (not shown) may perform a crack prevention function of absorbing an impact to prevent the impact from being transmitted toward the display area DA.

[0122] Figure 8 is along Figure 7 A cross-sectional view taken along line II”, Fig. 9 is along Figure 7 A cross-sectional view taken along line I'-I"'. Fig.10 is along Figure 7 A cross-sectional view taken along line II-II'.

[0123] Reference Figures 8 to 10 , the circuit layer CL, the pixel layer ELL and the encapsulation layer TFE are sequentially disposed on the base layer BL.

[0124] In an embodiment, the circuit layer CL includes a plurality of insulating layers BF, 10, 20, and 30. The plurality of insulating layers BF, 10, 20, and 30 include a barrier layer BF as an inorganic layer, a first intermediate insulating layer 10, a second intermediate insulating layer 20, and an upper insulating layer 30. Each of the barrier layer BF, the first intermediate insulating layer 10, and the second intermediate insulating layer 20 includes an inorganic material. The upper insulating layer 30 includes an inorganic material or an organic material. However, embodiments of the invention are not specifically limited to a specific kind of inorganic material or organic material.

[0125] The semiconductor pattern SP1 of the first transistor T1 (hereinafter, referred to as the first semiconductor pattern) and the semiconductor pattern SP2 of the second transistor T2 (hereinafter, referred to as the second semiconductor pattern) are disposed on the barrier layer BF. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include at least one selected from amorphous silicon, polycrystalline silicon, and a metal oxide semiconductor.

[0126] The first intermediate insulating layer 10 is disposed on the first and second semiconductor patterns SP1 and SP2 . The control electrode GE1 (hereinafter, referred to as the first control electrode) of the first transistor T1 and the control electrode GE2 (hereinafter, referred to as the second control electrode) of the second transistor T2 are disposed on the first intermediate insulating layer 10 .

[0127] A second intermediate insulating layer 20 covering the first control electrode GE1 and the second control electrode GE2 is disposed on the first intermediate insulating layer 10. An input electrode IE1 (hereinafter, referred to as a first input electrode) and an output electrode OE1 (hereinafter, referred to as a first output electrode) of the first transistor T1 and an input electrode IE2 (hereinafter, referred to as a second input electrode) and an output electrode OE2 (hereinafter, referred to as a second output electrode) of the second transistor T2 are disposed on the second intermediate insulating layer 20.

[0128] Each of the first input electrode IE1 and the first output electrode OE1 is connected to the first semiconductor pattern SP1 through a contact hole defined through the first and second intermediate insulating layers 10 and 20. Each of the second input electrode IE2 and the second output electrode OE2 is connected to the second semiconductor pattern SP2 through a contact hole defined through the first and second intermediate insulating layers 10 and 20.

[0129] Despite Figure 8 Each of the first transistor T1 and the second transistor T2 has a top gate structure in which the first control electrode GE1 and the second control electrode GE2 are disposed above the first semiconductor pattern SP1 and the second semiconductor pattern SP2, but the embodiment of the invention is not limited thereto. Alternatively, one of the first transistor T1 and the second transistor T2 may have a bottom gate structure.

[0130] The first input electrode IE1, the second input electrode IE2, and an upper insulating layer 30 covering the first and second input electrodes IE1 and IE2 are disposed on the second intermediate insulating layer 20. The upper insulating layer 30 may provide a planarized surface.

[0131] In an embodiment, the circuit layer CL may include a plurality of via layers VA1 and VA2 and a plurality of connection electrodes SCH1 and SCH2 .

[0132] The first via layer VA1 is disposed on the upper insulating layer 30. The first connection electrode SCH1 is disposed on the first via layer VA1. The first connection electrode SCH1 is connected to the second output electrode OE2 through a contact hole defined through the first via layer VA1.

[0133] The second via layer VA2 is disposed on the first via layer VA1. The second connection electrode SCH2 is disposed on the second via layer VA2. The second connection electrode SCH2 is connected to the first connection electrode SCH1 through a contact hole defined through the second via layer VA2.

[0134] In an alternative embodiment of the invention, the plurality of via layers VA1 and VA2 and the plurality of connection electrodes SCH1 and SCH2 may be omitted.

[0135] The display layer DPL is disposed on the second via layer VA2 . In an embodiment where the via layers VA1 and VA2 and the connection electrodes SCH1 and SCH2 are omitted, the display layer DPL may be disposed on the upper insulating layer 30 .

[0136] The display layer DPL includes a pixel defining layer 40 , an organic light emitting diode OLED, a protection layer 50 , and an encapsulation layer TFE.

[0137] The pixel defining layer 40 may include an organic material. The first electrode E1 is disposed on the second through-hole layer VA2. The first electrode E1 is connected to the second connection electrode SCH2 through a contact hole CH defined through the second through-hole layer VA2. In such an embodiment, the first electrode E1 is electrically connected to the second output electrode OE2 through the first connection electrode SCH1 and the second connection electrode SCH2. An opening is defined in the pixel defining layer 40. The opening of the pixel defining layer 40 exposes at least a portion of the first electrode E1. In an embodiment of the invention, the pixel defining layer 40 may be omitted.

[0138] The light emitting layer EL may be disposed in a region corresponding to the opening. In an embodiment, the light emitting layer EL may be patterned and separately disposed in each pixel PX (refer to Figure 5 and Figure 6 ). The light emitting layer EL may include an organic material and / or an inorganic material. The light emitting layer EL may generate colored light having a predetermined color.

[0139] In an embodiment, the light emitting layer EL may be patterned into portions separated from each other to be respectively disposed in the pixels PX, but the embodiments of the invention are not limited thereto. In an alternative embodiment, for example, the light emitting layer EL may be commonly disposed in the pixels PX (refer to Figure 5 and Figure 6 ). In such an embodiment, the light emitting layer EL may generate white light. In an embodiment, the light emitting layer EL may have a multilayer structure called a tandem. Here, "commonly disposed on..." may mean "formed integrally as a single unit to completely cover".

[0140] The second electrode E2 is disposed on the light emitting layer EL. The second electrode E2 is commonly disposed in the pixel PX (refer to Figure 5 and Figure 6 )superior.

[0141] The protection layer 50 covers the second electrode E2.

[0142] The encapsulation layer TFE is disposed on the pixel layer ELL. In an embodiment, the encapsulation layer TFE is disposed on the protective layer 50. The encapsulation layer TFE is disposed on the pixel layer PX (refer to Figure 5 and Figure 6 ) Figure 7 As shown in FIG. 1 , the encapsulation layer TFE is disposed on at least a portion of the display area DA and the first non-display area NDA1 . That is, on a plane, an area occupied by the encapsulation layer TFE may be smaller than an area occupied by the first non-bending area NBA1 .

[0143] The encapsulation layer TFE includes a lower encapsulation layer IOL1, an organic layer OL, and an upper encapsulation layer IOL2. However, the embodiments of the invention are not limited thereto. In one embodiment, for example, the encapsulation layer TFE may also include an inorganic layer and an organic layer, and at least one of the lower encapsulation layer IOL1, the organic layer OL, and the upper encapsulation layer IOL2 may be omitted.

[0144] The lower encapsulation layer IOL1 is disposed on the pixel layer ELL to directly contact the pixel layer ELL. The lower encapsulation layer IOL1 may be an inorganic layer including an inorganic compound.

[0145] The organic layer OL is disposed on the lower encapsulation layer 10L1. The organic layer OL may include an organic compound. The organic layer OL may have a relatively larger thickness than the thickness of each layer adjacent thereto. In one embodiment, for example, the thickness of the organic layer OL may be greater than the thickness of each of the lower encapsulation layer 10L1 and the upper encapsulation layer 10L2. The organic layer OL may be used as a protective layer for protecting the organic light emitting diode OLED, or as a planarization layer for planarizing the top surface.

[0146] The upper encapsulation layer IOL2 is disposed on the organic layer OL. The upper encapsulation layer IOL2 may be an inorganic layer including an inorganic compound. The upper encapsulation layer IOL2 may cover the organic layer OL to prevent the organic layer OL from contacting the outside. In such an embodiment, the upper encapsulation layer IOL2 may prevent moisture generated from the organic layer OL from escaping to the outside.

[0147] In an embodiment, Fig. 9 As shown in FIG. 1 , the protruding members DAM1, DAM2 and BNK are disposed between the circuit layer CL and the encapsulation layer TFE. The lower encapsulation layer IOL1 and the upper encapsulation layer IOL2 are bonded to each other on the first non-display area NDA1 and cover the protruding members DAM1, DAM2 and BNK. In such an embodiment, as shown in FIG. Fig. 9 As shown in FIG. 1 , the lower encapsulation layer IOL1 and the upper encapsulation layer IOL2 may cover only a portion of the bank BNK among the protruding members DAM1 , DAM2 , and BNK adjacent to the display area DA.

[0148] Each of the protruding members DAM1 , DAM2 , and BNK is disposed on the upper insulating layer 30 in a partial region of the first non-display area NDA1 on which the via layers VA1 and VA2 are not disposed.

[0149] Each of the protruding members DAM1, DAM2, and BNK may include a plurality of layers. In one embodiment, for example, the first dam DAM1 may be constructed by stacking two layers D1-1 and D1-2, and the second dam DAM2 may be constructed by stacking three layers D2-1, D2-2, and D2-3. The bank BNK may be constructed by stacking three layers BK-1, BK-2, and BK-3. In an embodiment, as Fig. 9 and Fig.10 As shown in , the opening OP may be defined through a portion of the upper insulating layer 30 , a portion of the second intermediate insulating layer 20 , a portion of the first intermediate insulating layer 10 , and a portion of the barrier layer BF located in the bending area BA on a plane.

[0150] In an embodiment, Fig. 9 As shown in FIG. 1 , a bank bonding hole CHB defined through the upper insulating layer 30 may be defined in the first non-display area NDA1 disposed adjacent to the bending area BA. In such an embodiment, a portion of the top surface of the second intermediate insulating layer 20 may be exposed through the bank bonding hole CHB.

[0151] The bank combination hole CHB overlaps the bank BNK on a plane. The bank BNK may be filled in the bank combination hole CHB. In one embodiment, for example, the first portion BK-1 as the lowermost portion of the bank BNK may be filled in the bank combination hole CHB. In such an embodiment, the second intermediate insulating layer 20 and the bank BNK may be combined with each other through the bank combination hole CHB.

[0152] In an embodiment, Fig.10 As shown in FIG. 1 , the bank coupling hole CHB is not defined in a region where the bank BNK overlaps one of the conductive patterns CP1 and CP2. The bank coupling hole CHB is insulated from the conductive patterns CP1 and CP2. That is, the bank coupling hole CHB according to the embodiment may be defined only in a region overlapping the bank BNK but not overlapping the conductive patterns CP1 and CP2.

[0153] In such an embodiment, a package coupling hole CHT defined through the upper insulating layer 30 may be defined in the first non-display area NDA1 disposed adjacent to the bending area BA. In such an embodiment, a portion of the top surface of the second intermediate insulating layer 20 may be exposed through the package coupling hole CHT.

[0154] The package coupling hole CHT is defined in plane between the bank BNK and the second dam DAM2. However, the embodiments of the invention are not limited thereto. Alternatively, although not shown in the drawings, the package coupling hole CHT may be defined in plane between the second dam DAM2 and the first dam DAM1.

[0155] At least the lower encapsulation layer IOL1 of the lower encapsulation layer IOL1 and the upper encapsulation layer IOL2 may be filled in the encapsulation coupling hole CHT. In such an embodiment, the second intermediate insulating layer 20 and the encapsulation layer TFE may be coupled to each other through the encapsulation coupling hole CHT.

[0156] According to an embodiment of the invention, since the bank coupling hole CHB is defined in the first non-bending area NBA1 disposed adjacent to the bending area BA, the contact area between the circuit layer CL and the bank BNK may be increased. In such an embodiment, the coupling force between the circuit layer CL and the bank BNK may be increased.

[0157] In embodiments, since the package bonding hole CHT is defined in the first non-bending area NBA1 disposed adjacent to the bending area BA, the contact area between the circuit layer CL and the encapsulation layer TFE may be increased. In such embodiments, the bonding force between the circuit layer CL and the encapsulation layer TFE may be increased.

[0158] Hereinafter, for convenience of description, a portion of the first non-bending area NBA1 or the first non-display area NDA1 defined between the bending area BA and the display area DA is defined as an invalid space DS (refer to Figure 5 and Figure 7 According to an embodiment of the invention, the dead space DS may have a width of about 400 micrometers (μm) or less in the first direction DR1.

[0159] In a conventional display device in which the coupling holes CHB and CHT are not defined on the invalid space DS, as the display panel DP is bent, bending stress acts in a direction from the bending area BA toward the display area DA. In this case, cracks may occur in the display area DA, or delamination may occur in each of the base layer BL, the circuit layer CL, and the display layer DPL. Specifically, as the width of the invalid space DS in the first direction DR1 decreases, the bending stress acting on the display area DA increases significantly. However, according to an embodiment of the invention, the coupling holes CHB and CHT are defined in the invalid space DS, so that the bonding force between the bank BNK and the circuit layer CL and between the encapsulation layer TFE and the circuit layer CL increases. Therefore, even when the bending area BA of the display panel DP is bent, the phenomenon of cracks occurring in the display area DA or delamination occurring in each of the base layer BL, the circuit layer CL, and the display layer DPL can be eliminated or substantially reduced. In such an embodiment, even when the bending area BA of the display panel DP is bent, the coupling holes CHB and CHT can absorb the bending stress transmitted from the bending area BA to the display area DA. In such an embodiment, the durability of the display device DD can be improved.

[0160] According to an embodiment of the present invention, each of the coupling holes CHB and CHT may have a width in the first direction DR1 that is differently set according to the size of the display panel DP and the width of the invalid space DS in the first direction DR1. As the width of each of the coupling holes CHB and CHT in the first direction increases, the absorption amount of the bending stress transmitted to the display area DA may increase. For example, when the invalid space DS has a width of about 400 μm or less in the first direction DR1, each of the coupling holes CHB and CHT may have a width of about 5 μm or more and about 200 μm or less in the first direction DR1. However, embodiments of the invention are not particularly limited to the width of each of the coupling holes CHB and CHT in the first direction DR1.

[0161] Fig.11 is a cross-sectional view showing a display panel DP-1 according to an alternative embodiment of the invention.

[0162] In addition to the bank-binding hole CHB-1, Fig.11 The cross-sectional view in Fig. 9 The cross-sectional view shown in FIG. 1 is substantially the same as that used to describe the Fig. 9 The exemplary embodiments of the display device shown in FIG. Fig.11 The same or similar elements shown in FIG. 1 are shown in FIG. 1 , and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0163] Reference Fig.11, the bank bonding hole CHB-1 of the display panel DP-1 may have a Fig. 9 The depth of the bank described in conjunction with the depth of the hole CHB is as deep as the depth of the hole CHB.

[0164] In such an embodiment, the bank combination hole CHB-1 may be defined to pass through the upper insulating layer 30, the intermediate insulating layers 10 and 20, and the barrier layer BF. In such an embodiment, a portion of the top surface of the base layer BL may be exposed through the bank combination hole CHB-1. The bank combination hole CHB-1 overlaps the bank BNK-1 on a plane. The bank BNK-1 may be filled in the bank combination hole CHB-1. In such an embodiment, the base layer BL and the bank BNK-1 may be connected to each other through the bank combination hole CHB-1.

[0165] According to embodiments, a contact area between the circuit layer CL and the bank BNK- 1 may be further increased due to the bank coupling hole CHB- 1 .

[0166] Fig.12 is a cross-sectional view showing a display panel DP-2 according to another alternative embodiment of the invention.

[0167] In addition to the binding holes CHD1 and CHD2, Fig.12 The cross-sectional view in Fig. 9 The cross-sectional view shown in FIG. 1 is substantially the same as that used to describe the Fig. 9 The exemplary embodiments of the display device shown in FIG. Fig.12 The same or similar elements shown in FIG. 1 are shown in FIG. 1 , and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0168] Reference Fig.12 , the display panel DP-2 includes dam coupling holes, for example, a first dam coupling hole CHD1 and a second dam coupling hole CHD2.

[0169] In an embodiment, Fig.12 As shown in , the first dam bonding hole CHD1 or the second dam bonding hole CHD2 defined or extended through the upper insulating layer 30 may be defined in the first non-display area NDA1 disposed adjacent to the bending area BA. In such an embodiment, a portion of the top surface of the second intermediate insulating layer 20 may be exposed by the first dam bonding hole CHD1 or the second dam bonding hole CHD2.

[0170] The first dam coupling hole CHD1 overlaps the first dam DAM1-2. The first dam DAM1-2 may be filled in the first dam coupling hole CHD1. In one embodiment, for example, the first portion D1-1 as the lowermost portion of the first dam DAM1-2 may be filled in the first dam coupling hole CHD1. That is, the second intermediate insulating layer 20 and the first dam DAM1-2 may be coupled to each other through the first dam coupling hole CHD1. The first dam coupling hole CHD1 is insulated from the first conductive pattern CP1 by the second intermediate insulating layer 20.

[0171] The second dam coupling hole CHD2 overlaps the second dam DAM2-2. The second dam DAM2-2 may be filled in the second dam coupling hole CHD2. In one embodiment, for example, the first portion D2-1 as the lowermost portion of the second dam DAM2-2 may be filled in the second dam coupling hole CHD2. In such an embodiment, the second intermediate insulating layer 20 and the second dam DAM2-2 may be coupled to each other through the second dam coupling hole CHD2.

[0172] Fig.13 is a cross-sectional view showing a display panel DP-3 according to another embodiment of the invention.

[0173] In addition to the bank-binding hole CHB-3, Fig.13 The cross-sectional view in Fig. 9 The cross-sectional view shown in FIG. 1 is substantially the same as that used to describe the Fig. 9 The exemplary embodiments of the display device shown in FIG. Fig.13 The same or similar elements shown in FIG. 1 are shown in FIG. 1 , and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0174] Reference Fig.13 In an embodiment, the bank combining hole CHB-3 of the display panel DP-3 may be provided in plurality.

[0175] In such an embodiment, a plurality of bank bonding holes CHB-3 defined through the upper insulating layer 30 may be defined in the first non-display area NDA1 disposed adjacent to the bending area BA. The plurality of bank bonding holes CHB-3 overlap the bank BNK-3 on a plane. The bank BNK-3 and the second intermediate insulating layer 20 may be bonded to each other through the bank bonding holes CHB-3.

[0176] According to the embodiment, since the bank coupling hole CHB- 3 is provided in plural, the contact area between the circuit layer CL and the bank BNK- 3 may be further increased.

[0177] Fig.14 is a cross-sectional view showing a display panel DP-4 according to another embodiment of the invention.

[0178] In addition to the package bonding hole CHT-4 or the dam bonding hole CHD2-4, Fig.14 The cross-sectional view in Fig.12 The cross-sectional view shown in FIG. 1 is substantially the same as that used to describe the Fig.12 The exemplary embodiments of the display device shown in FIG. Fig.14 The same or similar elements shown in FIG. 1 are shown in FIG. 1 , and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0179] Reference Fig.14 , in an embodiment, the package coupling hole CHT-4 or the dam coupling hole CHD2-4 of the display panel DP-4 may expose a portion of the barrier layer BF.

[0180] In such an embodiment, the package bonding hole CHT-4 may be defined or extended through the upper insulating layer 30 and the intermediate insulating layers 10 and 20. In such an embodiment, a portion of the top surface of the barrier layer BF may be exposed through the package bonding hole CHT-4.

[0181] In an embodiment, the dam coupling hole CHD2-4 may be defined or extended through the upper insulating layer 30 and the intermediate insulating layers 10 and 20. In such an embodiment, a portion of the top surface of the barrier layer BF may be exposed through the dam coupling hole CHD2-4. In such an embodiment, the second dam DAM2-4 and the barrier layer BF may be coupled to each other through the dam coupling hole CHD2-4.

[0182] In an embodiment, Fig.14 As shown in FIG, the first dam DAM1-4 overlaps the first conductive pattern CP1, and the second dam DAM2-4 does not overlap the first conductive pattern CP1, so that only the second dam coupling hole CHD2-4 is defined to expose the barrier layer BF. According to an alternative embodiment of the invention, when the second dam DAM2-4 overlaps the conductive patterns CP1 and CP2, and the first dam DAM1-4 does not overlap the conductive patterns CP1 and CP2, only the first dam coupling hole CHD1 may expose the barrier layer BF.

[0183] According to the embodiments of the invention, the display device can be improved in durability.

[0184] While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display device, comprising: a substrate layer, a display area and a non-display area surrounding the display area being defined on the substrate layer; A circuit layer, disposed on the base layer and comprising a plurality of insulating layers; a pixel layer, disposed in the display area and comprising a plurality of organic light emitting diodes; An encapsulation layer, disposed on the pixel layer to cover the pixel layer; as well as a protruding member disposed between the circuit layer and the encapsulation layer in the non-display area, wherein the bank bonding hole is defined in the circuit layer in the non-display area, wherein the bank coupling hole is defined to pass through at least an uppermost insulating layer among the plurality of insulating layers and overlap the protruding member in a plane, wherein the protruding member is provided in plurality, and the protruding member comprises: a dam provided to surround the display area; and a bank provided on the outer side of the dam in the first direction, and the bank combining hole overlaps with the bank on the plane, and Wherein, a package combining hole is defined to pass through at least the uppermost insulating layer in the non-display area, and the package combining hole is defined between the bank and the dam on the plane.

2. The display device according to claim 1, wherein: The circuit layer also includes: A barrier layer, disposed on the base layer; A plurality of thin film transistors are disposed on the barrier layer; and a plurality of conductive patterns are disposed on the barrier layer in the non-display area, and The plurality of insulating layers include: a plurality of intermediate insulating layers disposed on the barrier layer; and an upper insulating layer disposed on the plurality of intermediate insulating layers to cover the plurality of thin film transistors and the plurality of conductive patterns.

3. The display device according to claim 2, wherein: The bank coupling hole is defined through the upper insulating layer to expose a portion of the intermediate insulating layer, and The bank and the intermediate insulating layer are coupled to each other through the bank coupling hole.

4. The display device according to claim 2, wherein: The package combining hole is defined to pass through the upper insulating layer and the plurality of intermediate insulating layers, and The encapsulation layer and the barrier layer are coupled to each other through the encapsulation coupling hole.

5. The display device according to claim 2, wherein: The bank coupling hole is defined to pass through the upper insulating layer, the plurality of intermediate insulating layers, and the barrier layer, and The bank and the base layer are coupled to each other through the bank coupling hole.

6. The display device according to claim 5, wherein: The bank coupling hole does not overlap the plurality of conductive patterns on the plane and is insulated from the plurality of conductive patterns.

7. The display device according to claim 2, wherein: The circuit layer includes a dam coupling hole defined to pass through at least the upper insulating layer in the non-display area, and The dam coupling hole overlaps the dam on the plane.

8. The display device according to claim 7, wherein: The dam coupling hole overlaps at least a portion of the plurality of conductive patterns on the plane and is insulated from the plurality of conductive patterns.

9. The display device according to claim 7, wherein: The dam coupling hole is defined to pass through the upper insulating layer and the plurality of intermediate insulating layers, and The dam and the barrier layer are coupled to each other through the dam coupling hole.

10. The display device according to claim 9, wherein: The dam coupling hole does not overlap the plurality of conductive patterns on the plane and is insulated from the plurality of conductive patterns.

11. The display device according to claim 2, wherein: The dam is provided in a plurality of ways. The dam comprises: a first dam having a frame shape surrounding the display area on the plane; and a second dam having a frame shape surrounding the first dam on the plane, and At least one of the first dam and the second dam overlaps the plurality of conductive patterns.

12. The display device according to claim 1, wherein: The non-display area includes a bending area that is bent on the plane with respect to a bending axis that is perpendicular to the first direction.

13. The display device according to claim 12, wherein: A distance between the display area and the bending area in the first direction is 400 μm or less.

14. The display device according to claim 13, wherein: The bank coupling hole has a first direction width of 5 μm or more and 200 μm or less.

15. The display device according to claim 1, wherein: The bank combining holes are arranged in plurality.

16. The display device according to claim 1, wherein: The bank has a first-direction width greater than a first-direction width of the dam.

17. A display device, comprising: a substrate layer, a display area and a non-display area surrounding the display area being defined on the substrate layer; A circuit layer, disposed on the substrate layer; A display layer, disposed on the circuit layer; as well as a plurality of protruding members disposed on the circuit layer in the non-display area, wherein the circuit layer comprises: a plurality of insulating layers, wherein a combining hole is defined to pass through at least one uppermost insulating layer of the plurality of insulating layers in the non-display area; and a plurality of conductive patterns disposed between the plurality of insulating layers, and wherein at least one of the plurality of protruding members is filled in the combining hole, wherein the plurality of protruding members include: a dam disposed to surround the display area; and a bank disposed on an outer side of the dam in a first direction, and the coupling hole includes a bank coupling hole overlapped with the bank on a plane, Wherein, the dam is provided in multiple pieces, The dam comprises: a first dam having a frame shape surrounding the display area on the plane; and a second dam having a frame shape surrounding the first dam on the plane, and At least one of the first dam and the second dam overlaps the plurality of conductive patterns.

18. A display device, comprising: A display panel, a display area for displaying an image and a non-display area surrounding the display area are defined on the display panel, wherein at least a portion of the non-display area is bent, wherein the display panel comprises: a base layer; a circuit layer disposed on the base layer and comprising a plurality of insulating layers; a pixel layer disposed in the display area; an encapsulation layer disposed on the pixel layer to cover the pixel layer; and a dam disposed between the circuit layer and the encapsulation layer in the non-display area, wherein a dam coupling hole is defined in the circuit layer in a partial area disposed adjacent to a curved area in the non-display area, wherein the dam coupling hole is defined to pass through at least an upper insulating layer among the plurality of insulating layers, and wherein a lower portion of the dam is filled in the dam coupling hole, The display panel further comprises: a dam arranged to surround the display area; and the bank is arranged on the outer side of the dam in the first direction, and The circuit layer includes a dam coupling hole defined to pass through at least the upper insulating layer in the non-display area, and The dam combining hole overlaps with the dam in a plane.

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