On-chip passive power supply compensation circuit and operation unit, chip, computing power board and computing device applying same

Abstract

The application provides an on-chip passive power supply compensation circuit, an operation unit, a chip, a computing power board and a computing device applying the same. The on-chip passive power supply compensation circuit comprises two or more voltage domains to be powered, which are connected in series between a power supply and a ground; two or more isolation regions, in which the voltage domains to be powered are formed, the isolation regions being used for isolating the voltage domains to be powered; the isolation regions being connected in series between the power supply and the ground; and a power supply compensation unit connected between the voltage domains to be powered and the isolation regions, and used for providing power supply compensation to the voltage domains to be powered. The on-chip passive power supply compensation circuit can effectively reduce power consumption, design difficulty, chip area and production cost.

Description

Technical Field

[0001] This invention relates to a multi-voltage domain power supply circuit, and more particularly to a circuit that compensates for power supply voltage based on a substrate reference, as well as a computing unit, chip, computing board, and computing device using the same. Background Technology

[0002] Next-generation computing devices require a large number of repetitive logic computation pipelines. The core of this design lies in the performance-to-power ratio; higher performance and lower power consumption mean more computing power can be achieved with the same power consumption.

[0003] Furthermore, a large amount of repetitive logic calculations require a significant current supply to the computing device, resulting in substantial additional power consumption beyond that required for the logic calculations themselves. Therefore, it is necessary to reduce the operating current of the computing device to decrease its additional power consumption.

[0004] CN206039425U discloses a series power supply circuit, such as Figure 1 As shown, multiple package units are connected in series between the power supply terminal VCC and ground. Each package unit includes one or more groups of components. Each group of components includes a connected chip to be powered and an auxiliary power supply unit. A signal level conversion unit is connected in series between the chips to be powered in two adjacent groups of components. Although this series power supply circuit can provide a low power supply voltage to each chip to be powered, it is designed to provide series power to different package units on the printed circuit board and cannot provide series power to different voltage domains inside the chip.

[0005] Multi-supply voltage domain (MSV) power supply technology is increasingly widely used in System-on-Chip (SoC) and multiprocessor computing architectures. Chips employing MSV technology typically contain multiple independent voltage domains or voltage islands, with modules within each domain operating at appropriate supply voltages according to their timing requirements. Generally, timing-critical modules operate at higher supply voltages (VDDH) to meet the chip's speed performance requirements; while non-critical circuit modules operate at lower supply voltages (VDDL) or even subthreshold supply voltages to reduce power consumption and energy consumption.

[0006] CN206523836U discloses an internal series power supply system for a chip, such as Figure 2As shown, in a series power supply chip, each unit to be powered can include one chip core, or multiple chip cores connected in parallel. The chip core of each voltage domain includes a P-channel metal-oxide-semiconductor (PMOS) transistor and an N-channel metal-oxide-semiconductor (NMOS) transistor. The substrate of the PMOS transistor in each voltage domain is connected to the power supply voltage or operating voltage (VDD) of that voltage domain, and the VDD of that voltage domain is connected to the ground (VSS) of the previous voltage domain. The series power supply chip also includes n deep wells for isolation between different voltage domains. These n deep wells are independently configured and not connected to each other. Each of the n units to be powered is located in one deep well, thus achieving isolation between different voltage domains on the same chip and effectively preventing short circuits between different voltage domains. Although the internal series power supply system of the chip realizes the series power supply between different voltage domains inside the chip, each voltage domain needs to provide auxiliary voltage sources such as VDD_1 and VDD_2 in addition to the power supply VDD. Not only is the design of auxiliary voltage sources difficult, but it also occupies a large chip area and generates a large power consumption. Summary of the Invention

[0007] To address the aforementioned issues, this invention provides an on-chip passive power compensation circuit based on a substrate reference. This circuit not only reduces power consumption but also lowers design complexity, saves chip area, and reduces production costs.

[0008] To achieve the above objectives, the present invention provides an on-chip passive power compensation circuit, comprising:

[0009] Two or more voltage domains to be powered, wherein the voltage domains to be powered are connected in series between the power source and ground;

[0010] Two or more isolation regions, wherein the voltage domain to be supplied is formed within the isolation regions, and the isolation regions are used to isolate the voltage domain to be supplied.

[0011] The isolation zone is connected in series between the power source and the ground;

[0012] It also includes a power compensation unit, connected between the voltage domain to be powered and the isolation region, for providing power compensation to the voltage domain to be powered.

[0013] In the aforementioned on-chip passive power compensation circuit, the power compensation unit provides power compensation to the voltage domain to be supplied by operating in a saturation state.

[0014] In the aforementioned on-chip passive power compensation circuit, a first power supply terminal and a first ground terminal are formed at both ends of each of the isolation regions, and the first power supply terminal and / or the first ground terminal are used to provide a reference voltage to the power compensation unit.

[0015] In the aforementioned on-chip passive power compensation circuit, a second power supply terminal and a second ground terminal are formed at both ends of each of the voltage domains to be supplied with power, and the power compensation unit provides power compensation to the second power supply terminal and / or the second ground terminal.

[0016] In the aforementioned on-chip passive power compensation circuit, with the reference voltage as a reference, when the voltage variation range of the second power supply terminal and / or the second ground terminal exceeds the threshold of the power compensation unit, the power compensation unit operates in the saturation state.

[0017] In the aforementioned on-chip passive power compensation circuit, the power compensation unit is a switching transistor.

[0018] In the aforementioned on-chip passive power compensation circuit, the switching transistor is a PMOS switching transistor and / or an NMOS switching transistor.

[0019] In the aforementioned on-chip passive power compensation circuit, the PMOS switching transistor and / or the NMOS switching transistor may be one or more.

[0020] In the aforementioned on-chip passive power compensation circuit, one or more semiconductor devices are formed in the voltage domain to be powered, and the second power supply terminal and / or the second ground terminal provide a substrate bias to the semiconductor devices.

[0021] In the aforementioned on-chip passive power compensation circuit, the semiconductor device includes a PMOS transistor and / or an NMOS transistor, the second power supply terminal provides a substrate bias voltage to the PMOS transistor, and the second ground terminal provides a substrate bias voltage to the NMOS transistor.

[0022] To achieve the above objectives, the present invention also provides a data processing unit, wherein the data processing unit includes interconnected control circuits, processing circuits, storage circuits, and one or more on-chip passive power compensation circuits, wherein the on-chip passive power compensation circuit is any of the on-chip passive power compensation circuits described above.

[0023] To achieve the above objectives, the present invention also provides a chip, wherein the chip includes any of the data processing units described above.

[0024] To achieve the above objectives, the present invention also provides a computing board for use in a computing device, wherein the computing board includes any of the chips described above.

[0025] To achieve the above objectives, the present invention also provides a computing device, including a power board, a control board, a connection board, a heat sink, and a plurality of computing boards. The control board is connected to the computing boards through the connection board. The heat sink is disposed around the computing boards. The power board is used to provide power to the connection board, the control board, the heat sink, and the computing boards. The computing boards are any of the aforementioned computing boards.

[0026] The on-chip passive power compensation circuit of this invention can provide a relatively stable operating voltage to the voltage domain to be powered without the need for an auxiliary power supply. This not only reduces power consumption but also simplifies design, saves chip area, and lowers production costs.

[0027] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention. Attached Figure Description

[0028] Figure 1 A schematic diagram of an existing series power supply circuit;

[0029] Figure 2 A schematic diagram of an existing series power supply system within a chip;

[0030] Figure 3 This is a schematic diagram of the series power supply circuit structure of the present invention without the on-chip passive power compensation circuit;

[0031] Figure 4 This is a schematic diagram of an on-chip passive power compensation circuit according to an embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of an on-chip passive power compensation circuit according to another embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of an on-chip passive power compensation circuit according to another embodiment of the present invention;

[0034] Figure 7 This is a schematic diagram of an on-chip passive power compensation circuit according to another embodiment of the present invention;

[0035] Figure 8 This is a schematic diagram of the data processing unit of the present invention;

[0036] Figure 9 This is a schematic diagram of the chip of the present invention;

[0037] Figure 10 This is a schematic diagram of the computing board of the present invention;

[0038] Figure 11 This is a schematic diagram of the computing device of the present invention.

[0039] In the attached figures, the following labels are used:

[0040] 10: Series power supply circuit

[0041] 100: On-chip passive power compensation circuit

[0042] 101-1, 101-2, ..., 101-n: Voltage domain

[0043] 102-1, 102-2, ..., 102-n: Deep N-well

[0044] 103-1, 103-2, ..., 103-n: P-trap

[0045] 10⁴⁻¹, 10⁴⁻², ..., 10⁴⁻ⁿ: N-wells

[0046] 105, 105': Switching transistors

[0047] 106: Volume Resistance

[0048] VDD1, VDD2, ..., VDDn: Power supply terminals in the voltage domain

[0049] VSS1, VSS2, ..., VSSn: Ground terminals in the voltage domain

[0050] VPP1, VPP2, ..., VPPn: Power supply terminals of the deep N-well

[0051] VBB1, VBB2, ..., VBBn: Ground terminals of deep N-wells

[0052] VDD: System power; GND: System ground

[0053] S: Source extreme; D: Drain extreme

[0054] G: Gate terminal; B: Substrate terminal

[0055] 700 - Data Processing Unit; 701 - Control Circuit

[0056] 702 - Operational Circuit; 703 - Storage Circuit

[0057] 800: Chip; 801: Control Unit

[0058] 900: Computing board; 1000: Computing equipment

[0059] 1001: Connecting plate; 1002: Control plate

[0060] 1003: Heatsink 1004: Power Supply Board Detailed Implementation

[0061] The structural and working principles of the present invention will be described in detail below with reference to the accompanying drawings:

[0062] Certain terms are used in the specification and subsequent claims to refer to specific components. It will be understood by those skilled in the art that manufacturers may use different names to refer to the same component. This specification and subsequent claims do not distinguish components by differences in name, but rather by differences in function. Throughout the specification, the same reference numerals denote the same elements.

[0063] Throughout this specification and in the following claims, the terms "comprising" and "including" are open-ended and should be interpreted as "comprising but not limited to". Furthermore, the term "connection" here includes any direct and indirect electrical connection means. Indirect electrical connection means include connections made through other means.

[0064] Figure 3 This is a schematic diagram of the series power supply circuit structure of the present invention, excluding the on-chip passive power compensation circuit. For example... Figure 3 As shown, taking a P-type substrate as an example, the series power supply circuit 10 has n voltage domains 101-1, 101-2...101-n to be powered, where n is a positive integer greater than 1. Each voltage domain 101-1, 101-2...101-n is isolated from other voltage domains by a corresponding deep N-well 102-1, 102-2...102-n to avoid short circuits between different voltage domains. A certain number of P-wells 103-1, 103-2...103-n and N-wells 104-1, 104-2...104-n are formed within the deep N-wells 102-1, 102-2...102-n.

[0065] Each voltage domain 101-1, 101-2...101-n contains PMOS transistors and / or NMOS transistors. Resistors, capacitors, and other types of devices can also be formed if necessary. PMOS transistors are formed within N-wells 104-1, 104-2...104-n, and NMOS transistors are formed within P-wells 103-1, 103-2...103-n. PMOS and NMOS transistors are used to implement various functions of the chip.

[0066] Each voltage domain to be powered, 101-1, 101-2...101-n, is connected in series between the system power supply VDD and the system ground GND. The power supply terminal VDD1 of voltage domain 101-1 is connected to the system power supply VDD; the ground terminal VSS1 of voltage domain 101-1 is connected to the power supply terminal VDD2 of the next-level voltage domain 101-2; the ground terminal VSS2 of voltage domain 101-2 is connected to the power supply terminal VDD3 of the next-level voltage domain 101-3, and so on down to the next level. The ground terminal VSSn of voltage domain 101-n is connected to the system ground GND. This forms n voltage domains connected in series for power supply.

[0067] PMOS or NMOS transistors have four ports: S / D / G / B, referred to as the source, drain, gate, and substrate, respectively. Typically, the substrate and source terminals of PMOS transistors within voltage domains 101-1, 101-2, ..., 101-n are connected to the power supply terminals VDD1, VDD2, ..., VDDn for that voltage domain, while the substrate and source terminals of NMOS transistors are connected to the ground terminals VSS1, VSS2, ..., VSSn for that voltage domain. When the voltage between the gate and substrate exceeds a threshold voltage, a conductive path from the source to the drain is formed within the substrate, allowing charge carriers to flow within the substrate between the source and drain terminals, thus generating current.

[0068] When the n voltage domains connected in series are operating normally, the potentials of the power supply terminals VDD1, VDD2...VDDn and ground terminals VSS1, VSS2...VSSn of each voltage domain remain basically stable. However, when a large current flows through one of the n voltage domains 101-m (1≤m≤n), a significant voltage difference forms across it due to the resistance of the domain itself. This difference affects the voltages across other voltage domains that are not experiencing large current flows, causing a drift in the power supply voltage. This drift continues to occur with changes in current, and the drift is directly proportional to the current magnitude, potentially leading to chip malfunction.

[0069] To avoid the aforementioned issues, improvements are typically made by adding auxiliary power supplies, i.e., adding an auxiliary power supply to each voltage domain to power that voltage domain. This invention provides an on-chip passive power compensation circuit based on a substrate reference, which can reduce voltage drift across the voltage domain without adding an auxiliary power supply.

[0070] Example 1

[0071] Figure 4 This is a schematic diagram of an on-chip passive power compensation circuit according to an embodiment of the present invention. Figure 4As shown, taking a P-type substrate as an example, the on-chip passive power compensation circuit 100 of this invention forms n voltage domains 101-1, 101-2...101-n to be powered, where n is a positive integer greater than 1. Each voltage domain 101-1, 101-2...101-n is isolated from other voltage domains by a corresponding deep N-well 102-1, 102-2...102-n to avoid short circuits between different voltage domains. A certain number of P-wells 103-1, 103-2...103-n and N-wells 104-1, 104-2...104-n are formed within the deep N-wells 102-1, 102-2...102-n.

[0072] Each voltage domain 101-1, 101-2...101-n contains PMOS transistors and / or NMOS transistors. Resistors, capacitors, and other types of devices can also be formed if necessary. PMOS transistors are formed within N-wells 104-1, 104-2...104-n, and NMOS transistors are formed within P-wells 103-1, 103-2...103-n. PMOS and NMOS transistors are used to implement various functions of the chip.

[0073] Each voltage domain to be powered, 101-1, 101-2...101-n, is connected in series between the system power supply VDD and the system ground GND. The power supply terminal VDD1 of voltage domain 101-1 is connected to the system power supply VDD. The ground terminal VSS1 of voltage domain 101-1 is connected to the power supply terminal VDD2 of the next-level voltage domain 101-2. The ground terminal VSS2 of voltage domain 101-2 is connected to the power supply terminal VDD3 of the next-level voltage domain 101-3, and so on down to the next level. The ground terminal VSSn of voltage domain 101-n is connected to the system ground GND. This forms n voltage domains connected in series, with the power supply terminals of each voltage domain 101-1, 101-2...101-n being VDD1, VDD2...VDDn, and the ground terminals being VSS1, VSS2...VSSn, respectively.

[0074] The deep N-wells 102-1, 102-2...102-n are used to achieve isolation between different voltage domains. In addition to forming the aforementioned series power supply path, this invention also utilizes the bulk resistance 106 of the P-well and / or N-well to divide the system power supply VDD, generating a voltage divider across the deep N-wells 102-1, 102-2...102-n. Specifically, the power supply terminal VPP1 of deep N-well 102-1 is connected to the system power supply VDD, the ground terminal VBB1 of deep N-well 102-1 is connected to the power supply terminal VPP2 of the next-stage deep N-well 102-2, the ground terminal VBB2 of deep N-well 102-2 is connected to the power supply terminal VPP3 of the next-stage deep N-well 102-3, and so on in series with the next stage; the ground terminal VBBn of deep N-well 102-n is connected to the system ground GND. A deep N-well is formed between the system power supply VDD and ground GND, with the potentials at both ends being relatively stable. The power supply terminals of the deep N-wells 102-1, 102-2...102-n are VPP1, VPP2...VPPn, and the ground terminals are VBB1, VBB2...VBBn, respectively.

[0075] Ideally, the voltages of the power supply terminals VDD1, VDD2, ..., VDDn of voltage domains 101-1, 101-2, ..., 101-n are the same as the voltages of the power supply terminals VPP1, VPP2, ..., VPPn of deep N-wells 102-1, 102-2, ..., 102-n, respectively. Similarly, the voltages of the ground terminals VSS1, VSS2, ..., VSSn of voltage domains 101-1, 101-2, ..., 101-n are the same as the voltages of the ground terminals VBB1, VBB2, ..., VBBn of deep N-wells 102-1, 102-2, ..., 102-n, respectively.

[0076] In this embodiment, the source terminals of the PMOS transistors in each voltage domain 101-1, 101-2...101-n are connected to the power supply terminals VDD1, VDD2...VDDn of that voltage domain, and the substrate terminals of the PMOS transistors are connected to the power supply terminals VPP1, VPP2...VPPn of the deep N-wells 102-1, 102-2...102-n; the source terminals of the NMOS transistors in each voltage domain 101-1, 101-2...101-n are connected to the ground terminals VSS1, VSS2...VSSn of that voltage domain, and the substrate terminals of the NMOS transistors are connected to the ground terminals VBB1, VBB2...VBBn of the deep N-wells 102-1, 102-2...102-n.

[0077] In addition, the on-chip passive power compensation circuit of the present invention also includes a switching transistor 105, which is an NMOS transistor formed in voltage domains 101-2, 101-3...101-(n-1). Taking voltage domain 101-2 as an example, the drain terminal D of the switching transistor 105 in voltage domain 101-2 is connected to the power supply terminal VDD1 of the previous voltage domain 101-1, the source terminal S of the switching transistor 105 is connected to the power supply terminal VDD2 of the current voltage domain 101-2, the gate terminal G of the switching transistor 105 is connected to the power supply terminal VPP2 of the current deep N-well 102-2, and the substrate terminal B of the switching transistor 105 is connected to the ground terminal VBB2 of the current deep N-well 102-2.

[0078] The gate terminal G and substrate terminal B of the switching transistor 105 are connected to VPP2 and VBB2, respectively. Due to the influence of the gate capacitance and substrate bulk capacitance, no current flows between the gate and the substrate, thus keeping the potential of VPP2 stable. Ideally, the voltage VPP2 at the gate terminal G of the switching transistor 105 is greater than the voltage VBB2 at the substrate terminal B, thereby forming a conductive channel in the substrate. However, since the voltage VDD1 at the drain terminal D of the switching transistor is greater than the voltage VPP2 at the gate terminal G, the voltage VPP2 at the gate terminal G is the same as the voltage VDD2 at the source terminal S, i.e., VPP2 = VBB2. d > V g = V s That is V gs = 0, the conductive channel formed in the substrate is pinched off, and no current flows between the source terminal S and the drain terminal D.

[0079] When the power supply VDD2 in this voltage domain is insufficient, the voltage of VDD2 drops, that is, the voltage at the source terminal S of the switching transistor 105 drops. Since the voltage VPP2 at the gate terminal G remains unchanged, a V... gs The state is greater than 0. Because V ds > V gs When V gs = V th When the switching transistor 105 is turned on and operates in the saturation region, the current between the source terminal S and the drain terminal D of the switching transistor 105 is: I DS = [K*(W / L)*(V)] gs -V th ) 2 ] / 2. At this time, VDD1 at the drain terminal D provides sufficient charge to VDD2 at the source terminal S, and the potential of VDD2 will be clamped at (VPP2-V th ( ), and will not decrease further.

[0080] For the same reason, when the drain terminal D of the switching transistor 105 is connected to the ground terminal VSS1 of the previous voltage domain and the source terminal S is connected to the ground terminal VSS2 of the current voltage domain, the potential of VSS2 in the current voltage domain can be clamped at (VSS2 - V th Within the range of ).

[0081] Example 2

[0082] Figure 5 This is a schematic diagram of an on-chip passive power compensation circuit according to another embodiment of the present invention. Figure 5 As shown, the difference between this embodiment and Embodiment 1 lies in the type and connection method of the switching transistor 105'.

[0083] In this embodiment, the on-chip passive power compensation circuit 100 also includes a switching transistor 105', which is a PMOS transistor formed in voltage domains 101-2, 101-3...101-(n-1). Taking voltage domain 101-2 as an example, the drain terminal D of the switching transistor 105' in voltage domain 101-2 is connected to the ground terminal VSS3 of the next voltage domain 101-3, the source terminal S of the switching transistor 105' is connected to the ground terminal VSS2 of the current voltage domain 101-2, the gate terminal G of the switching transistor 105' is connected to the ground terminal VBB2 of the current deep N-well 102-2, and the substrate terminal B of the switching transistor 105' is connected to the power supply terminal VPP2 of the current deep N-well 102-2.

[0084] The gate terminal G and substrate terminal B of the switching transistor 105' are connected to VBB2 and VPP2, respectively. Due to the influence of the gate capacitance and substrate bulk capacitance, no current flows between the gate and the substrate, thus keeping the potentials of VBB2 and VPP2 stable. Ideally, the voltage VBB2 at the gate terminal G of the switching transistor 105' is less than the voltage VPP2 at the substrate terminal B, thereby forming a conductive channel in the substrate. However, since the voltage VSS3 at the drain terminal D of the switching transistor 105' is lower than the voltage VBB2 at the gate terminal G, the voltage VBB2 at the gate terminal G is the same as the voltage VSS2 at the source terminal S, i.e., V... d > V g = V s That is V gs = 0, the conductive channel formed in the substrate is pinched off, and no current flows between the source terminal S and the drain terminal D.

[0085] When an overcurrent forms in VSS2 within this voltage domain, the potential of VSS2 rises, meaning the voltage at the source terminal S of the switching transistor 105' increases. Since the voltage VBB2 at the gate terminal G remains constant, a V... gs The state is < 0. The threshold voltage of the switching transistor 105' is V.th Because of V ds > V gs When V gs = V th When the switching transistor 105' is turned on and operates in the saturation region, the current between the source terminal S and the drain terminal D of the switching transistor 105' is: I DS = [K*(W / L)*(V)] gs -V th ) 2 ] / 2. At this time, VSS3 at the drain terminal D provides sufficient charge discharge to VSS2 at the source terminal S, and the potential of VSS2 will be clamped at (VSS2 + V th Within the range, it will not rise further.

[0086] For the same reason, when the drain terminal D of the switching transistor 105' is connected to the power supply terminal VDD3 of the next voltage domain, and the source terminal S is connected to the power supply terminal VDD2 of the current voltage domain, the potential of the power supply terminal VDD2 of the current voltage domain can be clamped at (VDD2 + V th Within the range of ).

[0087] Example 3

[0088] Examples 1 and 2 only show the case where the switching transistors formed in the same voltage domain are of one type, namely, a PMOS transistor or an NMOS transistor. In different cases, both PMOS transistors and NMOS transistors can be formed simultaneously as switching transistors in each voltage domain.

[0089] Figure 6 This is a schematic diagram of an on-chip passive power compensation circuit according to another embodiment of the present invention. Figure 6 As shown, taking the m-th voltage domain 101-m of the on-chip passive power compensation circuit 100 as an example, a switching transistor 105 and a switching transistor 105' are formed in the voltage domain 101-m. Switching transistor 105 is an NMOS transistor, and its connection method is the same as that of switching transistor 105 in Embodiment 1; switching transistor 105' is a PMOS transistor, and its connection method is the same as that of switching transistor 105' in Embodiment 2.

[0090] Example 4

[0091] Example 3 illustrates a scenario where both a PMOS transistor and an NMOS transistor are simultaneously used as switching transistors within the same voltage domain. If only one set of switching transistors 105 and 105' is used, they can quickly compensate for large current changes in nearby circuits. However, when large current changes occur in circuits located further away, they cannot compensate in time, potentially causing the power supply voltage across the entire voltage domain to change with the operating current, thus leading to malfunction of the entire voltage domain circuit. In practical design and production, the number of switching transistors can be set to multiple.

[0092] Figure 7 This is a schematic diagram of an on-chip passive power compensation circuit according to another embodiment of the present invention. Figure 7 As shown, each voltage domain 101 of the on-chip passive power compensation circuit 100 contains multiple switching transistors 105 and 105'.

[0093] In each voltage domain 101, besides the area where necessary devices are formed, there is also a certain amount of spare area. In order to quickly provide power compensation to adjacent circuits and improve the power compensation capability, as many switching transistors 105 and 105' as possible can be formed in the spare area of ​​voltage domain 101. The specific number can be determined according to the size of the spare area in voltage domain 101. The multiple switching transistors 105 and 105' formed can be arranged uniformly or non-uniformly.

[0094] The present invention also provides a data processing unit. Figure 8 This is a schematic diagram of the data processing unit of the present invention. Figure 8 As shown, the data processing unit 700 includes an interconnected control circuit 701, a processing circuit 702, a storage circuit 703, and one or more on-chip passive power compensation circuits 100.

[0095] The present invention also provides a chip, Figure 9 This is a schematic diagram of the chip used in this invention. Figure 9 As shown, chip 800 includes one or more data processing units 700.

[0096] The present invention also provides a computing board, Figure 10 This is a schematic diagram of the computing board of the present invention. Figure 10 As shown, each computing board 900 includes one or more chips 800, which perform hash operations on the distributed work data.

[0097] The present invention also provides a computing device, Figure 11 This is a schematic diagram of the computing device of the present invention. Figure 11As shown, each computing device 1000 includes a connection board 1001, a control board 1002, a heat sink 1003, a power board 1004, and one or more computing boards 900. The control board 1002 is connected to the computing board 900 via the connection board 1001, and the heat sink 1003 is disposed around the computing board 900. The power board 1004 is used to provide power to the connection board 1001, the control board 1002, the heat sink 1003, and the computing board 900.

[0098] It should be noted that in the description of this invention, the terms "lateral", "longitudinal", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0099] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

[0100] In other words, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. An on-chip passive power compensation circuit, characterized in that, include: Two or more voltage domains to be powered are connected in series between the power source and the ground, and a second power terminal and a second ground terminal are formed at both ends of each voltage domain to be powered. Two or more isolation regions are provided, wherein the voltage domain to be supplied is formed within the isolation regions, and the isolation regions are used to isolate the voltage domain to be supplied. The isolation region is connected in series between the power source and the ground, and a first power terminal and a first ground terminal are formed at both ends of each isolation region; It also includes a power compensation unit connected between the voltage domain to be powered and the isolation region, the power compensation unit including a switching transistor; The switching transistor is an NMOS transistor and / or a PMOS transistor, and is formed in the voltage domain to be supplied; wherein: The drain terminal of the NMOS transistor in the voltage domain to be supplied in this stage is connected to the second power supply terminal of the voltage domain to be supplied in the previous stage, and the source terminal of the NMOS transistor is connected to the second power supply terminal of the voltage domain to be supplied in this stage; or the drain terminal of the NMOS transistor in the voltage domain to be supplied in this stage is connected to the second ground terminal of the voltage domain to be supplied in the previous stage, and the source terminal of the NMOS transistor is connected to the second ground terminal of the voltage domain to be supplied in this stage; and the gate terminal of the NMOS transistor is connected to the first power supply terminal of the isolation region in this stage, and the substrate terminal of the NMOS transistor is connected to the first ground terminal of the isolation region in this stage; And / or, The drain terminal of the PMOS transistor in the voltage domain to be supplied in this stage is connected to the second ground terminal of the voltage domain to be supplied in the next stage, and the source terminal of the PMOS transistor is connected to the second ground terminal of the voltage domain to be supplied in this stage; or the drain terminal of the PMOS transistor in the voltage domain to be supplied in this stage is connected to the second power supply terminal of the voltage domain to be supplied in the next stage, and the source terminal of the PMOS transistor is connected to the second power supply terminal of the voltage domain to be supplied in this stage; and the gate terminal of the PMOS transistor is connected to the first ground terminal of the isolation region of this stage, and the substrate terminal of the PMOS transistor is connected to the first power supply terminal of the isolation region of this stage. In this process, the first power supply terminal and the first ground terminal of the isolation region generate a reference voltage through a body resistor voltage divider. Based on the reference voltage, when the switching transistor is operating in saturation, the potential of the second power supply terminal and / or the second ground terminal of the voltage domain to be supplied in this stage is clamped to provide power compensation to the second power supply terminal and / or the second ground terminal.

2. The on-chip passive power compensation circuit as described in claim 1, characterized in that: The first power supply terminal and / or the first ground terminal are used to provide the reference voltage to the power compensation unit.

3. The on-chip passive power compensation circuit as described in claim 1, characterized in that: With the reference voltage as a reference, when the voltage variation range of the second power supply terminal and / or the second ground terminal exceeds the threshold of the power compensation unit, the power compensation unit operates in the saturation state.

4. The on-chip passive power compensation circuit as described in claim 1, characterized in that: The PMOS transistor and / or the NMOS transistor may be one or more.

5. The on-chip passive power compensation circuit as described in claim 4, characterized in that: One or more semiconductor devices are formed in the voltage domain to be powered, and the first power supply terminal and / or the first ground terminal provide a substrate bias to the semiconductor devices.

6. The on-chip passive power compensation circuit as described in claim 5, characterized in that: The semiconductor device includes a PMOS transistor and / or an NMOS transistor, wherein the first power supply terminal provides a substrate bias to the PMOS transistor, and the first ground terminal provides a substrate bias to the NMOS transistor.

7. A data processing unit, comprising interconnected control circuitry, processing circuitry, storage circuitry, and one or more on-chip passive power compensation circuits, characterized in that: The on-chip passive power compensation circuit is any one of the on-chip passive power compensation circuits described in claims 1-6.

8. A chip, characterized in that, It includes at least one data processing unit as described in claim 7.

9. A computing board for use in a computing device, characterized in that, Includes the chips described in multiple claims 8.

10. A computing device, comprising a power board, a control board, a connection board, a heat sink, and a plurality of computing boards, wherein the control board is connected to the computing boards via the connection board, the heat sink is disposed around the computing boards, and the power board is used to provide power to the connection board, the control board, the heat sink, and the computing boards, wherein... The computing board is the computing board described in claim 9.

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