Method for manufacturing a semiconductor device

Abstract

A method for manufacturing a semiconductor device includes: providing a first wafer, the first wafer including a base substrate and a component region, the base substrate having a first surface and a second surface facing each other, the component region being arranged on the first surface of the base substrate, wherein the first wafer includes a first semiconductor chip region and a second semiconductor chip region adjacent to each other, the first semiconductor chip region and the second semiconductor chip region each including a portion of the base substrate and a portion of the component region; forming a cutting pattern in the base substrate between the first semiconductor chip region and the second semiconductor chip region; grinding a portion of the base substrate to form a second wafer from the first wafer; forming a stress release layer on the ground second surface of the base substrate; and expanding the second wafer to separate the first semiconductor chip region and the second semiconductor chip region from each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0113223 filed on September 20, 2018 in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor package. Background Art

[0004] In response to higher functionality in electronic devices and expansion to mobile applications, semiconductor devices are strongly required to have high density and high integration. Therefore, large-capacity and high-density integrated circuit (IC) packages are being developed.

[0005] In a method of manufacturing a semiconductor device, after grinding the wafer, a support film (eg, a die attach film (DAF)) is bonded to the semiconductor wafer, and the wafer is cut into individual semiconductor elements by dicing.

[0006] A damaged film generated in the process of grinding a wafer may become a seed, thereby causing cracks in the wafer. This may react with stress in the expansion process for dicing, thereby causing damage to the IC pattern. Summary of the invention

[0007] Aspects of the present disclosure provide a method of manufacturing a semiconductor device using a stress relief layer that suppresses stress occurring during an expansion process to a minimum.

[0008] Aspects of the present disclosure also provide a method for manufacturing a semiconductor device capable of providing high bonding force between a stress relaxation layer and a support film through a plasma process.

[0009] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: providing a first wafer, the first wafer comprising a base substrate and an element region, the base substrate having a first surface and a second surface facing each other, the element region being arranged on the first surface of the base substrate, wherein the first wafer comprises a first semiconductor chip region and a second semiconductor chip region adjacent to each other, the first semiconductor chip region and the second semiconductor chip region each comprising a portion of the base substrate and a portion of the element region; forming a cutting pattern in the base substrate between the first semiconductor chip region and the second semiconductor chip region; after forming the cutting pattern, grinding a portion of the base substrate to form a second wafer from the first wafer; forming a stress release layer on the ground second surface of the base substrate; and expanding the second wafer to separate the first semiconductor chip region and the second semiconductor chip region from each other.

[0010] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: providing a first wafer, the first wafer comprising a base substrate and a component region, the base substrate having a first surface and a second surface facing each other, the component region being arranged on the first surface of the base substrate; grinding a portion of the base substrate to form a second wafer from the first wafer; forming a stress release layer on the ground second surface of the base substrate of the second wafer; post-treating the stress release layer using a plasma process; forming a support film on the post-treated stress release layer; and expanding the second wafer to slice the second wafer.

[0011] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: providing a base substrate in a first wafer, the base substrate having a first surface and a second surface facing each other, the first wafer having an element region on the first surface of the base substrate, wherein the first wafer comprises a first semiconductor chip region and a second semiconductor chip region adjacent to each other, the first semiconductor chip region and the second semiconductor chip region each comprising a portion of the base substrate and a portion of the element region; forming a first supporting film on the element region; forming a cutting pattern in the base substrate between the first semiconductor chip region and the second semiconductor chip region using a laser incident from the second surface of the base substrate; after forming the cutting pattern, grinding a portion of the base substrate to form a second wafer from the first wafer; forming a stress release layer on the ground second surface of the base substrate; post-treating the stress release layer using a plasma process; forming a second supporting film on the post-treated stress release layer; and expanding the second wafer to separate the first semiconductor chip region and the second semiconductor chip region from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0013] Figure 1 is an exemplary cross-sectional view for explaining cracks occurring after grinding a wafer;

[0014] Figure 2A is an exemplary cross-sectional view of a portion in which a crack is damaged to an IC pattern due to stress caused by extension;

[0015] Figure 2B is an exemplary view for explaining that stress caused by expansion is released by a stress release layer;

[0016] Figure 3 is a flowchart illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0017] Figure 4 is a perspective view for explaining a method of forming a cutting pattern on a wafer using a laser;

[0018] Figure 5A is an exemplary view showing a process of grinding a base substrate of a wafer;

[0019] Figure 5B Observed from the top Figure 5A A view of the grinding process;

[0020] Figure 6 is an exemplary view for explaining a process of depositing a stress relief layer on a base substrate of a wafer by plasma enhanced chemical vapor deposition (PECVD);

[0021] Figure 7 is an exemplary view showing separation of semiconductor chip regions by an expansion process;

[0022] Figure 8 It is shown Figure 3 A flow chart of a cross section of a wafer in process;

[0023] Fig. 9 is a flowchart illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0024] Fig.10 It shows that according to Fig. 9 A flow chart of a cross section of a wafer of the process;

[0025] Fig.11 is a flowchart illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0026] Fig.12 It shows that according to Fig.11 A flow chart of a cross section of a wafer of the process;

[0027] Fig.13 is a flowchart illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0028] Fig.14 is a view for explaining a method of coating a stress relaxation layer using plasma; and

[0029] Fig.15 It shows that according to Fig.13 Flowchart of a cross section of a wafer of the process.

[0030] because Figure 1-15 The drawings in the drawings are intended for illustrative purposes, and therefore the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for the purpose of clarity. DETAILED DESCRIPTION

[0031] Due to the demand for lighter, thinner, shorter and compact semiconductor products, thin wafers are constantly needed. Various processes have been produced to meet these needs. In the newly produced laser post-grinding (GAL) process, in order to divide the semiconductor chip area, a cutting pattern can be formed inside the wafer by laser. After the cutting pattern is formed on the wafer, the wafer can be ground. After the wafer is ground, the wafer can be expanded to divide the semiconductor chip area along the cutting pattern on the support film (e.g., die attachment film (DAF)) bonded to the wafer.

[0032] Figure 1 is an exemplary cross-sectional view for explaining cracks occurring after grinding a wafer.

[0033] refer to Figure 1 Due to the stress occurring when grinding the wafer 100, a damaged film may be generated on the wafer 100. Due to the stress applied to the wafer 100 during the grinding process, the damaged film may become a seed, resulting in a crack 122. The crack 122 may penetrate from the amorphous silicon 124 to the plastic silicon 126, from the amorphous silicon 124 to the elastic silicon 128, or from the amorphous silicon 124 to the crystalline silicon 121 on which an integrated circuit (IC) pattern is formed. The elastic silicon 128, the plastic silicon 126, and the amorphous silicon 124 are sequentially arranged on the crystalline silicon 121.

[0034] Figure 2A is an exemplary cross-sectional view in which a portion having a crack causes damage to an IC pattern due to stress caused by extension.

[0035] refer to Figure 2A After grinding, an expansion process may be used to cut the semiconductor chip region and the support film (e.g., DAF). Stress such as tensile stress due to the expansion process may be applied to the wafer 200. Microcracks in the damaged film on the wafer 200 may grow due to the applied stress at the portion where the crack 202 occurs, and the size may increase as the tensile stress is applied to the wafer 200 for a period of time.

[0036] The growing crack 202 may also affect the IC pattern portion of the wafer 200. In addition, the semiconductor chip region is not separated along the cutting pattern 204 formed to separate the semiconductor chip region, and the portion where the crack 202 occurs may be separated due to stress. For example, the semiconductor chip region may be separated due to the crack 202, rather than being separated by the cutting pattern 204. This may result in incorrect separation of the miniaturized semiconductor chip region.

[0037] Figure 2Bis an exemplary view for explaining that stress caused by expansion is released through a stress relief layer.

[0038] refer to Figure 2B , the stress release layer 206 may be deposited on the wafer 200. The stress release layer 206 may be deposited on the wafer by a chemical vapor deposition process (e.g., a plasma enhanced chemical vapor deposition (PECVD) process). However, the present disclosure is not limited thereto. For example, as a method for forming the stress release layer 206, in addition to PECVD, the deposition of the stress release layer 206 may also be performed by other methods capable of molecular bonding between silicon of the wafer 200 and the stress release layer 206.

[0039] and Figure 2A The stress relief layer 206 can reduce the transfer of stress such as tensile stress to the wafer 200 during the expansion process. The stress relief layer 206 includes a material capable of molecularly bonding with the wafer 200 (eg, silicon atoms of the wafer 200) and can be a polymer, but the present disclosure is not limited thereto.

[0040] The stress transmitted to the wafer 200 is reduced at the portion where the crack 202 occurs by the stress release layer 206, which can prevent the crack 202 from growing to the IC pattern. Therefore, when the wafer 200 is expanded and each semiconductor chip region is separated, the semiconductor chip region can be separated along the portion where the cutting pattern 204 is formed. For example, tensile stress can be applied to the cutting pattern 204 to cause an internal crack to develop along the cutting pattern 204 toward both surfaces of the wafer 200, and the wafer 200 is separated.

[0041] Hereinafter, a method of manufacturing a semiconductor device using a stress relaxation layer will be described.

[0042] Figure 3 is a flowchart illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure. Figure 4 is a perspective view for explaining a method of forming a cutting pattern on a wafer using a laser. Figure 5A 2 is an exemplary view illustrating a process of grinding a base substrate of a wafer. Figure 5B Observed from the top Figure 5A View of the grinding process. Figure 6 is an exemplary view for explaining a process of depositing a stress relaxation layer on a base substrate of a wafer by PECVD. Figure 7 is an exemplary view showing separation of semiconductor chip regions through an expansion process.

[0043] refer to Figure 3, IC patterning is performed on the first surface of the wafer (S200). The IC pattern formed by the IC patterning (S200) may be a front end of line (FEOL) process, and may include but is not limited to individual components, such as transistors, capacitors, and resistors of semiconductor components.

[0044] Film coating ( S212 ) is performed on the wafer on which IC patterning ( S200 ) is performed.

[0045] Before performing the grinding process to be described below, film coating (S212) may be performed to protect the IC pattern. The adhesive film adhered to the wafer when the adhesive film is laminated to the wafer before the cutting process may have excellent adhesion without bubbles. In addition, due to the process water used in the cutting process and the water and air used for cleaning, peeling or water immersion should not occur between the adhesive film and the back of the wafer or the support film. In addition, in the process of picking up the separated chips in the cutting process, the separated chips should be easily picked up.

[0046] In the case of products requiring high processing speed and high storage density, in the method for manufacturing semiconductor devices, the bonding strength of the film should be high. The film coating layer may include an adhesive composition. The film should have excellent adhesion and adhesion to the wafer when laminated. The film may have, but is not limited to, a plurality of layer structures, such as the first adhesive composition layer and the second adhesive composition layer, a substrate layer and an adhesive composition layer, an adhesive composition layer and a substrate layer, or a substrate layer, an adhesive composition layer and an adhesion layer (sticking layer). In addition to the above-mentioned two-layer and three-layer structures for film, four-layer and more multi-layer structures may also be used. For example, in an exemplary embodiment of the present disclosure, four-layer laminated films may include a first substrate layer, a first adhesive composition layer, a second adhesive composition layer, and a second substrate layer.

[0047] The adhesive composition may include, but is not limited to, a solvent such as a component generally used in an adhesive composition for semiconductor processes (eg, acetone, methyl ethyl ketone, n-butyl acetate, heptane, toluene, ethyl acetate, etc.).

[0048] Materials generally usable as a base film of an adhesive film for semiconductor manufacturing, such as polyethylene terephthalate, a polyolefin-based material, or a polyvinyl chloride-based material, may be used for the base layer, but the present disclosure is not limited thereto.

[0049] As the adhesive layer, an adhesive material generally used for manufacturing an adhesive film for a semiconductor, such as an acrylic material including a photoreactive oligomer, may be used, but the present disclosure is not limited thereto.

[0050] A cutting pattern for separating the semiconductor chip regions subjected to the film coating ( S212 ) is formed ( S220 ).

[0051] As a method for separating semiconductor chip areas, a mechanical cutting method can be used. A circular blade made of a high hardness material such as diamond can be rotated at high speed to cut a semiconductor wafer. As such a mechanical cutting method, a method is used in which an adhesive dicing tape is used to fix the wafer and then the wafer is cut along the scribe line with a blade. Therefore, the mechanical cutting method cannot be performed in a batch process of cutting a plurality of wafers at the same time. In addition, in the mechanical cutting method, a plurality of cutting processes need to be partially performed. Therefore, the mechanical cutting method requires a lot of time. In addition, in the cutting process using the blade, problems caused by mechanical damage and frictional heat generated in the semiconductor wafer may occur. For example, the blade often causes defects on the front and back of the wafer. The generation of debris is also one of the main problems of using the mechanical cutting method. In addition, there is a disadvantage of high process cost due to replacement of the blade with a limited life.

[0052] In order to maintain strength and fix the blade to the device, the blade may have a specific thickness or more. Therefore, it is difficult to perform a fine cutting process by the mechanical cutting method. In addition, due to the interval between the cutting parts for protecting the components from mechanical and thermal damage generated around the cutting parts, it is difficult to apply the mechanical cutting method to a small packaging process of a size of tens of micrometers (μm) or less.

[0053] In recent years, with the development of semiconductor element technology, the semiconductor chip area has been miniaturized. In addition to the traditional memory device structure, various fields such as flexible components and components using carbon-based materials have also emerged. However, it is difficult to apply the mechanical cutting method to the miniaturized semiconductor chip area and various fields. Therefore, an invisible cutting method using a laser to form a cutting pattern can be used as a new dicing method that can perform fine processes while maintaining process reliability, improving process yield and improving economy.

[0054] Laser-based cutting methods can be roughly divided into two methods. The first method is a method of cutting a sample by removing a portion of the sample by phase change (such as liquefaction, evaporation or plasma formation) using a laser with a wavelength corresponding to the absorption band of the sample to be cut. Therefore, the laser beam can be absorbed by the sample. In addition, the laser beam can be focused on the surface of the wafer. In the first method, the amount of sample that can be removed using one laser irradiation is limited. Therefore, cutting can be performed in a manner that removes the sample material in the depth direction by multiple scans. Therefore, wafer processing may require a lot of time. In addition, a wide heat-affected zone may be formed in the peripheral area of ​​wafer processing. In addition, during the laser process, molten particles (such as silicon dust or other types of semiconductor dust) from the removed sample may be scattered on the surface of the wafer. The first method has limitations, for example, it changes the physical properties of the wafer, leaves residual stress in the wafer, weakens the strength of the sample, or reduces the uniformity of the sample.

[0055] The second approach is to indirectly support cutting by generating cutting patterns on the wafer instead of physically removing sample material.

[0056] refer to Figure 4 , irradiating the focusing lens 310 with the laser 305. The portion of the wafer 345 to be cut can be precisely irradiated with the laser 305 through the focusing lens 310, thereby forming a cutting pattern 380. The laser 305 is not limited to nano(10 -9 ) second pulse laser or pico(10 -12 ) second pulse laser.

[0057] It takes at least several picoseconds for the energy of the laser to be converted into heat energy in the wafer 345. The pulses of the nanosecond pulse laser or the picosecond pulse laser can be converted into heat energy in the wafer 345 after taking several picoseconds or longer.

[0058] The cutting patterns 380 may be formed along the moving line of the laser 305. The first semiconductor chip region 350 and the second semiconductor chip region 355 may be distinguished by the cutting patterns 380. The first semiconductor chip region 350 and the second semiconductor chip region 355 may include a base substrate 320 and an element region 340 (the element region 340 may include an IC pattern 325 and a film 330) on which the cutting patterns 380 are formed. For example, the first semiconductor chip region 350 and the second semiconductor chip region 355 may be adjacent to each other and may each include a portion of the base substrate 320 and a portion of the element region 340. The cutting patterns 380 may be formed in the base substrate 320 at an inner point between the first semiconductor chip region 350 and the second semiconductor chip region 355.

[0059] The cutting pattern 380 may be formed in the base substrate 320 inside the wafer 345 by the laser 305. The laser 305 may be incident on the wafer 345 from the base substrate 320 side (eg, the back side of the wafer 345), such as Figure 4 As shown. For example, the laser 305 can irradiate an internal point in the base substrate 320 to form the cutting pattern 380, and therefore, the position of the cutting pattern 380 can be determined by the focus depth of the laser 305. Therefore, dust generated when physically cutting the surface of the wafer 345 can be suppressed. In addition, by forming the cutting pattern 380 in the base substrate 320 via the laser 305, it is not necessary to clean the wafer 345.

[0060] Reference again Figure 3 , grinding (S230) a portion of the base substrate (S220) of the wafer on which the cutting pattern is formed. The grinding (S230) may be performed to control the thickness and flatness of the wafer.

[0061] Grinding (S230) is an additional process to meet the high flatness required as semiconductor devices become highly integrated. In addition, grinding (S230) can be used to thin the wafer 345 to obtain the desired minimum wafer thickness. The flatness of the wafer 345 can be defined by the total thickness variation (TTV) representing the difference between the maximum and minimum values ​​of the thickness of the wafer 345 and the position back ideal range (SBIR), and the SBIR is the local thickness variation (LTV) representing the difference between local thicknesses. As the line width of semiconductor devices is miniaturized, it is difficult to meet the requirements of TTV and SBIR using only traditional grinding and polishing processes. Therefore, since it is difficult to form a high-quality wafer, a grinding (S230) process that can meet the flatness of the wafer 345 is additionally performed.

[0062] refer to Figure 5A The grinding apparatus used in step S230 includes a chuck table 335 to which the wafer 345 is adsorbed, a grinding wheel 412 to which grinding teeth 415 are attached, and a grinding shaft 405 for rotating the grinding wheel 412 .

[0063] When the wafer 345 is loaded on the chuck stage 335, the chuck stage 335 can adsorb the loaded wafer 345 by vacuum. In addition to vacuum, as long as the chuck stage 335 provides the required uniformity and does not cause deformation or damage to the loaded wafer 345, the chuck stage 335 can also adsorb the loaded wafer 345 by electrostatic force, mechanical force or magnetic force. The chuck stage 335 can rotate the adsorbed wafer 345 at a constant speed. In addition, the grinding teeth 415 can be lowered onto the top of the chuck stage 335 while rotating. The grinding teeth 415 can be attached to the grinding wheel 412 and can be spaced apart from each other at a predetermined interval. The grinding teeth 415 can contact the wafer 345 and start the grinding (S230) of the base substrate 320 of the wafer 345.

[0064] The material of the grinding teeth 415 may be diamond, but the present disclosure is not limited thereto. The grinding teeth 415 may be bonded to the grinding wheel 412 at regular intervals with an adhesive. The grinding teeth 415 may be formed to protrude from the grinding wheel 412. The grinding shaft 405 may rotate at high speed. Therefore, the grinding teeth 415 may rotate on the surface of the base substrate 320 of the wafer 345. Finally, the grinding teeth 415 may grind the base substrate 320 of the wafer 345 on the chuck table 335.

[0065] refer to Figures 4 to 5B , the grinding device used in step S230 can be seen from the top. The grinding wheel 412 can be lowered to the wafer 345 located on the chuck table 335 rotating at a high speed in the clockwise direction while rotating in the clockwise direction. Figure 5B As shown, the wafer 345 can be fixed on the chuck table 335 so that its center substantially corresponds to the rotation center of the chuck table 335. In addition, the grinding wheel 412 can be positioned so that the rotation center of the wafer 345 touches the edge area formed by the grinding teeth 415 of the grinding wheel 412. Therefore, the entire surface of the wafer 345 can be ground. Therefore, the grinding teeth 415 of the grinding wheel 412 can grind the base substrate 320 of the wafer 345 to a specified thickness. The rotation direction of the wafer 345 and the grinding wheel 412 on the chuck table 335 is not limited thereto.

[0066] Therefore, in step S230, cracks may be left on the back side of wafer 345.For typical mechanical treatment, such as the grinding process described here, it is expected that other surface damage or subsurface damage may occur.Due to the difference in thermal expansion coefficient between epoxy molding compound (EMC) or printed circuit board (PCB) and semiconductor chip area (for example, first semiconductor chip area 350 and second semiconductor chip area 355), cracks may become the key reason for fracture.In addition, wafer 345 tolerates compressive stress, but may be susceptible to tensile stress.If tensile stress caused by expansion occurs on the back side of wafer 345 with cracks due to step S230, the fracture strength of wafer 345 can be significantly reduced.For example, incorrect separation may occur in miniaturized semiconductor chip area (for example, first semiconductor chip area 350 and second semiconductor chip area 355).

[0067] The cracks occurring in the wafer 345 may be formed in a spiral pattern from the center of the wafer 345. At this time, when expansion is performed to cut the wafer 345 into individual semiconductor chip regions (e.g., the first semiconductor chip region 350 and the second semiconductor chip region 355), the degree of stress concentration varies greatly depending on the direction of the cracks existing in the wafer 345.

[0068] In order to reduce the influence of the cracks generated through step S230 on the wafer 345, a process of forming a stress relaxation layer (S240) is required, which will be described later.

[0069] Reference again Figure 3 After step S230, a stress release layer may be formed on the wafer (S240). The stress release layer may be deposited on the wafer 345 using a PECVD process, but the present disclosure is not limited thereto. For example, any deposition process may be used as long as the stress release layer 360 may be deposited on the wafer 345 by molecular bonding.

[0070] refer to Figure 6 , the equipment for performing step S240 includes a plasma chamber 530, a gas injection port 540, and a gas exhaust port 550. The gas to be deposited into the stress release layer 360 can be injected into the plasma chamber 530 through the gas injection port 540. A high voltage can be applied to the plasma chamber 530 to change the gas to form the stress release layer 360 into a plasma state. The gases ionized into the plasma state can chemically react with each other and then can form a molecular bond with the silicon of the base substrate 320. The gas ionized into the plasma state can form a stable and continuous network structure on one side of the base substrate 320 of the wafer 345. In addition, the stable and continuous network structure can be uniformly accumulated on one side of the base substrate 320 of the wafer 345 to form the stress release layer 360. The remaining ions can be discharged through the gas exhaust port 550.

[0071] In PECVD, the energy required to dissociate the source gas can be obtained from voltage rather than thermal energy. Therefore, vapor deposition can be performed at low temperature and low cost in a wide area. By vapor deposition at low temperature, the disadvantage of melting the aluminum wire or glass substrate on the wafer 345 during high temperature processes can be compensated. Therefore, it can be used in display devices and solar cell manufacturing processes. In addition, compared with other processes, the vapor deposition rate of PECVD is relatively high.

[0072] The bonds between the silicon of the wafer 345 are broken due to the grinding (S230), and dangling bonds may be formed. When the vapor deposition temperature of the stress release layer 360 reaches 400° C. or higher, the hydrogen atoms may react with each other and form H 2 Therefore, in order to allow the stress release layer 360 molecules to be bonded to the dangling bonds, a low vapor deposition temperature is required. The stress release layer 360 can be molecularly bonded to the dangling bonds of the wafer 345 through step S240 (for example, using a PECVD process) that can be vapor deposited at a low temperature. Therefore, through the molecular bonding between the stress release layer 360 and the dangling bonds of the wafer 345, a strong bonding force can be obtained.

[0073] Reference again Figure 3, from the wafer on which the stress release layer is formed (S240), the semiconductor chip region of the wafer may be separated through an expansion process (S250).

[0074] refer to Figure 7 , by using a tensile force to expand the wafer 345 divided based on the cutting pattern 380, the wafer 345 can be expanded by applying a uniform force, thereby accurately separating the semiconductor chip regions on the wafer 345.

[0075] Figure 8 It is shown in Figure 3 Flowchart of a cross section of a wafer during the process.

[0076] refer to Figure 3 and Figure 8 In step S200 , IC patterning is performed on the first wafer 700 to form IC patterns 725 before being ground.

[0077] In step S212, a film 730 may be formed on the IC pattern 725 of the first wafer 700. The IC pattern 725 and the film 730 may be included in the element region 745. The film 730 may protect the IC pattern 725 when grinding the base substrate 720 of the first wafer 700. For example, the film 730 should have excellent adhesion and adhesion to the first wafer 700.

[0078] In step S220, a cutting pattern 780 may be formed in the base substrate 720 of the first wafer 700. The cutting pattern 780 may be formed by Figure 4 The laser formation described in , but the present disclosure is not limited thereto.

[0079] In an exemplary embodiment of the present disclosure, the cutting pattern 780 may be formed by an etching process rather than by the above-mentioned laser. For example, a groove is formed as the cutting pattern 780, and a liquid is applied to the surface of the wafer on which the groove is formed, and the liquid may be injected into the groove. After the liquid is injected into the groove, the wafer may be cooled. The volume of the liquid injected into the groove expands due to cooling, and the wafer may be separated.

[0080] The method may also include a surface treatment step for enhancing wettability inside the groove when applying the liquid, and the surface treatment step may be performed by a plasma surface treatment process. An anisotropic etching process may be used to form the groove. The liquid coating may be performed by a spray coating method or a spin coating method, and the liquid may be water, but the present disclosure is not limited thereto.

[0081] By using the expansion force generated when cooling the liquid to separate the semiconductor chip area, a fine cutting process can be performed while maintaining process reliability. In addition, since the entire semiconductor wafer can be cut at the same time instead of a partial cut, and the dicing process can be composed of batch processing, the process yield of the dicing process can be improved.

[0082] In step S230 , a portion of the base substrate 720 of the first wafer 700 is ground to form a second wafer 710 .

[0083] Reference again Figure 5A , a portion of the base substrate 720 of the first wafer 700 may be ground while rotating the grinding wheel 412 to which the grinding teeth 415 are attached. Figure 1 In addition to the crack 122 described in FIG. 1 , since high heat due to the rotation occurs on the grinding wheel 412 and the first wafer 700 and accumulates, problems such as burning of the first wafer 700 may occur.

[0084] Grinding debris generated during grinding may adhere to fine pores present on the processing surface of the grinding teeth 415. A clogging phenomenon may occur due to the debris, which reduces the polishing force of the grinding teeth 415. Therefore, the polishing time for polishing the thickness of the first wafer 700 to the target thickness increases. This reduces the production yield of the wafer. In addition, this deteriorates the flatness and nano-quality of the wafer.

[0085] In step S240 , a stress release layer 790 may be formed on the base substrate 720 of the second wafer 710 after grinding. The stress applied to the damaged second wafer 710 may be relieved via the stress release layer 790 .

[0086] For the second wafer 710 having a thickness of about 10 μm or more and about 60 μm or less according to the size of the miniaturized semiconductor chip, damage to the second wafer 710 due to stress caused by the expansion can be prevented by the stress relief layer 790 having a thickness of about 10 nm or more and about 500 nm or less. In an excessively thick stress relief layer 790, vacant spaces between molecules increase, and bonding strength may be further weakened.

[0087] In step S250, dicing may be performed to separate semiconductor chip regions along the cutting pattern 780 by an expansion process. In this process, cracks may be formed in the second wafer 710 formed by grinding (S230), such as Figure 2A However, the stress release layer 790 can reduce the influence of the stress due to the expansion. Therefore, accurate scribing can be performed along the cutting pattern 780 to separate the miniaturized semiconductor chip area.

[0088] In an exemplary embodiment of the present disclosure, the cutting pattern 780 formed by the laser may be a hair-like crack in the base substrate 720. During the expansion step S250, when the dicing tape or film below is stretched, the hair-like crack of the cutting pattern 780 may enable the semiconductor chip regions to be cleaved evenly, thereby separating the semiconductor chip regions from each other. The dicing film or tape is connected to the second wafer 710 and is expandable so that the separated semiconductor chip regions can be picked up one by one.

[0089] Fig. 9 is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0090] refer to Fig. 9 , IC patterning is performed on the first surface of the wafer (S300).

[0091] After step S300, film coating is performed on the wafer (S312). Figure 3 The process is the same as step S212 of , and thus a description thereof will not be provided.

[0092] After step S312, a cutting pattern for separating the semiconductor chip regions is formed (S320). Figure 3 The process is the same as step S220, so a description thereof will not be provided.

[0093] After step S320, coarse grinding (S330) and fine grinding (S340) are performed.

[0094] refer to Figure 5A , the base substrate 320 of the semiconductor wafer 345 can be appreciably ground using the grinding wheel 412 (S330). Thereafter, a fine grinding process (S340) can be performed to grind fine scratches. For example, through the fine grinding of step S340, the coarse scratches on the semiconductor wafer 345 can be reduced to finer scratches. Figure 3 Compared with the single grinding process in step S230, a more precise thickness can be ground through the double grinding process.

[0095] After step S340, a stress release layer is formed (S350). Figure 3 The process is the same as step S240 of FIG. 1 , and thus a description thereof will not be provided.

[0096] After step S350, an expansion process (S360) is performed. Figure 3 The process is the same as step S250 of , and thus a description thereof will not be provided.

[0097] Fig.10 It shows that according to Fig. 9 Flowchart of a cross section of a wafer of the process.

[0098] refer to Fig. 9 and Fig.10 ,because Fig.10 Steps S300 to S320 and steps S350 to S360 are the same as Figure 8 Steps S200 to S250 are the same and thus no description will be provided.

[0099] The second wafer 910 may be manufactured by performing rough grinding (S330) and fine grinding (S340) on the first wafer 900. The first wafer 900 may include an element region 945 (which may include an IC pattern 925 and a film 930) and a cutting pattern 980. Figure 5A The grinding wheel 412 performs considerable grinding on the base substrate 920 of the first wafer 900 (S330). Figure 3 Compared with the one-time grinding process of step S230, the fine grinding process (S340) of grinding fine scratches can grind to a more precise thickness. The second wafer 910 may include a stress release layer 935. Therefore, the stress release layer 935 can reduce the influence of stress due to expansion, and accurate scribing can be performed along the cutting pattern 980 to separate the miniaturized semiconductor chip area.

[0100] Fig.11 is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0101] refer to Fig.11 ,because Fig.11 Steps S400 to S440 and steps S460 to S470 are the same as Fig. 9 Steps S300 to S360 are the same, and thus description thereof will not be provided.

[0102] After step S440, the wafer is polished (S450).

[0103] Due to the high density and miniaturization of semiconductor elements and multi-layer wiring structures, this step can be added. In order to flatten the wafer, various flattening methods have been developed, such as spin-on glass (SOG), ETCHBACK (etch-back) and REFLOW (reflow). The developed method is applied to the process of flattening the wafer. In the flattening process of the wafer, there are mechanical polishing methods and chemical polishing methods. In the mechanical polishing method, a layer affected by the operation is formed, which becomes a defect on the semiconductor chip. In the chemical polishing method, although a layer affected by the operation is not produced, a flat shape (i.e., shape accuracy) may not be obtained. Therefore, it is necessary to polish the flattening process of the wafer by combining the mechanical polishing method and the chemical polishing method. Therefore, a chemical mechanical polishing (CMP) technology has been developed.

[0104] The CMP process can rotate the polishing table with the polishing pad attached. The polishing head performs rotational motion and oscillating motion at the same time, and pressurization can be performed at a constant pressure. Therefore, during the CMP process, both the polishing table and the polishing head rotate, and the polishing head keeps oscillating. The wafer can be mounted on the polishing head part by surface tension or vacuum. The wafer surface and the polishing pad can contact each other by the dead weight of the polishing head and the pressure applied. The slurry as a working fluid can flow in the tiny gap between the contact surfaces. The CMP slurry generally includes nano-scale abrasive particles dispersed in an acidic or alkaline solution. In addition, a mechanical removal action can be performed by the abrasive particles in the slurry and the surface protrusions of the pad. In addition, a chemical removal action can be performed by the chemical components in the slurry. When the polishing process is performed by CMP, irregular wear may occur on the polishing pad. Therefore, the refurbishment of the next polishing pad can be performed during or after polishing. The polishing process of step S450 is not limited to CMP.

[0105] Fig.12 It shows that according to Fig.11 Flowchart of a cross section of a wafer of the process.

[0106] refer to Fig.11 and Fig.12 ,because Fig.12 Steps S400 to S440 and steps S460 to S470 are the same as Fig.10 Steps S300 to S360 are the same, and thus a description thereof will not be provided.

[0107] The first wafer 1000 may be made into the second wafer 1010 by rough grinding (S430). The first wafer 1000 may include an element area 1045 (which may include an IC pattern 1025 and a film 1030) and a cutting pattern 1080. After fine grinding (S440), a portion of the base substrate 1020 of the second wafer 1010 is polished (S450). Slurry may be supplied between one side of the second wafer 1010 and the polishing pad. Polishing may be performed by relatively rotating the second wafer 1010 in contact with the polishing pad. The polishing process of step S450 is a CMP process, but the present disclosure is not limited thereto. The second wafer 1010 may include a stress release layer 1035. Therefore, the stress release layer 1035 may reduce the influence of stress due to expansion, and accurate dicing may be performed along the cutting pattern 1080 to separate the miniaturized semiconductor chip area.

[0108] Fig.13 is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure. Fig.14 is a view for explaining a method of coating a stress relaxation layer using plasma.

[0109] refer to Fig.13 , since steps S500 to S540 and step S570 are Figure 3 Steps S200 to S240 and S250 are the same, so descriptions thereof will not be provided.

[0110] After step S540 , the stress release layer is plasma coated ( S550 ).

[0111] refer to Fig.14 , the plasma nozzle 1110 may apply a plasma beam to the stress release layer 1160 formed on one side of the base substrate 1120 of the second wafer 1145 while moving. The second wafer 1145 may include an element region 1140 (which may include an IC pattern 1125 and a film 1130) and a base substrate 1120. The base substrate 1120 may include a cutting pattern 1180. Plasma coating includes, but is not limited to, atmospheric pressure plasma.

[0112] The coating using plasma can use an apparatus having a relatively simple plasma nozzle 1110. Plasma is generated by discharge, and thus the wettability of the surface of the stress release layer 1160 can be chemically and physically enhanced. In addition, the contact angle of the stress release layer 1160 can be reduced. Therefore, the surface energy of the stress release layer 1160 increases, which can lead to an increase in adhesive strength. This can facilitate bonding with a support film to be described later.

[0113] In the case of an atmospheric pressure type plasma that is simpler than a vacuum type, pretreatment can be performed even when the plasma nozzle 1110 is used. For example, a reaction chamber is not required to maintain a desired pressure, such as a pressure higher than atmospheric pressure or a pressure lower than atmospheric pressure. In addition, since the discharge using high voltage is performed under an atmospheric pressure state, the initial facility cost can be reduced. In addition, continuous pretreatment can be performed. Therefore, a plasma pretreatment method focusing on high value-added industries such as the current IT and electronics industries can be applied to polymer elements such as the stress release layer 1160.

[0114] Reference again Fig.13 After step S550, a support film is formed on the plasma-coated stress release layer to allow the chips to contact each other (S560). The support film can be easily bonded to the stress release layer whose bonding strength is increased due to plasma coating (S550). The support film can also be bonded to the component area.

[0115] The adhesive between chips that has been applied to existing general packages is a liquid adhesive in the form of epoxy resin / paste. When bonding individual chips to a substrate or lead frame, the adhesive can use an adhesive dispensing method. The dispensing process added separately for the chip bonding process may require considerable process costs. In addition to the cost, the adhesive dispensing method may have other reliability issues. For example, due to the lack of precision and physical limitations of the dispensing method, it is difficult to control the amount and thickness of the adhesive applied. In addition, even after bonding between chips, it is difficult to maintain the uniformity of the adhesive coating.

[0116] The lamination technology of chips is one of the main technologies that affect the utility and performance of semiconductor packages. If the interfacial bonding strength between the stacked chips is weak, the dimensional stability of the package will be reduced. In addition, the package may be easily deformed by external moisture or heat and other stresses. Therefore, the wire as the electrical connection part may be damaged. Or, the front of the chip on which the circuit is mounted may be damaged, thereby significantly reducing the reliability of the package. Therefore, it is necessary to replace the liquid coating paste traditionally used as a support film. DAF can be used for the support film, as an interface adhesive, which can accurately bond the laminated chip interface according to these needs. However, the present disclosure is not limited to this. DAF can be an epoxy adhesive or any other suitable adhesive, and is based on a film, rather than the above-mentioned liquid coating paste. DAF is attached to the wafer by a lamination process rather than a drop coating process. Because there is no need to transform the liquid adhesive material from a drop shape into a thin two-dimensional film, the process window for films such as DAF is much wider than the process window for liquid paste materials.

[0117] In the chip bonding process performed by DAF designed to have excellent adhesion, the adhesive can be bonded to the back side of the wafer during the wafer processing step. Thereafter, the wafer dicing process immediately leads to the chip bonding process, and the adhesive can be directly bonded to the chip and substrate or lead frame.

[0118] Since the bonding process is performed starting from the wafer dicing step, a separate bonding process (such as a paste dispensing process) is not required. In addition, the uniform thickness and position of the DAF can be ensured by the film shape of the solid shape. Therefore, strict process consistency can be achieved by DAF. In addition, the productivity and yield of the package can be improved by DAF.

[0119] Fig.15 It shows that according to Fig.13 Flowchart of a cross section of a wafer of the process.

[0120] refer to Fig.13 and Fig.15 , since steps S500 to S540 and step S570 are Figure 8Steps S200 to S250 are the same as those of FIG. 1 , and thus a description thereof will not be provided.

[0121] The second wafer 1210 may be formed by grinding (S530) the first wafer 1200. The first wafer 1200 may include an element region 1245 (which may include an IC pattern 1225 and a film 1230) and a cutting pattern 1280. After step S540, a stress release layer 1290 formed on one side of the base wafer 1220 of the second wafer 1210 is coated with plasma (S550). The second wafer 1210 may include the stress release layer 1290.

[0122] After step S550, a support film 1260 for bonding a chip is formed on the coated stress release layer 1290. The support film 1260 includes but is not limited to DAF. The support film 1260 can be easily bonded to the stress release layer 1290 by plasma coating (S550). Therefore, the stress release layer 1290 can reduce the influence of stress due to expansion, and accurate scribing can be performed along the cutting pattern 1280 to separate the miniaturized semiconductor chip area.

[0123] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the preferred exemplary embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed preferred exemplary embodiments of the present disclosure are used in a general and descriptive sense only, and not for the purpose of limitation.

[0124] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: Providing a first wafer, the first wafer comprising a base substrate and a component region, the base substrate having a first surface and a second surface facing each other, the component region being arranged on the first surface of the base substrate, wherein the first wafer comprises a first semiconductor chip region and a second semiconductor chip region adjacent to each other, the first semiconductor chip region and the second semiconductor chip region each comprising a portion of the base substrate and a portion of the component region; forming a cutting pattern in the base substrate between the first semiconductor chip region and the second semiconductor chip region; After forming the cutting pattern, grinding a portion of the base substrate to form a second wafer from the first wafer; forming a stress release layer on the second surface of the ground base substrate so that the stress release layer is molecularly bonded to silicon atoms of the base substrate, wherein after forming the stress release layer on the second surface of the ground base substrate, post-treating the stress release layer using a plasma coating process that modifies the surface properties of the stress release layer; forming a support film on the post-treated stress release layer; and expanding the second wafer to separate the first semiconductor chip region and the second semiconductor chip region from each other, The forming of the stress release layer includes: applying voltage to change the gas used to form the stress release layer into a plasma state, so that the gases ionized into the plasma state chemically react with each other and form molecular bonds with the silicon atoms of the base substrate.

2. The method according to claim 1, wherein: The thickness of the stress relaxation layer is 500 nm or less relative to the thickness of the second wafer being 60 μm or less.

3. The method according to claim 1, wherein: Grinding a portion of the base substrate includes rough grinding the portion of the base substrate and then fine grinding the portion of the base substrate.

4. The method according to claim 3, further comprising: After fine grinding the portion of the base substrate, polishing the portion of the base substrate is performed.

5. The method according to claim 1, wherein: The stress relief layer includes a polymer material.

6. The method according to claim 1, wherein: The cutting pattern is formed in the base substrate using a laser.

7. A method for manufacturing a semiconductor device, the method comprising: Providing a first wafer, the first wafer comprising a base substrate and a component region, the base substrate having a first surface and a second surface facing each other, the component region being arranged on the first surface of the base substrate; grinding a portion of the base substrate to form a second wafer from the first wafer; forming a stress release layer on the second surface of the ground base substrate of the second wafer, so that the stress release layer is molecularly bonded with silicon atoms of the base substrate; After forming the stress relief layer on the second surface of the ground base substrate, post-treating the stress relief layer using a plasma coating process that modifies the surface properties of the stress relief layer; forming a support film on the post-treated stress release layer; as well as expanding the second wafer to perform dicing on the second wafer, The forming of the stress release layer includes: applying voltage to change the gas used to form the stress release layer into a plasma state, so that the gases ionized into the plasma state chemically react with each other and form molecular bonds with the silicon atoms of the base substrate.

8. The method according to claim 7, wherein: The first wafer includes a first semiconductor chip region and a second semiconductor chip region adjacent to each other, each of the first semiconductor chip region and the second semiconductor chip region including a portion of the base substrate and a portion of the element region, The method further includes forming a cutting pattern in the base substrate between the first semiconductor chip region and the second semiconductor chip region.

9. The method according to claim 8, wherein: Laser is used to form the cutting pattern in the base substrate between the first semiconductor chip region and the second semiconductor chip region.

10. The method according to claim 7, wherein: Grinding a portion of the base substrate includes rough grinding the portion of the base substrate and then fine grinding the portion of the base substrate.

11. The method according to claim 10, further comprising: After fine grinding the portion of the base substrate, polishing the portion of the base substrate is performed.

12. The method according to claim 7, wherein: The stress relief layer includes a polymer material.

13. The method according to claim 7, wherein: The thickness of the stress relaxation layer is 500 nm or less relative to the thickness of the second wafer being 60 μm or less.

14. A method for manufacturing a semiconductor device, the method comprising: Providing a base substrate in a first wafer, the base substrate having a first surface and a second surface facing each other, the first wafer having a device region on the first surface of the base substrate, wherein the first wafer includes a first semiconductor chip region and a second semiconductor chip region adjacent to each other, the first semiconductor chip region and the second semiconductor chip region each including a portion of the base substrate and a portion of the device region; forming a first supporting film on the element region; forming a cutting pattern in the base substrate between the first semiconductor chip region and the second semiconductor chip region using laser light incident from the second surface of the base substrate; After forming the cutting pattern, grinding a portion of the base substrate to form a second wafer from the first wafer; forming a stress release layer on the second surface of the ground base substrate, so that the stress release layer is molecularly bonded with silicon atoms of the base substrate; After forming the stress relief layer on the second surface of the ground base substrate, post-treating the stress relief layer using a plasma coating process that modifies the surface properties of the stress relief layer; forming a second supporting film on the post-processed stress release layer; and expanding the second wafer to separate the first semiconductor chip region and the second semiconductor chip region from each other, The forming of the stress release layer includes: applying voltage to change the gas used to form the stress release layer into a plasma state, so that the gases ionized into the plasma state chemically react with each other and form molecular bonds with the silicon atoms of the base substrate.

15. The method according to claim 14, wherein: Grinding a portion of the base substrate includes: performing rough grinding on the portion of the base substrate and then performing fine grinding on the portion of the base substrate; and The finely ground portion of the base substrate is polished.

16. The method according to claim 14, wherein: The stress relief layer includes a polymer material.

17. The method according to claim 14, wherein: The thickness of the stress relaxation layer is 500 nm or less relative to the thickness of the second wafer being 60 μm or less.

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