AC-linked chopper signal for high impedance buffer

Abstract

The present invention discloses a technique for receiving a DC or low frequency input signal using a chopper-stabilized amplifier, the technique comprising: chopping the input signal using a chopper clock signal to produce a chopped input signal. The input signal has a first voltage range, and the chopper clock signal has a second voltage range. The chopper clock signal has a peak-to-peak voltage within a period of the chopper clock signal. The peak-to-peak voltage is less than the first voltage range and less than the second voltage range. The frequency of the input signal is at least one order of magnitude less than the frequency of the chopper clock signal. The second voltage range may be greater than or equal to the first voltage range. The technique may include generating a bias signal based on a voltage reference signal and an output signal having a first voltage range.

Description

Technical Field

[0001] The present application relates to integrated circuits, and more particularly to integrated circuits including input amplifiers. Background Art

[0002] In conventional integrated circuit applications, the input signal can have any voltage within a target voltage range, ranging from a minimum voltage, such as ground (i.e., 0V), to a maximum input voltage, such as 2.5V in low-power applications. However, input amplifiers often have voltage offsets or other low-frequency noise due to, for example, bias errors and transistor mismatches. Figure 1 , the input amplifier 100 is a conventional inverting amplifier topology, whose gain is determined by the ratio of resistor R2 to resistor R1. If configured as a unity gain stage for an exemplary application, resistors R1 and R2 are each, for example, 10k ohms. If the input amplifier 100 has a large open-loop gain A, then the voltage swing V at the input terminal x Relatively small. Even if the input V IN The signal swing is large and the output V OUT The resulting signal swing is large, and nodes a and b also have relatively small voltage changes. Chopper-stabilization is a technique that reduces DC offset by chopping a DC or low-frequency input signal at the input node of an amplifier to produce a buffered or amplified high-frequency signal, and chopping it again at the output node to return the signal to a DC or low-frequency format output signal. This technique converts offset and low-frequency noise into a high-frequency signal portion that can be filtered out at the output.

[0003] In conventional integrated circuit manufacturing processes, low voltage transistors have a specified maximum voltage (e.g., 2V) that can drop across the gate oxide of the transistor (e.g., gate-to-source voltage, gate-to-drain voltage, or gate-to-bulk voltage), beyond which the gate oxide degrades by either breaking down or by reducing the lifetime of the gate oxide until the gate oxide breaks down. This specified maximum voltage is referred to herein as the breakdown voltage or degradation voltage. Some semiconductor manufacturing processes include additional transistor types. Reference Figure 2 For example, high voltage transistor 204 has a thicker gate oxide (as indicated by the rectangular gate in the symbol) than the gate oxide of low voltage transistor 202 (represented by the line). High voltage transistor 204 has a higher step-down voltage (e.g., + / -5V) than the step-down voltage of low voltage transistor 202 (e.g., + / -2V). The high voltage transistor also has a threshold voltage that exceeds the corresponding low voltage transistor (e.g., V for low voltage n-type transistor 206).th =0.5V; and for the low voltage p-type transistor 208, V th =-0.5V) (for example, for high voltage n-type transistor 210, V th =1V; for the high voltage p-type transistor 212, V th =-1V).

[0004] High voltage transistors are often used in input and output circuits where the voltage swing (e.g., 3V or 5V voltage swing) may be greater than the voltage swing in the core circuit (e.g., 2V), which is made with low voltage transistors. However, back to reference Figure 1 Due to the lack of signal swing at points a and b at the input of the operational amplifier 102, a conventional input chopper circuit (not shown) is connected to nodes a and b, and low voltage transistors are used. If the common mode voltage is in the middle of the transistor voltage range (e.g., 1V), the transistors in the input chopper circuit driven by the inverter can have a voltage swing that does not exceed the transistor step-down voltage of the low voltage transistor (e.g., from 0V to 2V). For example, in the on state, the source and drain of the n-type transistor of the input chopper circuit are 1V at the source terminal or drain terminal, and 2V at the gate terminal, and have a gate-to-source voltage or a gate-to-drain voltage of 1V, so that the transistor has sufficient overdrive voltage above the threshold voltage (e.g., 0.5V) to become a good low resistance switch. It can be seen that the gate-to-source voltage or gate-to-drain voltage of the closed n-type transistor is -1V, which will result in insignificant leakage current and will not exceed its step-down voltage. Since the voltage swing at points a and b is negligible, the resistance of the transistor is constant, which results in linear behavior. However, Figure 1 The topology is not well suited for high impedance input stages, as described below. In an exemplary implementation, the input impedance is approximately equal to resistor R1 (e.g., 10k ohms). Therefore, the input amplifier 100 is loaded with a high impedance source, which causes the input signal V IN The attenuation or distortion of the output signal V OUT accuracy.

[0005] Figure 3 An exemplary amplifier topology with high impedance input is shown. Input amplifier 300 provides unity gain from input to output, although greater gain can be achieved using a feedback divider (not shown) coupled from the output terminal to the inverting input terminal of operational amplifier 302. The input impedance of input amplifier 300 can be nearly infinite in a typical metal oxide semiconductor process, with no current flowing into the non-inverting input terminal and no resistance connected to the input nodes. Due to the large amplifier gain (A), the voltage V across nodes a and b isx is very small, because the output DC signal V OUT Follows the input signal V IN and have the same voltage except for any noise and voltage offset contributions. However, since nodes a and b follow the input signal, the topology of input amplifier 300 performs chopping to eliminate the challenges of offset and low frequency noise. For example, if the input signal V IN Swinging from 0 to 2.5V, nodes a and b swing within this voltage range. In an input chopper circuit, it is difficult to maintain a stable and low on-resistance over this range of transistors, and the low voltage transistors will experience an overvoltage condition. However, high voltage transistors have poor switching characteristics, which will affect the performance of the input amplifier 300. Therefore, an improved technique for implementing a high impedance input amplifier is needed. Summary of the invention

[0006] In at least one embodiment of the present invention, a method for receiving a direct current (DC) or low frequency signal using a chopper-stabilized amplifier includes: chopping an input signal using a chopper clock signal to generate a chopped input signal. The input signal has a first voltage range. The chopper clock signal has a second voltage range. The chopper clock signal has a peak-to-peak voltage within a period of the chopper clock signal. The peak-to-peak voltage is less than the first voltage range and less than the second voltage range. The second voltage range may be greater than or equal to the first voltage range. The frequency of the input signal may be at least at least one order of magnitude less than the frequency of the chopper clock signal. The method may also include: generating a bias signal based on a voltage reference signal and an output signal having a first voltage range. The method may also include: modulating the bias signal using an AC-coupled clock signal having a third voltage range and having a peak-to-peak voltage to generate the chopper clock signal. The AC-coupled clock signal may have the same period as the chopper clock signal and have a peak-to-peak voltage over a period that is substantially the same as the chopper clock signal. The third voltage range may be less than the first voltage range, and the third voltage range may be less than the second voltage range.Chopping the input signal may include biasing a body terminal of a transistor in an input chopper circuit of the chopper-stabilized amplifier using the input signal.

[0007] In at least one embodiment of the present invention, a chopper-stabilized amplifier circuit includes an amplifier circuit configured to generate an output signal based on a chopped input signal, a clock signal, and a chopped feedback signal. The chopper-stabilized amplifier circuit includes a bias circuit configured to modulate the bias signal by an AC-connected clock signal to generate a chopper clock signal. The chopper-stabilized amplifier circuit includes an input chopper circuit configured to generate a chopped input signal based on an input signal and a chopper clock signal. The input chopper circuit is further configured to generate a chopped feedback signal based on an output signal and a chopper clock signal. The bias circuit may also be configured to generate the bias signal based on the output signal and a voltage reference signal. The input chopper circuit may include a first transistor having a first stepped-down voltage. The amplifier circuit may include a second transistor having a second stepped-down voltage. The first stepped-down voltage may be less than the second stepped-down voltage. The input signal and the chopped input signal may each have a voltage range exceeding the first stepped-down voltage.

[0008] In at least one embodiment of the present invention, a method for buffering a DC or low frequency signal using a chopper-stabilized amplifier includes: generating a bias signal based on a voltage reference signal and a chopper-stabilized amplifier output signal having a first voltage range. The method includes modulating the bias signal with an AC-coupled clock signal to generate a chopper clock signal having a peak-to-peak voltage within a period of the chopper clock signal and having a second voltage range greater than the peak-to-peak voltage. The method includes providing the chopper clock signal to an input chopper circuit of the chopper-stabilized amplifier. The method may include biasing a body terminal of a transistor in the input chopper circuit using an input signal chopped by the input chopper circuit at the frequency of the chopper clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0010] Figure 1 A functional block diagram of a conventional inverting amplifier suitable for chopper stabilization is shown.

[0011] Figure 2 An exemplary transistor useful in a typical integrated circuit fabrication process is shown.

[0012] Figure 3 shows a functional block diagram of a high input impedance amplifier.

[0013] Figure 4 A functional block diagram of a high input impedance amplifier consistent with at least one embodiment of the present invention is shown.

[0014] Figure 5 shows a method consistent with at least one embodiment of the present invention, Figure 4 A functional block diagram of an exemplary implementation of a chopper bias generator.

[0015] Figure 6 shows a method consistent with at least one embodiment of the present invention, Figure 4 Example waveforms for a high input impedance amplifier.

[0016] Figure 7 shows a method consistent with at least one embodiment of the present invention, Figure 4 A circuit diagram of an exemplary input chopper circuit.

[0017] Figure 8 shows a method consistent with at least one embodiment of the present invention, Figure 4 A circuit diagram of an exemplary operational amplifier.

[0018] The use of the same reference numbers in different drawings indicates similar or identical items. Specific embodiments

[0019] A technique for using low voltage transistors in an input chopper circuit that responds to an input signal having a voltage range greater than the step-down voltage of the low voltage transistor. The low voltage transistor has improved linear operation over the voltage range of the input signal compared to the high voltage transistor. Figure 4 The chopper-stabilized amplifier 400 includes an input chopper circuit 402 implemented by low-voltage transistors. The chopper clock signal CLKX and the complementary chopper clock signal CLKXB control the low-voltage transistors in the input chopper circuit 402 and extend the useful range of the low-voltage transistors in the input chopper circuit 402.

[0020] The chopper clock signal CLKX and the complementary chopper clock signal CLKXB are connected by the AC clock signal clk IN and the complementary clock signal clk INB In at least one embodiment, the clock signal clk IN and the complementary clock signal clk INB Each has a fixed frequency (and therefore a fixed period). The AC-coupled clock signal and the AC-coupled complementary clock signal modulate the bias signal V B1 and the bias signal V B2 , to generate a chopping clock signal CLKX and a complementary chopping clock signal CLKXB respectively. The bias signal V B1 and the bias signal V B2 is the output signal V OUTA scaled and offset version of the input signal V generated by amplifier 302 IN In at least one embodiment, the chopper clock signal CLKX and the complementary chopper clock signal CLKXB each have the same fixed frequency clock signal clk IN and the complementary clock signal clk INB Each cycle of the chopper clock signal CLKX and the complementary chopper clock signal CLKXB has the same period as the clock signal clk IN and the complementary clock signal clk INB In some embodiments, due to the AC coupling, the peak-to-peak voltage of the chopper clock signals (i.e., chopper clock signal CLKX and complementary chopper clock signal CLKXB) is substantially the same as the corresponding clock signals (i.e., clock signals clk IN and the complementary clock signal clk INB ) only a negligible difference occurs between them. However, the voltage level of the chopper clock signal CLKX and the voltage level of the complementary chopper clock signal CLKXB deviate from the clock signal clk IN and the complementary chopper clock signal clk INB The voltage level of the bias signal V B1 and the bias signal V B2 voltage level.

[0021] Amplifier 302 includes a high voltage version of clock signal clkiN and a complementary chopper clock signal clk INB The output chopper switches are controlled by the amplifier 302 (as shown by "chop out"). High voltage transistors are suitable here because the first stage gain of amplifier 302 reduces their effect on linearity. A standard CMOS clock driver is used for the output chopper switches. Therefore, the chopper clock signal CLKX and the complementary chopper clock signal CLKXB both follow the input signal V IN .

[0022] The chopper clock signal CLKX and the complementary chopper clock signal CLKXB have peak-to-peak voltage levels that are compatible with the low voltage transistors included in the input chopper circuit 402. For example, the clock signal clk IN and the complementary chopper clock signal clk INB Each has a peak-to-peak voltage of 2V, and the voltage swing is 0V to 2V. Capacitors C1 and C2 convert the clock signal clk IN and the complementary chopper clock signal clk INB The chopper clock generator 408 uses those AC-coupled clock signals to modulate the bias signal VB1 and the bias signal V B2 , to generate a chopper clock signal CLKX and a complementary chopper clock signal CLKB respectively.

[0023] Figure 5 4 shows an exemplary implementation of a bias generator 406, which includes a voltage divider network (with a reference voltage V MID ), the voltage V MID Center the bias signal. Resistors R1, R2, R3, and R4 may be selected to obtain the maximum achievable clock swing for the target signal range without exceeding the low voltage transistor dropout voltage. Resistors R1 and R2 are selected to adequately follow the input signal within the signal range received by the input chopping circuit 402. Reference Figure 4 and 5 As shown, resistors R3 and R4 are selected to produce high impedance so that the AC-linked clock signal is substantially unattenuated when passing through the voltage divider formed between capacitor C1 or capacitor C2 and the corresponding resistor looking back to resistor C1. B1 and the bias signal V B2 V MID is the center and follows the output DC signal V OUT .

[0024] Figure 6 Waveforms consistent with manufacturing technology are shown, which have a low voltage transistor with a step-down voltage of 2V and a high voltage transistor with a step-down voltage of 5V. Waveform 702 shows the clock signal CLKIN (or clock signal CLKINB), which is INB The waveform 704 shows that the input signal V has a voltage swing of 2V (i.e., peak-to-peak voltage) in each cycle and changes rapidly between a low voltage level (0V) and a high voltage level (2V) at the chopping frequency (e.g., 4MHz). IN range (which is a DC signal or a low frequency signal, that is, a signal with a frequency greater than the clock signal clk INB (e.g., 4 MHz) is at least one order of magnitude smaller than a frequency (e.g., 10 kHz), and waveform 706 shows the bias signal V B1 (or bias signal V B2 ), the bias signal follows waveform 704 because the bias signal V B1 (or bias signal V B2 ) follows the input signal V IN The waveform 706 has a voltage swing that depends on the output DC signal V OUT The voltage swing of the voltage divider 406 and the resistance value in the voltage divider 406 are, for example, about one quarter of the voltage swing of the waveform 704 and are based on the voltage reference V MIDThe level is centered, for example, when the input signal V IN Approximately the middle of the expected voltage range. Figure 6 The waveform 708 is shown when the waveform 704 is subjected to the input signal V IN The chopper clock signal CLKX (or chopper clock signal CLKXB) as a function of voltage when it varies sinusoidally over all possible voltage values ​​within the target signal range of 0 to 2.5 V. Waveform 708 varies between two varying levels at the chopping frequency, but at approximately INB The waveform 708 has a peak-to-peak voltage on each cycle of the voltage swing (e.g., 2V) and is shifted to follow the input signal V IN (waveform 704), which results in waveform 708 having a voltage range of 0 to a voltage just above 2.5V. Waveform 708 shows that the chopper clock signal CLKX (or chopper clock signal CLKXB) has a voltage swing that limits the voltage across the gate oxide of the low voltage transistor of the input chopper circuit 402, while still providing the maximum specified gate-to-source voltage for the low voltage transistor. In other embodiments, the voltage range of the chopper clock signal is similar to the input signal V IN The voltage range is the same as or less than the input signal V IN The voltage range of , but is greater than the peak-to-peak voltage of the chopper clock signal by an amount that limits the voltage across the gate oxide of the low voltage transistor but provides sufficient overdrive for the low voltage transistor.

[0025] Reference Figure 6 and 7 , an exemplary embodiment of the input chopper circuit 402 includes transmission gates 604, 608, 610, and 612. Each transmission gate includes a p-type low voltage transistor connected in parallel with a corresponding n-type low voltage transistor and is controlled by complementary chopper clock signals CLKX and CLKXB. The input signal V IN is connected to the input of transmission gate 604 and the input of transmission gate 608. Similarly, the feedback signal V FB The input of transmission gate 610 and the input of transmission gate 612 are connected. Waveform 704 shows an input signal V having a maximum voltage of 2.5V at 25μs. IN At this input voltage level, the corresponding n-type low-voltage transistor cannot be turned on. When the gate voltage (for example, the chopper clock signal CLKX or the chopper clock signal CLKXB) is lower than the source voltage (the input signal V IN, which is 2.5V at 25μs) exceeds the threshold voltage by a small amount, the corresponding p-type low-voltage transistor is turned on. When the gate voltage switches to a voltage of approximately 0.7V (which is the low voltage of the swing of the chopper clock signal at approximately 25μs) and is 1.8V lower than the source / drain, the low-voltage p-type transistor will be strongly turned on. However, the voltage across the gate oxide does not exceed the rated voltage of the low-voltage transistor. In contrast, if a chopper clock signal that swings to a low voltage of 0V is used when the input signal is 2.5V, the voltage across the gate oxide will exceed the degradation voltage; that is, the minimum value of waveform 708 is 2.5V lower than the input voltage, and the source / drain voltage is 2.5V. Note that at the same point (time approximately equal to 25μs), the chopper clock signal CLKX (or chopper clock signal CLKXB) swings a small amount that is greater than the input signal V IN This ensures that at the maximum input voltage the p-type transistor is completely off and leakage current is negligible.

[0026] When the input signal V IN (shown by waveform 704) has a voltage in the middle of the signal swing (e.g., at time 50 μs), waveform 708 (which represents the chopper clock signal CLKX or chopper clock signal CLKXB) at the input signal V IN centered about (e.g., centered about 1.25V and having a maximum voltage of about 2.25V and a minimum voltage of about 0.25V). Therefore, when the chopper clock signal CLKX and the chopper clock signal CLKXB have a level that enables any of the transmission gates 604, 608, 610, and 612, the gate of the corresponding low voltage n-type transistor is driven at about 1V above its source terminal. Source terminal. Similarly, when the chopper clock signal CLKX and the chopper clock signal CLKXB have a level that enables any of the transmission gates 604, 608, 610, and 612, the gate of the corresponding low voltage p-type transistor is driven at about 1V below its source terminal (or drain terminal). As a result, the gate-to-source voltage V of the complementary transistor in the enabled transmission gate of the input chopper circuit 402 is GS The magnitude of is substantially greater than the corresponding threshold voltage, and the complementary transistors operate in parallel to form a switch that passes the input signal V INWhen the chopper clock signal CLKX and the chopper clock signal CLKXB have a level that disables any of the transmission gates 604, 608, 610, and 612, the gate voltage of the low voltage n-type transistor that should be turned off is lower than the source voltage by more than 1V. Similarly, when the chopper clock signal CLKX and the chopper clock signal CLKXB have a level that disables the transmission gate 604, 608, 610, or 612, the voltage level of the p-type transistor at its gate terminal is higher than the source voltage by about 1V. Therefore, the transmission gate of the disabled input chopper circuit 402 is not turned on by the input signal V IN And has negligible leakage current.

[0027] When the input signal V IN (shown by waveform 704) with a minimum input voltage level just above the 0V voltage level (e.g., at time 75μs), none of the low voltage transistors have a gate-to-source voltage with a magnitude greater than its maximum specified gate-to-source voltage. The low voltage n-type transistors in the transmission gates 604, 608, 610, and 612 are turned on when the associated chopper clock signal has a high level (slightly below 2V). When enabled, the gate-to-source voltage of the low voltage n-type transistors is slightly below 2V. In the off state, the gate-to-source voltage of the low voltage n-type transistors is slightly above 0V, and the n-type transistors are completely off with negligible leakage current. The corresponding p-type transistors are not turned on and never see a gate-to-source voltage greater than 2V. Therefore, in response to the chopper clock signal CLKX and the chopper clock signal CLKXB, the topology of the input chopper circuit 402 is turned on when the input signal V IN The whole range is good.

[0028] Note that at power-up, the bias and AC-connected clock signals stabilize to the target voltage levels. During the settling time, safe voltage levels may be exceeded. However, gate oxide degradation is not an instantaneous breakdown, but rather a reduction in lifetime in response to a modest exceedance of the gate oxide degradation voltage. The settling time is relatively short (i.e., for a voltage range of, e.g., 10 μs, it does not substantially affect gate oxide lifetime). In an exemplary manufacturing technique, applying a voltage twice the degradation voltage for several minutes has a negligible effect on gate oxide lifetime.

[0029] Reference Figure 4 and 8, an exemplary embodiment of amplifier 302 includes two amplifier stages responsive to the output of an input chopper switch, a chopping input signal Vipx and a chopping feedback signal Vinx. Amplifier 302 includes an output chopper p 802 and an output chopper n 804, which are controlled by a chopper clock signal CLK_HV and a chopper clock signal CLKB_HV. Chopper clock signal CLK_HV and chopper clock signal CLKB_HV are larger swing versions of CLKIN and CLKINB, and have a peak-to-peak voltage consistent with the high-voltage transistors of amplifier 302. Because the high-voltage transistors are within amplifier 302 (wherein the high-voltage transistors act on the signal current within amplifier 302, but not on the signal voltage), the terminal voltages of the transistors in output chopper p 802 and output chopper n 804 do not follow the signal. Therefore, the high-voltage transistors have suitable characteristics, namely low leakage when disconnected, even in the presence of large input signal swings or output signal swings. The output chopper p 802 circuit includes a p-type high voltage transistor controlled by CLK_HV and CLKB_HV, and the output chopper n 804 includes an n-type high voltage transistor controlled by CLK_HV and CLKB_HV. The combined operation of the output chopper p 802 and the output chopper n 804 will chop the buffered version of the chopped input Vinx and Vipx to produce a follow input signal V IN The output DC signal V OUT Note that amplifier 302 is exemplary only and other operational amplifier topologies implemented using high voltage transistors may be used.

[0030] Return to reference Figure 4 and 7 , the chopper clock signal CLKX and the chopper clock signal CLKXB are not power supply based and do not oscillate between power supply voltage levels. The chopper clock signal CLKX and the chopper clock signal CLKXB track the input signal V IN , although other techniques for generating the reference midpoint voltage chopper clock signal CLKX and chopper clock signal CLKXB may be used. In addition, the body terminal of each transistor in the transmission gates 604, 608, 610 and 612 is coupled to receive the input signal N IN The terminals of the transmission gates 604, 608, 610, and 612 are connected to ensure that the voltage drop across the gate oxide of the transistor in the off state is less than the specified de-rated voltage (e.g., less than 2V for the low voltage transistor). Therefore, the low voltage transistors in the transmission gates 604, 608, 610, and 612 never have a gate-to-source voltage or a gate-to-drain voltage that exceeds the specified de-rated voltage.

[0031] This configuration of the body terminals of the low voltage transistors in transmission gates 604, 608, 610, and 612 is in contrast to conventional body terminal biasing, which couples the body terminals of the low voltage n-type transistors to a ground voltage (i.e., 0V) and the body terminals of the low voltage p-type transistors to a supply voltage (i.e., VDD, e.g., 2V). The body terminal of each transmission gate transistor is coupled to an input signal V IN The configuration increases the layout area of ​​the transmission gate and increases the parasitic capacitance of the corresponding transistors, which slows down the switching of those transistors. However, because the frequencies of the chopper clock signal CLKX and the chopper clock signal CLKXB are relatively low and the reduction in the switching speed of the transistors in the transmission gate has minimal impact on system performance (i.e., the reduction in switching speed is much less than (e.g., orders of magnitude less than) the switching speed), the benefit of increasing the effective signal range of the low voltage transistors of the input chopper circuit in the chopper-stabilized amplifier outweighs the cost of the biasing technique. In addition to increasing the input voltage range, the topology of the chopper-stabilized amplifier 400 allows the use of low voltage transistors in the input chopper circuit 402 that have low on-resistance and low charge injection current to the input. The constant switching impedance within the range of the low voltage transistors maintains a more constant impedance and consistent swing of the chopper clock signal as it swings, thereby reducing signal distortion, compared to topologies that use high voltage transistors with higher threshold voltages in the input chopper switch circuit.

[0032] The techniques described herein may be used in a variety of applications including input circuits that receive DC or low frequency input signals. The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. For example, although the invention has been described in an embodiment using a unity gain buffer, those skilled in the art will appreciate that the teachings herein may be used in other embodiments of a chopper-stabilized amplifier 400 configured to have a higher gain. Additionally, although the invention has been described in an embodiment where the low voltage transistor has a 2V step-down voltage, the high voltage transistor has a 5V step-down voltage, and the input signal V IN With a voltage swing of 2.5V, one skilled in the art will appreciate that the teachings herein can be used in other embodiments of a chopper-stabilized amplifier 400 configured with low voltage transistors and high voltage transistors having different step-down voltages and having an input signal V with a different voltage swing exceeding the step-down voltage of the low voltage transistor. IN. The techniques described herein may be applicable to manufacturing techniques for transistors that include more than two voltage types. In other embodiments of the techniques described herein, an offset signal range (e.g., 0.5V < V < 3V) and a bias point at the midpoint of the signal range (e.g., 1.75V) are used. Variations and modifications to the embodiments disclosed herein may be made based on the description made herein without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for receiving a DC or low frequency signal using a chopper-stabilized amplifier, the method comprising: modulating the bias signal using the AC-connected clock signal to generate a chopper clock signal; as well as The input signal is chopped to produce a chopped input signal, the chopping being controlled by a chopper clock signal, The input signal has a first voltage range, and the chopper clock signal has a second voltage range, the chopper clock signal has a peak-to-peak voltage within a period of the chopper clock signal, the peak-to-peak voltage being smaller than the first voltage range and smaller than the second voltage range.

2. The method according to claim 1, in, The second voltage range is greater than or equal to the first voltage range, and Therein, the frequency of the input signal is at least one order of magnitude smaller than the frequency of the chopper clock signal.

3. The method according to claim 1, further comprising: generating a bias signal based on a voltage reference signal and an output signal having a first voltage range, wherein the AC-connected clock signal has a third voltage range; wherein the AC-coupled clock signal has the same period as the chopper clock signal and has a peak-to-peak voltage over a period that is substantially the same as the chopper clock signal, and The third voltage range is smaller than the first voltage range, and the third voltage range is smaller than the second voltage range.

4. The method according to claim 1, wherein: Chopping the input signal includes biasing a body terminal of a transistor in an input chopper circuit of the chopper-stabilized amplifier using the input signal.

5. The method according to claim 4, wherein: Chopping maintains all voltages less than or equal to the peak-to-peak voltage across the gate oxide of each transistor in the input chopping circuit.

6. The method of claim 1, 2, 3, 4 or 5, further comprising: The chopped input signal is amplified and chopped to generate an output signal.

7. The method according to claim 6, further comprising: A high voltage version of the chopper clock signal is generated, wherein the amplifying and chopping includes chopping an amplified version of the chopped input signal using the high voltage version of the chopper clock signal to generate the output signal.

8. The method according to claim 1, 2, 3, 4 or 5, wherein: The peak-to-peak voltage is less than a first stepped-down voltage of a first transistor in an input chopper circuit of the chopper-stabilized amplifier, the first voltage range is less than a second stepped-down voltage of a second transistor in an amplifier circuit coupled to the input chopper circuit of the chopper-stabilized amplifier, and the second stepped-down voltage is greater than the first stepped-down voltage.

9. The method of claim 1, 2, 3, 4 or 5, further comprising: providing a chopper clock signal to an input chopper circuit including a first transistor; as well as The output of the input chopper circuit is provided to an amplifier circuit of a chopper-stabilized amplifier, the amplifier circuit including a second transistor, the first transistor having a first gate oxide thickness, the second transistor having a second gate oxide thickness, the second gate oxide thickness being greater than the first gate oxide thickness.

10. The method of claim 1, 2, 3, 4 or 5, further comprising: controlling a first transmission gate and a second transmission gate using a chopper clock signal and a complementary version of the chopper clock signal to transmit an input signal to a first node and a second node on first alternating phases of the chopper clock signal; as well as The third transmission gate and the fourth transmission gate are controlled using the chopper clock signal and a complementary version of the chopper clock signal to send output signals to the second node and the first node on a second alternating phase of the chopper clock signal that is out of phase with the first alternating phase of the chopper clock signal.

11. A chopper-stabilized amplifier circuit, comprising: an amplifier circuit configured to generate an output signal based on the chopped input signal, the clock signal, and the chopped feedback signal; a bias circuit configured to modulate a bias signal with an AC-coupled clock signal to generate a chopper clock signal; as well as An input chopper circuit is controlled by the chopper clock signal to generate a chopped input signal based on the input signal.

12. The chopper-stabilized amplifier circuit of claim 11, wherein: The input chopping circuit is also controlled by the chopper clock signal to generate a chopped feedback signal based on the output signal.

13. The chopper-stabilized amplifier circuit of claim 11, wherein: The bias circuit is further configured to generate the bias signal based on the output signal and a voltage reference signal.

14. A chopper-stabilized amplifier circuit according to claim 11, 12 or 13, wherein: The input chopping circuit includes a first transistor having a first derating voltage, and the amplifier circuit includes a second transistor having a second derating voltage, the first derating voltage is less than the second derating voltage, and the input signal and the chopped input signal each have a voltage range exceeding the first derating voltage.

15. The chopper-stabilized amplifier circuit of claim 14, wherein: Each of the first transistors includes a source terminal, a drain terminal, a gate terminal, and a body terminal, the body terminal being coupled to the input signal.

16. The chopper-stabilized amplifier circuit of claim 14, wherein: The first transistor includes a first n-type transistor and a first p-type transistor configured as a pair of transmission gates, each transmission gate of the pair of transmission gates being controlled by a chopper clock signal and a complementary chopper clock signal to transmit an input signal to a first node and a second node at a first alternating phase of the chopper clock signal, and to transmit an output signal to a second node and the first node at a second alternating phase of the chopper clock signal, the second alternating phase being out of phase with the first alternating phase of the chopper clock signal.

17. The chopper-stabilized amplifier circuit of claim 16, wherein: The first transistor has a first gate oxide thickness, and the second transistor has a second gate oxide thickness, the second gate oxide thickness being greater than the first gate oxide thickness.

18. A chopper-stabilized amplifier circuit according to claim 11, 12 or 13, wherein: The amplifier circuit is a non-inverting amplifier. The amplifier circuit includes: at least one amplifier stage; and An output chopper circuit is controlled by a high voltage version of the chopper clock signal to chop an output of the at least one amplifier stage.

19. A method of buffering a DC or low frequency signal using a chopper-stabilized amplifier, the method comprising: generating a bias signal based on a voltage reference signal and a chopper-stabilized amplifier output signal having a first voltage range; as well as modulating the bias signal with an AC-coupled clock signal to generate a chopper clock signal having a peak-to-peak voltage within a period of the chopper clock signal and having a second voltage range greater than the peak-to-peak voltage; and A chopper clock signal is provided to an input chopper circuit of a chopper-stabilized amplifier.

20. The method according to claim 19, further comprising: The bulk terminals of transistors in the input chopper circuit are biased using an input signal chopped by the input chopper circuit at the frequency of the chopper clock signal.

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